CN118366929B - Manufacturing method of semiconductor device - Google Patents

本发明公开了一种半导体器件的制作方法，属于半导体技术领域。所述制作方法包括：提供一衬底，在所述衬底上形成伪栅极，所述伪栅极的栅极材料层包括无定型碳氮层；在所述伪栅极两侧形成侧墙结构；在所述侧墙结构远离所述伪栅极一侧的所述衬底内形成重掺杂区；在所述重掺杂区上形成金属硅化物层；在所述衬底上形成介质层，所述介质层的表面与所述伪栅极的表面齐平；干法刻蚀去除所述伪栅极，形成凹部；在所述凹部内形成金属栅极。通过本发明提供的一种半导体器件的制作方法，能够控制金属栅极的高度，提高半导体器件的电学性能。

The present invention discloses a method for manufacturing a semiconductor device, belonging to the field of semiconductor technology. The manufacturing method comprises: providing a substrate, forming a dummy gate on the substrate, the gate material layer of the dummy gate comprising an amorphous carbon nitride layer; forming a sidewall structure on both sides of the dummy gate; forming a heavily doped region in the substrate on the side of the sidewall structure away from the dummy gate; forming a metal silicide layer on the heavily doped region; forming a dielectric layer on the substrate, the surface of the dielectric layer being flush with the surface of the dummy gate; dry etching to remove the dummy gate to form a recess; forming a metal gate in the recess. Through the method for manufacturing a semiconductor device provided by the present invention, the height of the metal gate can be controlled and the electrical performance of the semiconductor device can be improved.

一种半导体器件的制作方法Method for manufacturing a semiconductor device

技术领域Technical Field

本发明属于半导体技术领域，特别涉及一种半导体器件的制作方法。The invention belongs to the technical field of semiconductors, and in particular relates to a method for manufacturing a semiconductor device.

背景技术Background Art

随着集成电路制造技术的不断发展，为了达到更快的运算速度、更大的数据存储量以及更多的功能，集成电路芯片朝向更高的半导体器件密度、更高的集成度方向发展。随着半导体器件的特征尺寸不断缩小，多晶硅栅极工艺不能满足半导体器件的要求，采用金属栅极替代多晶硅栅极，能够解决阈值电压漂移、多晶硅栅耗尽效应、过高的栅电阻和费米能级的钉扎等问题。其中，但在金属栅极制作过程中，多晶硅伪栅极易出现金属化或离子化等问题，导致多晶硅伪栅残留或栅极高度难以控制等问题，限制金属栅极的性能。With the continuous development of integrated circuit manufacturing technology, in order to achieve faster computing speed, larger data storage capacity and more functions, integrated circuit chips are moving towards higher semiconductor device density and higher integration. As the feature size of semiconductor devices continues to shrink, the polysilicon gate process cannot meet the requirements of semiconductor devices. The use of metal gates instead of polysilicon gates can solve problems such as threshold voltage drift, polysilicon gate depletion effect, excessive gate resistance and Fermi level pinning. However, during the metal gate manufacturing process, polysilicon pseudo gates are prone to metallization or ionization problems, resulting in polysilicon pseudo gate residues or gate height being difficult to control, limiting the performance of the metal gate.

发明内容Summary of the invention

本发明的目的在于提供一种半导体器件的制作方法，通过本发明提供的半导体器件的制作方法，在形成金属栅极时，能够完全去除伪栅极内的栅极材料层，控制金属栅极的高度，提高金属栅极的高度一致性，提高半导体器件的电学性能。The object of the present invention is to provide a method for manufacturing a semiconductor device. Through the method for manufacturing a semiconductor device provided by the present invention, when forming a metal gate, the gate material layer in the dummy gate can be completely removed, the height of the metal gate can be controlled, the height consistency of the metal gate can be improved, and the electrical performance of the semiconductor device can be improved.

为解决上述技术问题，本发明提供一种半导体器件的制作方法，包括以下步骤：In order to solve the above technical problems, the present invention provides a method for manufacturing a semiconductor device, comprising the following steps:

提供一衬底，在所述衬底上形成伪栅极，所述伪栅极的栅极材料层包括无定型碳氮层；Providing a substrate, forming a dummy gate on the substrate, wherein the gate material layer of the dummy gate includes an amorphous carbon nitride layer;

在所述伪栅极两侧形成侧墙结构；Forming sidewall structures on both sides of the dummy gate;

在所述侧墙结构远离所述伪栅极一侧的所述衬底内形成重掺杂区；forming a heavily doped region in the substrate on a side of the sidewall structure away from the dummy gate;

在所述重掺杂区上形成金属硅化物层；forming a metal silicide layer on the heavily doped region;

在所述衬底上形成介质层，所述介质层的表面与所述伪栅极的表面齐平；forming a dielectric layer on the substrate, wherein a surface of the dielectric layer is flush with a surface of the dummy gate;

干法刻蚀去除所述伪栅极，形成凹部；以及removing the dummy gate by dry etching to form a recess; and

在所述凹部内形成金属栅极。A metal gate is formed in the recess.

在本发明一实施例中，所述栅极材料层中，氮原子与碳原子的原子比为15:85~20:80。In one embodiment of the present invention, in the gate material layer, the atomic ratio of nitrogen atoms to carbon atoms is 15:85-20:80.

在本发明一实施例中，所述栅极材料层表面的光滑粗糙度小于1nm。In one embodiment of the present invention, the surface roughness of the gate material layer is less than 1 nm.

在本发明一实施例中，所述干法刻蚀的气体包括刻蚀气体和载气，所述刻蚀气体包括氢气和氮气，载气包括氩气。In one embodiment of the present invention, the dry etching gas includes an etching gas and a carrier gas, the etching gas includes hydrogen and nitrogen, and the carrier gas includes argon.

在本发明一实施例中，所述刻蚀气体和所述载气的总流量为60sccm~80sccm，所述载气的流量为40sccm~60sccm，在所述刻蚀气体中，氮气的占比为0.2~0.3。In one embodiment of the present invention, the total flow rate of the etching gas and the carrier gas is 60 sccm-80 sccm, the flow rate of the carrier gas is 40 sccm-60 sccm, and the proportion of nitrogen in the etching gas is 0.2-0.3.

在本发明一实施例中，所述干法刻蚀的直流偏压为40V~60V。In one embodiment of the present invention, the DC bias voltage of the dry etching is 40V~60V.

在本发明一实施例中，在所述干法刻蚀中，所述栅极材料层、氧化硅和氮化硅的刻蚀选择比为10:1:1~8:1:1。In one embodiment of the present invention, in the dry etching, the etching selection ratio of the gate material layer, silicon oxide and silicon nitride is 10:1:1-8:1:1.

在本发明一实施例中，所述制作方法还包括：在所述伪栅极上形成硬掩膜层，所述硬掩膜层包括依次设置在所述伪栅极上的第一硬掩膜层和第二硬掩膜层。In an embodiment of the present invention, the manufacturing method further includes: forming a hard mask layer on the dummy gate, the hard mask layer including a first hard mask layer and a second hard mask layer sequentially disposed on the dummy gate.

在本发明一实施例中，所述第一硬掩膜层为氮化硅层，所述第二硬掩膜层为氧化硅层。In one embodiment of the present invention, the first hard mask layer is a silicon nitride layer, and the second hard mask layer is a silicon oxide layer.

在本发明一实施例中，所述栅极材料层通过多孔空心阴极等离子体增强化学气相沉积制备，In one embodiment of the present invention, the gate material layer is prepared by porous hollow cathode plasma enhanced chemical vapor deposition.

综上所述，本发明提供一种半导体器件的制作方法，本申请意想不到的技术效果是能够提高栅极材料层的热稳定性和附着力，确保后续形成的伪栅极的准确性。能够减少制作过程缺陷的产生，提高制作良率。能够避免伪栅极的金属化或离子化，从而在后工序中，在去除伪栅极时可实现高选择比和完全去除，稳定金属栅极的高度。能够减少侧墙结构产生破口的情况，提高伪栅极与侧墙结构的刻蚀选择比，缩短去除时间，进一步减少侧墙结构刻蚀量，从而易于控制金属栅极的高度，提高金属栅极的高度一致性，提高半导体器件的电学性能。In summary, the present invention provides a method for manufacturing a semiconductor device. The unexpected technical effect of the present application is that it can improve the thermal stability and adhesion of the gate material layer, and ensure the accuracy of the pseudo gate formed subsequently. It can reduce the generation of defects in the manufacturing process and improve the manufacturing yield. It can avoid the metallization or ionization of the pseudo gate, so that in the later process, when removing the pseudo gate, a high selectivity and complete removal can be achieved, and the height of the metal gate can be stabilized. It can reduce the occurrence of cracks in the sidewall structure, improve the etching selectivity of the pseudo gate and the sidewall structure, shorten the removal time, and further reduce the etching amount of the sidewall structure, so that it is easy to control the height of the metal gate, improve the height consistency of the metal gate, and improve the electrical performance of the semiconductor device.

当然，实施本发明的任一产品并不一定需要同时达到以上所述的所有优点。Of course, any product implementing the present invention does not necessarily need to achieve all of the above-mentioned advantages at the same time.

附图说明BRIEF DESCRIPTION OF THE DRAWINGS

为了更清楚地说明本发明实施例的技术方案，下面将对实施例描述所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for describing the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

图1为本发明一实施例中在衬底上形成垫氧化层和垫氮化层的示意图。FIG. 1 is a schematic diagram of forming a pad oxide layer and a pad nitride layer on a substrate according to an embodiment of the present invention.

图2为本发明一实施例中形成第一光刻胶层的示意图。FIG. 2 is a schematic diagram of forming a first photoresist layer in one embodiment of the present invention.

图3为本发明一实施例中形成浅沟槽隔离结构的示意图。FIG. 3 is a schematic diagram of forming a shallow trench isolation structure in one embodiment of the present invention.

图4为本发明一实施例中形成阱区的示意图。FIG. 4 is a schematic diagram of forming a well region in one embodiment of the present invention.

图5为本发明一实施例中形成栅极材料层和硬掩膜层的示意图。FIG. 5 is a schematic diagram of forming a gate material layer and a hard mask layer in one embodiment of the present invention.

图6为本发明一实施例中形成伪栅极的示意图。FIG. 6 is a schematic diagram of forming a dummy gate according to an embodiment of the present invention.

图7为本发明一实施例中形成轻掺杂区的示意图。FIG. 7 is a schematic diagram of forming a lightly doped region in one embodiment of the present invention.

图8为本发明一实施例中形成侧墙结构和重掺杂区的示意图。FIG. 8 is a schematic diagram of forming a sidewall structure and a heavily doped region in one embodiment of the present invention.

图9为本发明一实施例中形成接触孔刻蚀停止层和介质层的示意图。FIG. 9 is a schematic diagram of forming a contact hole etching stop layer and a dielectric layer in one embodiment of the present invention.

图10为本发明一实施例中平坦化介质层至第一硬掩膜层的示意图。FIG. 10 is a schematic diagram of a planarization dielectric layer to a first hard mask layer according to an embodiment of the present invention.

图11为本发明一实施例中去除第一硬掩膜层后的示意图。FIG. 11 is a schematic diagram showing a state after the first hard mask layer is removed according to an embodiment of the present invention.

图12为本发明一实施例中去除伪栅极的示意图。FIG. 12 is a schematic diagram of removing a dummy gate according to an embodiment of the present invention.

图13为本发明一实施例中半导体器件的示意图。FIG. 13 is a schematic diagram of a semiconductor device according to an embodiment of the present invention.

标号说明：Description of labels:

10、衬底；101、阱区；11、垫氧化层；12、垫氮化层；13、第一光刻胶层；131、开口；14、浅沟槽隔离结构；15、栅极氧化层；16、第一栅极介质层；17、第二栅极介质层；18、栅极材料层；181、伪栅极；19、第一硬掩膜层；20、第二硬掩膜层；21、第二光刻胶层；22、轻掺杂区；23、侧墙结构；231、第一子层；232、第二子层；233、第三子层；234、第四子层；24、重掺杂区；25、金属硅化物层；26、接触孔刻蚀停止层；27、介质层；28、金属栅极；201、凹部。10. substrate; 101. well region; 11. pad oxide layer; 12. pad nitride layer; 13. first photoresist layer; 131. opening; 14. shallow trench isolation structure; 15. gate oxide layer; 16. first gate dielectric layer; 17. second gate dielectric layer; 18. gate material layer; 181. dummy gate; 19. first hard mask layer; 20. second hard mask layer; 21. second photoresist layer; 22. lightly doped region; 23. sidewall structure; 231. first sublayer; 232. second sublayer; 233. third sublayer; 234. fourth sublayer; 24. heavily doped region; 25. metal silicide layer; 26. contact hole etch stop layer; 27. dielectric layer; 28. metal gate; 201. recess.

具体实施方式DETAILED DESCRIPTION

下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其它实施例，都属于本发明保护的范围。The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施方式的目的，不是旨在于限制本申请。Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

在本说明书的描述中，需要理解的是，术语中“中心”、“上”、“下”、“前”、“后”、“左”、“右”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本方案和简化描述，而不是指示或暗示所指的装置或组件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本方案的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性。In the description of this specification, it should be understood that the directions or positional relationships indicated by the terms "center", "upper", "lower", "front", "back", "left", "right", etc. are based on the directions or positional relationships shown in the drawings, and are only for the convenience of describing the present solution and simplifying the description, rather than indicating or implying that the device or component referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as limiting the present solution. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.

本发明提供的一种半导体器件的制作方法，在形成金属栅极时，能够完全去除伪栅极内的栅极材料层，同时，减少侧墙结构的刻蚀，控制金属栅极的高度，提高金属栅极的高度一致性，提高半导体器件的电学性能。且本发明制备的半导体器件可广泛应用于光通信、数码显示、图像接收、光集成、交通、能源、医学、家用电器以及航空航天等各个领域。The present invention provides a method for manufacturing a semiconductor device, which can completely remove the gate material layer in the dummy gate when forming a metal gate, and at the same time, reduce the etching of the sidewall structure, control the height of the metal gate, improve the height consistency of the metal gate, and improve the electrical performance of the semiconductor device. The semiconductor device prepared by the present invention can be widely used in various fields such as optical communication, digital display, image reception, optical integration, transportation, energy, medicine, household appliances, and aerospace.

请参阅图1和图2所示，在本发明一实施例中，首先提供衬底10，衬底10可以为任意适于形成半导体器件的材料，例如为碳化硅（SiC）、氮化镓（GaN）、氮化铝（AlN）、氮化铟（InN）、磷化铟（InP）、砷化镓（GaAs）、硅锗（GeSi）、蓝宝石、硅片或者其它III/V化合物形成的半导体材料等，还包括这些半导体材料构成的叠层结构，或者为绝缘体上硅、绝缘体上层叠硅、绝缘体上锗化硅以及绝缘体上锗等。在本实施例中，衬底10例如为硅片半导体衬底。在其他实施例中，依据制作的半导体器件，选择衬底10的类型。本发明并不限制半导体器件的种类，半导体器件例如为场效应管（Field Effect Transistor，FET）、金属-氧化物半导体场效应晶体管（Metal-Oxide-Semiconductor Field-Effect Transistor，MOSFET）、互补金属氧化物半导体（Complementary Metal Oxide Semiconductor，CMOS）、绝缘栅双极型晶体管(Insulated Gate Bipolar Transistor，IGBT)、栅极可关断晶闸管（Gate Turn offThyristor，GTO）或晶闸管(Thyristor)等半导体器件中的一种或几种。在本实施例中，例如以MOS晶体管为例，对半导体器件的制作方法进行阐述。Referring to FIG. 1 and FIG. 2 , in one embodiment of the present invention, a substrate 10 is first provided. The substrate 10 may be any material suitable for forming a semiconductor device, such as silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), indium phosphide (InP), gallium arsenide (GaAs), silicon germanium (GeSi), sapphire, silicon wafer or other semiconductor materials formed by III/V compounds, etc., and also includes a stacked structure composed of these semiconductor materials, or silicon on insulator, stacked silicon on insulator, silicon germanium on insulator, and germanium on insulator. In this embodiment, the substrate 10 is, for example, a silicon wafer semiconductor substrate. In other embodiments, the type of the substrate 10 is selected according to the semiconductor device to be manufactured. The present invention does not limit the type of semiconductor devices, and the semiconductor devices are, for example, field effect transistors (FET), metal-oxide-semiconductor field-effect transistors (MOSFET), complementary metal oxide semiconductors (CMOS), insulated gate bipolar transistors (IGBT), gate turn off thyristors (GTO), or thyristors. In this embodiment, for example, a MOS transistor is taken as an example to describe the method for manufacturing a semiconductor device.

请参阅图1所示，在本发明一实施例中，在衬底10上形成垫氧化层11，垫氧化层11作为缓冲层可以改善衬底10与后续形成的垫氮化层12之间的应力，垫氧化层11例如为致密的氧化硅等材料，且垫氧化层11例如可以通过干氧氧化法、湿氧氧化法或原位水汽生长法(In-Situ Steam Generation，ISSG)等方法中的任意一种方法形成。在本实施例中，例如通过干氧氧化法形成垫氧化层11，具体的，将衬底10放入例如900℃~1150℃温度下的炉管内，通入氧气，衬底10的表面与氧气在高温下反应，生成致密的垫氧化层11，且生成的垫氧化层11的质量较好。其中，垫氧化层11例如为氧化硅，且垫氧化层11的厚度例如为10nm~40nm，具体例如10nm、20nm、30nm或40nm等。Please refer to FIG. 1 . In one embodiment of the present invention, a pad oxide layer 11 is formed on a substrate 10. The pad oxide layer 11 can improve the stress between the substrate 10 and the subsequently formed pad nitride layer 12 as a buffer layer. The pad oxide layer 11 is, for example, a dense silicon oxide material, and the pad oxide layer 11 can be formed by, for example, any one of the methods such as dry oxygen oxidation, wet oxygen oxidation, or in-situ steam growth (ISSG). In this embodiment, the pad oxide layer 11 is formed by, for example, dry oxygen oxidation. Specifically, the substrate 10 is placed in a furnace tube at a temperature of, for example, 900° C. to 1150° C., oxygen is introduced, and the surface of the substrate 10 reacts with oxygen at high temperature to generate a dense pad oxide layer 11, and the quality of the generated pad oxide layer 11 is good. Among them, the pad oxide layer 11 is, for example, silicon oxide, and the thickness of the pad oxide layer 11 is, for example, 10 nm to 40 nm, specifically, for example, 10 nm, 20 nm, 30 nm or 40 nm.

请参阅图1至图3所示，在本发明一实施例中，在垫氧化层11上形成垫氮化层12，垫氮化层12例如为氮化硅或氮化硅和氧化硅的叠层。在本实施例中，垫氮化层12例如为氮化硅，且例如可以通过低压化学气相沉积法（Low Pressure Chemical Vapor Deposition，LPCVD）等方法形成。具体例如将带有垫氧化层11的衬底10放置于充有二氯硅烷与氨气的炉管内，在压力例如为2T~10T，且温度例如为700℃~900℃下反应，沉积垫氮化层12，且可以通过控制加热时间调整垫氮化层12的厚度。垫氮化层12的厚度例如为50nm~80nm，具体例如为50nm、60nm或70nm等，通过设置垫氮化层12，可以保护衬底10免受浅沟槽隔离结构14制作过程中涉及的化学机械研磨（Chemical Mechanical Polishing，CMP）等平坦化工艺的影响。且垫氮化层12在后续浅沟槽隔离结构形成过程中，可以作为掩膜，在对衬底10进行刻蚀时，保护衬底10不受损伤。Please refer to FIG. 1 to FIG. 3 . In one embodiment of the present invention, a pad nitride layer 12 is formed on the pad oxide layer 11. The pad nitride layer 12 is, for example, silicon nitride or a stack of silicon nitride and silicon oxide. In this embodiment, the pad nitride layer 12 is, for example, silicon nitride, and can be formed, for example, by a method such as low pressure chemical vapor deposition (LPCVD). Specifically, for example, a substrate 10 with a pad oxide layer 11 is placed in a furnace tube filled with dichlorosilane and ammonia, and reacts at a pressure of, for example, 2T~10T and a temperature of, for example, 700°C~900°C to deposit the pad nitride layer 12, and the thickness of the pad nitride layer 12 can be adjusted by controlling the heating time. The thickness of the pad nitride layer 12 is, for example, 50 nm to 80 nm, specifically, 50 nm, 60 nm, or 70 nm. By providing the pad nitride layer 12, the substrate 10 can be protected from the influence of the planarization process such as chemical mechanical polishing (CMP) involved in the process of manufacturing the shallow trench isolation structure 14. In addition, the pad nitride layer 12 can be used as a mask in the subsequent shallow trench isolation structure formation process to protect the substrate 10 from damage when etching the substrate 10.

请参阅图1至图3所示，在本发明一实施例中，在形成垫氮化层12后，在垫氮化层12上形成第一光刻胶层13，通过曝光和显影工艺，在第一光刻胶层13上形成多个开口131，开口131用于定义浅沟槽隔离结构14的位置。以第一光刻胶层13为掩膜，进行刻蚀，去除开口131暴露的垫氮化层12、垫氧化层11以及部分衬底10，以形成浅沟槽。在本实施例中，例如采用干法刻蚀形成浅沟槽（图中未显示），刻蚀完成后，去除第一光刻胶层13。在形成浅沟槽后，在浅沟槽内沉积绝缘介质，直至绝缘介质覆盖垫氮化层12的表面。在本实施例中，绝缘介质例如为氧化硅。本发明并不限制绝缘介质的沉积方式，例如可以通过高密度等离子体化学气相沉积（High Density Plasma CVD，HDP-CVD）或高深宽比化学气相沉积（HighAspect Ratio Process CVD，HARP-CVD）等方式，以形成高质量的绝缘介质。在其他实施例中，绝缘介质还可以为其他适用于隔离的绝缘材料以及形成方法。Please refer to FIG. 1 to FIG. 3. In one embodiment of the present invention, after forming the pad nitride layer 12, a first photoresist layer 13 is formed on the pad nitride layer 12. Through exposure and development processes, a plurality of openings 131 are formed on the first photoresist layer 13. The openings 131 are used to define the position of the shallow trench isolation structure 14. The first photoresist layer 13 is used as a mask to perform etching to remove the pad nitride layer 12, the pad oxide layer 11 and a portion of the substrate 10 exposed by the opening 131 to form a shallow trench. In this embodiment, for example, dry etching is used to form a shallow trench (not shown in the figure). After the etching is completed, the first photoresist layer 13 is removed. After the shallow trench is formed, an insulating medium is deposited in the shallow trench until the insulating medium covers the surface of the pad nitride layer 12. In this embodiment, the insulating medium is, for example, silicon oxide. The present invention does not limit the deposition method of the insulating medium. For example, a high-quality insulating medium can be formed by high-density plasma chemical vapor deposition (HDP-CVD) or high-aspect ratio chemical vapor deposition (HARP-CVD). In other embodiments, the insulating medium can also be other insulating materials and formation methods suitable for isolation.

请参阅图1至图3所示，在本发明一实施例中，在制备绝缘介质后，对绝缘介质进行平坦化处理，例如利用化学机械研磨（Chemical Mechanical Polish，CMP）平坦化绝缘介质。例如研磨去除部分绝缘介质和部分垫氮化层12，再去除垫氮化层12，获得浅沟槽隔离结构14，且浅沟槽隔离结构14例如高出两侧的垫氧化层11。本发明并不限制垫氮化层12的去除方法，例如采用干法刻蚀、湿法刻蚀或干法刻蚀和湿法刻蚀相结合等方法去除。在本实施例中，例如采用热磷酸去除垫氮化层12，以形成浅沟槽隔离结构14，以隔离相邻的半导体器件。Please refer to FIG. 1 to FIG. 3. In one embodiment of the present invention, after preparing the insulating medium, the insulating medium is planarized, for example, by using chemical mechanical polish (CMP) to planarize the insulating medium. For example, a portion of the insulating medium and a portion of the pad nitride layer 12 are removed by grinding, and then the pad nitride layer 12 is removed to obtain a shallow trench isolation structure 14, and the shallow trench isolation structure 14 is, for example, higher than the pad oxide layer 11 on both sides. The present invention does not limit the method for removing the pad nitride layer 12, for example, dry etching, wet etching, or a combination of dry etching and wet etching are used for removal. In the present embodiment, for example, hot phosphoric acid is used to remove the pad nitride layer 12 to form a shallow trench isolation structure 14 to isolate adjacent semiconductor devices.

请参阅图3至图4所示，在本发明一实施例中，在浅沟槽隔离结构14制备完成后，以垫氧化层11为离子注入缓冲层，对衬底10进行离子注入，以形成阱区101。在本发明一实施例中，半导体器件例如为PMOS晶体管，阱区101中的掺杂离子例如为N型掺杂离子，又例如为磷（P）或砷（As）等。在本发明另一实施例中，半导体器件例如为NMOS晶体管，阱区101中的掺杂离子例如为P型掺杂离子，又例如为硼（B）或镓（Ga）等。在离子注入后，对阱区101进行快速热退火制程（Rapid Thermal Anneal，RTA），使得离子注入扩散至合适深度，同时提高半导体器件的抗雪崩击穿能力。再例如采用湿法刻蚀对垫氧化层11进行刻蚀，且湿法刻蚀的刻蚀液例如为氢氟酸或缓冲氧化物刻蚀液（Buffered Oxide Etch，BOE）等。Please refer to FIG. 3 and FIG. 4. In one embodiment of the present invention, after the shallow trench isolation structure 14 is prepared, the substrate 10 is ion-implanted with the pad oxide layer 11 as an ion-implanted buffer layer to form a well region 101. In one embodiment of the present invention, the semiconductor device is, for example, a PMOS transistor, and the doping ions in the well region 101 are, for example, N-type doping ions, such as phosphorus (P) or arsenic (As). In another embodiment of the present invention, the semiconductor device is, for example, an NMOS transistor, and the doping ions in the well region 101 are, for example, P-type doping ions, such as boron (B) or gallium (Ga). After the ion implantation, the well region 101 is subjected to a rapid thermal annealing process (RTA) so that the ion implantation diffuses to a suitable depth and improves the avalanche breakdown resistance of the semiconductor device. For another example, the pad oxide layer 11 is etched by wet etching, and the wet etching etchant is, for example, hydrofluoric acid or buffered oxide etchant (BOE).

请参阅图4至5所示，在本发明一实施例中，去除垫氧化层后，在衬底10上形成栅极氧化层15，栅极氧化层15例如为氧化硅层，且栅极氧化层15例如通过原位水汽生长法形成，栅极氧化层15的厚度例如为8Å~15Å。在形成栅极氧化层15后，在栅极氧化层15上以及浅沟槽隔离结构14上沉积第一栅极介质层16，且第一栅极介质层16例如为氧化铪（HfO₂）、氮氧化铪（HfON）、氧化锆（ZrO₂）、氮氧化锆（ZrON）、氧氮硅酸锆（ZrSiON）、硅酸铪（HfSiO）、氧氮硅酸铪（HfSiON）、镧氧氮化铪（HfLaON）或氧化铪铝（HfAlO）等高介电常数介质中的一种或几种混合，且第一栅极介质层16厚度例如为12Å~20Å。第一栅极介质层16例如可通过利用原子层沉积法（Atomic Layer Deposition，ALD）、金属有机气相沉积法（Metal-OrganicChemical Vapor Deposition，MOCVD）、分子束外延法（Molecular BeamEpitaxy，MBE）、化学气相沉积法或物理气相沉积法（Physical Vapor Deposition，PVD）等方法形成。通过形成栅极氧化层15，能够改善第一栅极介质层16与衬底10之间的界面品质较差的问题，提高半导体器件的性能。Referring to FIGS. 4 and 5 , in one embodiment of the present invention, after removing the pad oxide layer, a gate oxide layer 15 is formed on the substrate 10. The gate oxide layer 15 is, for example, a silicon oxide layer, and the gate oxide layer 15 is, for example, formed by an in-situ water vapor growth method, and the thickness of the gate oxide layer 15 is, for example, 8Å to 15Å. After forming the gate oxide layer 15, a first gate dielectric layer 16 is deposited on the gate oxide layer 15 and the shallow trench isolation structure 14, and the first gate dielectric layer 16 is, for example, one or a mixture of high dielectric constant dielectrics such as hafnium oxide (HfO ₂ ), hafnium oxynitride (HfON), zirconium oxide (ZrO ₂ ), zirconium oxynitride (ZrON), zirconium oxynitride silicate (ZrSiON), hafnium silicate (HfSiO), hafnium oxynitride silicate (HfSiON), hafnium lanthanum oxynitride (HfLaON) or hafnium aluminum oxide (HfAlO), and the thickness of the first gate dielectric layer 16 is, for example, 12Å to 20Å. The first gate dielectric layer 16 can be formed, for example, by using atomic layer deposition (ALD), metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), chemical vapor deposition or physical vapor deposition (PVD). By forming the gate oxide layer 15, the problem of poor interface quality between the first gate dielectric layer 16 and the substrate 10 can be improved, thereby improving the performance of the semiconductor device.

请参阅图5所示，在本发明一实施例中，在形成第一栅极介质层16后，在第一栅极介质层16上形成第二栅极介质层17，第二栅极介质层17例如为氮化钛或钛等，且第二栅极介质层17例如采用直流磁控溅射或原子层沉积法等方法制备，第二栅极介质层17的厚度例如为15Å~25Å。通过设置第二栅极介质层17，可以在后续制备过程中，防止第一栅极介质层16受到污染或损伤，提高后续制备的金属栅极的性能。再在第二栅极介质层17上形成栅极材料层18，栅极材料层18例如包括无定型碳氮层（α-CN）等。在本实施例中，栅极材料层18例如通过多孔空心阴极等离子体增强化学气相沉积(HC-PECVD)技术制备，栅极材料层18的厚度例如为50nm~150nm，依据最终金属栅极的厚度进行选择。具体的，在沉积腔室内，工作气压例如为50Pa~80Pa，工作温度例如为500℃~700℃，直流工作电压例如为200V~800V，在此条件下，例如通入含氮气体、含碳气体以及载气，其中，含氮气体例如包括氨气（NH₃）或氮气（N₂）等，含碳气体例如包括甲烷（CH₄）或乙炔（C₂H₂）等，载气例如包括氢气（H₂），载气用于促进气相反应，清洁和净化沉积腔室，确保沉积质量等。在本实施例中，含氮气体和载气的总流量例如为1mL/min~3mL/min，含氮气体和载气的体积比例如其1:7~1:9，含碳气体的流量例如为1mL/min~10mL/min。通过控制沉积时间，控制栅极材料层18的厚度。在本实施例中，在无定型碳氮层中，氮原子与碳原子的原子比例如为15:85~20:80，以提高栅极材料层18的热稳定性，同时无定型碳氮层的硬度高，与第二栅极介质层17的附着力好，在制作过程中不易出现剥离，确保后续形成的伪栅极的准确性。栅极材料层18表面的光滑粗糙度小于1nm，能够提高栅极材料层18与其他层的界面接触性能，从而在制作过程减少缺陷的产生，提高制作良率。通过形成无定型碳氮层，相对于碳层的致密层高，且能够在后续制作过程中，避免伪栅极的金属化或离子化，从而在后工序中去除伪栅极时可实现高选择比和完全去除，稳定金属栅极的高度。Please refer to FIG. 5 . In one embodiment of the present invention, after forming the first gate dielectric layer 16 , a second gate dielectric layer 17 is formed on the first gate dielectric layer 16 . The second gate dielectric layer 17 is, for example, titanium nitride or titanium, and the second gate dielectric layer 17 is, for example, prepared by DC magnetron sputtering or atomic layer deposition. The thickness of the second gate dielectric layer 17 is, for example, 15Å to 25Å. By providing the second gate dielectric layer 17 , the first gate dielectric layer 16 can be prevented from being contaminated or damaged during the subsequent preparation process, thereby improving the performance of the metal gate prepared subsequently. A gate material layer 18 is then formed on the second gate dielectric layer 17 . The gate material layer 18 includes, for example, an amorphous carbon nitride layer (α-CN). In this embodiment, the gate material layer 18 is prepared, for example, by a porous hollow cathode plasma enhanced chemical vapor deposition (HC-PECVD) technique. The thickness of the gate material layer 18 is, for example, 50nm to 150nm, which is selected according to the thickness of the final metal gate. Specifically, in the deposition chamber, the working pressure is, for example, 50Pa-80Pa, the working temperature is, for example, 500°C-700°C, and the DC working voltage is, for example, 200V-800V. Under this condition, for example, nitrogen-containing gas, carbon-containing gas and carrier gas are introduced, wherein the nitrogen-containing gas includes, for example, ammonia (NH ₃ ) or nitrogen (N ₂ ), etc., the carbon-containing gas includes, for example, methane (CH ₄ ) or acetylene (C ₂ H ₂ ), etc., and the carrier gas includes, for example, hydrogen (H ₂ ), and the carrier gas is used to promote gas phase reaction, clean and purify the deposition chamber, ensure deposition quality, etc. In this embodiment, the total flow rate of the nitrogen-containing gas and the carrier gas is, for example, 1mL/min-3mL/min, the volume ratio of the nitrogen-containing gas to the carrier gas is, for example, 1:7-1:9, and the flow rate of the carbon-containing gas is, for example, 1mL/min-10mL/min. The thickness of the gate material layer 18 is controlled by controlling the deposition time. In this embodiment, in the amorphous carbon nitride layer, the atomic ratio of nitrogen atoms to carbon atoms is, for example, 15:85~20:80, so as to improve the thermal stability of the gate material layer 18. At the same time, the amorphous carbon nitride layer has high hardness and good adhesion to the second gate dielectric layer 17, and is not prone to peeling during the manufacturing process, thereby ensuring the accuracy of the pseudo gate formed subsequently. The smooth roughness of the surface of the gate material layer 18 is less than 1nm, which can improve the interface contact performance between the gate material layer 18 and other layers, thereby reducing the generation of defects during the manufacturing process and improving the manufacturing yield. By forming an amorphous carbon nitride layer, the dense layer height relative to the carbon layer can be avoided, and the metallization or ionization of the pseudo gate can be avoided in the subsequent manufacturing process, so that a high selectivity and complete removal can be achieved when removing the pseudo gate in the later process, and the height of the metal gate can be stabilized.

请参阅图5所示，在本发明一实施例中，在形成栅极材料层18后，在栅极材料层18上形成硬掩膜层，其中，硬掩膜层例如包括第一硬掩膜层19和第二硬掩膜层20，第一硬掩膜层19设置在栅极材料层18上，第二硬掩膜层20设置在第一硬掩膜层19上。在本实施例中，第一硬掩膜层19例如为氮化硅层等，且厚度例如为15nm~25nm，第二硬掩膜层20例如为氧化硅层等，且厚度例如为25nm~35nm。通过设置两层硬掩膜层，第二硬掩膜层20保护第一硬掩膜层19，以防止在后续形成侧墙结构、重掺杂区或接触孔刻蚀停止层等结构时，第一硬掩膜层19被完全刻蚀，导致伪栅极被刻蚀，第二硬掩膜层20能够在去除伪栅极之前的制程中，确保伪栅极的高度，从而确保金属栅极的高度，并提高后续金属栅极的高度一致性。Referring to FIG. 5 , in one embodiment of the present invention, after forming the gate material layer 18, a hard mask layer is formed on the gate material layer 18, wherein the hard mask layer, for example, includes a first hard mask layer 19 and a second hard mask layer 20, wherein the first hard mask layer 19 is disposed on the gate material layer 18, and the second hard mask layer 20 is disposed on the first hard mask layer 19. In this embodiment, the first hard mask layer 19 is, for example, a silicon nitride layer, etc., and has a thickness of, for example, 15 nm to 25 nm, and the second hard mask layer 20 is, for example, a silicon oxide layer, etc., and has a thickness of, for example, 25 nm to 35 nm. By setting two hard mask layers, the second hard mask layer 20 protects the first hard mask layer 19 to prevent the first hard mask layer 19 from being completely etched when the sidewall structure, heavily doped area or contact hole etching stop layer and other structures are subsequently formed, resulting in the etching of the pseudo gate. The second hard mask layer 20 can ensure the height of the pseudo gate in the process before removing the pseudo gate, thereby ensuring the height of the metal gate and improving the height consistency of the subsequent metal gate.

请参阅图5至图6所示，在本发明一实施例中，在栅极材料层18形成后，在栅极材料层18上形成第二光刻胶层21，然后对第二光刻胶层21进行曝光以及显影，去除需要形成伪栅极以外区域的第二光刻胶层21。然后以第二光刻胶层21为掩膜，以栅极氧化层15为刻蚀停止层，例如通过干法刻蚀工艺、湿法刻蚀工艺或干法刻蚀工艺与湿法刻蚀工艺相结合来刻蚀第二硬掩膜层20、第一硬掩膜层19、第一栅极介质层16和第二栅极介质层17，将剩余的栅极材料层18定义为伪栅极181。Referring to FIG. 5 and FIG. 6 , in one embodiment of the present invention, after the gate material layer 18 is formed, a second photoresist layer 21 is formed on the gate material layer 18, and then the second photoresist layer 21 is exposed and developed to remove the second photoresist layer 21 in the area other than the area where the dummy gate is to be formed. Then, the second photoresist layer 21 is used as a mask and the gate oxide layer 15 is used as an etching stop layer, for example, by a dry etching process, a wet etching process, or a combination of a dry etching process and a wet etching process to etch the second hard mask layer 20, the first hard mask layer 19, the first gate dielectric layer 16, and the second gate dielectric layer 17, and the remaining gate material layer 18 is defined as a dummy gate 181.

请参阅图6至图7所示，在本发明一实施例中，在形成伪栅极181后，在伪栅极181两侧的衬底10内形成轻掺杂区22。其中，轻掺杂区22的掺杂离子例如通过离子注入形成，且注入的离子类型与阱区101中的离子类型相反。在本实施例中，当半导体器件为PMOS晶体管时，轻掺杂区22内的掺杂离子例如为硼或镓等P型杂质，当半导体器件为NMOS晶体管时，轻掺杂区22内的掺杂离子例如为磷或砷等N型杂质，且在注入掺杂离子的过程，形成的轻掺杂区22与伪栅极部分交叠。Please refer to FIG. 6 and FIG. 7 . In one embodiment of the present invention, after forming the dummy gate 181, a lightly doped region 22 is formed in the substrate 10 on both sides of the dummy gate 181. The doping ions in the lightly doped region 22 are formed, for example, by ion implantation, and the type of the implanted ions is opposite to the type of ions in the well region 101. In this embodiment, when the semiconductor device is a PMOS transistor, the doping ions in the lightly doped region 22 are, for example, P-type impurities such as boron or gallium, and when the semiconductor device is an NMOS transistor, the doping ions in the lightly doped region 22 are, for example, N-type impurities such as phosphorus or arsenic, and in the process of implanting the doping ions, the lightly doped region 22 formed overlaps with the dummy gate.

请参阅图7至图8所示，在本发明一实施例中，在形成轻掺杂区22后，在伪栅极的两侧形成侧墙结构23，其中，侧墙结构23例如为叠层结构。在本实施例中，侧墙结构23从靠近伪栅极181的侧边起，例如包括层叠的第一子层231、第二子层232、第三子层233和第四子层234，其中，第一子层231和第三子层233例如为氮化硅层，第二子层232和第四子层234例如为氧化硅层。通过将第一子层231设置为氮化硅层，在后续形成重掺杂区过程中，能够在图案化过程中，减少侧墙结构产生破口的情况，同时，能够提高去除伪栅极后，侧墙结构23的稳定性。在其他实施例中，侧墙结构23例如为其他叠层结构。通过将侧墙结构23设置为叠层结构，提高伪栅极的均匀性，从而提高半导体器件的阈值电压的稳定性。Referring to FIG. 7 and FIG. 8, in one embodiment of the present invention, after forming the lightly doped region 22, a sidewall structure 23 is formed on both sides of the dummy gate, wherein the sidewall structure 23 is, for example, a stacked structure. In this embodiment, the sidewall structure 23, starting from the side close to the dummy gate 181, includes, for example, a stacked first sublayer 231, a second sublayer 232, a third sublayer 233 and a fourth sublayer 234, wherein the first sublayer 231 and the third sublayer 233 are, for example, silicon nitride layers, and the second sublayer 232 and the fourth sublayer 234 are, for example, silicon oxide layers. By setting the first sublayer 231 as a silicon nitride layer, in the subsequent process of forming the heavily doped region, the situation of the sidewall structure generating cracks can be reduced during the patterning process, and at the same time, the stability of the sidewall structure 23 after removing the dummy gate can be improved. In other embodiments, the sidewall structure 23 is, for example, other stacked structures. By setting the sidewall structure 23 as a stacked structure, the uniformity of the dummy gate is improved, thereby improving the stability of the threshold voltage of the semiconductor device.

请参阅图8至图9所示，在本发明一实施例中，在形成侧墙结构23后，在侧墙结构23远离伪栅极181一侧的衬底10内形成重掺杂区24，重掺杂区24的边缘与侧墙结构23远离伪栅极181一侧对齐。其中，通过光阻工艺，暴露需要形成重掺杂区24的区域，例如通过离子注入掺杂离子形成重掺杂区24，且注入的离子类型与阱区中的离子类型相反，即与轻掺杂区22中的离子类型相同，且重掺杂区24的掺杂浓度大于轻掺杂区22的掺杂浓度。在重掺杂区24形成后，对重掺杂区24和轻掺杂区22进行激活，例如将衬底10进行快速热退火。通过快速热退火，能够修复制作过程中产生的晶格缺陷并激活掺杂离子，进而激活重掺杂区24和轻掺杂区22。在形成重掺区时，部分掺杂离子会进入伪栅极内，但无定型碳氮不会反生离子化而导致在去除过程中，刻蚀速率降低，从而加快后续伪栅极的去除速度，缩短去除时间，进一步减少侧墙结构刻蚀量，从而易于控制金属栅极的高度。Referring to FIG. 8 and FIG. 9 , in one embodiment of the present invention, after forming the sidewall structure 23, a heavily doped region 24 is formed in the substrate 10 on the side of the sidewall structure 23 away from the dummy gate 181, and the edge of the heavily doped region 24 is aligned with the side of the sidewall structure 23 away from the dummy gate 181. The photoresist process is used to expose the area where the heavily doped region 24 needs to be formed, for example, by ion implantation to form the heavily doped region 24, and the type of the implanted ions is opposite to the type of ions in the well region, that is, the same as the type of ions in the lightly doped region 22, and the doping concentration of the heavily doped region 24 is greater than the doping concentration of the lightly doped region 22. After the heavily doped region 24 is formed, the heavily doped region 24 and the lightly doped region 22 are activated, for example, the substrate 10 is subjected to rapid thermal annealing. Through rapid thermal annealing, the lattice defects generated during the manufacturing process can be repaired and the doped ions can be activated, thereby activating the heavily doped region 24 and the lightly doped region 22. When forming the heavily doped area, some doped ions will enter the pseudo-gate, but the amorphous carbon nitrogen will not be reversed and ionized, resulting in a lower etching rate during the removal process, thereby speeding up the subsequent removal of the pseudo-gate, shortening the removal time, and further reducing the etching amount of the sidewall structure, making it easier to control the height of the metal gate.

请参阅图8至图9所示，在本发明一实施例中，在形成重掺杂区24后，例如通过刻蚀去除侧墙结构23和伪栅极181以外区域的栅极氧化层15，在衬底10上的全部结构上形成金属层（图中未显示），通过热处理，金属与暴露的衬底10反应，在重掺杂区24上形成金属硅化物层25，再去除未反应的金属层，金属硅化物层25以改善后续在源极和漏极上形成的导电插塞的接触电阻。在形成重掺杂区过程中，虽然减少侧墙结构23的破口问题，但仍有部分金属通过侧墙结构进入伪栅极182内，在热处理时，金属不与伪栅极181内的栅极材料层反应而导致栅极材料层金属化，从而能够确保伪栅极的栅极材料层易去除，不存在残留。在形成金属硅化物层25后，在衬底10上形成接触孔刻蚀停止层26，接触孔刻蚀停止层26例如为氮化硅等。接触孔刻蚀停止层26例如覆盖侧墙结构23、伪栅极181、金属硅化物层25和浅沟槽隔离结构14上，避免后续制作过程中，影响侧墙结构23的稳定性或对衬底10造成损伤，从而提高半导体器件的性能。Please refer to FIG. 8 and FIG. 9. In one embodiment of the present invention, after forming the heavily doped region 24, the gate oxide layer 15 in the area other than the sidewall structure 23 and the dummy gate 181 is removed by etching, and a metal layer (not shown in the figure) is formed on all structures on the substrate 10. Through heat treatment, the metal reacts with the exposed substrate 10 to form a metal silicide layer 25 on the heavily doped region 24, and then the unreacted metal layer is removed. The metal silicide layer 25 is used to improve the contact resistance of the conductive plug formed on the source and drain electrodes later. In the process of forming the heavily doped region, although the crack problem of the sidewall structure 23 is reduced, some metal still enters the dummy gate 182 through the sidewall structure. During the heat treatment, the metal does not react with the gate material layer in the dummy gate 181 to cause the gate material layer to be metallized, thereby ensuring that the gate material layer of the dummy gate is easy to remove and there is no residue. After forming the metal silicide layer 25, a contact hole etching stop layer 26 is formed on the substrate 10. The contact hole etching stop layer 26 is, for example, silicon nitride. The contact hole etching stop layer 26, for example, covers the sidewall structure 23, the dummy gate 181, the metal silicide layer 25 and the shallow trench isolation structure 14 to avoid affecting the stability of the sidewall structure 23 or damaging the substrate 10 during subsequent manufacturing processes, thereby improving the performance of the semiconductor device.

请参阅图9至图10所示，在本发明一实施例中，在形成接触孔刻蚀停止层26后，在衬底10上形成介质层27，介质层27例如覆盖伪栅极181、侧墙结构23、浅沟槽隔离结构14和衬底10等。其中，介质层27例如为氧化硅，且例如通过化学气相沉积法等方法获得。在其他实施例中，介质层27例如为氟化硅（SiF）、碳氧化硅（SiOC）或氟氧化硅（SiOF）等材料，本发明不做具体限制。在形成介质层27后，对介质层27进行平坦化处理，例如利用化学机械研磨平坦化介质层27。在研磨过程中，以第一硬掩膜层19为研磨停止层，采用非选择性研磨，控制研磨时间，去除伪栅极181上的介质层27、接触孔刻蚀停止层26和第二硬掩膜层20，在平坦化处理后，介质层27的表面、第一硬掩膜层19的表面以及接触孔刻蚀停止层26的表面齐平。Please refer to FIG. 9 and FIG. 10. In one embodiment of the present invention, after forming the contact hole etching stop layer 26, a dielectric layer 27 is formed on the substrate 10. The dielectric layer 27, for example, covers the pseudo gate 181, the sidewall structure 23, the shallow trench isolation structure 14 and the substrate 10. The dielectric layer 27 is, for example, silicon oxide, and is obtained by, for example, chemical vapor deposition. In other embodiments, the dielectric layer 27 is, for example, silicon fluoride (SiF), silicon oxycarbide (SiOC) or silicon oxyfluoride (SiOF) and other materials, and the present invention does not make specific restrictions. After the dielectric layer 27 is formed, the dielectric layer 27 is planarized, for example, by chemical mechanical polishing to planarize the dielectric layer 27. During the grinding process, the first hard mask layer 19 is used as the grinding stop layer, non-selective grinding is adopted, and the grinding time is controlled to remove the dielectric layer 27, the contact hole etch stop layer 26 and the second hard mask layer 20 on the pseudo gate 181. After the planarization treatment, the surface of the dielectric layer 27, the surface of the first hard mask layer 19 and the surface of the contact hole etch stop layer 26 are flush.

请参阅图10至图11所示，在本发明一实施例中，在平坦化介质层27后，去除第一硬掩膜层19，暴露出伪栅极181的表面，同时去除部分介质层27、接触孔刻蚀停止层26和侧墙结构23，使伪栅极181和两侧的结构齐平。其中，第一硬掩膜层19例如通过刻蚀或平坦化等工艺去除，本申请不做具体限制。Referring to FIG. 10 and FIG. 11 , in one embodiment of the present invention, after the dielectric layer 27 is planarized, the first hard mask layer 19 is removed to expose the surface of the dummy gate 181, and a portion of the dielectric layer 27, the contact hole etching stop layer 26 and the sidewall structure 23 are removed at the same time, so that the dummy gate 181 is flush with the structures on both sides. The first hard mask layer 19 is removed, for example, by etching or planarization, and the present application does not make any specific restrictions.

请参阅图11至图12所示，在本发明一实施例中，在去除第一硬掩膜层19后，去除伪栅极181，以在伪栅极181的位置形成凹部201，在去除栅极材料层时，可采用干法刻蚀、湿法刻蚀或干法刻蚀和湿法刻蚀相结合。在本实施例中，例如采用干法刻蚀去除伪栅极181，以第二栅极介质层17为刻蚀停止层，且刻蚀气体例如包括刻蚀气体和载气等。其中，刻蚀气体例如包括氢气和氮气等不含氧原子的气体，载气例如为氩气等惰性气体，刻蚀气体和载气的总流量例如为60sccm~80sccm，载气的流量例如为40sccm~60sccm，氮气与氮气和氢气总流量的流量比率例如为0.2~0.3，即刻蚀气体中，氮气的占比例如为0.2~0.3。在刻蚀过程中，刻蚀腔室的压力例如为12mTorr~18mTorr，顶部电极功率例如为150W~250W，直流偏压例如为40V~60V。在刻蚀过程中，刻蚀气体中不含氧原子，能够提高伪栅极181内的栅极材料层与硅基材料的刻蚀选择比，在本实施例中，栅极材料层、氧化硅和氮化硅的刻蚀选择比例如为10:1:1~8:1:1，栅极材料层与氮化硅和氮化硅的刻蚀选择比较大，从而提高伪栅极181和侧墙结构23以及伪栅极181和接触孔刻蚀停止层26的刻蚀选择比，能够减小侧墙结构23和接触孔刻蚀停止层26的损失，可以有效控制后续金属栅极的高度。通过控制直流偏压的大小，可以控制等离子体的准直性，可以有效控制伪栅极181内栅极材料层的去除，同时在去除过程中，不破坏侧墙结构23，以作为后期制备的金属栅极的侧墙结构，提高半导体器件的电学性能。Please refer to FIG. 11 and FIG. 12. In one embodiment of the present invention, after removing the first hard mask layer 19, the dummy gate 181 is removed to form a recess 201 at the position of the dummy gate 181. When removing the gate material layer, dry etching, wet etching, or a combination of dry etching and wet etching can be used. In this embodiment, for example, dry etching is used to remove the dummy gate 181, and the second gate dielectric layer 17 is used as an etching stop layer, and the etching gas includes, for example, an etching gas and a carrier gas. Among them, the etching gas includes, for example, a gas that does not contain oxygen atoms such as hydrogen and nitrogen, and the carrier gas is, for example, an inert gas such as argon. The total flow of the etching gas and the carrier gas is, for example, 60 sccm~80 sccm, the flow of the carrier gas is, for example, 40 sccm~60 sccm, and the flow ratio of nitrogen to the total flow of nitrogen and hydrogen is, for example, 0.2~0.3, that is, the proportion of nitrogen in the etching gas is, for example, 0.2~0.3. During the etching process, the pressure of the etching chamber is, for example, 12mTorr~18mTorr, the top electrode power is, for example, 150W~250W, and the DC bias is, for example, 40V~60V. During the etching process, the etching gas does not contain oxygen atoms, which can improve the etching selectivity of the gate material layer and the silicon-based material in the pseudo gate 181. In this embodiment, the etching selectivity of the gate material layer, silicon oxide and silicon nitride is, for example, 10:1:1~8:1:1, and the etching selectivity of the gate material layer and silicon nitride and silicon nitride is relatively large, thereby improving the etching selectivity of the pseudo gate 181 and the sidewall structure 23 and the pseudo gate 181 and the contact hole etching stop layer 26, which can reduce the loss of the sidewall structure 23 and the contact hole etching stop layer 26, and can effectively control the height of the subsequent metal gate. By controlling the magnitude of the DC bias voltage, the collimation of the plasma can be controlled, and the removal of the gate material layer inside the pseudo gate 181 can be effectively controlled. At the same time, during the removal process, the side wall structure 23 is not destroyed, so as to serve as the side wall structure of the metal gate prepared later, thereby improving the electrical performance of the semiconductor device.

请参阅图12和13所示，在本发明一实施例中，在去除伪栅极181后，在介质层27上以及凹部201的底部和侧壁沉积多层金属功函数层和金属导电层（图中未显示），金属导电层设置在多层金属功函数层上，直至完全填充凹部201。然后对金属导电层和金属功函数层进行平坦化处理，直至与介质层27的表面齐平，以形成金属栅极28。其中金属功函数层的材料例如为氮化钽（TaN）、氮化钛、铝化钛（TiAl）、氮化钛铝（TiAIN）或氮化钨（WN）等中的一种或叠层，且金属功函数层例如通过等离子体增强化学的气相沉积法(Plasma EnhancedChemical Vapor Deposition，PECVD)、原子层沉积或物理气相沉积等方法形成。其中，金属功函数层的层数以及材料依据半导体器件的种类进行选择，以满足不同半导体器件的阈值电压需求。金属导电层例如选择金属铝、钨、铜或银等导电性较好的金属材料，且金属导电层例如为单层金属、多层金属或金属化合物堆叠等结构。在形成金属栅极28后，例如再进行导电插塞和金属布线层等的制作，在此不多作阐述。Referring to FIGS. 12 and 13 , in one embodiment of the present invention, after removing the dummy gate 181, a plurality of metal work function layers and metal conductive layers (not shown in the figure) are deposited on the dielectric layer 27 and the bottom and sidewall of the recess 201, and the metal conductive layer is disposed on the plurality of metal work function layers until the recess 201 is completely filled. Then, the metal conductive layer and the metal work function layer are planarized until they are flush with the surface of the dielectric layer 27 to form a metal gate 28. The material of the metal work function layer is, for example, one or a stack of tantalum nitride (TaN), titanium nitride, titanium aluminide (TiAl), titanium aluminum nitride (TiAIN) or tungsten nitride (WN), and the metal work function layer is formed, for example, by plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition or physical vapor deposition. The number of layers and materials of the metal work function layer are selected according to the type of semiconductor device to meet the threshold voltage requirements of different semiconductor devices. The metal conductive layer is made of a metal material with good conductivity such as aluminum, tungsten, copper or silver, and the metal conductive layer is a single-layer metal, a multi-layer metal or a metal compound stack. After the metal gate 28 is formed, for example, a conductive plug and a metal wiring layer are fabricated, which will not be elaborated here.

综上所述，本发明提供一种半导体器件的制作方法，通过对半导体器件的制作方法进行改进，本申请意想不到的技术效果是能够提高栅极材料层的热稳定性和附着力，确保后续形成的伪栅极的准确性。能够减少制作过程缺陷的产生，提高制作良率。能够避免伪栅极的金属化或离子化，从而在后工序中，在去除伪栅极时可实现高选择比和完全去除，稳定金属栅极的高度。能够减少侧墙结构产生破口的情况，提高伪栅极与侧墙结构的刻蚀选择比，缩短去除时间，进一步减少侧墙结构刻蚀量，从而易于控制金属栅极的高度，提高金属栅极的高度一致性，提高半导体器件的电学性能。In summary, the present invention provides a method for manufacturing a semiconductor device. By improving the method for manufacturing a semiconductor device, the unexpected technical effect of the present application is that the thermal stability and adhesion of the gate material layer can be improved, ensuring the accuracy of the pseudo gate formed subsequently. It is possible to reduce the generation of defects in the manufacturing process and improve the manufacturing yield. It is possible to avoid the metallization or ionization of the pseudo gate, so that in the later process, when removing the pseudo gate, a high selectivity and complete removal can be achieved, and the height of the metal gate can be stabilized. It is possible to reduce the occurrence of cracks in the sidewall structure, improve the etching selectivity of the pseudo gate and the sidewall structure, shorten the removal time, and further reduce the etching amount of the sidewall structure, thereby making it easy to control the height of the metal gate, improve the height consistency of the metal gate, and improve the electrical performance of the semiconductor device.

本发明所示实施例的上述描述(包括在说明书摘要中所述的内容)并非意在详尽列举或将本发明限制到本文所公开的精确形式。尽管在本文仅为说明的目的而描述了本发明的具体实施例和本发明的实例，但是正如本领域技术人员将认识和理解的，各种等效修改是可以在本发明的精神和范围内的。如所指出的，可以按照本发明所述实施例的上述描述来对本发明进行这些修改，并且这些修改将在本发明的精神和范围内。The above description of the illustrated embodiments of the present invention (including that described in the Abstract) is not intended to be exhaustive or to limit the present invention to the precise form disclosed herein. Although specific embodiments of the present invention and examples of the present invention are described herein for illustrative purposes only, various equivalent modifications are possible within the spirit and scope of the present invention as will be recognized and appreciated by those skilled in the art. As noted, these modifications may be made to the present invention in accordance with the above description of the embodiments described in the present invention, and these modifications will be within the spirit and scope of the present invention.

以上描述仅为本申请的较佳实施例以及对所运用技术原理的说明，本领域技术人员应当理解，本申请中所涉及的发明范围，并不限于上述技术特征的特定组合而成的技术方案，同时也应涵盖在不脱离所述发明构思的情况下，由上述技术特征或其等同特征进行任意组合而形成的其它技术方案，例如上述特征与本申请中公开的(但不限于)具有类似功能的技术特征进行互相替换而形成的技术方案。除说明书所述的技术特征外，其余技术特征为本领域技术人员的已知技术，为突出本发明的创新特点，其余技术特征在此不再赘述。The above description is only a preferred embodiment of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of the invention involved in the present application is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept, such as the technical solution formed by replacing the above features with (but not limited to) technical features with similar functions disclosed in this application. In addition to the technical features described in the specification, the remaining technical features are known technologies to those skilled in the art. In order to highlight the innovative features of the present invention, the remaining technical features will not be repeated here.