CN118740958A - A serial deserializer and network device - Google Patents

The invention relates to the technical field of design of a serial deserializer, and discloses a serial deserializer and network equipment, wherein the serial deserializer comprises a first-in first-out queue module, a physical coding sub-layer module and a physical medium additional layer module; one end of the first-in first-out queue module is connected with the target media access control layer module, and the other end of the first-in first-out queue module is connected with one end of the physical coding sublayer module; the physical coding sublayer module comprises a first state configuration machine and a coding unit, wherein the first state configuration machine is used for receiving configuration instructions and adjusting the configuration information of the first-in first-out queue module, the configuration information of the coding unit and the configuration information of the physical medium additional layer module according to the configuration instructions, so that the first-in first-out queue module, the coding unit and the physical medium additional layer module are adapted to data transmission under a target communication protocol.

一种串行解串器及网络设备A serial deserializer and network device

技术领域Technical Field

本发明涉及串行解串器设计技术领域，具体涉及一种串行解串器及网络设备。The present invention relates to the technical field of serial deserializer design, and in particular to a serial deserializer and a network device.

背景技术Background Art

串行解串器(Serializer/Deserializer，SerDes)能够将多路低速并行数据流合并为一路高速串行数据流进行传输，然后在接收端再将串行数据流解码恢复为并行数据流，以便在通信系统中高效准确地传输数据。A serializer/deserializer (SerDes) can combine multiple low-speed parallel data streams into one high-speed serial data stream for transmission, and then decode the serial data streams back into parallel data streams at the receiving end, so as to transmit data efficiently and accurately in the communication system.

SerDes包括物理编码子层(Physical Coding Sublayer，PCS)和物理媒介附加层(Physical Medium Attachment，PMA)两部分，PCS负责数据的编码和解码，将并行数据转换为适合串行传输的格式，并在接收端执行相反的操作。PMA负责将PCS提供的编码数据转换为物理信号，以适应特定的物理传输媒介(如铜缆或光纤等)，并在接收端执行相反的操作(物理信号转换为数字信号)。SerDes consists of two parts: the Physical Coding Sublayer (PCS) and the Physical Medium Attachment (PMA). The PCS is responsible for encoding and decoding data, converting parallel data into a format suitable for serial transmission, and performing the opposite operation at the receiving end. The PMA is responsible for converting the coded data provided by the PCS into a physical signal to adapt to a specific physical transmission medium (such as copper cable or optical fiber, etc.), and performing the opposite operation (converting physical signals into digital signals) at the receiving end.

目前，一般基于专用集成电路(Application Specific Integrated Circuit，ASIC)设计SerDes，基于ASIC设计SerDes的PCS一般根据协议要求进行专项设计，比如以支持以太网协议的需求为例，会专门设计基于以太网协议的PCS，导致SerDes只适用于特定的网络通信协议，灵活性较差。At present, SerDes is generally designed based on Application Specific Integrated Circuit (ASIC). The PCS designed based on ASIC for SerDes is generally specially designed according to the protocol requirements. For example, taking the demand for supporting the Ethernet protocol as an example, a PCS based on the Ethernet protocol will be specially designed, resulting in SerDes being only suitable for specific network communication protocols and having poor flexibility.

发明内容Summary of the invention

有鉴于此，本发明提供了一种串行解串器及网络设备，以解决串行解串器只适用于特定的网络通信协议，灵活性较差的问题。In view of this, the present invention provides a serial deserializer and a network device to solve the problem that the serial deserializer is only applicable to a specific network communication protocol and has poor flexibility.

第一方面，本发明提供了一种串行解串器，所述串行解串器基于现场可编程逻辑门阵列形成，所述串行解串器包括先进先出队列模块、物理编码子层模块和物理媒介附加层模块；所述先进先出队列模块的一端与目标媒体访问控制层模块连接，所述先进先出队列模块的另一端与所述物理编码子层模块的一端连接，所述物理编码子层模块的另一端与所述物理媒介附加层模块的一端连接，所述物理媒介附加层模块的另一端与物理传输媒介连接，其中，所述目标媒体访问控制层模块为多个媒体访问控制层模块中的其中一个，所述多个媒体访问控制层模块对应的通信协议不同；所述先进先出队列模块，用于隔离所述物理编码子层模块与所述目标媒体访问控制层模块的时钟域，以及用于隔离所述物理媒介附加层模块与所述目标媒体访问控制层模块的时钟域；所述物理编码子层模块包括第一状态配置机和编码单元，所述第一状态配置机用于接收配置指令，并用于根据所述配置指令调整所述先进先出队列模块的配置信息、所述编码单元的配置信息和所述物理媒介附加层模块的配置信息，使所述先进先出队列模块、所述编码单元和所述物理媒介附加层模块适配目标通信协议下的数据传输，其中，所述配置信息包括位宽信息、速率信息和时钟信息中的至少一种，所述目标通信协议为所述目标媒体访问控制层模块对应的通信协议。In a first aspect, the present invention provides a serial deserializer, which is formed based on a field programmable logic gate array, and includes a first-in-first-out queue module, a physical coding sublayer module and a physical medium attachment layer module; one end of the first-in-first-out queue module is connected to a target media access control layer module, the other end of the first-in-first-out queue module is connected to one end of the physical coding sublayer module, the other end of the physical coding sublayer module is connected to one end of the physical medium attachment layer module, and the other end of the physical medium attachment layer module is connected to a physical transmission medium, wherein the target media access control layer module is one of a plurality of media access control layer modules, and the plurality of media access control layer modules correspond to different communication protocols; the first-in-first-out queue module is used to isolate the physical media access control layer module. The physical coding sublayer module comprises a first state configuration machine and a coding unit, wherein the first state configuration machine is used to receive configuration instructions, and to adjust the configuration information of the first-in-first-out queue module, the configuration information of the coding unit and the configuration information of the physical medium attachment layer module according to the configuration instructions, so that the first-in-first-out queue module, the coding unit and the physical medium attachment layer module are adapted to the data transmission under the target communication protocol, wherein the configuration information comprises at least one of bit width information, rate information and clock information, and the target communication protocol is the communication protocol corresponding to the target media access control layer module.

在本实施例中，在基于现场可编程逻辑门阵列设计串行解串器时，对物理编码子层模块进行去协议化处理，在目标媒体访问控制层模块与串行解串器对接之后，通过物理编码子层模块中设置的第一状态配置机，将先进先出队列模块的配置信息、编码单元的配置信息以及物理媒介附加层模块的配置信息调整为目标配置信息，使先进先出队列模块、编码单元和物理媒介附加层模块适配目标通信协议下的数据传输，进而使串行解串器能够灵活的对接各种通信协议下的媒体访问控制层模块，满足不同应用场景的使用需求。In this embodiment, when designing a serial deserializer based on a field programmable gate array, the physical coding sublayer module is de-protocolized. After the target media access control layer module is connected to the serial deserializer, the configuration information of the first-in-first-out queue module, the configuration information of the encoding unit and the configuration information of the physical medium attachment layer module are adjusted to the target configuration information through the first state configuration machine set in the physical coding sublayer module, so that the first-in-first-out queue module, the encoding unit and the physical medium attachment layer module are adapted to the data transmission under the target communication protocol, thereby enabling the serial deserializer to flexibly connect to the media access control layer modules under various communication protocols to meet the usage requirements of different application scenarios.

在一种可选的实施方式中，所述物理媒介附加层模块包括数据通道和初始化单元；所述第一状态配置机与所述初始化单元连接，所述第一状态配置机通过所述初始化单元调整所述数据通道的配置信息。In an optional implementation, the physical medium attachment layer module includes a data channel and an initialization unit; the first state configuration machine is connected to the initialization unit, and the first state configuration machine adjusts the configuration information of the data channel through the initialization unit.

在一种可选的实施方式中，所述串行解串器还包括旁路通道，所述旁路通道的一端连接所述物理媒介附加层模块，另一端连接所述先进先出队列模块；所述旁路通道用于将所述数据通道的第一数据传输至所述先进先出队列模块，或者用于将所述先进先出队列模块的第二数据传输至所述数据通道。In an optional embodiment, the serial deserializer also includes a bypass channel, one end of the bypass channel is connected to the physical medium attachment layer module, and the other end is connected to the first-in-first-out queue module; the bypass channel is used to transfer the first data of the data channel to the first-in-first-out queue module, or to transfer the second data of the first-in-first-out queue module to the data channel.

在本实施例中，在不需要物理编码子层进行额外编码、解码或其他处理操作时，通过旁路通道可以直接将物理媒介附加层模块输出的串行数据传输至先进先出队列模块，或从先进先出队列模块传输到物理媒介附加层模块进行传输，能够缩短数据传输的路径，减少处理延迟。In this embodiment, when the physical coding sublayer does not need to perform additional encoding, decoding or other processing operations, the serial data output by the physical medium attachment layer module can be directly transmitted to the first-in-first-out queue module through the bypass channel, or transmitted from the first-in-first-out queue module to the physical medium attachment layer module for transmission, which can shorten the data transmission path and reduce processing delays.

在一种可选的实施方式中，所述旁路通道包括第二状态配置机，所述第二状态配置机用于使所述编码单元、所述数据通道和所述先进先出队列模块处于旁路模式，以将所述第一数据传输至所述先进先出队列模块或将所述第二数据传输至所述数据通道。In an optional embodiment, the bypass channel includes a second state configuration machine, which is used to put the encoding unit, the data channel and the first-in-first-out queue module in bypass mode to transfer the first data to the first-in-first-out queue module or to transfer the second data to the data channel.

在一种可选的实施方式中，所述编码单元、所述数据通道和所述先进先出队列模块的数量为多个，多个所述编码单元和多个所述数据通道一一对应，多个所述编码单元和多个所述先进先出队列模块一一对应。In an optional embodiment, there are multiple encoding units, multiple data channels and multiple first-in-first-out queue modules, and multiple encoding units correspond one-to-one to multiple data channels, and multiple encoding units correspond one-to-one to multiple first-in-first-out queue modules.

在一种可选的实施方式中，多个所述先进先出队列模块通过全互联网络软件配置模块与所述多个媒体访问控制层模块连接，所述全互联网络软件配置模块用于使所述目标媒体访问控制层模块与目标先进先出队列模块连接，目标先进先出队列模块为多个所述先进先出队列模块中的至少一个。In an optional embodiment, the multiple first-in-first-out queue modules are connected to the multiple media access control layer modules via a fully interconnected network software configuration module, and the fully interconnected network software configuration module is used to connect the target media access control layer module with the target first-in-first-out queue module, and the target first-in-first-out queue module is at least one of the multiple first-in-first-out queue modules.

在一种可选的实施方式中，所述全互联网络软件配置模块包括互联网络单元、输入接口和输出接口；所述输入接口的多个输入引脚分别连接所述多个媒体访问控制层模块，所述输出接口的多个输出引脚分别连接多个所述先进先出队列模块，所述互联网络单元用于使目标输入引脚和目标输出引脚处于连通状态，所述目标输入引脚为所述多个输入引脚中与所述目标媒体访问控制层模块连接的输入引脚，所述目标输出引脚为所述多个输出引脚中与所述目标先进先出队列模块连接的输出引脚。In an optional embodiment, the fully interconnected network software configuration module includes an interconnection unit, an input interface and an output interface; the multiple input pins of the input interface are respectively connected to the multiple media access control layer modules, and the multiple output pins of the output interface are respectively connected to the multiple first-in-first-out queue modules. The interconnection unit is used to make the target input pin and the target output pin in a connected state, the target input pin is an input pin among the multiple input pins connected to the target media access control layer module, and the target output pin is an output pin among the multiple output pins connected to the target first-in-first-out queue module.

在一种可选的实施方式中，所述先进先出队列模块还用于在接收来自于所述目标媒体访问控制层模块的第三数据之后，调整所述第三数据的位宽，使所述第三数据的时钟频率和所述编码单元的时钟频率同步。In an optional embodiment, the first-in-first-out queue module is also used to adjust the bit width of the third data after receiving the third data from the target media access control layer module, so that the clock frequency of the third data is synchronized with the clock frequency of the encoding unit.

在一种可选的实施方式中，所述第一状态配置机用于从外围总线接口获取所述配置指令。In an optional implementation, the first state configuration machine is used to obtain the configuration instruction from a peripheral bus interface.

第二方面，本发明提供了一种网络设备，包括：上述第一方面或其对应的任一实施方式的串行解串器、全互联网络软件配置模块和多个媒体访问控制层模块，所述串行解串器通过所述全互联网络软件配置模块与多个媒体访问控制层模块连接。In a second aspect, the present invention provides a network device, comprising: a serial deserializer of the above-mentioned first aspect or any corresponding embodiment thereof, a fully interconnected network software configuration module and multiple media access control layer modules, wherein the serial deserializer is connected to the multiple media access control layer modules through the fully interconnected network software configuration module.

附图说明BRIEF DESCRIPTION OF THE DRAWINGS

为了更清楚地说明本发明具体实施方式或相关技术中的技术方案，下面将对具体实施方式或相关技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图是本发明的一些实施方式，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the related technologies, the drawings required for use in the specific embodiments or the related technical descriptions will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

图1是常规的串行解串器与媒体访问控制层模块对接的结构示意图；FIG1 is a schematic diagram of the structure of a conventional serial deserializer and a media access control layer module;

图2是根据本发明实施例的一种串行解串器的结构示意图；FIG2 is a schematic diagram of the structure of a serial deserializer according to an embodiment of the present invention;

图3是根据本发明实施例的另一种串行解串器的结构示意图；FIG3 is a schematic diagram of the structure of another serial deserializer according to an embodiment of the present invention;

图4是根据本发明实施例的又一种串行解串器的结构示意图；FIG4 is a schematic diagram of the structure of another serial deserializer according to an embodiment of the present invention;

图5是根据本发明实施例的旁路通道的结构示意图；FIG5 is a schematic structural diagram of a bypass channel according to an embodiment of the present invention;

图6是根据本发明实施例的一种串行解串器与多个媒体访问控制层模块对接的结构示意图；6 is a schematic diagram of the structure of a serial deserializer connected to multiple media access control layer modules according to an embodiment of the present invention;

图7是根据本发明实施例的全互联网络软件配置模块的结构示意图。FIG. 7 is a schematic diagram of the structure of a fully interconnected network software configuration module according to an embodiment of the present invention.

附图标记：200、串行解串器；210、先进先出队列模块；220、物理编码子层模块；221、第一状态配置机；222、编码单元；230、物理媒介附加层模块；231、数据通道；232、初始化单元；240、旁路通道；241、第二状态配置机；300、媒体访问控制层模块；301、目标媒体访问控制层模块；400、全互联网络软件配置模块；410、互联网络单元；420、输入接口；430、输出接口。Figure numerals: 200, serial deserializer; 210, first-in-first-out queue module; 220, physical coding sublayer module; 221, first state configuration machine; 222, encoding unit; 230, physical medium attachment layer module; 231, data channel; 232, initialization unit; 240, bypass channel; 241, second state configuration machine; 300, media access control layer module; 301, target media access control layer module; 400, full internetwork software configuration module; 410, internetwork unit; 420, input interface; 430, output interface.

具体实施方式DETAILED DESCRIPTION

为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

基于ASIC的SerDes的PCS模块需要根据协议要求进行专项设计，与特定通信协议对应的媒体访问控制层(Media Access Control，MAC)模块连接，示例性的，如图1所示，MAC(A)模块通过接口(Interface)与PCS(N)模块连接，MAC(B)模块通过接口(Interface)与PCS(N-1)模块连接。其中，PCS(N)模块还通过SerDes接口与PMA(N)模块连接，PCS(N-1)模块还通过SerDes接口与PMA(N-1)模块连接，MAC(A)模块和MAC(B)模块还通过总线协议(Advanced eXtensible Interface，AXI)接口与其他系统(例如处理器等)连接。基于ASIC设计的SerDes中的PCS模块只能和特定的通信协议对应的MAC模块连接，在与其他通信协议对应的MAC模块连接传输数据时，需要重新设计相应的SerDes，SerDes的灵活性较差。The PCS module of the SerDes based on ASIC needs to be specially designed according to the protocol requirements and connected to the media access control layer (Media Access Control, MAC) module corresponding to the specific communication protocol. For example, as shown in Figure 1, the MAC (A) module is connected to the PCS (N) module through an interface (Interface), and the MAC (B) module is connected to the PCS (N-1) module through an interface (Interface). Among them, the PCS (N) module is also connected to the PMA (N) module through the SerDes interface, and the PCS (N-1) module is also connected to the PMA (N-1) module through the SerDes interface. The MAC (A) module and the MAC (B) module are also connected to other systems (such as processors, etc.) through the bus protocol (Advanced eXtensible Interface, AXI) interface. The PCS module in the SerDes designed based on ASIC can only be connected to the MAC module corresponding to a specific communication protocol. When connecting to the MAC module corresponding to other communication protocols to transmit data, the corresponding SerDes needs to be redesigned, and the flexibility of the SerDes is poor.

有鉴于此，本发明基于现场可编程逻辑门阵列(Field Programmable GateArray，FPGA)设计串行解串器，利用FPGA的可灵活配置性，优化PCS模块的结构设计，使串行解串器能够灵活的对接各种通信协议下的MAC模块，满足不同应用场景需求。In view of this, the present invention designs a serial deserializer based on a field programmable gate array (FPGA), utilizes the flexible configurability of FPGA, optimizes the structural design of the PCS module, and enables the serial deserializer to flexibly connect to MAC modules under various communication protocols to meet the needs of different application scenarios.

下面结合附图对本发明提供的串行解串器进行详细说明。The serial deserializer provided by the present invention is described in detail below with reference to the accompanying drawings.

本发明提供的串行解串器基于FPGA设计，如图2所示，串行解串器(SerDes)200包括先进先出队列(First Input First Output，FIFO)模块210、物理编码子层(PCS)模块220和物理媒介附加层(PMA)模块230。The serial deserializer provided by the present invention is designed based on FPGA. As shown in FIG. 2 , the serial deserializer (SerDes) 200 includes a first input first output (FIFO) module 210 , a physical coding sublayer (PCS) module 220 and a physical medium attachment (PMA) module 230 .

具体地，FIFO模块210的一端与目标MAC模块301连接，FIFO模块210的另一端与PCS模块220的一端连接，PCS模块220的另一端与PMA模块230的一端连接，PMA模块230的另一端与物理传输媒介(例如光纤或铜缆等)连接。Specifically, one end of the FIFO module 210 is connected to the target MAC module 301, the other end of the FIFO module 210 is connected to one end of the PCS module 220, the other end of the PCS module 220 is connected to one end of the PMA module 230, and the other end of the PMA module 230 is connected to a physical transmission medium (such as an optical fiber or a copper cable, etc.).

其中，目标MAC模块301为多个MAC模块中的其中一个，多个MAC模块对应的通信协议不同，例如，通信协议可以为以太网协议、高速串行计算机扩展总线(peripheralcomponent interconnect express，PCIE)协议或通用串行总线(Universal Serial Bus，USB)协议等。Among them, the target MAC module 301 is one of multiple MAC modules, and the communication protocols corresponding to the multiple MAC modules are different. For example, the communication protocol can be an Ethernet protocol, a high-speed serial computer expansion bus (peripheral component interconnect express, PCIE) protocol or a universal serial bus (Universal Serial Bus, USB) protocol, etc.

FIFO模块210用于隔离PCS模块220与目标MAC模块301的时钟域，以及用于隔离PMA模块230的时钟域与目标MAC模块301的时钟域。具体地，FIFO模块210可以为外部目标MAC模块301和内部PCS模块220、PMA模块230的时钟域桥梁，在不同频率的时钟域间提供数据缓冲，解决时钟域交叉的同步问题，比如时钟边沿不对齐或时钟偏位等。即在跨时钟域间传输数据时，FIFO模块210可以作为同步点，确保数据在适当的时钟沿被正确捕获，减少数据损失和错误。The FIFO module 210 is used to isolate the clock domains of the PCS module 220 and the target MAC module 301, and to isolate the clock domain of the PMA module 230 and the clock domain of the target MAC module 301. Specifically, the FIFO module 210 can be a clock domain bridge between the external target MAC module 301 and the internal PCS module 220 and the PMA module 230, provide data buffering between clock domains of different frequencies, and solve synchronization problems of clock domain crossing, such as clock edge misalignment or clock offset, etc. That is, when transmitting data across clock domains, the FIFO module 210 can serve as a synchronization point to ensure that data is correctly captured at the appropriate clock edge, thereby reducing data loss and errors.

PCS模块220包括第一状态配置机(CONFIG FSM)221和编码单元222，第一状态配置机221用于接收配置指令，并用于根据配置指令调整FIFO模块210的配置信息、编码单元222的配置信息和PMA模块230的配置信息，使FIFO模块210、编码单元222和PMA模块230适配目标通信协议下的数据传输。即，第一状态配置机221根据配置指令将FIFO模块210、编码单元222和PMA模块230的配置信息调整为目标配置信息，使FIFO模块210、编码单元222和PMA模块230适配目标通信协议下的数据传输。The PCS module 220 includes a first state configuration machine (CONFIG FSM) 221 and an encoding unit 222. The first state configuration machine 221 is used to receive a configuration instruction, and is used to adjust the configuration information of the FIFO module 210, the configuration information of the encoding unit 222, and the configuration information of the PMA module 230 according to the configuration instruction, so that the FIFO module 210, the encoding unit 222, and the PMA module 230 adapt to the data transmission under the target communication protocol. That is, the first state configuration machine 221 adjusts the configuration information of the FIFO module 210, the encoding unit 222, and the PMA module 230 to the target configuration information according to the configuration instruction, so that the FIFO module 210, the encoding unit 222, and the PMA module 230 adapt to the data transmission under the target communication protocol.

其中，配置指令用于指示第一状态配置机221调整FIFO模块210的配置信息、编码单元222的配置信息和PMA模块230的配置信息，配置指令包括与目标通信协议匹配的目标配置信息，配置信息包括位宽信息、速率信息和时钟信息中的至少一种，目标通信协议为目标MAC模块301对应的通信协议。Among them, the configuration instruction is used to instruct the first state configuration machine 221 to adjust the configuration information of the FIFO module 210, the configuration information of the encoding unit 222 and the configuration information of the PMA module 230. The configuration instruction includes target configuration information that matches the target communication protocol. The configuration information includes at least one of bit width information, rate information and clock information. The target communication protocol is the communication protocol corresponding to the target MAC module 301.

应理解，位宽指的是数据总线的数目，即每次传输数据的并行数据的位数，位宽的配置决定了并行数据处理能力和传输接口的宽度，与MAC的位宽相匹配，保证了数据在传输和接收端能无缝对接，没有丢失或错位对齐问题。速率指数据传输速率，可以为每秒内传输数据量的比特数。与MAC协商的通信速率一致，能够确保两端预期和实际传输的数据速率相匹配，避免数据溢出或欠载。时钟是同步数据传输的核心，与MAC的时钟同步，能够确保数据的准确传输和接收。It should be understood that the bit width refers to the number of data buses, that is, the number of bits of parallel data transmitted each time. The configuration of the bit width determines the parallel data processing capability and the width of the transmission interface. It matches the bit width of the MAC, ensuring that the data can be seamlessly connected at the transmission and receiving ends without loss or misalignment. Rate refers to the data transmission rate, which can be the number of bits of data transmitted per second. The communication rate negotiated with the MAC is consistent with the expected and actual transmission data rates at both ends to avoid data overflow or underload. The clock is the core of synchronous data transmission. Synchronizing with the clock of the MAC can ensure accurate transmission and reception of data.

具体地，对PCS模块220进行去协议化处理，使PCS模块220不再对应特定的通信协议，在串行解串器200与目标MAC模块301对接时，第一状态配置机221接收配置指令，并根据配置指令配置FIFO模块210、编码单元222和PMA模块230，使FIFO模块210、编码单元222和PMA模块230的状态满足目标通信协议的需求。Specifically, the PCS module 220 is de-protocolized so that the PCS module 220 no longer corresponds to a specific communication protocol. When the serial deserializer 200 is connected to the target MAC module 301, the first state configuration machine 221 receives the configuration instruction and configures the FIFO module 210, the encoding unit 222 and the PMA module 230 according to the configuration instruction so that the states of the FIFO module 210, the encoding unit 222 and the PMA module 230 meet the requirements of the target communication protocol.

示例性的，第一状态配置机221用于从外围总线(Advanced Peripheral Bus，APB)接口获取配置指令。配置指令可以由处理器等设备基于目标MAC模块301的目标通信协议生成。Exemplarily, the first state configuration machine 221 is used to obtain configuration instructions from an Advanced Peripheral Bus (APB) interface. The configuration instructions may be generated by a device such as a processor based on a target communication protocol of the target MAC module 301.

在进行数据传输时，FIFO模块210接收到来自于目标MAC模块301的第二数据之后，将第二数据发送至编码单元222，编码单元222用于对接收到的第二数据进行编码处理，得到第二编码数据，并将第二编码数据发送至PMA模块230，PMA模块230接收第二编码数据之后，用于将第二编码数据转换为第二物理信号，使第二编码数据适应物理传输媒介。During data transmission, after the FIFO module 210 receives the second data from the target MAC module 301, it sends the second data to the encoding unit 222. The encoding unit 222 is used to encode the received second data to obtain second encoded data, and send the second encoded data to the PMA module 230. After receiving the second encoded data, the PMA module 230 is used to convert the second encoded data into a second physical signal so that the second encoded data adapts to the physical transmission medium.

PMA模块230从物理传输媒介接收到第一物理信号之后，还用于将第一物理信号转化为第一数据，并将第一数据发送至编码单元222，编码单元222还用于对接收到的第一数据进行解码处理，得到第一解码数据，并将第一解码数据发送至FIFO模块210，由FIFO模块210转发至目标MAC模块301。After receiving the first physical signal from the physical transmission medium, the PMA module 230 is also used to convert the first physical signal into first data and send the first data to the encoding unit 222. The encoding unit 222 is also used to decode the received first data to obtain first decoded data, and send the first decoded data to the FIFO module 210, which is forwarded to the target MAC module 301 by the FIFO module 210.

具体地，编码单元222可以进行8b/10b编码和64b/66b编码等。其中，8b/10b编码中，每8位数据会被编码成10位符号，额外的2位用于同步和错误检测，常用于较低速率的以太网标准如千兆以太网。64b/66b编码中，64位数据块编码为66位的数据块，适用于更高的数据传输速率，如万兆以太网及以上的标准。Specifically, the encoding unit 222 can perform 8b/10b encoding and 64b/66b encoding. In 8b/10b encoding, every 8 bits of data will be encoded into a 10-bit symbol, and the additional 2 bits are used for synchronization and error detection, which is often used in lower-rate Ethernet standards such as Gigabit Ethernet. In 64b/66b encoding, a 64-bit data block is encoded into a 66-bit data block, which is suitable for higher data transmission rates, such as 10 Gigabit Ethernet and above.

在数据传输前对原始数据流进行编码，增加额外的位元以实现直流平衡(保证信号中1和0的数量大致相等，避免长时间的连续高电平或低电平导致接收端同步困难)和错误检测能力。The original data stream is encoded before data transmission, and extra bits are added to achieve DC balance (ensuring that the number of 1s and 0s in the signal is roughly equal, avoiding long periods of continuous high or low levels that cause synchronization difficulties at the receiving end) and error detection capabilities.

在本实施例中，在基于FPGA设计串行解串器时，对PCS模块进行去协议化处理，在目标MAC模块301与串行解串器200对接之后，通过PCS模块220中设置的第一状态配置机221，将FIFO模块210的配置信息、编码单元222的配置信息以及PMA模块230的配置信息调整为目标配置信息，使FIFO模块210、编码单元222和PMA模块230适配目标通信协议下的数据传输，进而使串行解串器能够灵活的对接各种通信协议下的MAC模块，满足不同应用场景的使用需求。In this embodiment, when designing a serial deserializer based on FPGA, the PCS module is de-protocolized. After the target MAC module 301 is connected to the serial deserializer 200, the configuration information of the FIFO module 210, the configuration information of the encoding unit 222, and the configuration information of the PMA module 230 are adjusted to the target configuration information through the first state configuration machine 221 set in the PCS module 220, so that the FIFO module 210, the encoding unit 222 and the PMA module 230 are adapted to the data transmission under the target communication protocol, thereby enabling the serial deserializer to flexibly connect to MAC modules under various communication protocols to meet the usage requirements of different application scenarios.

示例性的，FIFO模块210还用于在接收来自于目标MAC模块301的第三数据之后，调整第三数据的位宽，使第三数据的时钟频率和编码单元的时钟频率同步。具体地，目标MAC模块301的时钟频率小于编码单元222的时钟频率，数据从目标MAC模块301传输到编码单元222之前，FIFO模块210可以累积数据，再以较快的速度将数据输出至编码单元222，实现位宽展宽。其中，位宽展宽是指通过增加每次传输的数据位数来提升数据吞吐量的过程。Exemplarily, the FIFO module 210 is also used to adjust the bit width of the third data after receiving the third data from the target MAC module 301, so that the clock frequency of the third data is synchronized with the clock frequency of the encoding unit. Specifically, the clock frequency of the target MAC module 301 is less than the clock frequency of the encoding unit 222. Before the data is transmitted from the target MAC module 301 to the encoding unit 222, the FIFO module 210 can accumulate the data and then output the data to the encoding unit 222 at a faster speed to achieve bit width widening. Among them, bit width widening refers to the process of increasing data throughput by increasing the number of data bits transmitted each time.

进一步地，如图2所示，PMA模块230包括数据通道(Lane)231和初始化单元(Initialize Block)232。初始化单元232和第一状态配置机221连接，第一状态配置机221通过初始化单元232调整数据通道231的配置信息。具体地，第一状态配置机221用于向初始化单元232发送目标配置信息，初始化单元232接收目标配置信息之后，对数据通道231进行训练，将数据通道231的配置信息调整为目标配置信息。Further, as shown in FIG2 , the PMA module 230 includes a data lane (Lane) 231 and an initialization block (Initialize Block) 232. The initialization block 232 is connected to the first state configuration machine 221, and the first state configuration machine 221 adjusts the configuration information of the data lane 231 through the initialization block 232. Specifically, the first state configuration machine 221 is used to send target configuration information to the initialization block 232, and after receiving the target configuration information, the initialization block 232 trains the data lane 231 and adjusts the configuration information of the data lane 231 to the target configuration information.

本申请对编码单元222、数据通道231和FIFO模块210的数量不做限定，编码单元222、数据通道231和FIFO模块210的数量可以均为1，编码单元222、数据通道231和FIFO模块210的数量也可以均为多个。The present application does not limit the number of encoding units 222, data channels 231 and FIFO modules 210. The number of encoding units 222, data channels 231 and FIFO modules 210 can all be 1, or the number of encoding units 222, data channels 231 and FIFO modules 210 can all be multiple.

示例性的，如图3所示，多个编码单元222和多个数据通道231一一对应，多个编码单元222和多个FIFO模块210一一对应。其中，图3以编码单元222、数据通道231和FIFO模块210的数量均为4为例，但不限于此。例如，编码单元222、数据通道231和FIFO模块210的数量也可以均为2或8等。Exemplarily, as shown in FIG3 , multiple encoding units 222 correspond to multiple data channels 231 one by one, and multiple encoding units 222 correspond to multiple FIFO modules 210 one by one. In particular, FIG3 takes the number of encoding units 222, data channels 231, and FIFO modules 210 as 4 as an example, but is not limited thereto. For example, the number of encoding units 222, data channels 231, and FIFO modules 210 may also be 2 or 8.

示例性的，如图4所示，串行解串器200还包括旁路(Bypass)通道240，旁路通道240的一端连接PMA模块230，另一端连接FIFO模块210。旁路通道240用于直接将数据通道231的第一数据传输至FIFO模块210，或者用于直接将FIFO模块210的第二数据传输至数据通道231，实现PMA模块230和外部接口的直接对接，提高灵活性。Exemplarily, as shown in FIG4 , the serial deserializer 200 further includes a bypass channel 240, one end of the bypass channel 240 is connected to the PMA module 230, and the other end is connected to the FIFO module 210. The bypass channel 240 is used to directly transmit the first data of the data channel 231 to the FIFO module 210, or to directly transmit the second data of the FIFO module 210 to the data channel 231, so as to achieve direct connection between the PMA module 230 and the external interface and improve flexibility.

在本实施例中，在不需要PCS模块220进行额外编码、解码或其他处理操作时，通过旁路通道240可以直接将PMA模块230输出的串行数据传输至FIFO模块210，或从FIFO模块210传输到PMA模块230进行传输，能够缩短数据传输的路径，减少处理延迟。In this embodiment, when the PCS module 220 is not required to perform additional encoding, decoding or other processing operations, the serial data output by the PMA module 230 can be directly transmitted to the FIFO module 210 through the bypass channel 240, or transmitted from the FIFO module 210 to the PMA module 230 for transmission, which can shorten the data transmission path and reduce processing delays.

具体地，如图5所示，旁路通道240包括第二状态配置机241，第二状态配置机241用于使编码单元222、数据通道231和FIFO模块210处于旁路模式，以将第一数据传输至FIFO模块210或将第二数据传输至数据通道231。具体地，第二状态配置机241被触发之后，调整编码单元222、数据通道231和FIFO模块210的状态，使编码单元222停止编码或解码，数据通道231直接与FIFO模块210对接。5 , the bypass channel 240 includes a second state configuration machine 241, and the second state configuration machine 241 is used to put the encoding unit 222, the data channel 231 and the FIFO module 210 in the bypass mode to transmit the first data to the FIFO module 210 or to transmit the second data to the data channel 231. Specifically, after the second state configuration machine 241 is triggered, the states of the encoding unit 222, the data channel 231 and the FIFO module 210 are adjusted so that the encoding unit 222 stops encoding or decoding, and the data channel 231 is directly connected to the FIFO module 210.

示例性的，如图6所示，多个FIFO模块210通过全互联网络软件配置(Soft ConfigMux)模块400与多个媒体访问控制层模块(MAC)300连接，全互联网络软件配置模块400用于使目标MAC模块301与目标FIFO模块连接，目标FIFO模块为多个FIFO模块210中的至少一个。即，通过全互联网络软件配置模块400，可以根据需求使不同的FIFO模块210和不同的MAC模块300对接。Exemplarily, as shown in FIG6 , multiple FIFO modules 210 are connected to multiple media access control layer modules (MAC) 300 through a fully interconnected network software configuration (Soft ConfigMux) module 400, and the fully interconnected network software configuration module 400 is used to connect the target MAC module 301 to the target FIFO module, and the target FIFO module is at least one of the multiple FIFO modules 210. That is, through the fully interconnected network software configuration module 400, different FIFO modules 210 and different MAC modules 300 can be connected according to needs.

具体地，如图7所示，全互联网络软件配置模块400包括互联网络单元(SWITCHBOX)410、输入接口(Input MUX)420和输出接口(Output MUX)430，输入接口420的多个输入引脚分别连接多个MAC模块300，输出接口430的多个输出引脚分别连接多个FIFO模块210，互联网络单元410用于使目标输入引脚和目标输出引脚处于连通状态，目标输入引脚为多个输入引脚中与目标MAC模块301连接的输入引脚，目标输出接口为多个输出引脚中与目标FIFO模块连接的输出引脚。Specifically, as shown in FIG7 , the fully interconnected network software configuration module 400 includes an interconnection network unit (SWITCHBOX) 410, an input interface (Input MUX) 420, and an output interface (Output MUX) 430. The multiple input pins of the input interface 420 are respectively connected to the multiple MAC modules 300, and the multiple output pins of the output interface 430 are respectively connected to the multiple FIFO modules 210. The interconnection network unit 410 is used to connect the target input pin and the target output pin. The target input pin is an input pin connected to the target MAC module 301 among the multiple input pins, and the target output interface is an output pin connected to the target FIFO module among the multiple output pins.

具体地，互联网络单元410为软件可配置的全互联网络，通过软件配置，实现全互联网络，输入接口和输出接口对应的数据链路和时钟复位链路通过软件静态配置互联。示例性的，上电初始化的时候，软件根据真值表对互联网络单元410的硬件进行配置，实现数据，时钟和复位的互联。Specifically, the interconnection network unit 410 is a software-configurable fully interconnected network. Through software configuration, the fully interconnected network is realized, and the data links and clock reset links corresponding to the input interface and the output interface are interconnected through software static configuration. Exemplarily, when power is turned on and initialized, the software configures the hardware of the interconnection network unit 410 according to the truth table to realize the interconnection of data, clock and reset.

本发明实施例还提供了一种网络设备，如图6所示，网络设备包括多个MAC模块300、全互联网络软件配置模块400和上述任一实施例提供的串行解串器200，串行解串器200通过全互联网络软件配置模块400与多个MAC模块300连接。An embodiment of the present invention also provides a network device, as shown in Figure 6, the network device includes multiple MAC modules 300, a fully interconnected network software configuration module 400 and a serial deserializer 200 provided by any of the above embodiments, and the serial deserializer 200 is connected to the multiple MAC modules 300 through the fully interconnected network software configuration module 400.

具体地，在本实施例中，串行解串器200通过全互联网络软件配置模块400和FIFO模块210与MAC模块300对接，串行解串器200的数量也可以为多个，MAC模块300的数量和串行解串器200的数量可以根据需求灵活增减。Specifically, in this embodiment, the serial deserializer 200 is connected to the MAC module 300 through the fully interconnected network software configuration module 400 and the FIFO module 210. The number of serial deserializers 200 can also be multiple, and the number of MAC modules 300 and the number of serial deserializers 200 can be flexibly increased or decreased according to demand.

示例性的，网络设备可以为计算机设备或服务器等设备。Exemplarily, the network device may be a computer device or a server or other device.

在本发明的描述中，需要理解的是，术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”“内”、“外”、“顺时针”、“逆时针”、“轴向”、“径向”、“周向”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。In the description of the present invention, it is to be understood that the terms “center”, “longitudinal”, “lateral”, “length”, “width”, “thickness”, “up”, “down”, “front”, “back”, “left”, “right”, “vertical”, “horizontal”, “top”, “bottom”, “inside”, “outside”, “clockwise”, “counterclockwise”, “axial”, “radial”, “circumferential”, etc., indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

在本发明中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”、“固定”等术语应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或成一体；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系，除非另有明确的限定。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本发明中的具体含义。In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

应当理解，本发明的各部分可以用硬件、软件、固件或它们的组合来实现。在上述实施方式中，多个步骤或方法可以用存储在存储器中且由合适的指令执行系统执行的软件或固件来实现。例如，如果用硬件来实现，和在另一实施方式中一样，可用本领域公知的下列技术中的任一项或他们的组合来实现：具有用于对数据信号实现逻辑功能的逻辑门电路的离散逻辑电路，具有合适的组合逻辑门电路的专用集成电路，可编程门阵列(Programmable Gate Array，PGA)，现场可编程门阵列(Field Programmable Gate Array，FPGA)等。It should be understood that the various parts of the present invention can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, a plurality of steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

在本说明书的描述中，参考术语“本实施例”、“一个实施例”、“一些实施例”、“示例”、“具体示例”、或“一些示例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特点包含于本发明的至少一个实施例或示例中。在本说明书中，对上述术语的示意性表述不必须针对的是相同的实施例或示例。而且，描述的具体特征、结构、材料或者特点可以在任一个或多个实施例或示例中以合适的方式结合。此外，在不相互矛盾的情况下，本领域的技术人员可以将本说明书中描述的不同实施例或示例以及不同实施例或示例的特征进行结合和组合。In the description of this specification, the description with reference to the terms "this embodiment", "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, unless they are contradictory.

此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括至少一个该特征。在本发明的描述中，“多个”的含义是至少两个，例如两个，三个等，除非另有明确具体的限定。In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

虽然结合附图描述了本发明的实施例，但是本领域技术人员可以在不脱离本发明的精神和范围的情况下做出各种修改和变型，这样的修改和变型均落入本发明所限定的范围之内。Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations are all within the scope defined by the present invention.