CN118782577A - Semiconductor structure and preparation method thereof, semiconductor packaging structure - Google Patents

具体实施方式DETAILED DESCRIPTION

由背景技术可知，目前半导体结构中的深沟槽电容器的电容值还有待提高。As can be seen from the background art, the capacitance value of deep trench capacitors in current semiconductor structures needs to be improved.

本公开实施例提供一种半导体结构，每一沟槽电容器的极板数量与第一电接触结构的数量相同，以分别实现每一极板与外部电源之间的信号传输。衬底多个沟槽电容器中处于相同层的极板均和同一第一电接触结构电接触，从而将不同的深沟槽电容器并联，增大电容值。还设置衬底上的第一电接触结构在衬底第一面的正投影为环形，使得不同的第一电接触结构之间为嵌套式排布，如此，一方面可以大大节省第一电接触结构所占用的空间，从而有多余的空间来设置更多的沟槽电容器，进一步增大电容值。另一方面，还能减小相邻的第一电接触结构之间发生短路的风险。The disclosed embodiment provides a semiconductor structure, in which the number of plates of each trench capacitor is the same as the number of first electrical contact structures, so as to respectively realize signal transmission between each plate and an external power source. The plates on the same layer of multiple trench capacitors on the substrate are all electrically contacted with the same first electrical contact structure, so that different deep trench capacitors are connected in parallel to increase the capacitance value. The first electrical contact structure on the substrate is also arranged in a ring-shaped orthographic projection on the first surface of the substrate, so that different first electrical contact structures are arranged in a nested manner. In this way, on the one hand, the space occupied by the first electrical contact structure can be greatly saved, so that there is extra space to set more trench capacitors, further increasing the capacitance value. On the other hand, the risk of short circuit between adjacent first electrical contact structures can also be reduced.

下面将结合附图对本公开的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本公开各实施例中，为了使读者更好地理解本公开而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本公开所要求保护的技术方案。The following will describe the various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, it will be appreciated by those skilled in the art that in the various embodiments of the present disclosure, many technical details are provided in order to enable the reader to better understand the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can be implemented.

图1为本公开一实施例提供的一种半导体结构的一种剖视示意图，图2为本公开一实施例提供的一种半导体结构的俯视结构示意图；图3为本公开一实施例提供的一种半导体结构的另一种剖面结构示意图。其中，图1为图2中AA’方向的剖面结构示意图，图3为图2中BB’方向的剖面结构示意图。FIG1 is a schematic cross-sectional view of a semiconductor structure provided in one embodiment of the present disclosure, FIG2 is a schematic top view of a semiconductor structure provided in one embodiment of the present disclosure; FIG3 is another schematic cross-sectional view of a semiconductor structure provided in one embodiment of the present disclosure. Among them, FIG1 is a schematic cross-sectional view of the structure along the AA' direction in FIG2, and FIG3 is a schematic cross-sectional view of the structure along the BB' direction in FIG2.

参考图1以及图2，半导体结构包括：衬底100，衬底100具有相对的第一面11和第二面12，衬底100内具有多个间隔排布的沟槽13，每一沟槽13自第一面11向第二面12延伸，每一沟槽13内填充有沟槽电容器101，沟槽电容器101包括：N层极板102，相邻极板102之间具有电介质层103，N＞1，其中，第n层极板102位于第n-1层极板102远离沟槽13侧壁的一侧，1＜n≤N。半导体结构还包括：位于第一面11上的N个第一电接触结构104，每一第一电接触结构104在第一面11的正投影形状为环形，且相邻的两个第一电接触结构104中，一第一电接触结构104绕设于另一第一电接触结构104外周；多个沟槽电容器101中处于相同层的极板102均与同一第一电接触结构104电接触，且多个沟槽13电容的第1层极板102至第N层极板102中的所有极板102与不同的第一电接触结构104电接触。1 and 2 , the semiconductor structure includes: a substrate 100, the substrate 100 has a first surface 11 and a second surface 12 relative to each other, the substrate 100 has a plurality of spaced grooves 13, each groove 13 extends from the first surface 11 to the second surface 12, each groove 13 is filled with a trench capacitor 101, and the trench capacitor 101 includes: N layers of plates 102, a dielectric layer 103 is provided between adjacent plates 102, N＞1, wherein the nth layer of plate 102 is located on the side of the n-1th layer of plate 102 away from the side wall of the groove 13, 1＜n≤N. The semiconductor structure also includes: N first electrical contact structures 104 located on the first surface 11, each first electrical contact structure 104 has a ring-shaped orthographic projection on the first surface 11, and in two adjacent first electrical contact structures 104, one first electrical contact structure 104 is arranged around the outer periphery of the other first electrical contact structure 104; the plates 102 in the same layer of the multiple trench capacitors 101 are all electrically contacted with the same first electrical contact structure 104, and all the plates 102 from the 1st layer plate 102 to the Nth layer plate 102 of the multiple trench 13 capacitors are electrically contacted with different first electrical contact structures 104.

每一沟槽电容器101中极板102的数量为N个，第一电接触结构104的数量为N个，一个第一电接触结构104与每一第一电接触结构104中的其中一极板102对应，使得每一第一电接触结构104中的所有极板102均可以与不同的第一电接触结构104电连接。The number of plates 102 in each trench capacitor 101 is N, the number of first electrical contact structures 104 is N, and one first electrical contact structure 104 corresponds to one of the plates 102 in each first electrical contact structure 104, so that all the plates 102 in each first electrical contact structure 104 can be electrically connected to different first electrical contact structures 104.

多个沟槽电容器101中处于相同层的极板102均与同一第一电接触结构104电连接，也就是说，如此，一个第一电接触结构104可以电连接多个沟槽电容器101中的极板102，进而将多个沟槽电容器101进行并联，增大电容值。The plates 102 in the same layer of multiple trench capacitors 101 are all electrically connected to the same first electrical contact structure 104. That is, in this way, one first electrical contact structure 104 can electrically connect the plates 102 in multiple trench capacitors 101, thereby connecting multiple trench capacitors 101 in parallel to increase the capacitance value.

值得注意的是，多个沟槽电容器101中，均处于第n层的极板102被认为是处于相同层的极板102。例如，每一沟槽电容器101中极板102的数量为3个，则每一沟槽电容器101的第1层极板102为相同层的极板102，每一沟槽电容器101的第2层极板102为相同层的极板102，每一沟槽电容器101的第3层极板102为相同层的极板102。It is worth noting that, in the plurality of trench capacitors 101, the plates 102 that are all in the nth layer are considered to be in the same layer. For example, if the number of plates 102 in each trench capacitor 101 is 3, then the first layer of plates 102 of each trench capacitor 101 is the plates 102 in the same layer, the second layer of plates 102 of each trench capacitor 101 is the plates 102 in the same layer, and the third layer of plates 102 of each trench capacitor 101 is the plates 102 in the same layer.

每一沟槽电容器101的N层极板102中，第1层极板102朝向沟槽13侧壁设置，在一些实施例中，第1层极板102与沟槽13侧壁之间可以具有隔离层105，隔离层105一方面起到隔离第一层极板102与衬底100的作用，另一方面，还可以阻挡第一层极板102与衬底100之间发生离子扩散的问题。在一些实施例中，隔离层105的材料可以是氧化硅、氮化硅或者氮氧化硅中的至少一者。In each of the N-layer plates 102 of the trench capacitor 101, the first-layer plate 102 is disposed toward the sidewall of the trench 13. In some embodiments, an isolation layer 105 may be provided between the first-layer plate 102 and the sidewall of the trench 13. The isolation layer 105, on the one hand, serves to isolate the first-layer plate 102 from the substrate 100, and on the other hand, may also prevent ion diffusion from occurring between the first-layer plate 102 and the substrate 100. In some embodiments, the material of the isolation layer 105 may be at least one of silicon oxide, silicon nitride, or silicon oxynitride.

相邻两层极板102之间的电介质层103用于隔离相邻的两层极板102，在一些实施例中，电介质层103的材料可以为绝缘材料，例如氧化铝。在一些实施例中，极板102的材料可以为半导体导电材料，例如氮化钛。The dielectric layer 103 between two adjacent plates 102 is used to isolate the two adjacent plates 102. In some embodiments, the dielectric layer 103 may be made of an insulating material, such as aluminum oxide. In some embodiments, the plate 102 may be made of a semiconductor conductive material, such as titanium nitride.

衬底100上的第一电接触结构104在衬底100第一面11的正投影为环形，且一个第一电接触结构104环绕另一第一电接触结构104的外周。也就是说，多个第一电接触结构104之间为嵌套式设计，一方面可以大大减小多个第一电接触结构104所占用的空间，进而可以为形成更多的沟槽电容器101提供较多的空间，有利于增加沟槽电容器101的数量，进一步提高电容值，另一方面，多个第一电接触结构104之间嵌套式设计，使得相邻的第一电接触结构104之间不容易发生接触，进而可以减小相邻的第一电接触结构104之间发生短路的风险。The orthographic projection of the first electrical contact structure 104 on the substrate 100 on the first surface 11 of the substrate 100 is annular, and one first electrical contact structure 104 surrounds the outer circumference of another first electrical contact structure 104. In other words, the multiple first electrical contact structures 104 are designed in a nested manner, which can greatly reduce the space occupied by the multiple first electrical contact structures 104 on the one hand, thereby providing more space for forming more trench capacitors 101, which is conducive to increasing the number of trench capacitors 101 and further improving the capacitance value. On the other hand, the nested design between the multiple first electrical contact structures 104 makes it difficult for adjacent first electrical contact structures 104 to contact each other, thereby reducing the risk of short circuit between adjacent first electrical contact structures 104.

在一些实施例中，沟槽电容器101可以为半导体结构领域的深沟槽电容器101。In some embodiments, the trench capacitor 101 may be a deep trench capacitor 101 in the field of semiconductor structures.

在一些实施例中，衬底100的材料为半导体材料，在一些实施例中，衬底100的材料为硅。在一些实施例中，衬底100也可以为锗、锗硅或者绝缘体上的硅。In some embodiments, the material of the substrate 100 is a semiconductor material, and in some embodiments, the material of the substrate 100 is silicon. In some embodiments, the substrate 100 may also be germanium, germanium silicon, or silicon on insulator.

在一些实施例中，第一电接触结构104在第一面11的正投影形状为封闭环形。也就是说，第一电接触结构104为闭合的环形，如此，使得第一电接触结构104在第一面11上的所占面积较大，进而使得第一电接触结构104具有较大的体积，能够使第一电接触结构104本身具有较小的电阻，从而可以提升第一电接触结构104的电传输性能。In some embodiments, the orthographic projection of the first electrical contact structure 104 on the first surface 11 is a closed ring. In other words, the first electrical contact structure 104 is a closed ring, so that the area occupied by the first electrical contact structure 104 on the first surface 11 is larger, and the first electrical contact structure 104 has a larger volume, which can make the first electrical contact structure 104 itself have a smaller resistance, thereby improving the electrical transmission performance of the first electrical contact structure 104.

在一些实施例中，第一电接触结构104在第一面11上的正投影形状也可以是非闭合环形。In some embodiments, the orthographic projection shape of the first electrical contact structure 104 on the first surface 11 may also be a non-closed ring.

在一些实施例中，第一电接触结构104在第一面11的正投影形状为圆环形或者环状多边形中的任一者。在一些实施例中，第一电接触结构104在第一面11的正投影形状为圆环形，即第一电接触结构104为筒状结构，如此，使得第一电接触结构104的结构较为简单，进而使得制备第一电接触结构104的工艺较为简单，有利于提高半导体结构的良率。此外，设置第一电接触结构104在第一面11上的正投影为圆环形，使得第一电接触结构104的外侧面较为圆滑，进而使得嵌套的第一电接触结构104中，相邻的两个第一电接触结构104不容易发生接触，有效避免短路问题的发生。In some embodiments, the orthographic projection shape of the first electrical contact structure 104 on the first surface 11 is either a circular ring or a ring-shaped polygon. In some embodiments, the orthographic projection shape of the first electrical contact structure 104 on the first surface 11 is a circular ring, that is, the first electrical contact structure 104 is a cylindrical structure, so that the structure of the first electrical contact structure 104 is relatively simple, and thus the process of preparing the first electrical contact structure 104 is relatively simple, which is conducive to improving the yield of the semiconductor structure. In addition, the orthographic projection of the first electrical contact structure 104 on the first surface 11 is set to be a circular ring, so that the outer side surface of the first electrical contact structure 104 is relatively smooth, and thus in the nested first electrical contact structures 104, it is not easy for two adjacent first electrical contact structures 104 to contact, effectively avoiding the occurrence of short circuit problems.

在一些实施例中，第一电接触结构104也可以为环状多边形，例如可以是三角环形、环状矩形、环状五边形或者环状六边形等。本申请实施例不对环状多边形的边的数量进行具体限定，仅需满足第一电接触结构104在第一面11上的正投影形状为环形即可。In some embodiments, the first electrical contact structure 104 may also be an annular polygon, for example, a triangular ring, an annular rectangle, an annular pentagon, or an annular hexagon, etc. The embodiment of the present application does not specifically limit the number of sides of the annular polygon, and only needs to satisfy that the orthographic projection shape of the first electrical contact structure 104 on the first surface 11 is annular.

在一些实施例中，N可以为3。也就是说，每一沟槽电容器101中的极板102的数量为3个，则第1层极板102与第2层极板102构成一个电容器，第3层极板102与第2层极板102构成一个电容器，以形成三面电容器。在一些实施例中，第1层极板102与第3层极板102可以电连接至同一个外部电源，即电连接至同一电位，第2层极板102可以电连接至另一电位，进而实现对不同电位的去耦。In some embodiments, N may be 3. That is, the number of plates 102 in each trench capacitor 101 is 3, and the first layer of plates 102 and the second layer of plates 102 constitute a capacitor, and the third layer of plates 102 and the second layer of plates 102 constitute a capacitor, so as to form a three-sided capacitor. In some embodiments, the first layer of plates 102 and the third layer of plates 102 may be electrically connected to the same external power supply, that is, electrically connected to the same potential, and the second layer of plates 102 may be electrically connected to another potential, thereby achieving decoupling of different potentials.

3个第一电接触结构104中的每一个电连接多个沟槽电容器101中处于相同层的极板102，进而将多个沟槽电容器101并联。Each of the three first electrical contact structures 104 is electrically connected to the plates 102 in the same layer of the plurality of trench capacitors 101 , thereby connecting the plurality of trench capacitors 101 in parallel.

在一些实施例中，N也可以为2。在一些实施例中，N还可以为4。在一些实施例中，N还可以为5。本申请实施例不对每一沟槽电容器101中极板102的数量以及第一电接触结构104的数量进行具体限定，可以根据不同的需求调整极板102的数量以及第一电接触结构104的数量。In some embodiments, N may also be 2. In some embodiments, N may also be 4. In some embodiments, N may also be 5. The embodiment of the present application does not specifically limit the number of plates 102 and the number of first electrical contact structures 104 in each trench capacitor 101, and the number of plates 102 and the number of first electrical contact structures 104 may be adjusted according to different requirements.

在一些实施例中，N个第一电接触结构104中的每一个在第二面12的正投影与每一沟槽电容器101在第二面12的正投影部分重合，也就是说，每一第一电接触结构104与每一沟槽电容器101正对设置，进而使得第一电接触结构104与沟槽电容器101中的极板102之间的距离较近，减小信号传输距离。In some embodiments, the orthographic projection of each of the N first electrical contact structures 104 on the second surface 12 partially overlaps with the orthographic projection of each trench capacitor 101 on the second surface 12, that is, each first electrical contact structure 104 is arranged opposite to each trench capacitor 101, so that the distance between the first electrical contact structure 104 and the plate 102 in the trench capacitor 101 is closer, thereby reducing the signal transmission distance.

在一些实施例中，第一电接触结构104的材料可以为金属，例如可以为钨。In some embodiments, the material of the first electrical contact structure 104 may be metal, such as tungsten.

在一些实施例中，多个沟槽13环形排布。环形排布指的是，多个沟槽13环绕一个预设点间隔排布。预设点可以位于处于最内侧的第一电接触结构104所围成的环形内。在一些实施例中，沟槽13的数量可以为3个，每一沟槽13中填充有沟槽电容器101，沟槽电容器101的数量为3个，第一电接触结构104将3个沟槽电容器101进行并联。如此，一方面使得沟槽电容器101的数量不至于过多，使得相邻的沟槽电容器101的间隔距离较大，减小相邻的沟槽电容器101的极板102之间发生电接触而导致短路的风险。另一方面，3个环形排布的沟槽13在工艺上较容易实现，有利于提高形成的半导体结构的良率。In some embodiments, a plurality of grooves 13 are arranged in a ring. The ring arrangement means that a plurality of grooves 13 are arranged at intervals around a preset point. The preset point may be located in a ring surrounded by the first electrical contact structure 104 at the innermost side. In some embodiments, the number of grooves 13 may be 3, each groove 13 is filled with a trench capacitor 101, the number of trench capacitors 101 is 3, and the first electrical contact structure 104 connects the 3 trench capacitors 101 in parallel. In this way, on the one hand, the number of trench capacitors 101 is not too large, so that the spacing distance between adjacent trench capacitors 101 is larger, reducing the risk of electrical contact between the plates 102 of adjacent trench capacitors 101 and causing short circuit. On the other hand, the 3 grooves 13 arranged in a ring are easier to implement in terms of process, which is conducive to improving the yield of the formed semiconductor structure.

在一些实施例中，沟槽13的数量也可以为2个。在一些实施例中，沟槽13的数量还可以为4个，在一些实施例中，沟槽13的数量又可以为5个，本申请实施例不对沟槽13的数量进行具体限定，可以根据不同的需求设置沟槽13的数量。In some embodiments, the number of grooves 13 may also be 2. In some embodiments, the number of grooves 13 may also be 4. In some embodiments, the number of grooves 13 may be 5. The embodiment of the present application does not specifically limit the number of grooves 13, and the number of grooves 13 may be set according to different requirements.

参考图1，在一些实施例中，每一极板102具有高于沟槽13开口且沿平行于第一面11的方向延伸的第一部分1，第n层极板102的第一部分1露出第n-1层极板102的第一部分1的部分顶面，第一电接触结构104与露出顶面的第一部分1电接触。第1层极板102的第一部分1与沟槽13相对两侧的第一面11正对，第n层极板102的第一部分1与第n-1层极板102的部分第一部分1正对。由于第一部分1高于沟槽13开口设置，使得第一部分1的尺寸不受沟槽13的深宽比的限制，进而可以为实际形成多个第一电接触结构104提供较大的空间，防止相邻的第一电接触结构104之间的距离过近而发生短路的问题。Referring to FIG. 1 , in some embodiments, each electrode plate 102 has a first portion 1 that is higher than the opening of the groove 13 and extends in a direction parallel to the first surface 11, the first portion 1 of the n-th electrode plate 102 exposes a portion of the top surface of the first portion 1 of the n-1-th electrode plate 102, and the first electrical contact structure 104 is in electrical contact with the first portion 1 that is exposed on the top surface. The first portion 1 of the first electrode plate 102 is directly opposite to the first surfaces 11 on opposite sides of the groove 13, and the first portion 1 of the n-th electrode plate 102 is directly opposite to a portion of the first portion 1 of the n-1-th electrode plate 102. Since the first portion 1 is arranged higher than the opening of the groove 13, the size of the first portion 1 is not limited by the aspect ratio of the groove 13, thereby providing a larger space for actually forming a plurality of first electrical contact structures 104, thereby preventing the problem of short circuits caused by the distance between adjacent first electrical contact structures 104 being too close.

在一些实施例中，第一电接触结构104也可以与位于沟槽13中的极板102电接触。在一些实施例中，每一极板102具有与沟槽13侧壁正对的第二部分，第n层极板102的第二部分露出第n-1层极板102的第二部分的部分表面，第一电接触结构104与露出表面的第一部分1电接触。In some embodiments, the first electrical contact structure 104 may also be in electrical contact with the electrode plate 102 located in the groove 13. In some embodiments, each electrode plate 102 has a second portion directly opposite to the sidewall of the groove 13, the second portion of the n-th electrode plate 102 exposes a portion of the surface of the second portion of the n-1-th electrode plate 102, and the first electrical contact structure 104 is in electrical contact with the first portion 1 of the exposed surface.

参考图3，在一些实施例中，多个间隔排布的沟槽电容器101以及与沟槽电容器101的极板102电接触的第一电接触结构104组成一电容器单元20，衬底100中具有多个间隔排布的电容器单元20，相邻的两个电容器单元20中，与第n层极板102电接触的两个第一电接触结构104彼此电连接。Referring to Figure 3, in some embodiments, a plurality of spaced-apart trench capacitors 101 and a first electrical contact structure 104 electrically in contact with a plate 102 of the trench capacitor 101 form a capacitor unit 20, a substrate 100 having a plurality of spaced-apart capacitor units 20, and in two adjacent capacitor units 20, two first electrical contact structures 104 electrically in contact with an n-th layer of plate 102 are electrically connected to each other.

也就是说，每一电容器单元20包括：多个间隔排布的沟槽电容器101，以及与多个沟槽电容器101中处于相同层的极板102电接触的N个第一电接触结构104。在一些实施例中，每一电容器单元20中的多个沟槽电容器101环形排布。That is, each capacitor unit 20 includes: a plurality of trench capacitors 101 arranged at intervals, and N first electrical contact structures 104 electrically contacting the plates 102 in the same layer of the plurality of trench capacitors 101. In some embodiments, the plurality of trench capacitors 101 in each capacitor unit 20 are arranged in a ring.

每一电容器单元20中的多个沟槽电容器101通过第一电接触结构104并联，以使每一电容器单元20形成一个电容值较大的电容群组。不难发现，一个电容器单元20中，每一第一电接触结构104均与多个沟槽电容器101中处于相同层的极板102电接触，例如，其中一个第一电接触结构104与多个沟槽电容器101中处于第n-1层的极板102电接触，另一第一电接触结构104与多个沟槽电容器101中处于第n层的极板102电接触。基于此，设置相邻的两个电容器单元20中，与第n层极板102电接触的两个第一电接触结构104彼此电连接，也就是说，两个电容器单元20中，均与多个沟槽电容器101中的第n-1层极板102电接触的两个第一电接触结构104电连接，均与沟槽电容器101中的第n层极板102电接触的两个第一电接触结构104电连接，从而将相邻的两个电容器单元20所构成的两个电容群组并联，进一步增大电容值。The multiple trench capacitors 101 in each capacitor unit 20 are connected in parallel through the first electrical contact structure 104, so that each capacitor unit 20 forms a capacitor group with a larger capacitance value. It is not difficult to find that in a capacitor unit 20, each first electrical contact structure 104 is electrically in contact with the plates 102 in the same layer of the multiple trench capacitors 101, for example, one of the first electrical contact structures 104 is electrically in contact with the plates 102 in the n-1th layer of the multiple trench capacitors 101, and another first electrical contact structure 104 is electrically in contact with the plates 102 in the nth layer of the multiple trench capacitors 101. Based on this, in two adjacent capacitor units 20, the two first electrical contact structures 104 electrically in contact with the n-th layer of plate 102 are electrically connected to each other. That is to say, in the two capacitor units 20, the two first electrical contact structures 104 electrically in contact with the n-1-th layer of plate 102 in the plurality of trench capacitors 101 are electrically connected, and the two first electrical contact structures 104 electrically in contact with the n-th layer of plate 102 in the trench capacitor 101 are electrically connected, thereby connecting the two capacitor groups formed by the two adjacent capacitor units 20 in parallel to further increase the capacitance value.

为更好地体现相邻两个电容器单元20之间的电连接关系，以下以一个具体的例子为例进行说明。在一些实施例中，每一电容器单元20中的第一电接触结构104的数量为3个，记为第一个第一电接触结构104、第二个第一电接触结构104以及第三个第一电接触结构104，每一沟槽电容器101的极板102数量为3，其中，第一个第一电接触结构104与多个沟槽电容器101中的第1层极板102电接触，第二个第一电接触结构104与多个沟槽电容器101中的第2层极板102电接触，第三个第一电接触结构104与多个沟槽电容器101中的第3层极板102电接触。相邻的两个电容器单元20中的第一个第一电接触结构104彼此电连接，相邻的两个电容器单元20中的第二个第二电接触结构彼此电连接，相邻的两个电容器单元20中的第三个第一电接触结构104彼此电连接。In order to better reflect the electrical connection relationship between two adjacent capacitor units 20, a specific example is used for explanation below. In some embodiments, the number of first electrical contact structures 104 in each capacitor unit 20 is 3, which are recorded as the first first electrical contact structure 104, the second first electrical contact structure 104 and the third first electrical contact structure 104, and the number of plates 102 in each trench capacitor 101 is 3, wherein the first first electrical contact structure 104 is in electrical contact with the first layer of plates 102 in multiple trench capacitors 101, the second first electrical contact structure 104 is in electrical contact with the second layer of plates 102 in multiple trench capacitors 101, and the third first electrical contact structure 104 is in electrical contact with the third layer of plates 102 in multiple trench capacitors 101. The first first electrical contact structures 104 in two adjacent capacitor units 20 are electrically connected to each other, the second second electrical contact structures in two adjacent capacitor units 20 are electrically connected to each other, and the third first electrical contact structures 104 in two adjacent capacitor units 20 are electrically connected to each other.

值得注意的是，图3中仅以电容器单元20为2个示出，实际上，电容器单元20的数量可以为3个、4个或者4个以上。本申请实施例不对电容器单元20的具体数量进行限定，仅需满足相邻的电容器单元20中，与第n层极板102电接触的两个第一电接触结构104彼此电连接即可。It is worth noting that only two capacitor units 20 are shown in FIG3 , but in fact, the number of capacitor units 20 may be 3, 4, or more than 4. The embodiment of the present application does not limit the specific number of capacitor units 20, and it is only required that the two first electrical contact structures 104 in adjacent capacitor units 20 that are in electrical contact with the n-th layer of plate 102 are electrically connected to each other.

参考图2以及图3，在一些实施例中，还包括：多个金属层107，金属层107位于第一电接触结构104远离沟槽电容器101的一侧，金属层107用于电连接相邻的两个电容器单元20中，与第n层极板102电接触的两个第一电接触结构104；多个第二电接触结构106，每一第二电接触结构106位于一第一电接触结构104远离沟槽电容器101的一侧，与第一电接触结构104电接触，用于电连接金属层107与第一电接触结构104。Referring to Figures 2 and 3, in some embodiments, it also includes: multiple metal layers 107, the metal layer 107 is located on the side of the first electrical contact structure 104 away from the trench capacitor 101, and the metal layer 107 is used to electrically connect two first electrical contact structures 104 in two adjacent capacitor units 20 that are electrically in contact with the n-th layer plate 102; multiple second electrical contact structures 106, each second electrical contact structure 106 is located on the side of a first electrical contact structure 104 away from the trench capacitor 101, and is electrically in contact with the first electrical contact structure 104, and is used to electrically connect the metal layer 107 and the first electrical contact structure 104.

可以理解的是，由于半导体结构的尺寸较小，且半导体结构中，处了沟槽电容器101之外，还具有非常多的其它结构，为了防止金属层107的走线对其它结构产生干扰，需要对金属层107进行走线设计。为了实现金属层107与第一电接触结构104之间的电连接，还设置第二电接触结构106，作为金属层107与第一电接触结构104之间的电连接结构，如此，若金属层107的走线由于受到半导体结构中其它结构的影响而不能直接与第一电接触结构104电连接，则可以通过第二电接触结构106实现第一电接触结构104与金属层107的电连接。It is understandable that, since the size of the semiconductor structure is relatively small and there are many other structures in the semiconductor structure besides the trench capacitor 101, in order to prevent the routing of the metal layer 107 from interfering with other structures, it is necessary to design the routing of the metal layer 107. In order to achieve the electrical connection between the metal layer 107 and the first electrical contact structure 104, a second electrical contact structure 106 is also provided as an electrical connection structure between the metal layer 107 and the first electrical contact structure 104. In this way, if the routing of the metal layer 107 cannot be directly electrically connected to the first electrical contact structure 104 due to the influence of other structures in the semiconductor structure, the electrical connection between the first electrical contact structure 104 and the metal layer 107 can be achieved through the second electrical contact structure 106.

在一些实施例中，第二电接触结构106可以包括沿远离第一面11方向依次堆叠的第一层31以及第二层32，其中，第一层31在第一面11上的正投影位于第二层32在第一面11上的正投影内。也就是说，第一层31与第一电接触结构104直接电接触，第二层32与金属层107直接电接触。设置第二层32的尺寸大于第一层31的尺寸，使得在实际制备第二电接触结构106的工艺中，第二层32与第一层31的对准精度更高，保证第二层32与第一层31之间的接触面积较大，减小第二层32与第一层31的接触电阻，有利于提高第二接触结构整体的电传输性能。在一些实施例中，第一层31与第二层32的材料可以相同。In some embodiments, the second electrical contact structure 106 may include a first layer 31 and a second layer 32 stacked in sequence in a direction away from the first surface 11, wherein the orthographic projection of the first layer 31 on the first surface 11 is located within the orthographic projection of the second layer 32 on the first surface 11. That is, the first layer 31 is in direct electrical contact with the first electrical contact structure 104, and the second layer 32 is in direct electrical contact with the metal layer 107. The size of the second layer 32 is set to be larger than the size of the first layer 31, so that in the actual process of preparing the second electrical contact structure 106, the alignment accuracy of the second layer 32 and the first layer 31 is higher, the contact area between the second layer 32 and the first layer 31 is ensured to be larger, the contact resistance between the second layer 32 and the first layer 31 is reduced, and it is beneficial to improve the overall electrical transmission performance of the second contact structure. In some embodiments, the materials of the first layer 31 and the second layer 32 may be the same.

在一些实施例中，第二电接触结构106的材料可以为金属，例如可以为铜、钨或者镍中的至少一者。In some embodiments, the material of the second electrical contact structure 106 may be metal, for example, at least one of copper, tungsten or nickel.

在一些实施例中，金属层107的材料可以包括铜、钨或者镍中的至少一者。参考图2以及图3，在一些实施例中，半导体结构还包括：第一隔离结构109以及第二隔离结构110，其中，第一隔离结构109覆盖多个深沟槽电容器101，其中，第一隔离结构109可以覆盖每一沟槽电容器101中第n层极板102顶面，且第一隔离结构109将每一第一电接触结构104包覆在内，用于隔离相邻的第一电接触结构104。在一些实施例中，第一隔离结构109的材料可以为氧化硅等绝缘材料。In some embodiments, the material of the metal layer 107 may include at least one of copper, tungsten or nickel. Referring to FIG. 2 and FIG. 3, in some embodiments, the semiconductor structure further includes: a first isolation structure 109 and a second isolation structure 110, wherein the first isolation structure 109 covers a plurality of deep trench capacitors 101, wherein the first isolation structure 109 may cover the top surface of the n-th layer of the plate 102 in each trench capacitor 101, and the first isolation structure 109 encloses each first electrical contact structure 104 to isolate adjacent first electrical contact structures 104. In some embodiments, the material of the first isolation structure 109 may be an insulating material such as silicon oxide.

第二隔离结构110位于第一隔离结构109远离衬底100一侧，覆盖第一隔离结构109顶面，且第二隔离结构110将第二电接触结构106包覆在内，用于隔绝第二电接触结构106。在一些实施例中，第二隔离结构110还露出第二电接触结构106远离第一面11的一侧表面。The second isolation structure 110 is located on a side of the first isolation structure 109 away from the substrate 100, covering the top surface of the first isolation structure 109, and the second isolation structure 110 encloses the second electrical contact structure 106 to isolate the second electrical contact structure 106. In some embodiments, the second isolation structure 110 also exposes a side surface of the second electrical contact structure 106 away from the first surface 11.

在一些实施例中，第二隔离结构110的材料可以包括氧化硅等绝缘材料。In some embodiments, the material of the second isolation structure 110 may include insulating materials such as silicon oxide.

参考图1以及图2，在一些实施例中，半导体结构还包括：与衬底100堆叠设置的硅中介层111，硅中介层111包括相对的第三面以及第四面，硅中介层111中具有多个第一电连接结构112，每一第一电连接结构112由第三面向第四面延伸，且第四面露出第一电连接结构112底部，衬底100的第一面11与硅中介层111的第四面键合，以使一第一电连接结构112底部与一第一电接触结构104电连接。硅中介层111用于起到电传输作用，例如，在一些实施例中，硅中介层111可以用于电连接芯片与基板，实现芯片与基板之间的信号传输。在一些实施例中，基板可以是PCB(Printed Circuit Board，印刷电路板)。Referring to FIG. 1 and FIG. 2 , in some embodiments, the semiconductor structure further includes: a silicon interposer 111 stacked with the substrate 100, the silicon interposer 111 includes a third surface and a fourth surface opposite to each other, the silicon interposer 111 has a plurality of first electrical connection structures 112, each of the first electrical connection structures 112 extends from the third surface to the fourth surface, and the fourth surface exposes the bottom of the first electrical connection structure 112, and the first surface 11 of the substrate 100 is bonded to the fourth surface of the silicon interposer 111, so that the bottom of a first electrical connection structure 112 is electrically connected to a first electrical contact structure 104. The silicon interposer 111 is used to perform an electrical transmission function. For example, in some embodiments, the silicon interposer 111 can be used to electrically connect the chip and the substrate to realize signal transmission between the chip and the substrate. In some embodiments, the substrate can be a PCB (Printed Circuit Board).

在一些实施例中，硅中介层111的材料可以包括硅。在一些实施例中，硅中介层111的材料也可以为锗、锗硅或者绝缘体上的硅。In some embodiments, the material of the silicon interposer 111 may include silicon. In some embodiments, the material of the silicon interposer 111 may also be germanium, germanium silicon, or silicon on insulator.

也就是说，本申请实施例中，沟槽电容器101不形成于硅中介层111中，而是分别形成沟槽电容器101与硅中介层111，再将硅中介层111以及衬底100键合，实现第一电连接结构112与第一电接触结构104的电连接。如此，沟槽电容器101可以通过硅中介层111实现与外部的信号传输，例如可以通过硅中介层111连接至外部电源，进而对外部电源进行去耦。That is to say, in the embodiment of the present application, the trench capacitor 101 is not formed in the silicon interposer 111, but the trench capacitor 101 and the silicon interposer 111 are formed separately, and then the silicon interposer 111 and the substrate 100 are bonded to realize the electrical connection between the first electrical connection structure 112 and the first electrical contact structure 104. In this way, the trench capacitor 101 can realize signal transmission with the outside through the silicon interposer 111, for example, it can be connected to an external power supply through the silicon interposer 111, thereby decoupling the external power supply.

由于沟槽电容器101与硅中介层111不位于同一衬底100中，使得衬底100中可以有较大的空间来用于形成沟槽电容器101，进而能够增加沟槽电容器101的数量，进一步提高电容值。Since the trench capacitors 101 and the silicon interposer 111 are not located in the same substrate 100 , there is a larger space in the substrate 100 for forming the trench capacitors 101 , thereby increasing the number of trench capacitors 101 and further improving the capacitance value.

在一些实施例中，第一电连接结构112可以贯穿硅中介层111，即第三面露出第一电连接结构112的顶部，使得第一电连接结构112易于与其它用于实现电信号传输的电连接结构连接。在一些实施例中，第一电连接结构112可以是TSV(Through Silicon Via，硅通孔)。In some embodiments, the first electrical connection structure 112 can penetrate the silicon interposer 111, that is, the top of the first electrical connection structure 112 is exposed on the third surface, so that the first electrical connection structure 112 can be easily connected to other electrical connection structures for realizing electrical signal transmission. In some embodiments, the first electrical connection structure 112 can be a TSV (Through Silicon Via).

在一些实施例中，第一电连接结构112可以包括导电主体部36以及覆盖于导电主体部36外表面的阻挡层37，其中，导电主体部36用于起到导电作用，阻挡层37可以防止导电主体部36与硅中介层111之间发生离子扩散的问题。在一些实施例中，导电主体部36的材料可以是金属，例如可以是铜。在一些实施例中，阻挡层37的材料可以是氮化钛。In some embodiments, the first electrical connection structure 112 may include a conductive body portion 36 and a barrier layer 37 covering the outer surface of the conductive body portion 36, wherein the conductive body portion 36 is used to conduct electricity, and the barrier layer 37 can prevent the problem of ion diffusion between the conductive body portion 36 and the silicon interposer 111. In some embodiments, the material of the conductive body portion 36 may be metal, such as copper. In some embodiments, the material of the barrier layer 37 may be titanium nitride.

在一些实施例中，半导体结构还包括：第一介质层113，位于第一面11上，第一介质层113位于第一电接触结构104远离第一面11的一侧；第二电连接结构114，位于第一介质层113中，且第二电连接结构114位于第一电接触结构104远离第一面11的一侧，第一介质层113露出第二电连接结构114顶部，第二电连接结构114的顶部与第一电连接结构112电接触，底部与第一电接触结构104电接触。In some embodiments, the semiconductor structure further includes: a first dielectric layer 113, located on the first surface 11, and the first dielectric layer 113 is located on a side of the first electrical contact structure 104 away from the first surface 11; a second electrical connection structure 114, located in the first dielectric layer 113, and the second electrical connection structure 114 is located on a side of the first electrical contact structure 104 away from the first surface 11, the first dielectric layer 113 exposes the top of the second electrical connection structure 114, the top of the second electrical connection structure 114 is electrically in contact with the first electrical connection structure 112, and the bottom is electrically in contact with the first electrical contact structure 104.

在一些实施例中，半导体结构还包括第二隔离结构110，第二隔离结构110覆盖第一电接触结构104顶面，则第一介质层113可以位于第二隔离结构110顶面，第二电连接结构114贯穿第一介质层113以及第二隔离结构110，第二隔离结构110露出第二电连接结构114底面，第二电连接结构114底面与第一电接触结构104电接触。In some embodiments, the semiconductor structure also includes a second isolation structure 110, and the second isolation structure 110 covers the top surface of the first electrical contact structure 104. The first dielectric layer 113 can be located on the top surface of the second isolation structure 110, and the second electrical connection structure 114 penetrates the first dielectric layer 113 and the second isolation structure 110. The second isolation structure 110 exposes the bottom surface of the second electrical connection structure 114, and the bottom surface of the second electrical connection structure 114 is electrically contacted with the first electrical contact structure 104.

第一介质层113起到重布线的作用，实现第一电接触结构104与第一电连接结构112的电连接。The first dielectric layer 113 plays a role of rewiring to achieve electrical connection between the first electrical contact structure 104 and the first electrical connection structure 112 .

在一些实施例中，第一介质层113的材料可以是碳氮化硅、氧化硅或者氮化硅中的至少一者。In some embodiments, the material of the first dielectric layer 113 may be at least one of silicon carbonitride, silicon oxide, or silicon nitride.

在一些实施例中，第二电连接结构114可以包括沿远离第一面11方向依次堆叠的第一部33、第二部34以及第三部35，其中，第一部33在第一面11上的正投影位于第二部34在第一面11上的正投影内，第三部35在第一面11上的正投影位于第二部34在第一面11上的正投影内。也就是说，第二部34的尺寸大于第一部33的尺寸，且大于第三部35的尺寸，第一部33与第一电接触结构104直接电接触，第三部35与第一电连接结构112直接电接触。设置第二部34位于第一部33与第三部35之间，使得在实际制备第二电连接结构114的工艺中，第二部34与第一部33的对准精度更高，使得第二部34与第一部33之间的接触面积较大，减小第二部34与第一部33的接触电阻，且第三部35与第二部34的对准精度更高，使第三部35与第二部34之间的接触面积较大，减小第三部35与第二部34之间的接触面积，从而使得第一部33与第三部35之间具有较好的电传输性能，有利于提高第二电连接结构114整体的电传输性能。在一些实施例中，第一部33、第二部34与第三部35的材料可以相同。In some embodiments, the second electrical connection structure 114 may include a first portion 33, a second portion 34, and a third portion 35 stacked in sequence in a direction away from the first surface 11, wherein the orthographic projection of the first portion 33 on the first surface 11 is located within the orthographic projection of the second portion 34 on the first surface 11, and the orthographic projection of the third portion 35 on the first surface 11 is located within the orthographic projection of the second portion 34 on the first surface 11. That is, the size of the second portion 34 is larger than the size of the first portion 33, and larger than the size of the third portion 35, the first portion 33 is in direct electrical contact with the first electrical contact structure 104, and the third portion 35 is in direct electrical contact with the first electrical connection structure 112. The second portion 34 is arranged between the first portion 33 and the third portion 35, so that in the actual process of preparing the second electrical connection structure 114, the alignment accuracy of the second portion 34 and the first portion 33 is higher, so that the contact area between the second portion 34 and the first portion 33 is larger, and the contact resistance between the second portion 34 and the first portion 33 is reduced, and the alignment accuracy of the third portion 35 and the second portion 34 is higher, so that the contact area between the third portion 35 and the second portion 34 is larger, and the contact area between the third portion 35 and the second portion 34 is reduced, so that the first portion 33 and the third portion 35 have better electrical transmission performance, which is conducive to improving the overall electrical transmission performance of the second electrical connection structure 114. In some embodiments, the materials of the first portion 33, the second portion 34 and the third portion 35 can be the same.

在一些实施例中，若第二电连接结构114贯穿第一介质层113与第二隔离结构110，则第二电连接结构114中的第一部33可以位于第二隔离结构110中，第二电连接结构114中能够的第二部34以及第三部35可以位于第一介质层113中。或者，第二电连接结构114中的第一部33与第二部34位于第二隔离结构110中，第三部35位于第一介质层113中。In some embodiments, if the second electrical connection structure 114 penetrates the first dielectric layer 113 and the second isolation structure 110, the first portion 33 in the second electrical connection structure 114 may be located in the second isolation structure 110, and the second portion 34 and the third portion 35 in the second electrical connection structure 114 may be located in the first dielectric layer 113. Alternatively, the first portion 33 and the second portion 34 in the second electrical connection structure 114 are located in the second isolation structure 110, and the third portion 35 is located in the first dielectric layer 113.

不难发现，第二电接触结构106与第二电连接结构114均与第一电接触结构104直接电接触，为了防止第二电接触结构106与第二电连接结构114之间发生电接触而导致短路的问题，第二电接触结构106与第二电连接结构114间隔设置。It is not difficult to find that the second electrical contact structure 106 and the second electrical connection structure 114 are both in direct electrical contact with the first electrical contact structure 104. In order to prevent the second electrical contact structure 106 and the second electrical connection structure 114 from electrical contacting each other and causing a short circuit, the second electrical contact structure 106 and the second electrical connection structure 114 are spaced apart.

在一些实施例中，第二电连接结构114的材料可以为金属，例如可以为铜、钨或者镍中的至少一者。In some embodiments, the material of the second electrical connection structure 114 may be metal, for example, at least one of copper, tungsten or nickel.

在一些实施例中，衬底100中具有多个间隔排布的电容器单元20，相邻的两个电容器单元20中，与第n层极板102电接触的两个第一电接触结构104彼此电连接。则第二电连接结构114还可以用于电连接相邻的两个电容器单元20中，与第n层极板102电接触的两个第一电接触结构104。即第二电连接结构114还可以起到后端绕线的作用，如此，可以无需在半导体结构中设置金属层107以及第二电接触结构106来电连接相邻的两个电容器单元20中与第n层极板102电接触的两个第一电接触结构104，从而可以为在衬底中形成更多的沟槽电容器101提供较多的空间，有利于进一步增大电容值。In some embodiments, the substrate 100 has a plurality of capacitor units 20 arranged at intervals, and in two adjacent capacitor units 20, the two first electrical contact structures 104 electrically in contact with the n-th layer of plate 102 are electrically connected to each other. Then the second electrical connection structure 114 can also be used to electrically connect the two first electrical contact structures 104 electrically in contact with the n-th layer of plate 102 in the two adjacent capacitor units 20. That is, the second electrical connection structure 114 can also play the role of back-end winding, so that it is not necessary to set the metal layer 107 and the second electrical contact structure 106 in the semiconductor structure to electrically connect the two first electrical contact structures 104 electrically in contact with the n-th layer of plate 102 in the two adjacent capacitor units 20, thereby providing more space for forming more trench capacitors 101 in the substrate, which is conducive to further increasing the capacitance value.

在一些实施例中，为了实现硅中介层111与其它元件的电连接，例如，为了实现硅中介层111与芯片的电连接，还可以在硅中介层111的第三面设置第二介质层116，第二介质层116中具有第三电连接结构115，第二介质层116露出第三电连接结构115顶面以及底面，第三电连接结构115底面与第一电连接结构112顶面电接触。在一些实施例中，第二介质层116的材料可以是碳氮化硅、氧化硅或者氮化硅中的至少一者。In some embodiments, in order to realize electrical connection between the silicon interposer 111 and other components, for example, in order to realize electrical connection between the silicon interposer 111 and the chip, a second dielectric layer 116 may be further provided on the third surface of the silicon interposer 111, and the second dielectric layer 116 has a third electrical connection structure 115, and the second dielectric layer 116 exposes the top and bottom surfaces of the third electrical connection structure 115, and the bottom surface of the third electrical connection structure 115 is in electrical contact with the top surface of the first electrical connection structure 112. In some embodiments, the material of the second dielectric layer 116 may be at least one of silicon carbonitride, silicon oxide, or silicon nitride.

在一些实施例中，第三电连接结构115可以包括：沿第四面指向第三面方向依次堆叠设置的第一子电连接结构38、第二子电连接结构39、第三子电连接结构40、第四子电连接结构41以及第五子电连接结构42，其中，第一子电连接结构38底部与第一电连接结构112顶部电接触。第一子电连接结构38以及第三子电连接结构40在第三面上的正投影位于第二子电连接结构39在第三面上的正投影内，且第一子电连接结构38以及第三子电连接结构40在第三面上的正投影位于第四子电连接结构41在第三面上的正投影内。也就是说，第一子电连接结构38的横截面面积以及第三子电连接结构40的横截面面积均小于第二子电连接结构39的横截面面积，第三子电连接结构40的横截面面积小于第四子电连接结构41的横截面面积，如此，有利于实现第一子电连接结构38、第二子电连接结构39、第三子电连接结构40、第四子电连接结构41的精确对准。In some embodiments, the third electrical connection structure 115 may include: a first sub-electrical connection structure 38, a second sub-electrical connection structure 39, a third sub-electrical connection structure 40, a fourth sub-electrical connection structure 41, and a fifth sub-electrical connection structure 42 stacked in sequence along the fourth surface pointing to the third surface, wherein the bottom of the first sub-electrical connection structure 38 is in electrical contact with the top of the first electrical connection structure 112. The orthographic projections of the first sub-electrical connection structure 38 and the third sub-electrical connection structure 40 on the third surface are located within the orthographic projection of the second sub-electrical connection structure 39 on the third surface, and the orthographic projections of the first sub-electrical connection structure 38 and the third sub-electrical connection structure 40 on the third surface are located within the orthographic projection of the fourth sub-electrical connection structure 41 on the third surface. That is to say, the cross-sectional area of the first sub-electrical connection structure 38 and the cross-sectional area of the third sub-electrical connection structure 40 are both smaller than the cross-sectional area of the second sub-electrical connection structure 39, and the cross-sectional area of the third sub-electrical connection structure 40 is smaller than the cross-sectional area of the fourth sub-electrical connection structure 41. This is conducive to achieving precise alignment of the first sub-electrical connection structure 38, the second sub-electrical connection structure 39, the third sub-electrical connection structure 40, and the fourth sub-electrical connection structure 41.

在一些实施例中，半导体结构还包括：第一刻蚀阻挡层43、第二刻蚀阻挡层44以及第三刻蚀阻挡层45，第一刻蚀阻挡层43内嵌于第二介质层116内，环绕第二子电连接结构39底部设置，防止在形成第二子电连接结构39的工艺中发生过刻蚀问题，控制第二子电连接结构39的深度。第二刻蚀阻挡层44内嵌于第二介质层116内，环绕第三子电连接结构40底部设置，防止在形成第三子电连接结构40的工艺中发生过刻蚀问题，控制第三子电连接结构40的深度。第三刻蚀阻挡层45内嵌于第二介质层116内，环绕第五子电连接结构42底部设置，防止在形成第五子电连接结构42的工艺中发生过刻蚀问题，控制第五子电连接结构42的深度。In some embodiments, the semiconductor structure further includes: a first etch stop layer 43, a second etch stop layer 44, and a third etch stop layer 45, wherein the first etch stop layer 43 is embedded in the second dielectric layer 116, and is disposed around the bottom of the second sub-electrical connection structure 39, so as to prevent over-etching during the process of forming the second sub-electrical connection structure 39 and control the depth of the second sub-electrical connection structure 39. The second etch stop layer 44 is embedded in the second dielectric layer 116, and is disposed around the bottom of the third sub-electrical connection structure 40, so as to prevent over-etching during the process of forming the third sub-electrical connection structure 40 and control the depth of the third sub-electrical connection structure 40. The third etch stop layer 45 is embedded in the second dielectric layer 116, and is disposed around the bottom of the fifth sub-electrical connection structure 42, so as to prevent over-etching during the process of forming the fifth sub-electrical connection structure 42 and control the depth of the fifth sub-electrical connection structure 42.

在一些实施例中，第一子电连接结构38、第二子电连接结构39、第三子电连接结构40以及第四子电连接结构41的材料可以相同，例如可以为铜。In some embodiments, the first sub-electrical connection structure 38 , the second sub-electrical connection structure 39 , the third sub-electrical connection structure 40 , and the fourth sub-electrical connection structure 41 may be made of the same material, such as copper.

第二介质层116露出第五子电连接结构42的顶面，第五子电连接结构42用于与外部元件电连接。在一些实施例中，可以通过焊接工艺实现第五子电连接结构42与外部元件的电连接。在一些实施例中，第五子电连接结构42的材料可以为铝。The second dielectric layer 116 exposes the top surface of the fifth sub-electrical connection structure 42, and the fifth sub-electrical connection structure 42 is used to be electrically connected to an external element. In some embodiments, the electrical connection between the fifth sub-electrical connection structure 42 and the external element can be achieved by a welding process. In some embodiments, the material of the fifth sub-electrical connection structure 42 can be aluminum.

在一些实施例中，第五子电连接结构42远离第四子电连接结构41的一端凸出于第三面，还可以包括：绝缘层117、阻挡部118以及保护层119，其中，绝缘层117位于凸出于第三面的第五子电连接结构42的外侧壁，阻挡部118位于绝缘层117远离第五子电连接结构42的一侧，且绝缘层117还覆盖第三面。保护层119位于绝缘层117远离第五子电连接结构42的一侧。在一些实施例中，绝缘层117的材料可以是氧化硅。在一些实施例中，阻挡部118的材料可以是氮化硅。在一些实施例中，保护层119的材料可以是聚酰亚胺，用于对第二介质层116起到保护作用。In some embodiments, the end of the fifth sub-electrical connection structure 42 away from the fourth sub-electrical connection structure 41 protrudes from the third surface, and may further include: an insulating layer 117, a blocking portion 118, and a protective layer 119, wherein the insulating layer 117 is located on the outer side wall of the fifth sub-electrical connection structure 42 protruding from the third surface, the blocking portion 118 is located on the side of the insulating layer 117 away from the fifth sub-electrical connection structure 42, and the insulating layer 117 also covers the third surface. The protective layer 119 is located on the side of the insulating layer 117 away from the fifth sub-electrical connection structure 42. In some embodiments, the material of the insulating layer 117 may be silicon oxide. In some embodiments, the material of the blocking portion 118 may be silicon nitride. In some embodiments, the material of the protective layer 119 may be polyimide, which is used to protect the second dielectric layer 116.

上述实施例提供的半导体结构中，每一沟槽电容器101的极板102数量与第一电接触结构104的数量相同，以分别实现每一极板102与外部电源之间的信号传输。衬底100多个沟槽电容器101中处于相同层的极板102均和同一第一电接触结构104电接触，从而将不同的深沟槽电容器101并联，增大电容值。还设置衬底100上的第一电接触结构104在衬底100第一面11的正投影为环形，使得不同的第一电接触结构104之间为嵌套式排布，如此，一方面可以大大节省第一电接触结构104所占用的空间，从而有多余的空间来设置更多的沟槽电容器101，进一步增大电容值。另一方面，还能减小相邻的第一电接触结构104之间发生短路的风险。In the semiconductor structure provided by the above embodiment, the number of plates 102 of each trench capacitor 101 is the same as the number of first electrical contact structures 104, so as to respectively realize signal transmission between each plate 102 and an external power source. The plates 102 in the same layer of multiple trench capacitors 101 on the substrate 100 are all in electrical contact with the same first electrical contact structure 104, so that different deep trench capacitors 101 are connected in parallel to increase the capacitance value. The first electrical contact structure 104 on the substrate 100 is also set to be a ring in the positive projection of the first surface 11 of the substrate 100, so that different first electrical contact structures 104 are nested. In this way, on the one hand, the space occupied by the first electrical contact structure 104 can be greatly saved, so that there is extra space to set more trench capacitors 101, further increasing the capacitance value. On the other hand, the risk of short circuit between adjacent first electrical contact structures 104 can also be reduced.

相应地，本公开实施例还提供一种半导体结构的制备方法，该半导体结构的制备方法可用于制备上述实施例提供的半导体结构，以下将结合附图对本公开一实施例提供的半导体结构进行详细说明。Correspondingly, an embodiment of the present disclosure also provides a method for preparing a semiconductor structure, which can be used to prepare the semiconductor structure provided by the above embodiment. The semiconductor structure provided by an embodiment of the present disclosure will be described in detail below in conjunction with the accompanying drawings.

半导体结构的制备方法包括：The method for preparing a semiconductor structure comprises:

参考图4，提供衬底100，衬底100具有相对的第一面11和第二面12。4 , a substrate 100 is provided. The substrate 100 has a first surface 11 and a second surface 12 that are opposite to each other.

在一些实施例中，衬底100的材料为半导体材料，在一些实施例中，衬底100的材料为硅。在一些实施例中，衬底100也可以为锗、锗硅或者绝缘体上的硅。In some embodiments, the material of the substrate 100 is a semiconductor material, and in some embodiments, the material of the substrate 100 is silicon. In some embodiments, the substrate 100 may also be germanium, germanium silicon, or silicon on insulator.

参考图5，在衬底100内形成多个间隔排布的沟槽13，每一沟槽13自第一面11向第二面12延伸。5 , a plurality of trenches 13 arranged at intervals are formed in the substrate 100 , and each trench 13 extends from the first surface 11 to the second surface 12 .

在一些实施例中，可以首先对衬底100进行图案化工艺，用于定义沟槽13的开口，再对图案化的衬底100进行刻蚀，以形成沟槽13。在一些实施例中，可以采用干法刻蚀工艺或者湿法刻蚀工艺中的任一者形成沟槽13。在一些实施例中，对衬底100的图案化工艺可以包括自对准双重成像技术(Self-aligned Double Patterning，SADP)或者自对准四重图形工艺(self-aligned Quardruple Patterning，SAQP)中的任一者。In some embodiments, the substrate 100 may be first subjected to a patterning process to define the opening of the groove 13, and then the patterned substrate 100 may be etched to form the groove 13. In some embodiments, the groove 13 may be formed by either a dry etching process or a wet etching process. In some embodiments, the patterning process of the substrate 100 may include either a self-aligned double patterning technology (SADP) or a self-aligned quadruple patterning process (SAQP).

参考图6，在每一沟槽13内形成沟槽电容器101，沟槽电容器101包括：N层极板102，相邻极板102之间具有电介质层103，N＞1，其中，第n层极板102位于第n-1层极板102远离沟槽13侧壁的一侧，第n层极板102与第n-1层极板102正对，1＜n≤N。在一些实施例中，N可以为3。也就是说，每一沟槽电容器101中的极板102的数量为3个，则第1层极板102与第2层极板102构成一个电容器，第3层极板102与第2层极板102构成一个电容器，以形成三面电容器。Referring to FIG6 , a trench capacitor 101 is formed in each trench 13, and the trench capacitor 101 includes: N layers of plates 102, and a dielectric layer 103 is provided between adjacent plates 102, N>1, wherein the nth layer of plate 102 is located on the side of the n-1th layer of plate 102 away from the sidewall of the trench 13, the nth layer of plate 102 is directly opposite to the n-1th layer of plate 102, 1<n≤N. In some embodiments, N can be 3. That is, the number of plates 102 in each trench capacitor 101 is 3, then the first layer of plate 102 and the second layer of plate 102 form a capacitor, and the third layer of plate 102 and the second layer of plate 102 form a capacitor, so as to form a three-sided capacitor.

在一些实施例中，形成沟槽电容器101的方法包括：In some embodiments, a method of forming the trench capacitor 101 includes:

形成随形覆盖沟槽13的隔离层105，隔离层105还位于沟槽13两侧的衬底100第一面11。在一些实施例中，可以采用沉积工艺形成隔离层105，例如可以采用原子层沉积工艺或者化学气相沉积工艺中的任一者。在一些实施例中，隔离层105的材料可以为氧化硅。An isolation layer 105 is formed to conformally cover the trench 13, and the isolation layer 105 is also located on the first surface 11 of the substrate 100 on both sides of the trench 13. In some embodiments, the isolation layer 105 can be formed by a deposition process, for example, an atomic layer deposition process or a chemical vapor deposition process. In some embodiments, the material of the isolation layer 105 can be silicon oxide.

在隔离层105表面形成交替堆叠的极板102以及电介质层103，每一极板102具有高于沟槽13开口且沿平行于第一面11的方向延伸的第一部分1，第n层极板102的第一部分1露出第n-1层极板102的第一部分1的部分第一面11。Alternatingly stacked electrodes 102 and dielectric layers 103 are formed on the surface of the isolation layer 105. Each electrode 102 has a first portion 1 that is higher than the opening of the groove 13 and extends in a direction parallel to the first surface 11. The first portion 1 of the n-th electrode 102 exposes part of the first surface 11 of the first portion 1 of the n-1-th electrode 102.

在一些实施例中，形成交替堆叠的极板102以及电介质层103的方法可以包括：采用沉积工艺形成交替堆叠的初始极板(未图示)以及初始电介质层(未图示)，朝向第一面11的初始极板位于隔离层105顶面以及第一面11。其中，初始极板的数量为N层，第n层初始极板位于第n-1层初始极板远离第一面11的一侧，初始电介质层位于第n-1层初始极板与第n层初始极板之间。In some embodiments, the method of forming the alternately stacked plates 102 and the dielectric layer 103 may include: forming alternately stacked initial plates (not shown) and initial dielectric layers (not shown) by a deposition process, wherein the initial plates facing the first surface 11 are located on the top surface of the isolation layer 105 and the first surface 11. The number of initial plates is N, the nth initial plate is located on the side of the n-1th initial plate away from the first surface 11, and the initial dielectric layer is located between the n-1th initial plate and the nth initial plate.

接着，依次对第N层初始极板至第1层初始极板进行图案化工艺并刻蚀图案化的初始极板。Next, the Nth layer of initial electrode plates to the first layer of initial electrode plates are subjected to a patterning process in sequence, and the patterned initial electrode plates are etched.

在一些实施例中，首先对第N层初始极板进行图案化工艺，在对第n层初始极板进行图案化工艺的步骤中，还对位于第N层初始极板与第N-1层初始极板之间的初始电介质层进行图案化工艺。之后对图案化的第N层初始极板以及图案化的初始电介质层进行刻蚀，以露出位于第一面11上的第N-1层初始极板的部分顶面，形成第N层极板102。In some embodiments, the N-th layer initial plate is first patterned, and in the step of patterning the n-th layer initial plate, the initial dielectric layer between the N-th layer initial plate and the N-1-th layer initial plate is also patterned. Then, the patterned N-th layer initial plate and the patterned initial dielectric layer are etched to expose a portion of the top surface of the N-1-th layer initial plate on the first surface 11, thereby forming the N-th layer plate 102.

接着对第N-1层初始极板进行图案化工艺，在对第N-1层初始极板进行图案化工艺的步骤中，还对位于第N-1层初始极板与第N-2层初始极板之间的初始电介质层进行图案化工艺。之后对图案化的第N-1层初始极板以及图案化的初始电介质层进行刻蚀，以露出位于第一面11上的第N-2层初始极板的部分顶面，形成第N-1层极板102。依次类推，直至形成第1层极板102。Then, the N-1th layer initial plate is patterned. In the step of patterning the N-1th layer initial plate, the initial dielectric layer between the N-1th layer initial plate and the N-2th layer initial plate is also patterned. Then, the patterned N-1th layer initial plate and the patterned initial dielectric layer are etched to expose a portion of the top surface of the N-2th layer initial plate on the first surface 11, thereby forming the N-1th layer plate 102. The same process is repeated until the first layer plate 102 is formed.

在一些实施例中，电介质层103的材料可以为绝缘材料，例如氧化铝。在一些实施例中，极板102的材料可以为半导体导电材料，例如氮化钛。In some embodiments, the material of the dielectric layer 103 may be an insulating material, such as aluminum oxide. In some embodiments, the material of the electrode plate 102 may be a semiconductor conductive material, such as titanium nitride.

参考图7至图10，在第一面11形成N个第一电接触结构104，第一电接触结构104在衬底100第一面11的正投影形状为环形，且相邻的两个第一电接触结构104中，一第一电接触结构104绕设于另一第一电接触结构104外周，多个沟槽电容器101中处于相同层的极板102均与同一第一电接触结构104电接触，且多个沟槽电容器101的第1层极板102至第N层极板102中的所有极板102与不同的第一电接触结构104电接触。Referring to Figures 7 to 10, N first electrical contact structures 104 are formed on the first surface 11, and the orthographic projection shape of the first electrical contact structure 104 on the first surface 11 of the substrate 100 is a ring, and in two adjacent first electrical contact structures 104, one first electrical contact structure 104 is arranged around the outer periphery of the other first electrical contact structure 104, and the plates 102 in the same layer of the multiple trench capacitors 101 are all electrically contacted with the same first electrical contact structure 104, and all the plates 102 from the 1st layer plate 102 to the Nth layer plate 102 in the multiple trench capacitors 101 are electrically contacted with different first electrical contact structures 104.

也就是说，多个第一电接触结构104之间为嵌套式设计，一方面可以大大减小多个第一电接触结构104所占用的空间，进而可以为形成更多的沟槽电容器101提供较多的空间，有利于增加沟槽电容器101的数量，进一步提高电容值，另一方面，多个第一电接触结构104之间嵌套式设计，使得相邻的第一电接触结构104之间不容易发生接触，进而可以减小相邻的第一电接触结构104之间发生短路的风险。That is to say, the nested design between the multiple first electrical contact structures 104 can, on the one hand, greatly reduce the space occupied by the multiple first electrical contact structures 104, thereby providing more space for forming more trench capacitors 101, which is beneficial to increase the number of trench capacitors 101 and further improve the capacitance value. On the other hand, the nested design between the multiple first electrical contact structures 104 makes it difficult for adjacent first electrical contact structures 104 to contact each other, thereby reducing the risk of short circuit between adjacent first electrical contact structures 104.

参考图7，在一些实施例中，在形成沟槽电容器101的步骤之后，还包括：在沟槽电容器101顶面形成第一隔离结构109，第一隔离结构109覆盖多个沟槽电容器101。在一些实施例中，可以采用沉积工艺形成第一隔离结构109，例如可以采用原子层沉积工艺或者化学气相沉积工艺中的任一者。在一些实施例中，第一隔离结构109的材料可以包括氧化硅。Referring to FIG. 7 , in some embodiments, after the step of forming the trench capacitor 101, the step further includes: forming a first isolation structure 109 on the top surface of the trench capacitor 101, the first isolation structure 109 covering the plurality of trench capacitors 101. In some embodiments, the first isolation structure 109 may be formed by a deposition process, for example, an atomic layer deposition process or a chemical vapor deposition process. In some embodiments, the material of the first isolation structure 109 may include silicon oxide.

形成N个第一电接触结构104的方法包括：The method of forming N first electrical contact structures 104 includes:

参考图8，刻蚀第一隔离结构109，以在第一隔离结构109中形成N个第一凹槽50，每一第一凹槽50底部露出多个沟槽电容器101中的每一沟槽电容器101的第n层极板102的第一部分1的部分顶面，第一凹槽50在衬底100第一面11的正投影形状为圆环形。值得注意的是，这里的第n层极板102指的至从第1层极板102至第N层极板102。例如，若N为3，则，n可以为1，n可以为2，n也可以为3。第一凹槽50的数量为3个，第一个第一凹槽50露出多个沟槽电容器101中每一沟槽电容器101的第1层极板102的第一部分1的部分顶面。第二个第一凹槽50露出多个沟槽电容器101中每一沟槽电容器101的第2层极板102的第一部分1的部分顶面。第三个第一凹槽50露出多个沟槽电容器101中每一沟槽电容器101的第3层极板102的第一部分1的部分顶面。Referring to FIG8 , the first isolation structure 109 is etched to form N first grooves 50 in the first isolation structure 109 , and the bottom of each first groove 50 exposes a portion of the top surface of the first portion 1 of the n-th layer plate 102 of each trench capacitor 101 in the plurality of trench capacitors 101 , and the orthographic projection shape of the first groove 50 on the first surface 11 of the substrate 100 is a circular ring. It is worth noting that the n-th layer plate 102 here refers to from the first layer plate 102 to the N-th layer plate 102. For example, if N is 3, then n can be 1, n can be 2, and n can also be 3. The number of the first grooves 50 is 3, and the first first groove 50 exposes a portion of the top surface of the first portion 1 of the first layer plate 102 of each trench capacitor 101 in the plurality of trench capacitors 101. The second first groove 50 exposes a portion of the top surface of the first portion 1 of the second layer plate 102 of each trench capacitor 101 in the plurality of trench capacitors 101. The third first groove 50 exposes a portion of the top surface of the first portion 1 of the third layer plate 102 of each of the plurality of trench capacitors 101 .

在一些实施例中，形成第一凹槽50的方法可以包括：In some embodiments, a method of forming the first groove 50 may include:

在第一隔离结构109顶面形成第一掩膜层；对第一掩膜层进行图案化工艺，以在第一掩膜层中形成第一开口，第一开口用于定义第一凹槽50开口，且第一开口露出第一隔离结构109的部分顶面；沿第一开口对第一隔离结构109进行刻蚀工艺，以在第一隔离结构109中形成第一凹槽50。在一些实施例中，刻蚀工艺可以是干法刻蚀工艺或者湿法刻蚀工艺中的任一种。A first mask layer is formed on the top surface of the first isolation structure 109; a patterning process is performed on the first mask layer to form a first opening in the first mask layer, the first opening is used to define the opening of the first groove 50, and the first opening exposes a portion of the top surface of the first isolation structure 109; an etching process is performed on the first isolation structure 109 along the first opening to form a first groove 50 in the first isolation structure 109. In some embodiments, the etching process can be any one of a dry etching process and a wet etching process.

形成的第一凹槽50在第一面11的正投影形状为圆环形，使得后续在第一凹槽50中形成的第一电接触结构104在第一面11的正投影形状为圆环形。The orthographic projection shape of the formed first groove 50 on the first surface 11 is a circular ring, so that the orthographic projection shape of the first electrical contact structure 104 subsequently formed in the first groove 50 on the first surface 11 is a circular ring.

在一些实施例中，形成的第一凹槽50在第一面11的正投影形状可以为封闭环形，例如可以是环状多边形。在一些实施例中，环状多边形可以是三角环形、环形四边形或者环形五边形中的任一者。本申请实施例不对环状多边形的边数进行具体限定。可以根据不同的需求形成具有不同边数环状多边形。In some embodiments, the orthographic projection shape of the first groove 50 formed on the first surface 11 can be a closed ring, for example, a ring-shaped polygon. In some embodiments, the ring-shaped polygon can be any one of a triangular ring, a ring-shaped quadrilateral, or a ring-shaped pentagon. The embodiment of the present application does not specifically limit the number of sides of the ring-shaped polygon. Ring-shaped polygons with different numbers of sides can be formed according to different requirements.

在形成第一凹槽50之后，在每一第一凹槽50中填充导电材料以形成第一电接触结构104。After the first grooves 50 are formed, a conductive material is filled in each first groove 50 to form a first electrical contact structure 104 .

参考图9，在一些实施例中，形成第一电接触结构104的方法可以包括：采用沉积工艺在每一第一凹槽50中形成初始第一电接触结构46，初始第一电接触结构46填满整个第一凹槽50，并且还高于第一凹槽50顶部，高于第一凹槽50顶部的初始第一电接触结构46位于第一隔离结构109顶面。Referring to Figure 9, in some embodiments, the method of forming the first electrical contact structure 104 may include: using a deposition process to form an initial first electrical contact structure 46 in each first groove 50, the initial first electrical contact structure 46 fills the entire first groove 50, and is also higher than the top of the first groove 50, and the initial first electrical contact structure 46 higher than the top of the first groove 50 is located on the top surface of the first isolation structure 109.

参考图10，对初始第一电接触结构46进行平坦化工艺，以去除高于第一凹槽50顶部的初始第一电接触结构46以及位于第一隔离结构109顶面的初始第一电接触结构46，以形成第一电接触结构104，形成的第一电接触结构104顶面与第一凹槽50开口齐平。Referring to Figure 10, the initial first electrical contact structure 46 is planarized to remove the initial first electrical contact structure 46 that is higher than the top of the first groove 50 and the initial first electrical contact structure 46 located on the top surface of the first isolation structure 109 to form a first electrical contact structure 104, and the top surface of the formed first electrical contact structure 104 is flush with the opening of the first groove 50.

在一些实施例中，第一电接触结构104的材料可以是金属，例如可以是铜、镍或者钨中的任一种。In some embodiments, the material of the first electrical contact structure 104 may be metal, for example, copper, nickel or tungsten.

在一些实施例中，多个间隔排布的沟槽电容器101以及与沟槽电容器101的极板102电接触的第一电接触结构104组成一电容器单元20(参考图3)，在衬底100中形成多个间隔排布的电容器单元20，还包括：In some embodiments, a plurality of spaced trench capacitors 101 and a first electrical contact structure 104 electrically contacting the plates 102 of the trench capacitors 101 form a capacitor unit 20 (see FIG. 3 ). The plurality of spaced capacitor units 20 are formed in the substrate 100 and further include:

参考图11至图14，在第一隔离结构109顶面形成第二隔离结构110。在一些实施例中，可以采用沉积工艺在第一隔离结构109顶面形成第二隔离结构110，沉积工艺可以是原子层沉积工艺或者化学气相沉积工艺中的任一者。在一些实施例中，第二隔离结构110的材料可以是氧化硅。11 to 14, a second isolation structure 110 is formed on the top surface of the first isolation structure 109. In some embodiments, a deposition process may be used to form the second isolation structure 110 on the top surface of the first isolation structure 109, and the deposition process may be any one of an atomic layer deposition process or a chemical vapor deposition process. In some embodiments, the material of the second isolation structure 110 may be silicon oxide.

刻蚀第二隔离结构110，以在第二隔离结构110中形成多个第二凹槽53，一第二凹槽53与一第一电接触结构104对应，且第二凹槽53底部露出一第一电接触结构104的部分顶面。The second isolation structure 110 is etched to form a plurality of second grooves 53 in the second isolation structure 110 . A second groove 53 corresponds to a first electrical contact structure 104 , and a portion of a top surface of a first electrical contact structure 104 is exposed at the bottom of the second groove 53 .

在一些实施例中，形成第二凹槽53的方法可以包括：在第二隔离结构110顶面形成第二掩膜层；对第二掩膜层进行图案化工艺，以在第二掩膜层中形成第二开口，第二开口用于定义第二凹槽53的开口，且第二开口露出部分第二隔离结构110顶面；沿第二开口对第二隔离结构110进行刻蚀以在第二隔离结构110中形成第二凹槽53。In some embodiments, the method for forming the second groove 53 may include: forming a second mask layer on the top surface of the second isolation structure 110; performing a patterning process on the second mask layer to form a second opening in the second mask layer, the second opening being used to define the opening of the second groove 53, and the second opening exposing a portion of the top surface of the second isolation structure 110; etching the second isolation structure 110 along the second opening to form a second groove 53 in the second isolation structure 110.

参考图15，在一些实施例中，若第二电接触结构106包括沿远离第一面11方向依次层叠的第一层31以及第二层32，且第一层31在第一面11的正投影位于第二层32在第一面11的正投影内，则第二隔离结构110可以包括：依次层叠的第一隔离层47以及第二隔离层49。形成第二凹槽53的方法可以包括：Referring to FIG. 15 , in some embodiments, if the second electrical contact structure 106 includes a first layer 31 and a second layer 32 stacked in sequence in a direction away from the first surface 11, and the orthographic projection of the first layer 31 on the first surface 11 is located within the orthographic projection of the second layer 32 on the first surface 11, then the second isolation structure 110 may include: a first isolation layer 47 and a second isolation layer 49 stacked in sequence. The method of forming the second groove 53 may include:

参考图11，首先在第一隔离结构109顶面以及第一电接触结构104顶面形成第一隔离层47，对第一隔离层47进行刻蚀工艺以在第一隔离层47中形成多个子第一凹槽51，每一子第一凹槽51底部露出一第一电接触结构104的部分顶面。11 , a first isolation layer 47 is first formed on the top surface of the first isolation structure 109 and the top surface of the first electrical contact structure 104 , and an etching process is performed on the first isolation layer 47 to form a plurality of sub-first grooves 51 in the first isolation layer 47 , wherein a portion of the top surface of the first electrical contact structure 104 is exposed at the bottom of each sub-first groove 51 .

参考图12，接着采用沉积工艺在每一子第一凹槽51中形成牺牲层48，牺牲层48的材料与第一隔离层47的材料不同，在一些实施例中，第一隔离层47的材料为氧化硅，牺牲层48的材料为氮化硅。牺牲层48顶面与子第一凹槽51开口齐平。Referring to FIG12 , a deposition process is then used to form a sacrificial layer 48 in each sub-first groove 51 . The material of the sacrificial layer 48 is different from that of the first isolation layer 47 . In some embodiments, the material of the first isolation layer 47 is silicon oxide, and the material of the sacrificial layer 48 is silicon nitride. The top surface of the sacrificial layer 48 is flush with the opening of the sub-first groove 51 .

参考图13，接着在牺牲层48顶面以及第一隔离层47顶面形成第二隔离层49，对第二隔离层49进行刻蚀工艺以在第二隔离层49中形成多个子第二凹槽52，每一子第二凹槽52露出牺牲层48顶面。13 , a second isolation layer 49 is then formed on the top surface of the sacrificial layer 48 and the top surface of the first isolation layer 47 , and the second isolation layer 49 is etched to form a plurality of sub-second grooves 52 in the second isolation layer 49 , each of which exposes the top surface of the sacrificial layer 48 .

参考图14，去除牺牲层48，例如可以采用湿法刻蚀工艺或者干法刻蚀工艺，以使每一子第二凹槽52与一子第一凹槽51一一对应，且相连通，相连通的子第一凹槽51与子第二凹槽52构成第二凹槽53。子第二凹槽52的宽度尺寸大于子第一凹槽51的宽度尺寸。14 , the sacrificial layer 48 is removed, for example, by a wet etching process or a dry etching process, so that each sub-second groove 52 corresponds to a sub-first groove 51 one by one and is connected, and the connected sub-first grooves 51 and sub-second grooves 52 constitute a second groove 53. The width of the sub-second groove 52 is greater than the width of the sub-first groove 51.

在一些实施例中，形成第一隔离层47和第二隔离层49以及对第一隔离层47和第二隔离层49进行刻蚀工艺的方法可以参考上述形成第二隔离结构110以及对第二隔离结构110进行刻蚀工艺的方法。In some embodiments, the method of forming the first isolation layer 47 and the second isolation layer 49 and etching the first isolation layer 47 and the second isolation layer 49 may refer to the above-mentioned method of forming the second isolation structure 110 and etching the second isolation structure 110 .

参考图15，在每一第二凹槽53中形成第二电接触结构106。在一些实施例中，可以采用沉积工艺在第二凹槽53中形成初始第二电接触结构(未图示)，初始第二电接触结构填满整个第二凹槽53，并且还高于第二凹槽53顶部，高于第二凹槽53顶部的初始第二电接触结构位于第二隔离结构110顶面。15 , a second electrical contact structure 106 is formed in each second groove 53. In some embodiments, a deposition process may be used to form an initial second electrical contact structure (not shown) in the second groove 53, the initial second electrical contact structure fills the entire second groove 53 and is higher than the top of the second groove 53, and the initial second electrical contact structure higher than the top of the second groove 53 is located on the top surface of the second isolation structure 110.

对初始第二电接触结构进行平坦化工艺，以去除高于第二凹槽53顶部的初始第二电接触结构以及位于第二隔离结构110顶面的初始第二电接触结构，以形成第二电接触结构106，形成的第二电接触结构106顶面与第二凹槽53开口齐平。The initial second electrical contact structure is planarized to remove the initial second electrical contact structure above the top of the second groove 53 and the initial second electrical contact structure located on the top surface of the second isolation structure 110 to form a second electrical contact structure 106 , the top surface of the formed second electrical contact structure 106 is flush with the opening of the second groove 53 .

参考图3，形成第二电接触结构106之后，在第二电接触结构106远离第一电接触结构104的一侧形成多个金属层107，金属层107分别与相邻的两个电容器单元20中的一第二电接触结构106电连接，以使相邻的两个电容器单元20中，与第n层极板102电接触的两个第一电接触结构104电连接。Referring to Figure 3, after the second electrical contact structure 106 is formed, a plurality of metal layers 107 are formed on a side of the second electrical contact structure 106 away from the first electrical contact structure 104, and the metal layers 107 are electrically connected to a second electrical contact structure 106 in two adjacent capacitor units 20, respectively, so that the two first electrical contact structures 104 in electrical contact with the n-th layer plate 102 in the two adjacent capacitor units 20 are electrically connected.

也就是说，每一电容器单元20包括：多个间隔排布沟槽电容器101，以及与多个沟槽电容器101中处于相同层的极板102电接触的N个第一电接触结构104。两个电容器单元20中，均与多个沟槽电容器101中的第n-1层极板102电接触的两个第一电接触结构104电连接，均与沟槽电容器101中的第n层极板102电接触的两个第一电接触结构104电连接，从而将相邻的两个电容器单元20所构成的两个电容群组并联，进一步增大电容值。That is, each capacitor unit 20 includes: a plurality of trench capacitors 101 arranged at intervals, and N first electrical contact structures 104 electrically contacting the plates 102 in the same layer in the plurality of trench capacitors 101. In two capacitor units 20, two first electrical contact structures 104 electrically contacting the plates 102 in the n-1th layer in the plurality of trench capacitors 101 are electrically connected, and two first electrical contact structures 104 electrically contacting the plates 102 in the nth layer in the trench capacitors 101 are electrically connected, so that two capacitor groups formed by two adjacent capacitor units 20 are connected in parallel, further increasing the capacitance value.

在一些实施例中，形成金属层107的方法可以包括：在第二电接触结构106远离第一电接触结构104一侧形成第三隔离结构(未图示)。对第三隔离结构进行图形化，以在第三隔离结构中形成第三凹槽(未图示)，第三凹槽的两端的底部分别露出相邻的两个电容器单元20中，与第n层极板102电连接的两个第二电接触结构106的部分顶面。接着采用沉积工艺在第三凹槽中形成金属层107。在一些实施例中，金属层107的材料可以为铜。In some embodiments, the method of forming the metal layer 107 may include: forming a third isolation structure (not shown) on the side of the second electrical contact structure 106 away from the first electrical contact structure 104. Patterning the third isolation structure to form a third groove (not shown) in the third isolation structure, the bottoms of both ends of the third groove respectively expose part of the top surface of the two second electrical contact structures 106 electrically connected to the n-th layer plate 102 in two adjacent capacitor units 20. Then, a deposition process is used to form the metal layer 107 in the third groove. In some embodiments, the material of the metal layer 107 may be copper.

参考图16至图18，在一些实施例中，还包括：形成硅中介层111，硅中介层111包括相对的第三面14以及第四面15，硅中介层111中具有多个第一电连接结构112，每一第一电连接结构112由第三面14向第四面15延伸，且第四面15露出第一电连接结构112底部，键合衬底100的第一面11与硅中介层111的第四面15，以使一第一电连接结构112底部与一第一电接触结构104电连接。Referring to Figures 16 to 18, in some embodiments, it also includes: forming a silicon interposer 111, the silicon interposer 111 includes a third surface 14 and a fourth surface 15 relative to each other, and the silicon interposer 111 has a plurality of first electrical connection structures 112, each first electrical connection structure 112 extends from the third surface 14 to the fourth surface 15, and the fourth surface 15 exposes the bottom of the first electrical connection structure 112, and the first surface 11 of the bonding substrate 100 and the fourth surface 15 of the silicon interposer 111 are electrically connected to the bottom of a first electrical connection structure 112 and a first electrical contact structure 104.

也就是说，本申请实施例中，沟槽电容器101不形成于硅中介层111中，而是分别形成沟槽电容器101与硅中介层111，再将硅中介层111以及衬底100键合，实现第一电连接结构112与第一电接触结构104的电连接。如此，沟槽电容器101可以通过硅中介层111实现与外部的信号传输，例如可以通过硅中介层111连接至外部电源，进而对外部电源进行去耦。That is to say, in the embodiment of the present application, the trench capacitor 101 is not formed in the silicon interposer 111, but the trench capacitor 101 and the silicon interposer 111 are formed separately, and then the silicon interposer 111 and the substrate 100 are bonded to realize the electrical connection between the first electrical connection structure 112 and the first electrical contact structure 104. In this way, the trench capacitor 101 can realize signal transmission with the outside through the silicon interposer 111, for example, it can be connected to an external power supply through the silicon interposer 111, thereby decoupling the external power supply.

由于沟槽电容器101与硅中介层111不位于同一衬底100中，使得衬底100中可以有较大的空间来用于形成沟槽电容器101，进而能够增加沟槽电容器101的数量，进一步提高电容值。Since the trench capacitors 101 and the silicon interposer 111 are not located in the same substrate 100 , there is a larger space in the substrate 100 for forming the trench capacitors 101 , thereby increasing the number of trench capacitors 101 and further improving the capacitance value.

在一些实施例，形成硅中介层111的方法包括：In some embodiments, a method of forming a silicon interposer 111 includes:

参考图16，提供初始衬底60，初始衬底60具有相对的第一侧与第二侧。在一些实施例中，初始衬底60的材料可以包括硅。在一些实施例中，硅中介层111的材料也可以为锗、锗硅或者绝缘体上的硅。16 , an initial substrate 60 is provided, the initial substrate 60 having a first side and a second side opposite to each other. In some embodiments, the material of the initial substrate 60 may include silicon. In some embodiments, the material of the silicon interposer 111 may also be germanium, silicon germanium, or silicon on insulator.

刻蚀初始衬底60，以在初始衬底60中形成多个通孔(未图示)。在一些实施例中，可以采用干法刻蚀工艺或者湿法刻蚀工艺在初始衬底60中形成多个通孔。The initial substrate 60 is etched to form a plurality of through holes (not shown) in the initial substrate 60. In some embodiments, the plurality of through holes may be formed in the initial substrate 60 by using a dry etching process or a wet etching process.

参考图17，在通孔侧壁形成阻挡层37。在一些实施例中，可以采用沉积工艺，例如原子层沉积工艺或者化学气相沉积工艺在通孔侧壁形成阻挡层37，在一些实施例中，阻挡层37的材料可以是氮化钛。17, a barrier layer 37 is formed on the sidewall of the through hole. In some embodiments, a deposition process such as an atomic layer deposition process or a chemical vapor deposition process may be used to form the barrier layer 37 on the sidewall of the through hole. In some embodiments, the material of the barrier layer 37 may be titanium nitride.

形成填充通孔的导电主体部36，导电主体部36还位于阻挡层37表面。在一些实施例中，可以采用沉积工艺，例如原子层沉积工艺形成导电主体部36。在一些实施例中，也可以采用电镀工艺形成导电主体部36。在一些实施例中，若采用电镀工艺形成导电主体部36，则在形成导电主体部36之前，还需在阻挡层37表面形成电镀种子层。在一些实施例中，导电主体部36的材料可以是金属。A conductive body portion 36 is formed to fill the through hole, and the conductive body portion 36 is also located on the surface of the barrier layer 37. In some embodiments, a deposition process, such as an atomic layer deposition process, can be used to form the conductive body portion 36. In some embodiments, an electroplating process can also be used to form the conductive body portion 36. In some embodiments, if the conductive body portion 36 is formed by an electroplating process, an electroplating seed layer needs to be formed on the surface of the barrier layer 37 before the conductive body portion 36 is formed. In some embodiments, the material of the conductive body portion 36 can be metal.

参考图18，形成导电主体部36之后，从第二侧减薄初始衬底60，以露出导电主体部36以及阻挡层37的底部，剩余阻挡层37与导电主体部36构成第一电连接结构112，且剩余初始衬底60与第一电连接结构112构成硅中介层111。即第一电连接结构112贯穿硅中介层111，使得第一电连接结构112易于与其它用于实现电信号传输的电连接结构连接。18, after the conductive body portion 36 is formed, the initial substrate 60 is thinned from the second side to expose the conductive body portion 36 and the bottom of the barrier layer 37, and the remaining barrier layer 37 and the conductive body portion 36 constitute a first electrical connection structure 112, and the remaining initial substrate 60 and the first electrical connection structure 112 constitute a silicon interposer 111. That is, the first electrical connection structure 112 penetrates the silicon interposer 111, so that the first electrical connection structure 112 is easy to connect with other electrical connection structures for realizing electrical signal transmission.

在一些实施例中，为了实现硅中介层111与其它元件的电连接，例如，为了实现硅中介层111与芯片的电连接，还可以在硅中介层111的第三面形成第二介质层，第二介质层中形成有第三电连接结构，第二介质层露出第三电连接结构顶面以及底面，第三电连接结构底面与第一电连接结构112顶面电接触。在一些实施例中，还可以在硅中介层111的第三面形成其它结构，例如可以参考图1，还可以形成第一刻蚀阻挡层43、第二刻蚀阻挡层44以及第三刻蚀阻挡层45。还可以形成绝缘层117、阻挡部118以及保护层119。值得注意的是，可以在硅中介层111的第三面形成需要形成的结构之后，例如，形成上述位于第三面的结构之后，键合衬底100的第一面11与硅中介层111的第四面15。In some embodiments, in order to realize the electrical connection between the silicon interposer 111 and other components, for example, in order to realize the electrical connection between the silicon interposer 111 and the chip, a second dielectric layer may be formed on the third surface of the silicon interposer 111, a third electrical connection structure may be formed in the second dielectric layer, the second dielectric layer may expose the top surface and the bottom surface of the third electrical connection structure, and the bottom surface of the third electrical connection structure may be in electrical contact with the top surface of the first electrical connection structure 112. In some embodiments, other structures may be formed on the third surface of the silicon interposer 111, for example, referring to FIG. 1, a first etch stop layer 43, a second etch stop layer 44, and a third etch stop layer 45 may be formed. An insulating layer 117, a stopper 118, and a protective layer 119 may also be formed. It is worth noting that after the required structure is formed on the third surface of the silicon interposer 111, for example, after the above-mentioned structure located on the third surface is formed, the first surface 11 of the substrate 100 and the fourth surface 15 of the silicon interposer 111 may be bonded.

在一些实施例，键合衬底100的第一面11与硅中介层111的第四面15包括：In some embodiments, the first surface 11 of the bonding substrate 100 and the fourth surface 15 of the silicon interposer 111 include:

参考图19，在衬底100第一面11上形成第一介质层113，第一介质层113位于第一电接触结构104远离第一面11的一侧。在一些实施例中，可以采用沉积工艺形成第一介质层113，例如原子层沉积工艺或者化学气相沉积工艺中的一者。在一些实施例中，第一介质层113的材料可以是碳氮化硅、氮化硅或者氧化硅中的至少一者。19, a first dielectric layer 113 is formed on the first surface 11 of the substrate 100, and the first dielectric layer 113 is located on a side of the first electrical contact structure 104 away from the first surface 11. In some embodiments, the first dielectric layer 113 may be formed by a deposition process, such as an atomic layer deposition process or a chemical vapor deposition process. In some embodiments, the material of the first dielectric layer 113 may be at least one of silicon carbonitride, silicon nitride, or silicon oxide.

在第一介质层113中以及第二隔离结构110中形成第二电连接结构114，第二电连接结构114位于第一电接触结构104远离第一面11的一侧，且第二电连接结构114与第一电接触结构104电接触。在一些实施例中，形成第二电连接结构114的方法可以包括：A second electrical connection structure 114 is formed in the first dielectric layer 113 and the second isolation structure 110. The second electrical connection structure 114 is located on a side of the first electrical contact structure 104 away from the first surface 11, and the second electrical connection structure 114 is in electrical contact with the first electrical contact structure 104. In some embodiments, the method of forming the second electrical connection structure 114 may include:

采用刻蚀工艺形成多个第四凹槽(未图示)，第四凹槽贯穿第一介质层113以及第二隔离结构110，每一第四凹槽露出一第二电接触结构106顶面。采用沉积工艺在第四凹槽中形成第二电连接结构114。在一些实施例中，第二电连接结构114的材料可以是为金属，例如可以为铜、钨或者镍中的至少一者。A plurality of fourth grooves (not shown) are formed by etching, and the fourth grooves penetrate the first dielectric layer 113 and the second isolation structure 110, and each fourth groove exposes a top surface of the second electrical contact structure 106. A second electrical connection structure 114 is formed in the fourth groove by deposition. In some embodiments, the material of the second electrical connection structure 114 may be metal, for example, at least one of copper, tungsten or nickel.

在硅中介层111的第四面15形成第三介质层(未图示)，第三介质层覆盖硅中介层111的第三面。在形成第三介质层之后，在第三介质层中形成第四电连接结构，第三介质层露出第四电连接结构的顶面，第四电连接结构的底面与第一电连接结构112的导电主体部36底部电接触。A third dielectric layer (not shown) is formed on the fourth surface 15 of the silicon interposer 111, and the third dielectric layer covers the third surface of the silicon interposer 111. After the third dielectric layer is formed, a fourth electrical connection structure is formed in the third dielectric layer, the third dielectric layer exposes the top surface of the fourth electrical connection structure, and the bottom surface of the fourth electrical connection structure is in electrical contact with the bottom of the conductive body portion 36 of the first electrical connection structure 112.

在一些实施例中，第三介质层的材料可以是碳氮化硅，第四电连接结构的材料可以是铜。In some embodiments, the material of the third dielectric layer may be silicon carbonitride, and the material of the fourth electrical connection structure may be copper.

将衬底100的第一面11与硅中介层111的第四面15键合，以使第二电连接结构114与第一电连接结构112对应连接。The first surface 11 of the substrate 100 is bonded to the fourth surface 15 of the silicon interposer 111 , so that the second electrical connection structure 114 is correspondingly connected to the first electrical connection structure 112 .

在一些实施例中，可以通过倒装工艺将位于硅中介层111的第三面的第四电连接结构与第二电连接结构114对准，将第三介质层与第一介质层113对准，以使硅中介层111与衬底100面对面键合。In some embodiments, the fourth electrical connection structure on the third surface of the silicon interposer 111 may be aligned with the second electrical connection structure 114 and the third dielectric layer may be aligned with the first dielectric layer 113 by a flip-chip process, so that the silicon interposer 111 and the substrate 100 are bonded face to face.

上述实施例提供的半导体结构的制备方法中，形成的多个第一电接触结构104之间为嵌套式设计，一方面可以大大减小多个第一电接触结构104所占用的空间，进而可以为形成更多的沟槽电容器101提供较多的空间，有利于增加沟槽电容器101的数量，进一步提高电容值，另一方面，多个第一电接触结构104之间嵌套式设计，使得相邻的第一电接触结构104之间不容易发生接触，进而可以减小相邻的第一电接触结构104之间发生短路的风险。In the method for preparing the semiconductor structure provided in the above-mentioned embodiment, the multiple first electrical contact structures 104 are formed in a nested design. On the one hand, the space occupied by the multiple first electrical contact structures 104 can be greatly reduced, thereby providing more space for forming more trench capacitors 101, which is beneficial to increase the number of trench capacitors 101 and further improve the capacitance value. On the other hand, the nested design between the multiple first electrical contact structures 104 makes it difficult for adjacent first electrical contact structures 104 to contact each other, thereby reducing the risk of short circuit between adjacent first electrical contact structures 104.

本公开实施例另一方面还提供一种半导体封装结构，包括：基板，基板具有相对的第一表面与第二表面。半导体封装结构还包括：上述实施例提供的半导体结构，与基板焊接或键合。Another aspect of the disclosed embodiment provides a semiconductor package structure, including: a substrate having a first surface and a second surface opposite to each other. The semiconductor package structure also includes: the semiconductor structure provided by the above embodiment, welded or bonded to the substrate.

在一些实施例中，基板可以是PCB，PCB上具有金属线，实现与芯片之间的中继传输。In some embodiments, the substrate may be a PCB having metal wires thereon to achieve relay transmission with the chip.

在一些实施例中，还包括芯片，芯片位于基板的第一表面。芯片可以为DRAM(动态随机存储器，Dynamic Random Access Memory)芯片、SRAM(静态随机存储器，StaticRandom-Access Memory)芯片或者SDRAM(同步动态随机存储器，Synchronous DynamicRandom-Access Memory)芯片中的任一者。In some embodiments, a chip is further included, and the chip is located on the first surface of the substrate. The chip can be any one of a DRAM (Dynamic Random Access Memory) chip, an SRAM (Static Random Access Memory) chip, or an SDRAM (Synchronous Dynamic Random Access Memory) chip.

在一些实施例中，半导体封装结构还包括：In some embodiments, the semiconductor package structure further includes:

硅中介层111(参考图1)，位于半导体结构中的衬底100(参考图1)朝向芯片的一侧，用于电连接芯片和基板，其中，硅中介层111具有相对的第三面以及第四面。硅中介层111中具有多个第一电连接结构112(参考图2)，每一第一电连接结构112由第三面向第四面延伸，且第四面露出第一电连接结构112底部，衬底100的第一面11(参考图1)与硅中介层111的第四面键合，以使以第一电连接结构112底部与半导体结构中的一第一电接触结构104(参考图1)电连接。The silicon interposer 111 (see FIG. 1 ) is located on the side of the substrate 100 (see FIG. 1 ) in the semiconductor structure facing the chip, and is used to electrically connect the chip and the substrate, wherein the silicon interposer 111 has a third surface and a fourth surface opposite to each other. The silicon interposer 111 has a plurality of first electrical connection structures 112 (see FIG. 2 ), each of which extends from the third surface to the fourth surface, and the bottom of the first electrical connection structure 112 is exposed on the fourth surface. The first surface 11 (see FIG. 1 ) of the substrate 100 is bonded to the fourth surface of the silicon interposer 111, so that the bottom of the first electrical connection structure 112 is electrically connected to a first electrical contact structure 104 (see FIG. 1 ) in the semiconductor structure.

也就是说，沟槽电容器101(参考图1)与硅中介层111不形成于同一衬底100中，从而使得衬底100中有较多的空间来制备沟槽电容器101，增大沟槽电容器101的数量，进而能够提高电容值，有利于改善半导体封装结构的去噪以及抗干扰性能。That is to say, the trench capacitor 101 (refer to Figure 1) and the silicon interposer 111 are not formed in the same substrate 100, so that there is more space in the substrate 100 to prepare the trench capacitor 101, increase the number of trench capacitors 101, and then increase the capacitance value, which is beneficial to improving the noise removal and anti-interference performance of the semiconductor packaging structure.

本领域的普通技术人员可以理解，上述各实施方式是实现本公开的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本公开的精神和范围。任何本领域技术人员，在不脱离本公开的精神和范围内，均可作各自更动与修改，因此本公开的保护范围应当以权利要求限定的范围为准。Those skilled in the art can understand that the above-mentioned embodiments are specific examples for realizing the present disclosure, and in practical applications, various changes can be made to them in form and details without departing from the spirit and scope of the present disclosure. Any person skilled in the art can make their own changes and modifications without departing from the spirit and scope of the present disclosure, so the protection scope of the present disclosure shall be based on the scope defined in the claims.