CN118921018A - Fractional frequency divider circuit for reducing fractional quantization noise - Google Patents

本申请涉及集成电路技术领域，公开了一种降低小数量化噪声的小数分频电路，包括：多模分频器，用于接收输入时钟并根据整数分频比序列生成分频时钟；相位选择器，用于接收与输入时钟频率相同的N相时钟信号并根据相位选择信号输出相应的时钟信号，小数分频电路根据相位选择器输出的时钟信号对分频时钟重定时并输出；调制电路，调制电路包括乘法器、差分累加调制器、第一除法器、累加器、加法器和第二除法器，其中乘法器、差分累加调制器、第一除法器和加法器依次连接，累加器的输入耦合到第一除法器的输出，输出耦合到第二除法器的输入，乘法器的放大倍数为2N，第一除法器的除数为2N，第二除法器接收频率控制字的小数部分，加法器输出整数分频比序列，第二除法器输出相位选择信号。本申请提供了一种简便的方法来提高分频器输出信号精度，降低量化噪声。

The present application relates to the technical field of integrated circuits, and discloses a fractional frequency division circuit for reducing fractional quantization noise, including: a multi-mode frequency divider for receiving an input clock and generating a frequency division clock according to an integer frequency division ratio sequence; a phase selector for receiving an N-phase clock signal with the same frequency as the input clock and outputting a corresponding clock signal according to a phase selection signal, and the fractional frequency division circuit retimes and outputs the frequency division clock according to the clock signal output by the phase selector; a modulation circuit, wherein the modulation circuit includes a multiplier, a differential accumulator modulator, a first divider, an accumulator, an adder, and a second divider, wherein the multiplier, the differential accumulator modulator, the first divider, and the adder are connected in sequence, the input of the accumulator is coupled to the output of the first divider, and the output is coupled to the input of the second divider, the amplification factor of the multiplier is 2N, the divisor of the first divider is 2N, the second divider receives the fractional part of the frequency control word, the adder outputs an integer frequency division ratio sequence, and the second divider outputs a phase selection signal. The present application provides a simple method to improve the accuracy of the frequency divider output signal and reduce quantization noise.

降低小数量化噪声的小数分频电路Fractional frequency division circuit to reduce fractional quantization noise

技术领域Technical Field

本申请涉及集成电路技术领域，特别涉及一种降低小数量化噪声的小数分频电路。The present application relates to the technical field of integrated circuits, and in particular to a fractional frequency division circuit for reducing fractional quantization noise.

背景技术Background Art

小数分频由于能够实现高精度的分频比，被广泛应用在各种电子系统中。但是小数分频由于分频器输出信号的精度受限于输入信号周期，会产生量化噪声。差分累加调制器能够将分频比序列进行整形，使得平均分频比仍是小数，量化噪声被整形到高频。Fractional frequency division is widely used in various electronic systems because it can achieve high-precision frequency division ratios. However, since the accuracy of the frequency divider output signal is limited by the input signal period, fractional frequency division will generate quantization noise. The differential sigma modulator can shape the frequency division ratio sequence so that the average frequency division ratio is still a fraction and the quantization noise is shaped to a high frequency.

传统的分频器只有输入一相信号进行分频，并用输入信号进行采样输出，输出信号实现的相位精度与输入信号周期保持一致。一般的做法采用差分信号对分频器输出的信号进行采样，并通过修改后的差分累加调制器输出控制信号在两个相位之间切换，分频器输出信号的相位精度能够实现为半个输出信号周期。现有方案只能利用差分的两个相位进行量化噪声的抑制，为了实现进一步的量化噪声抑制需要额外的相位产生电路实现，增加系统的噪声、功耗、复杂度等。Traditional frequency dividers only input one-phase signal for frequency division, and use the input signal for sampling and output. The phase accuracy of the output signal is consistent with the input signal period. The general practice is to use a differential signal to sample the signal output by the frequency divider, and switch between the two phases through the modified differential accumulator modulator output control signal. The phase accuracy of the frequency divider output signal can be achieved to half the output signal period. The existing solution can only use the two differential phases to suppress quantization noise. In order to achieve further quantization noise suppression, additional phase generation circuits are required, which increases the system noise, power consumption, complexity, etc.

本部分旨在为权利要求书中陈述的本申请的实施方式提供背景或上下文。此处的描述不因为包括在本部分中就承认是已被公开的现有技术。This section is intended to provide a background or context to the embodiments of the present application as recited in the claims. The description herein is not admitted to be prior art as disclosed by virtue of its inclusion in this section.

发明内容Summary of the invention

本申请的目的在于提供一种降低小数量化噪声的小数分频电路，提供了一种简便的方法来提高分频器输出信号精度，降低量化噪声。The purpose of the present application is to provide a fractional frequency division circuit for reducing fractional quantization noise, and to provide a simple method to improve the accuracy of the output signal of the frequency divider and reduce the quantization noise.

本申请公开了一种降低小数量化噪声的小数分频电路，包括：The present application discloses a fractional frequency division circuit for reducing fractional quantization noise, comprising:

多模分频器，用于接收输入时钟并根据整数分频比序列生成分频时钟；A multi-mode frequency divider, for receiving an input clock and generating a divided clock according to a sequence of integer frequency division ratios;

相位选择器，用于接收与所述输入时钟频率相同的N相时钟信号并根据相位选择信号输出相应的时钟信号；A phase selector, configured to receive an N-phase clock signal having the same frequency as the input clock and output a corresponding clock signal according to a phase selection signal;

触发器，所述触发器的数据端耦合到所述多模分频器的输出，所述触发器的时钟端耦合到所述相位选择器的输出；A trigger, wherein a data terminal of the trigger is coupled to the output of the multi-mode frequency divider, and a clock terminal of the trigger is coupled to the output of the phase selector;

调制电路，所述调制电路包括乘法器、差分累加调制器、第一除法器、累加器、加法器和第二除法器，其中所述乘法器、差分累加调制器、第一除法器和加法器依次连接，所述累加器的输入耦合到所述第一除法器的输出，输出耦合到所述第二除法器的输入，所述乘法器的放大倍数为2N，所述第一除法器的除数为2N，所述第一除法器接收频率控制字的小数部分，所述加法器输出所述整数分频比序列，所述第二除法器输出所述相位选择信号。A modulation circuit, the modulation circuit comprising a multiplier, a differential accumulator modulator, a first divider, an accumulator, an adder and a second divider, wherein the multiplier, the differential accumulator modulator, the first divider and the adder are connected in sequence, the input of the accumulator is coupled to the output of the first divider, and the output is coupled to the input of the second divider, the gain of the multiplier is 2N, the divisor of the first divider is 2N, the first divider receives the decimal part of the frequency control word, the adder outputs the integer division ratio sequence, and the second divider outputs the phase selection signal.

在一个优选例中，所述相位选择器接收两相差分时钟信号，所述乘法器的放大倍数为四，所述第一除法器的除数为四。In a preferred example, the phase selector receives a two-phase differential clock signal, the gain of the multiplier is four, and the divisor of the first divider is four.

在一个优选例中，所述触发器根据所述相位选择器输出的时钟信号对所述分频时钟重定时并输出。In a preferred example, the trigger retimes and outputs the divided clock according to the clock signal output by the phase selector.

在一个优选例中，所述相位选择器接收四相时钟信号，所述乘法器的放大倍数为八，所述第一除法器的除数为八。In a preferred example, the phase selector receives a four-phase clock signal, the gain of the multiplier is eight, and the divisor of the first divider is eight.

在一个优选例中，所述第二除法器的除数为二。In a preferred example, the divisor of the second divider is two.

在一个优选例中，所述加法器还接收所述频率控制字的整数部分。In a preferred example, the adder also receives the integer part of the frequency control word.

本申请还公开了一种降低小数量化噪声的小数分频电路，包括：The present application also discloses a fractional frequency division circuit for reducing fractional quantization noise, comprising:

多模分频器，用于接收输入时钟并根据整数分频比序列生成分频时钟；A multi-mode frequency divider, for receiving an input clock and generating a divided clock according to a sequence of integer frequency division ratios;

第一触发器和第二触发器，所述第一触发器和所述第二触发器的数据端均耦合到所述多模分频器的输出端，时钟端分别耦合到与输入时钟频率相同的N相时钟信号；A first trigger and a second trigger, wherein data terminals of the first trigger and the second trigger are coupled to the output terminal of the multi-mode frequency divider, and clock terminals are respectively coupled to an N-phase clock signal having the same frequency as the input clock;

相位选择器，所述相位选择器分别耦合到所述第一触发器和第二触发器的输出并根据相位选择信号输出相应的时钟信号；a phase selector, the phase selector being coupled to the outputs of the first flip-flop and the second flip-flop respectively and outputting a corresponding clock signal according to a phase selection signal;

调制电路，所述调制电路包括乘法器、差分累加调制器、第一除法器、累加器、加法器和第二除法器，其中所述乘法器、差分累加调制器、第一除法器和加法器依次连接，所述累加器的输入耦合到所述第一除法器的输出，输出耦合到所述第二除法器的输入，所述乘法器的放大倍数为2N，所述第一除法器的除数为2N，所述第一除法器接收频率控制字的小数部分，所述加法器输出所述整数分频比序列，所述第二除法器输出所述相位选择信号。A modulation circuit, the modulation circuit comprising a multiplier, a differential accumulator modulator, a first divider, an accumulator, an adder and a second divider, wherein the multiplier, the differential accumulator modulator, the first divider and the adder are connected in sequence, the input of the accumulator is coupled to the output of the first divider, and the output is coupled to the input of the second divider, the gain of the multiplier is 2N, the divisor of the first divider is 2N, the first divider receives the decimal part of the frequency control word, the adder outputs the integer division ratio sequence, and the second divider outputs the phase selection signal.

在一个优选例中，所述第一触发器和第二触发器的时钟端分别接收两相差分时钟信号，所述乘法器的放大倍数为四，所述第一除法器的除数为四。In a preferred example, the clock ends of the first trigger and the second trigger respectively receive two-phase differential clock signals, the gain of the multiplier is four, and the divisor of the first divider is four.

在一个优选例中，所述第二除法器的除数为二。In a preferred example, the divisor of the second divider is two.

本申请实施方式中，提供了一种简便的方法来提高分频器输出信号精度。对于两相差分时钟信号，不需要产生额外的相位，只需要利用差分的两相信号就可以降低小数量化噪声，提高分频器输出信号精度，使得设计实现简单。In the implementation of the present application, a simple method is provided to improve the accuracy of the output signal of the frequency divider. For a two-phase differential clock signal, no additional phase needs to be generated. Only the differential two-phase signal can be used to reduce the small quantization noise and improve the accuracy of the output signal of the frequency divider, making the design simple to implement.

本申请采用伪2N相的相位选择将分频器输出信号的相位精度提升至2N分之一输入时钟周期。相较于N相的量化噪声减小技术，本申请能够进一步降低高频的量化噪声，从而实现整体量化噪声的改善。The present application uses pseudo 2N phase phase selection to improve the phase accuracy of the divider output signal to 1/2N of the input clock cycle. Compared with the N-phase quantization noise reduction technology, the present application can further reduce the high-frequency quantization noise, thereby achieving an improvement in the overall quantization noise.

本申请的说明书中记载了大量的技术特征，分布在各个技术方案中，如果要罗列出本申请所有可能的技术特征的组合(即技术方案)的话，会使得说明书过于冗长。为了避免这个问题，本申请上述发明内容中公开的各个技术特征、在下文各个实施方式和例子中公开的各技术特征、以及附图中公开的各个技术特征，都可以自由地互相组合，从而构成各种新的技术方案(这些技术方案均应该视为在本说明书中已经记载)，除非这种技术特征的组合在技术上是不可行的。例如，在一个例子中公开了特征A+B+C，在另一个例子中公开了特征A+B+D+E，而特征C和D是起到相同作用的等同技术手段，技术上只要择一使用即可，不可能同时采用，特征E技术上可以与特征C相组合，则，A+B+C+D的方案因技术不可行而应当不被视为已经记载，而A+B+C+E的方案应当视为已经被记载。The specification of the present application records a large number of technical features, which are distributed in various technical solutions. If all possible combinations of technical features of the present application (i.e., technical solutions) are to be listed, the specification will be too long. In order to avoid this problem, the various technical features disclosed in the above-mentioned invention content of the present application, the various technical features disclosed in the various embodiments and examples below, and the various technical features disclosed in the accompanying drawings can be freely combined with each other to form various new technical solutions (these technical solutions should all be regarded as having been recorded in this specification), unless the combination of such technical features is technically infeasible. For example, in one example, feature A+B+C is disclosed, and in another example, feature A+B+D+E is disclosed, and features C and D are equivalent technical means that play the same role. Technically, only one can be used, and it is impossible to use them at the same time. Feature E can be combined with feature C technically. Then, the solution of A+B+C+D should not be regarded as having been recorded because it is technically infeasible, and the solution of A+B+C+E should be regarded as having been recorded.

附图说明BRIEF DESCRIPTION OF THE DRAWINGS

图1是根据本申请一个实施例中分频器以及相位选择器的结构示意图。FIG1 is a schematic diagram of the structure of a frequency divider and a phase selector according to an embodiment of the present application.

图2是根据本申请一个实施例中调制电路的结构示意图。FIG. 2 is a schematic diagram of the structure of a modulation circuit according to an embodiment of the present application.

图3是根据本申请另一个实施例中调制电路的结构示意图。FIG. 3 is a schematic diagram of the structure of a modulation circuit according to another embodiment of the present application.

图4是根据本申请另一个实施例中分频器以及相位选择器的结构示意图。FIG. 4 is a schematic diagram of the structure of a frequency divider and a phase selector according to another embodiment of the present application.

各附图中，各标示如下：In the accompanying drawings, the symbols are as follows:

101,101’-多模分频器；101,101’-Multi-mode divider;

102,102’-相位选择器；102,102'-phase selector;

103-触发器103-Trigger

1031-第一触发器；1031-first trigger;

1032-第二触发器；1032 - second trigger;

104,104’-差分累加调制器；104,104'-differential sigma modulator;

105,105’-第一除法器；105,105'- first divider;

106,106’-加法器；106,106'-adder;

107,107’-累加器；107,107’-Accumulator;

108,108’-第二除法器；108, 108'- second divider;

109,109’-乘法器。109,109’-Multiplier.

具体实施方式DETAILED DESCRIPTION

在以下的叙述中，为了使读者更好地理解本申请而提出了许多技术细节。但是，本领域的普通技术人员可以理解，即使没有这些技术细节和基于以下各实施方式的种种变化和修改，也可以实现本申请所要求保护的技术方案。In the following description, many technical details are provided to help readers better understand the present application. However, those skilled in the art can understand that the technical solution claimed in the present application can be implemented even without these technical details and various changes and modifications based on the following embodiments.

部分概念的说明：Description of some concepts:

小数分频；是一种在数字电路中常用的技术，用于将高频信号转换为低频信号，并且分频比可以是任意小数。小数分频的基本原理是在若干个分频周期中，通过某种方法使某几个周期多计或少计一个数，从而在整个计数周期的总体平均意义上获得一个小数分频比。小数分频器广泛应用于现代电子系统中，如直接数字频率合成中输出波形的频率控制以及步进电机中转速的控制等。Fractional frequency division is a commonly used technology in digital circuits to convert high-frequency signals into low-frequency signals, and the frequency division ratio can be any decimal. The basic principle of fractional frequency division is to use a certain method to make some cycles count one more or less in a number of frequency division cycles, so as to obtain a fractional frequency division ratio in the overall average sense of the entire counting cycle. Fractional frequency dividers are widely used in modern electronic systems, such as frequency control of output waveforms in direct digital frequency synthesis and speed control in stepper motors.

频率控制字(Frequency Control Word，简称FCW)是一种用于数字信号处理(DSP)和直接数字频率合成(DDS)中的参数。它主要用于确定输出信号的频率。频率控制字是一个16位或32位的二进制数，用于控制数字信号的频率，并且决定了数字信号的周期。频率控制字通常通过DAC芯片进行实现，将其转换为模拟信号后作为参考频率输入到PLL锁相环电路。在数字通信系统中，频率控制字通过DAC芯片实现，将其转换为模拟信号后作为参考频率输入到PLL锁相环电路，从而控制数字信号的频率和周期。Frequency Control Word (FCW) is a parameter used in digital signal processing (DSP) and direct digital frequency synthesis (DDS). It is mainly used to determine the frequency of the output signal. The frequency control word is a 16-bit or 32-bit binary number that is used to control the frequency of the digital signal and determines the period of the digital signal. The frequency control word is usually implemented through a DAC chip, which is converted into an analog signal and input into the PLL phase-locked loop circuit as a reference frequency. In digital communication systems, the frequency control word is implemented through a DAC chip, which is converted into an analog signal and input into the PLL phase-locked loop circuit as a reference frequency, thereby controlling the frequency and period of the digital signal.

多模分频器(Multi-Mode Divider)：是一种能够在多个分频模式之间切换的分频器电路，广泛应用于频率合成、时钟生成和通信系统中。Multi-Mode Divider: A divider circuit that can switch between multiple division modes and is widely used in frequency synthesis, clock generation and communication systems.

差分累加调制器(Delta-Sigma Modulator，简称ΔΣ调制器)是一种用于模拟信号数字化和小数分频的技术。Delta-Sigma Modulator (ΔΣ modulator for short) is a technology used for digitizing analog signals and performing fractional frequency division.

多路选择器：是数据选择器的别称。在多路数据传送过程中，能够根据需要将其中任意一路选出来的电路，叫做数据选择器，也称多路选择器或多路开关。Multiplexer: Another name for data selector. In the process of multi-channel data transmission, the circuit that can select any one of them according to the need is called a data selector, also known as a multiplexer or a multi-way switch.

加法器：一种数位电路，其可进行数字的加法计算。Adder: A digital circuit that can add numbers.

累加器：专门存放算术或逻辑运算的一个操作数和运算结果的寄存器。能进行加、减、读出、移位、循环移位和求补等操作。Accumulator: A register that is used to store an operand and result of an arithmetic or logical operation. It can perform operations such as addition, subtraction, readout, shift, circular shift, and complement.

为使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请的实施方式作进一步地详细描述。In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below in conjunction with the accompanying drawings.

实施例一Embodiment 1

本申请公开了一种降低小数量化噪声的小数分频电路，该小数分频电路包括：多模分频器、相位选择器、以及调制电路。多模分频器用于接收输入时钟并根据整数分频比序列生成分频时钟。相位选择器用于接收与输入时钟频率相同的N相时钟信号并根据相位选择信号输出相应的时钟信号。相位选择器可以采用多路选择器MUX实现。小数分频电路根据相位选择器输出的时钟信号对分频时钟重定时并输出。The present application discloses a fractional frequency division circuit for reducing fractional quantization noise, the fractional frequency division circuit comprising: a multi-mode frequency divider, a phase selector, and a modulation circuit. The multi-mode frequency divider is used to receive an input clock and generate a frequency division clock according to an integer frequency division ratio sequence. The phase selector is used to receive an N-phase clock signal with the same frequency as the input clock and output a corresponding clock signal according to a phase selection signal. The phase selector can be implemented by a multiplexer MUX. The fractional frequency division circuit retimes and outputs the frequency division clock according to the clock signal output by the phase selector.

图1示出了采用2相时钟信号进行量化噪声抑制的示意图。其中，多模分频器101接收输入时钟CKIN，并根据整数分频比序列对输入时钟CKIN进行分频，得到分频时钟CKDIV。相位选择器102接收一对2相的差分时钟信号CKIN_P和CKIN_N，相位选择器102根据相位选择信号输出时钟信号CKIN_P或CKIN_N。FIG1 shows a schematic diagram of quantization noise suppression using a 2-phase clock signal. The multi-mode divider 101 receives an input clock CKIN and divides the input clock CKIN according to an integer division ratio sequence to obtain a divided clock CKDIV. The phase selector 102 receives a pair of 2-phase differential clock signals CKIN_P and CKIN_N, and the phase selector 102 outputs a clock signal CKIN_P or CKIN_N according to a phase selection signal.

图2示出了调制电路的示意图。调制电路用于生成整数分频比序列和相位选择信号。其中调制电路包括乘法器109、差分累加调制器104、第一除法器105、累加器107、加法器106和第二除法器105。其中乘法器109、差分累加调制器104、第一除法器105和加法器106依次连接，累加器107的输入耦合到第一除法器105的输出，累加器107输出耦合到第二除法器108的输入，乘法器109的放大倍数为2N，第一除法器105的除数(或称为分频比)为2N，第一除法器105接收频率控制字(FCW)的小数部分，加法器106输出整数分频比序列到多模分频器101，第二除法器108输出相位选择信号到相位选择器102。FIG2 shows a schematic diagram of a modulation circuit. The modulation circuit is used to generate an integer frequency division ratio sequence and a phase selection signal. The modulation circuit includes a multiplier 109, a differential accumulator modulator 104, a first divider 105, an accumulator 107, an adder 106 and a second divider 105. The multiplier 109, the differential accumulator modulator 104, the first divider 105 and the adder 106 are connected in sequence, the input of the accumulator 107 is coupled to the output of the first divider 105, the output of the accumulator 107 is coupled to the input of the second divider 108, the amplification factor of the multiplier 109 is 2N, the divisor (or frequency division ratio) of the first divider 105 is 2N, the first divider 105 receives the fractional part of the frequency control word (FCW), the adder 106 outputs the integer frequency division ratio sequence to the multi-mode divider 101, and the second divider 108 outputs the phase selection signal to the phase selector 102.

在一个实施例中，相位选择器102接收两相差分时钟信号。其中乘法器109的放大倍数为四(4)，相应的，第一除法器105的除数(或称为分频比)为四(4)。In one embodiment, the phase selector 102 receives a two-phase differential clock signal. The gain of the multiplier 109 is four (4), and accordingly, the divisor (or frequency division ratio) of the first divider 105 is four (4).

在一个实施例中，第二除法器106的除数(或称为分频比)为二(2)。In one embodiment, the divisor (or division ratio) of the second divider 106 is two (2).

频率控制字(FCW)的小数部分首先被乘法器109放大四倍并输入到差分累加调制器104，经过调制后被除法器105分频，其中分频后的小数部分输入到累加器107，整数部分输入到加法器106。累加器107将累加结果输入到除法器108，除法器108进行二分频后输入相位选择信号到多路选择路。加法器106将分频后的整数部分和累加器107的进位信号相加的结果作为整数分批比序列输入到多模分频器。The fractional part of the frequency control word (FCW) is first amplified four times by the multiplier 109 and input to the differential accumulator modulator 104, and then divided by the divider 105 after modulation, wherein the fractional part after frequency division is input to the accumulator 107, and the integer part is input to the adder 106. The accumulator 107 inputs the accumulation result to the divider 108, and the divider 108 divides the frequency by two and inputs the phase selection signal to the multiplexer. The adder 106 adds the integer part after frequency division and the carry signal of the accumulator 107 as an integer batch ratio sequence and inputs it to the multi-mode divider.

在一个实施例中，加法器106还接收频率控制字FCW的整数部分。也就是，加法器106将分频后的整数部分、累加器107的进位信号以及率控制字FCW的整数部分相加的结果作为整数分频比序列输入到多模分频器。In one embodiment, the adder 106 also receives the integer part of the frequency control word FCW. That is, the adder 106 adds the divided integer part, the carry signal of the accumulator 107 and the integer part of the rate control word FCW to the multi-mode frequency divider as an integer frequency division ratio sequence.

在一个实施例中，小数分频电路包括触发器，例如D触发器(DFF)，触发器的数据端耦合到多模分频器的输出，时钟端耦合到相位选择器的输出端，触发器根据相位选择器输出的时钟信号对分频时钟重定时并输出。例如，参考图1所示，小数分频电路包括触发器103，触发器103的数据端(D)耦合到多模分频器101的输出端并接收分频时钟CKDIV，触发器103的时钟端(CLK)耦合到相位选择器102的输出端，并接收相位选择器102输出相应的时钟信号。触发器103根据时钟端接收的时钟信号对分频时钟CKDIV进行重定时并输出时钟信号CKOUT。本实施例中触发器耦合到相位选择器的输出进行重定时的为例进行说明，在其他实施例中，还可以将触发器耦合到相位选择器的输入进行重定时为例进行说明。In one embodiment, the fractional frequency division circuit includes a trigger, such as a D trigger (DFF), the data end of the trigger is coupled to the output of the multi-mode frequency divider, the clock end is coupled to the output end of the phase selector, and the trigger retimes and outputs the divided clock according to the clock signal output by the phase selector. For example, referring to FIG1, the fractional frequency division circuit includes a trigger 103, the data end (D) of the trigger 103 is coupled to the output end of the multi-mode frequency divider 101 and receives the divided clock CKDIV, the clock end (CLK) of the trigger 103 is coupled to the output end of the phase selector 102, and receives the corresponding clock signal output by the phase selector 102. The trigger 103 retimes the divided clock CKDIV according to the clock signal received at the clock end and outputs the clock signal CKOUT. In this embodiment, the trigger is coupled to the output of the phase selector for retiming as an example for explanation. In other embodiments, the trigger can also be coupled to the input of the phase selector for retiming as an example for explanation.

在另一个实施例中，还可以采用4相时钟信号进行量化噪声抑制的示意图，其中相位选择器接收与输入时钟频率相同的4相时钟信号(图中未示出)并根据相位选择信号输出相应的时钟信号，相应的，乘法器的放大倍数为八，从而第一除法器的除数为八。第二除法器106的除数为二(2)。如图3所示，调制电路包括乘法器109’、差分累加调制器104’、第一除法器105’、累加器107’、加法器106’和第二除法器105’。其中乘法器109’的放大倍数为八(8)，第一除法器105’的除数为八(8)，加法器106’输出整数分频比序列到多模分频器101，第二除法器108输出相位选择信号到相位选择器102。In another embodiment, a schematic diagram of quantization noise suppression using a 4-phase clock signal can also be used, wherein a phase selector receives a 4-phase clock signal (not shown) having the same frequency as the input clock and outputs a corresponding clock signal according to the phase selection signal. Accordingly, the gain of the multiplier is eight, and thus the divisor of the first divider is eight. The divisor of the second divider 106 is two (2). As shown in FIG3 , the modulation circuit includes a multiplier 109 ′, a differential accumulator modulator 104 ′, a first divider 105 ′, an accumulator 107 ′, an adder 106 ′, and a second divider 105 ′. The gain of the multiplier 109 ′ is eight (8), the divisor of the first divider 105 ′ is eight (8), the adder 106 ′ outputs an integer frequency division ratio sequence to the multi-mode divider 101, and the second divider 108 outputs a phase selection signal to the phase selector 102.

多模分频器将输出时钟进行分频，能够实时实现整数分频，更新整数序列能够等效地实现小数分频。但是，整数分频比的累积与小数分频比的累积之间存在实时的误差，会在分频时钟上造成量化噪声。量化噪声的大小与实现的分频精度相关。本方案采用伪多相时钟对分频时钟进行采样，在累积误差接近多相时钟时，选择对应的相位进行采样，能够等效地提升分频精度，消除累积的误差，从而减小量化噪声。The multi-modulus divider divides the output clock and can realize integer division in real time. Updating the integer sequence can equivalently realize fractional division. However, there is a real-time error between the accumulation of integer division ratios and the accumulation of fractional division ratios, which will cause quantization noise on the divided clock. The size of the quantization noise is related to the achieved division accuracy. This scheme uses a pseudo-multiphase clock to sample the divided clock. When the accumulated error is close to the multiphase clock, the corresponding phase is selected for sampling, which can equivalently improve the division accuracy, eliminate the accumulated error, and thus reduce the quantization noise.

实施例二Embodiment 2

本申请公开了一种降低小数量化噪声的小数分频电路，如图4所示，其中示出了采用2相时钟信号进行量化噪声抑制。该小数分频电路包括多模分频器101’、第一触发器1031、第二触发器1032、相位选择器102’、以及调制电路。多模分频器101’用于接收输入时钟CKIN并根据整数分频比序列生成分频时钟CKDIV。第一触发器1031和第二触发器1032的数据端均耦合到多模分频器101’的输出端，第一触发器1031和第二触发器1032的时钟端分别耦合到与输入时钟频率相同的N相时钟信号。相位选择器102’分别耦合到第一触发器1031和第二触发器1032的输出并根据相位选择信号输出相应的时钟信号。The present application discloses a fractional frequency division circuit for reducing fractional quantization noise, as shown in FIG4 , which shows the use of a 2-phase clock signal for quantization noise suppression. The fractional frequency division circuit includes a multi-mode frequency divider 101 ', a first trigger 1031, a second trigger 1032, a phase selector 102 ', and a modulation circuit. The multi-mode frequency divider 101 'is used to receive an input clock CKIN and generate a frequency division clock CKDIV according to an integer frequency division ratio sequence. The data ends of the first trigger 1031 and the second trigger 1032 are both coupled to the output end of the multi-mode frequency divider 101 ', and the clock ends of the first trigger 1031 and the second trigger 1032 are respectively coupled to an N-phase clock signal with the same frequency as the input clock. The phase selector 102 'is respectively coupled to the outputs of the first trigger 1031 and the second trigger 1032 and outputs a corresponding clock signal according to the phase selection signal.

本一个实施例中，调制电路的调制电路包括乘法器、差分累加调制器、第一除法器、累加器、加法器和第二除法器，其中乘法器、差分累加调制器、第一除法器和加法器依次连接，累加器的输入耦合到第一除法器的输出，输出耦合到第二除法器的输入，乘法器的放大倍数为2N，第一除法器的除数为2N，第一除法器接收频率控制字的小数部分，加法器输出整数分频比序列，第二除法器输出相位选择信号。调制电路的结构可以采用实施例一中的调制结构，在此不再赘述。In one embodiment, the modulation circuit of the modulation circuit includes a multiplier, a differential accumulator modulator, a first divider, an accumulator, an adder and a second divider, wherein the multiplier, the differential accumulator modulator, the first divider and the adder are connected in sequence, the input of the accumulator is coupled to the output of the first divider, the output is coupled to the input of the second divider, the gain of the multiplier is 2N, the divisor of the first divider is 2N, the first divider receives the decimal part of the frequency control word, the adder outputs an integer frequency division ratio sequence, and the second divider outputs a phase selection signal. The structure of the modulation circuit can adopt the modulation structure in the first embodiment, which will not be repeated here.

本实施例中采用2相时钟信号进行量化噪声抑制，其中第一触发器1031和第二触发器1032的时钟端分别接收两相差分时钟信号，相应的乘法器的放大倍数为四(4)，第一除法器的除数为四(4)。In this embodiment, a two-phase clock signal is used for quantization noise suppression, wherein the clock ends of the first flip-flop 1031 and the second flip-flop 1032 receive two-phase differential clock signals respectively, the corresponding multiplier gain is four (4), and the divisor of the first divider is four (4).

应当理解，在本申请的其他实施例中，例如采用4相时钟信号进行量化噪声抑制时，降低小数量化噪声的小数分频电路包括四个触发器，每个触发器的数据端均耦合到多模分频器的输出端，时钟端各自耦合到4相时钟信号，输出端均耦合到多项选择器的输入端。It should be understood that in other embodiments of the present application, for example, when a 4-phase clock signal is used for quantization noise suppression, the fractional division circuit for reducing the fractional quantization noise includes four triggers, the data end of each trigger is coupled to the output end of the multi-mode divider, the clock end is respectively coupled to the 4-phase clock signal, and the output end is coupled to the input end of the multiple selector.

为了能够更好地理解本申请的技术方案，下面结合一个具体的例子来进行说明，该例子中罗列的细节主要是为了便于理解，不作为对本申请保护范围的限制。In order to better understand the technical solution of the present application, a specific example is provided below for illustration. The details listed in the example are mainly for ease of understanding and are not intended to limit the scope of protection of the present application.

本方案的降低小数量化噪声的小数分频电路的实现包括相位选择电路以及相应控制信号的产生，分别如图1、2所示。The implementation of the fractional frequency division circuit for reducing the fractional quantization noise of the present solution includes a phase selection circuit and generation of corresponding control signals, as shown in FIGS. 1 and 2 respectively.

多模分频器101将输入时钟CKIN根据分频比进行分频并输出时钟CKDIV。相位选择器MUX的两个输出时钟为与多模分频器输入信号同频的差分信号，根据相位选择信号输出对应的信号给到DFF作为时钟，对CKDIV进行重定时输出时钟CKOUT。The multi-mode divider 101 divides the input clock CKIN according to the division ratio and outputs the clock CKDIV. The two output clocks of the phase selector MUX are differential signals with the same frequency as the multi-mode divider input signal. The corresponding signal is output according to the phase selection signal and given to the DFF as a clock. CKDIV is retimed to output the clock CKOUT.

小数分频器(频率控制字(FCW)的小数部分)首先被放大器放大四倍，再输入到差分累加调制器。差分累加调制器输出的分频比需要被第一除法器右移两位，小数部分进入到累加器，整数部分进入加法器。累加器的累加结果sum被第二除法器右移一位取整数部分作为相位选择的控制信号(即，相位选择信号)，累加器的进位信号co与差分累加调制器输出分频比右移两位的整数部分相加作为整数分频比序列控制多模分频器。The fractional frequency divider (the fractional part of the frequency control word (FCW)) is first amplified four times by the amplifier and then input to the differential accumulator modulator. The frequency division ratio output by the differential accumulator modulator needs to be right-shifted by two bits by the first divider, the fractional part enters the accumulator, and the integer part enters the adder. The accumulated result sum of the accumulator is right-shifted by one bit by the second divider to take the integer part as the control signal for phase selection (i.e., phase selection signal), and the carry signal co of the accumulator is added to the integer part of the frequency division ratio output by the differential accumulator modulator that is right-shifted by two bits as the integer frequency division ratio sequence to control the multi-mode frequency divider.

通过产生相位选择信号提升分频器输出信号的相位精度，降低量化噪声。采用四分之一量化噪声缩小的差分累加调制器实现两相差分的量化噪声抑制。该相位选择信号产生方式可以拓展成更多的相位。By generating a phase selection signal, the phase accuracy of the divider output signal is improved and the quantization noise is reduced. The differential accumulator modulator with a quarter quantization noise reduction is used to achieve quantization noise suppression of two-phase differential. This phase selection signal generation method can be expanded to more phases.

本方案在只有差分(两相位)信号的情况下采用了四分之一量化噪声缩小的差分累加器产生相位选择信号，相比于传统的采用两相差分信号实现二分之一量化噪声缩小方案能够降低高频的量化噪声，实现整体量化噪声的改善。相对于产生N相位信号实现N分之一量化噪声缩小的方案，本方案能够在相同相位信号输入的情况下实现进一步的量化噪声缩小。This solution uses a differential accumulator with a quarter quantization noise reduction to generate a phase selection signal when there is only a differential (two-phase) signal. Compared with the traditional solution of using a two-phase differential signal to achieve a half quantization noise reduction, it can reduce high-frequency quantization noise and improve the overall quantization noise. Compared with the solution of generating N-phase signals to achieve a one-N quantization noise reduction, this solution can achieve further quantization noise reduction when the same phase signal is input.

需要说明的是，在本专利的申请文件中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个”限定的要素，并不排除在包括所述要素的过程、方法、物品或者设备中还存在另外的相同要素。本专利的申请文件中，如果提到根据某要素执行某行为，则是指至少根据该要素执行该行为的意思，其中包括了两种情况：仅根据该要素执行该行为、和根据该要素和其它要素执行该行为。多个、多次、多种等表达包括2个、2次、2种以及2个以上、2次以上、2种以上。It should be noted that in the application documents of this patent, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "including one" do not exclude the existence of other identical elements in the process, method, article or device including the elements. In the application documents of this patent, if it is mentioned that an action is performed according to an element, it means that the action is performed at least according to the element, which includes two situations: performing the action only according to the element, and performing the action according to the element and other elements. Expressions such as multiple, multiple, and multiple include 2, 2 times, 2 kinds, and more than 2, more than 2 times, and more than 2 kinds.

可以在本文中使用术语“耦合到”及其派生词。“耦合”可以表示两个或更多个元件直接物理或电接触。然而，“耦合”还可以意味着两个或更多个元件间接地彼此接触，但是仍然彼此协作或相互作用，并且可以意味着一个或多个其他元件在被称为彼此耦合的元素之间耦合或连接。The term "coupled to" and its derivatives may be used herein. "Coupled" may mean that two or more elements are in direct physical or electrical contact. However, "coupled" may also mean that two or more elements are in indirect contact with each other, but still cooperate or interact with each other, and may mean that one or more other elements are coupled or connected between the elements referred to as being coupled to each other.

本说明书包括本文所描述的各种实施例的组合。对实施例的单独提及(例如“一个实施例”或“一些实施例”或“优选实施例”)不一定是指相同的实施例；然而，除非指示为是互斥的或者本领域技术人员很清楚是互斥的，否则这些实施例并不互斥。应当注意的是，除非上下文另外明确指示或者要求，否则在本说明书中以非排他性的意义使用“或者”一词。This specification includes combinations of the various embodiments described herein. Individual references to an embodiment (e.g., "one embodiment" or "some embodiments" or "preferred embodiments") do not necessarily refer to the same embodiment; however, these embodiments are not mutually exclusive unless indicated as mutually exclusive or it is clear to a person skilled in the art that they are mutually exclusive. It should be noted that the word "or" is used in this specification in a non-exclusive sense unless the context clearly indicates or requires otherwise.

在本说明书提及的所有文献都被认为是整体性地包括在本申请的公开内容中，以便在必要时可以作为修改的依据。此外应理解，以上所述仅为本说明书的较佳实施例而已，并非用于限定本说明书的保护范围。凡在本说明书一个或多个实施例的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本说明书一个或多个实施例的保护范围之内。All documents mentioned in this specification are considered to be included in the disclosure of this application as a whole, so that they can be used as a basis for modification when necessary. In addition, it should be understood that the above is only a preferred embodiment of this specification and is not intended to limit the scope of protection of this specification. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of one or more embodiments of this specification should be included in the scope of protection of one or more embodiments of this specification.