CN119125859A - A high-security chip scan chain test mode circuit and entry method - Google Patents

The invention discloses a high-safety chip scan chain test mode circuit and an entering method, relating to the field of integrated circuit design, and comprising a boundary scan test interface, a boundary scan test interface controller, a data register, a first data selector, a second data selector, an instruction decoder and an instruction register; the data register comprises an equipment mark register, a boundary scanning register, a bypass register and a test register, wherein the test register comprises N stages of test registers and M encoding and decoding modules, the encoding and decoding modules are used for generating read-write enabling signals of each stage of test registers, and the instruction register and the encoding and decoding modules are used for opening read-write permission of the test registers.

High-safety chip scan chain test mode circuit and entry method

Technical Field

The present invention relates to the field of integrated circuit design, and in particular, to a high security chip scan chain test mode circuit and access method.

Background

In the scan chain test mode, almost all registers inside the chip are connected together in a serial mode, and the values of the registers can be shifted in and out from the PAD in a shifting mode, so that the values of any registers inside the chip can be configured and observed through the scan chain, and the potential safety hazard is brought to the chip.

The existing scan chain test mode mainly comprises two modes, namely a mode of applying a fixed level on a specific pin, a mode of being too simple and extremely easy to attack a chip from outside by using a scan chain to steal information in the chip, and a mode of multiplexing JTAG ports and entering a scan chain test mode by configuring an Instruction register (Instruction Reg) and a Data register (Data Reg), wherein compared with the first mode, the mode has greatly improved safety and still has room for improvement.

The background description provided herein is for the purpose of generally presenting the context of the disclosure. Unless otherwise indicated herein, the materials described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.

Disclosure of Invention

Aiming at the technical problems in the related art, the invention provides a high-safety chip scan chain test mode circuit and an entering method.

In order to achieve the aim of the invention, the invention adopts the following technical scheme:

In a first aspect, the present invention provides a high security chip scan chain test mode circuit, the chip scan chain test mode circuit comprising a boundary scan test interface, a boundary scan test interface controller, a data register, a first data selector, a second data selector, an instruction decoder, and an instruction register; the boundary scan test interface is used for receiving test data and outputting the test data, the boundary scan interface controller is used for generating control signals of the instruction register and the data register, controlling the instruction register and the data register to capture, shift and update data, the instruction register is used for storing instructions to be executed, the instruction decoder is used for encoding and decoding the instructions to be executed, the data register comprises a boundary scan register and a test register, the boundary scan register is used for boundary scan test, the test register comprises N stages of test registers and M encoding and decoding modules, each stage of test registers is composed of one or more groups of registers, the encoding and decoding modules are used for generating read-write enabling signals of each stage of test registers, and the read-write permission of the test registers is opened through the instruction register and the encoding and decoding modules, wherein M is equal to N, and N is a positive integer greater than or equal to 2;

The boundary scan test interface is connected with a boundary scan test interface controller, a data register and an instruction register, the instruction register is connected with the data register through an instruction decoder, the data register and the data decoder are connected with a first data selector, the boundary scan test interface controller, the instruction register and the first data selector are connected with a second data selector, and the second data selector is connected with the boundary scan test interface;

the method comprises the steps that an instruction which is input into an instruction register is decoded by an instruction decoder to generate a control signal to control a data register and a first data selector;

The boundary scan test interface comprises a test data input end, a test data output end, a test mode selection end, a test clock end and a test reset end.

Specifically, the boundary scan test interface controller is a finite state transducer, generates control signals of the instruction register and the data register, and controls the instruction register and the data register to capture, shift and update data.

Specifically, the test mode selection terminal pulled up by 5 clock cycles may be regarded as a reset signal to make the boundary scan test interface controller enter a reset state.

Specifically, the test reset terminal is used for sending a reset signal to enable the boundary scan test interface controller to enter a reset state.

Specifically, the data register further comprises a bypass register, and the bypass register is 1-bit.

Specifically, the data register further comprises a device flag register, and the device flag register is 32-bit.

Specifically, each stage of test register in the test registers is a 1-bit or multi-bit register.

The read-write permission of the test register is obtained after all values of the test register of the previous level are correctly configured, and whether the chip enters a scanning link mode or not can be determined through the encoding and decoding module after all values of the test register of the last level are correctly configured.

The method comprises the steps that when all values of a test register of a last level are configured correctly, the read-write permission of a test register of a next level can be obtained, when all values of the test register of a last level are configured correctly, whether a chip enters a scanning link mode or not can be determined through a coding and decoding module, specifically, the test register comprises a first-stage test register, a second-stage test register, a first coding and decoding module and a second coding and decoding module, the first-stage test register comprises n register groups, the second-stage test register comprises m register groups, the read-write permission of the first-stage test register is opened through an instruction register, when the first-stage test register is configured to be the correct value, the first coding and decoding module generates a read-write permission of the second-stage test register under the combined action of the second-stage test enable signal and the instruction register, when the second-stage test register is configured to be the correct value, the second coding and decoding module generates a scanning link test enable signal, and the chip enters the scanning link test mode, wherein m is equal to or more than 3.

In a second aspect, the present invention provides a high security chip scan chain test mode entry method, based on the high security chip scan chain test mode circuit of any one of the first aspects, the method comprising the steps of:

state1, the test reset signal is low level, the boundary scan test interface controller, the instruction register and the data register are in reset state, the data or instructions can not be loaded in series from the test data input end in the state, and the output of the instruction register and the data register keeps the reset value;

state2, the test reset end signal is pulled high, and the boundary scan test interface controller is controlled to perform state transition through the test mode selection end signal and the test clock end;

state3, keeping the value of the test mode selection end unchanged when the boundary scan test interface controller is in the Shift-IR state, loading a specific instruction in series from the test data input end, and opening the read-write permission of a specific first stage test register when the state machine is switched to the Update-IR state;

state4, loading test data from the test data input end in serial under the Shift-DR state, and configuring a first stage test register, and circulating state3 to state4 until all values in a register group in the first stage test register are configured, wherein the chip acquires the read-write permission of a second stage test register;

state5, keeping the value of the test mode selection end unchanged when the TAP Controller is in the Shift-IR state, loading a specific instruction in series from the test data input end, and opening the read-write permission of a specific second-stage test register when the state machine is switched to the Update-IR state;

state6, loading test data from the test data input end TDI in series in the Shift-DR state, and configuring a second stage test register, and cycling state5 to state6 until all values in the register group in the second stage test register are configured;

state7, the chip enters a scan chain test mode.

The invention divides the register for test into two or more grades, each grade is composed of one or more groups of 1bit or multi bit registers, the read-write permission of the register of the next grade can be obtained only after the values of the registers of the last grade are all configured correctly, the value of the register of the last grade is determined to enter a scan chain test mode or other test modes after passing through the encoding and decoding module, the entry difficulty of the scan chain test mode is increased, and the safety performance of the chip is improved.

The invention multiplexes JTAG ports, reduces the pin number required by test, increases the difficulty of entering a scan chain test mode, and improves the safety performance of chips.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of a high security chip scan chain test mode circuit according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of a boundary scan test interface controller state transition provided in accordance with an embodiment of the present invention;

FIG. 3 is a schematic diagram of a scan chain test mode circuit provided according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of a high security chip scan chain test mode entry method according to an embodiment of the present invention;

wherein the interface comprises a 1-boundary scan test interface, a 2-boundary scan test interface controller, a 3-data register, a 4-first data selector, a 5-second data selector, a 6-instruction decoder, a 7-instruction register, an 8-device flag register, a 9-boundary scan register, a 10-bypass register and an 11-test register.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which are derived by a person skilled in the art based on the embodiments of the invention, fall within the scope of protection of the invention.

Embodiment one.

Referring to fig. 1, the present embodiment provides a high-security chip scan chain test mode circuit, which includes a boundary scan test interface 1 (TAP), a boundary scan test interface Controller 2 (TAP Controller), the Data register 3 (Data Reg), a first Data selector 4, a second Data selector 5, an Instruction decoder 6 (IRDecoder), and an Instruction register 7 (Instruction Reg);

The instruction register 7 is used to store instructions to be executed, and the instruction decoder 6 decodes the instructions to be executed.

The first data selector 4 and the second data selector 5 are multiplexers;

A Multiplexer (MUX) is an electronic device, and the main function is to select one of a plurality of input signals to output.

The boundary scan test interface 1 is connected with the boundary scan test interface controller 2, the data register 3 and the instruction register 7, the instruction register 7 is connected with the data register 3 through the instruction decoder 6, the data register 3 and the data decoder 6 are connected with the first data selector 4, the boundary scan test interface controller 2, the instruction register 7 and the first data selector 4 are connected with the second data selector 5, the second data selector 5 is connected with the boundary scan test interface 1, and the control signal is generated after the instruction decoder 6 decodes the input instruction in the instruction register 7 to control the data register 3 and the first data selector 4.

Specifically, the first end of the boundary scan test interface 1 is a test data output end, the second end of the boundary scan test interface 1 is a test data input end, the third end of the boundary scan test interface 1 is a test reset end, the fourth end of the boundary scan test interface 1 is a test mode selection end, the fifth end of the boundary scan test interface 1 is a test clock end, the boundary scan test interface controller 2, the first end of the boundary scan test interface controller 2 is electrically connected with the sixth end of the boundary scan test interface 1, the second end of the boundary scan test interface controller 2 is electrically connected with the seventh end of the boundary scan test interface 1, the third end of the boundary scan test interface controller 2 is electrically connected with the eighth end of the boundary scan test interface 1, the first end of the data register 3 is electrically connected with the ninth end of the boundary scan test interface 1, the second end of the data register 3 is electrically connected with the first end of the data register 3, the fourth end of the data register 3 is electrically connected with the fourth end of the data register 4, the data register 3 is electrically connected with the fourth end of the data register 3, the data register is electrically connected with the fourth end of the data register 3, and the fourth end of the data register is electrically connected with the fourth end of the data register 3, a second data selector 5, wherein the first end of the second data selector 5 is electrically connected with the fifth end of the first data selector 4, the second end of the second data selector 5 is electrically connected with the tenth end of the boundary scan test interface 1, and the third end of the second data selector 5 is electrically connected with the fifth end of the boundary scan test interface controller 2;

Specifically, the first end of the instruction decoder 6 is electrically connected to the tenth end of the data register 3, the second end of the instruction decoder 6 is electrically connected to the sixth end of the first data selector 4, the first end of the instruction register 7 is electrically connected to the fourth end of the data register 3, the second end of the instruction register 7 is electrically connected to the sixth end of the boundary scan test interface controller 2, the third end of the instruction register 7 is electrically connected to the third end of the instruction decoder 6, the fourth end of the instruction register 7 is electrically connected to the fourth end of the instruction decoder 6, the fifth end of the instruction register 7 is electrically connected to the fifth end of the instruction decoder 6, and the sixth end of the instruction register 7 is electrically connected to the fourth end of the second data selector.

The boundary scan test interface 1 may be 4 pins or 5 pins, and the boundary scan test interface 1 includes a test data input end (TDI), a test data output end (TDO), a test mode selection end (TMS), a test clock end (TCK), and a test reset end (TRST), where the test reset end can reset the boundary scan test interface controller 2, and pulling the test mode selection end up by 5 clock cycles can also enable the boundary scan test interface controller 2 to enter a reset state, so the test reset end is an optional interface;

preferably, in this embodiment, the scan test interface 1 is 5 pins, and the test reset terminal is an optional port.

The boundary scan test interface controller 2 is a 16-state finite state transducer, generates control signals of the Instruction register 7 (Instruction Reg) and the Data register 3 (Data Reg), and controls the Instruction register 7 and the Data register 3 to Capture, shift and Update Data.

The 16 states of the boundary Scan Test interface controller include: test-Logic-Reset, run-Test/Idle, select-DR-Scan, capture-DR, shift-DR, exit1-DR (Exit data register state 1), pause-DR (Pause data register state), exit2-DR (Exit data register state 2), update-DR (data register refresh), select-IR-Scan (Select instruction register Scan), capture-IR (Capture instruction register), shift-IR (instruction register Shift), exit1-IR (Exit instruction register state 1), pause-IR (Pause instruction register state), exit2-IR (Exit instruction register state 2), update-IR (instruction register refresh).

Specifically, as shown in fig. 2, the state transition diagram of the boundary scan test interface controller 2 controls the boundary scan test interface controller 2 to perform state transition at the rising edge of the test clock end by the test mode selection end. In the Capture state, data or instructions are loaded in parallel into the selected data register 3 or instruction register 7, in the Shift state, data or instructions are loaded in series into the selected data register 3 or instruction register 7 through the test data input while previous data or instructions are output in series from the test data output, and in the Update state, current data or instructions are updated.

The data register 3 comprises an equipment mark register 8 (IDCODE Reg), a boundary scan register 9 (Boundary Scan Reg), a Bypass register 10 (Bypass Reg) and a Test register 11 (Test Reg), wherein the Bypass register is 1-bit in JTAG standard protocol, the data path can be selected through a Bypass instruction, and the equipment mark register is 32-bit and is selectable.

The boundary scan register 9 is used for boundary scan testing, the bypass register 10 is used for bypassing boundary scan logic, connecting the input of the chip to the output through its internal 1-bit register, and the device flag register 8 is used for storing the identity information of the chip.

Specifically, the first end of the device flag register 8 is electrically connected to the ninth end of the boundary scan test interface 1, the second end of the device flag register 8 is electrically connected to the first end of the first data selector 4, the first end of the boundary scan register 9 is electrically connected to the first end of the device flag register 8, the second end of the boundary scan register 9 is electrically connected to the second end of the first data selector 4, the first end of the bypass register 10 is electrically connected to the first end of the boundary scan register 9, the second end of the bypass register 10 is electrically connected to the third end of the first data selector 4, the first end of the test register 11 is electrically connected to the first end of the bypass register 10, and the second end of the test register 11 is electrically connected to the fourth end of the first data selector 4.

The test register 11 is a register that needs to be used when the chip is tested, and the output of the register can generate key signals needed when the chip is tested through encoding and decoding (decoding).

The test register 11 includes N-level test registers and M codec modules, each level of test registers is composed of one or more groups of registers, the codec modules are used for generating a read-write enabling signal of each level of test registers, and the read-write permission of the test registers is opened through the instruction register and the codec modules, wherein M is equal to N and N is a positive integer greater than or equal to 2, and preferably, in this embodiment, both values of M and N are 2.

The read-write permission of the test register of the next level can be obtained after the values of the test register of the previous level are all configured correctly, and whether the chip enters a scanning link mode can be determined through the encoding and decoding module after the values of the test register of the last level are all configured correctly;

Wherein each stage of test register is a 1-bit or multi-bit register.

Referring to fig. 3, the test register 11 includes a first stage test register, a second stage test register, a first codec module and a second codec module, where the first stage test register includes n register sets, the second stage test register includes m register sets, the read-write permission of the first stage test register is opened through the instruction register, when the first stage test register is configured to be a correct value, the first codec module generates the read-write permission of the second stage test register by the combined action of the second stage test register read-write enable signal and the instruction register 7, and when the second stage test register is configured to be a correct value, the second codec module generates the scan chain test enable signal, and the chip enters the scan chain test mode, where m and n are positive integers greater than or equal to 3, and preferably, m and n are both 3.

FIG. 3 is an improved scan chain Test mode circuit, which is shown as dividing the Test registers into two levels, a first level Test register (level 1 Test Reg) and a second level Test register (level 2 Test Reg), and the first level Test registers comprise a plurality of groups of registers of group 1, group 2. The second-stage Test register includes a plurality of register groups of group 1, group 2. The read-write permission of the first stage Test register can be opened through the instruction register 7, when the first stage Test register is configured to be a correct value, the first codec module (Decode 1) generates a second stage Test register read-write enable signal (level 2 Test Reg W/R enable), the signal and the instruction register 7 act together, the read-write permission of the second stage Test register is opened, and when the second stage Test register is configured to be a correct value, the second codec module (Decode 2) generates a Scan chain Test enable signal (Scan Test enable) and the chip enters a Scan chain Test mode.

The embodiment provides a specific implementation mode of entering a scan chain test mode through a test register, which is as follows:

The instruction register is a group of 8-bit registers, the test register is divided into a first stage and a second stage, the first stage test register comprises three groups of 8-bit register groups of group 1, group 2 and group 3, when the value of the instruction register is configured to be 0x01, the group 1 can be connected in series between TDI and TDO, when the value of the instruction register is configured to be 0x02, the group 2 can be connected in series between TDI and TDO, when the value of the instruction register is configured to be 0x03, the group 3 can be connected in series between TDI and TDO, and when the value of the group 1 is configured to be 0x55, the value of the group 2 is configured to be 0x22, and when the value of the group 3 is configured to be 0x77, the read-write permission of the second stage test register can be obtained.

The second level test register comprises three 8bit register groups of group 1, group 2 and group 3, wherein when the value of the instruction register is configured to be 0x04, the group 1 can be connected in series between TDI and TDO, when the value of the instruction register is configured to be 0x05, the group 2 can be connected in series between TDI and TDO, when the value of the instruction register is configured to be 0x06, the group 3 can be connected in series between TDI and TDO, and when the value of the group 1 is configured to be 0x25, the value of the group 2 is configured to be 0x26, and the value of the group 3 is configured to be 0x27, the chip enters a scan chain test mode.

In this embodiment, the test registers are divided into two or more levels, each level is composed of one or more groups of 1-bit or multi-bit registers, the read-write permission of the next level of registers can be obtained only after the values of the registers of the previous level are all configured correctly, and the value of the register of the last level is determined whether the chip enters the scan chain test mode or other test modes after passing through the encoding and decoding module.

Embodiment two.

Referring to fig. 4, the present embodiment provides a high-security chip scan chain test mode entry method of a high-security chip scan chain test mode circuit according to the first embodiment, including the steps of:

state1, the test reset terminal TRST signal is at low level, the boundary scan test interface Controller TAP Controller, the Instruction register Instruction Reg and the Data register Data Reg are in reset state, under this state, data or instructions cannot be loaded in series from the test Data input terminal TDI, and the output of the Instruction register Instruction Reg and the Data register Data Reg keep reset values;

state2, the TRST signal of the test reset terminal is pulled up, and the TAP Controller is controlled to perform state transition through the TMS signal of the test mode selection terminal and the TCK of the test clock terminal;

state3, keeping the value of the test mode selection terminal TMS unchanged when the TAP Controller is in the Shift-IR state, loading a specific instruction from the test data input terminal TDI in series, and opening the read-write permission of a specific first-stage test register when the state machine is switched to the Update-IR state;

state4, loading test data from the test data input end TDI in series in the Shift-DR state, and configuring a first stage test register, and cycling state3 to state4 until all the values of register groups group 1 to group n in the first stage test register are configured, wherein the chip acquires the read-write permission of a second stage test register;

state5, keeping the value of the test mode selection terminal TMS unchanged when the TAP Controller is in the Shift-IR state, loading a specific instruction from the test data input terminal TDI in series, and opening the read-write permission of a specific second-stage test register when the state machine is switched to the Update-IR state;

state6, loading test data from the test data input end TDI in series in the Shift-DR state, and configuring a second stage test register, and cycling state5 to state6 until all values of register groups group 1 to group m in the second stage test register are configured;

state7, the chip enters a scan chain test mode.

The JTAG port is multiplexed, the pin number required by the test is reduced, the entering difficulty of a scan chain test mode is increased, and the safety performance of the chip is improved.

The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, alternatives, and improvements that fall within the spirit and scope of the invention.