CN119182695A - Delay detection method and device - Google Patents

本申请提供了延迟检测方法，涉及通信技术领域，该方法在第一NIC发送检测码和检测报文后，经过预设周期才开启开关矩阵，使得第二NIC一开始接收到不完整的检测报文。在第二NIC接收到不完整的检测报文的情况下，第一NIC发送更长的检测码，以使得第二NIC更可能接收到完整的检测报文。在第二NIC接收到完整的检测报文时，根据这一次第一NIC发送的检测码的位数和预设周期，可以得到第一NIC与交换机之间的延迟。相比于专用测量仪器的方案，本申请实施例可以实现延迟的“在线检测”，并且提高了检测效率和准确性。

The present application provides a delay detection method, which relates to the field of communication technology. After the first NIC sends a detection code and a detection message, the method turns on the switch matrix after a preset period, so that the second NIC receives an incomplete detection message at the beginning. In the case where the second NIC receives an incomplete detection message, the first NIC sends a longer detection code so that the second NIC is more likely to receive a complete detection message. When the second NIC receives the complete detection message, the delay between the first NIC and the switch can be obtained based on the number of bits of the detection code sent by the first NIC this time and the preset period. Compared with the solution of a dedicated measuring instrument, the embodiment of the present application can realize "online detection" of delay and improve detection efficiency and accuracy.

Delay detection method and device

Technical Field

The present application relates to the field of communications technology, and more particularly, to a delay detection method, apparatus, computing device, computer program product, and computer readable storage medium.

Background

The communication system may include a plurality of Network Interface Cards (NICs), switches, and controllers. The NIC may be configured to interface with a user device or a server, and convert traffic data into optical signals or electrical signals for exchange with a switch. For example, the switch may include a switch matrix, and different transmission links are mapped by controlling on or off of corresponding switches in the switch matrix, so as to implement many-to-many transmission. The controller may control the time when the NIC sends data and the opening and closing of the switch matrix to implement switching of the transmission link.

It is important to accurately measure the delay between the NIC and the switch. For example, in order to prevent the messages of each transmission link from losing subsequent data due to the variation of the switch matrix when partially passing through the switch, it is required that the messages of all transmission links pass through the switch in one slice (slice) period. In other words, the slicing period needs to be set large enough to cover the time for each transmission link to transmit a message. However, the delay of each transmission link is often different, if the message of the transmission link with high delay is sent later, the message of the transmission link with low delay is sent earlier, and when the two messages are transmitted in the links simultaneously, the slicing period needs to cover both the link which is sent earlier and transmitted faster and the link which is sent later and transmitted slower, so that the slicing period is increased. Conversely, the message of the transmission link with high delay is sent first, and the message of the transmission link with low delay is sent later, so that the slicing period can be reduced, and more messages can be sent in the same time.

However, the related technical scheme only adopts a special measuring instrument to carry out off-line measurement on the delay of the connecting line between the NIC and the switch, and cannot accurately measure the delay between the NIC and the switch in the actual application scene.

Therefore, how to accurately detect the delay between NIC and switch is a challenge.

Disclosure of Invention

The application provides a delay detection method which can accurately detect delay between NIC and a switch.

In a first aspect, a delay detection method is provided, including controlling a first Network Interface Card (NIC) to continuously send a first detection code and a first detection message to a second NIC through a switch matrix of a switch at a first time, wherein the first detection code is sent before the first detection message, starting the switch matrix when a preset period is set from the first time, wherein the switch matrix is closed after the second NIC receives the first detection message, controlling the first network interface card NIC to continuously send a second detection code and a second detection message to the second NIC through the switch matrix of the switch at a second time when the second NIC receives the first detection message, wherein the number of bits of the second detection code is larger than that of the first detection code, the length of the second detection message is equal to that of the first detection message, starting the switch matrix when the preset period is set from the second time, wherein the switch matrix is opened when the preset period is set from the second time, and the switch matrix is opened after the second NIC receives the second detection message, and the second detection message is delayed according to the preset period when the second NIC receives the second detection message.

In the embodiment of the application, after the first NIC sends the detection code and the detection message, the switch matrix is started after a preset period, so that the second NIC initially receives the incomplete detection message. In the case that the second NIC receives an incomplete detection message, the first NIC sends a longer detection code, so that the second NIC is more likely to receive the complete detection message. When the second NIC receives the complete detection message, the delay between the first NIC and the switch can be obtained according to the number of bits of the detection code sent by the first NIC and the preset period. Compared with the scheme of a special measuring instrument, the embodiment of the application can realize delayed online detection and improve the detection efficiency and accuracy.

With reference to the first aspect, in certain implementations of the first aspect, the switch matrix includes an optical switch matrix.

The method provided by the embodiment of the application can be applied to the optical switch with the optical switch matrix, and the delay detection method has wide application scene and strong applicability.

With reference to the first aspect, in some implementations of the first aspect, determining the delay between the first NIC and the switch according to the number of bits of the second detection code and the preset period includes determining an additional delay caused by adding the second detection code according to the number of bits of the second detection code, and determining the delay between the first NIC and the switch according to the additional delay and the preset period.

In the embodiment of the application, the accurate detection of the delay is realized according to the additional delay caused by sending the detection code and the preset period.

With reference to the first aspect, in certain implementation manners of the first aspect, determining the delay between the first NIC and the switch according to the number of bits of the second detection code and the preset period includes determining the delay between the first NIC and the switch according to the following formula:

T_delay＝ΔT_switch-ΔT_n;

Where T _delay is the delay between the first NIC and the switch, Δt _switch is the predetermined period, and Δt _n is the additional delay.

In the embodiment of the application, the accurate detection of the delay is realized according to the additional delay caused by sending the detection code and the preset period.

With reference to the first aspect, in some implementations of the first aspect, determining an additional delay caused by adding the second detection code according to the number of bits of the second detection code includes determining the additional delay according to the number of bits of the second detection code and a rate at which the first NIC transmits the second detection code.

According to the embodiment of the application, the extra delay can be determined according to the bit number of the detection code and the sending rate of the first NIC, so that the accurate detection of the delay between the first NIC and the switch is realized.

With reference to the first aspect, in certain implementations of the first aspect, a difference between the number of bits of the second detection code and the number of bits of the first detection code is 1.

In the embodiment of the application, the bit number of the detection code added each time can be 1, thereby realizing picosecond detection and improving the accuracy of delay detection.

With reference to the first aspect, in some implementations of the first aspect, the method further includes controlling the first NIC to send a third detection code and a third detection message to the second NIC through the switch matrix of the switch at a third time when the second NIC receives the incomplete second detection message, wherein a bit number of the third detection code is greater than a bit number of the second detection code, a length of the third detection message is equal to a length of the first detection message, opening the switch matrix when the preset period is spaced from the third time, wherein the switch matrix is closed after the second NIC receives the third detection message, and determining a delay between the first NIC and the switch according to the bit number of the third detection code and the preset period when the second NIC receives the complete third detection message.

By continuously increasing the length of the detection code until the second NIC can receive the complete detection message, the detection method provided by the embodiment of the application can accurately detect the delay between the first NIC and the switch.

With reference to the first aspect, in some implementations of the first aspect, the number of bits of 0 and 1 in the second detection code is similar.

In the embodiment of the application, the bit numbers of 0 and 1 in the detection code are similar, and the equalization of 0 and 1 in the link can be realized, thereby reducing the error rate of the NIC.

With reference to the first aspect, in some implementations of the first aspect, the second detection message includes an indication field, where the indication field is used to indicate a number of bits of the second detection code, and the method further includes determining, according to the second detection message, the number of bits of the second detection code.

The detection message can comprise an indication field, the indication field can indicate the number of bits of the detection code before the detection message, delay calculation is convenient, and detection efficiency is improved.

In a second aspect, an embodiment of the present application provides a delay detection device, which includes a module for implementing the first aspect or any one of the possible implementations of the first aspect.

In a third aspect, a computing device is provided, comprising a processor and a memory, the processor being configured to execute instructions stored in the memory, to cause the computing device to perform the delay detection method of the first aspect or any one of the possible implementations of the first aspect.

In a fourth aspect, there is provided a computer program product comprising instructions which, when executed by a computing device, cause the computing device to perform the method of delay detection of the first aspect or any one of the possible implementations of the first aspect.

In a fifth aspect, a computer readable storage medium is provided, comprising computer program instructions which, when executed by a computing device, perform the delay detection method of the first aspect or any one of the possible implementations of the first aspect.

Drawings

Fig. 1 is a schematic block diagram of an architecture of a switching network provided by an embodiment of the present application.

Fig. 2 is a schematic diagram of a message transmission according to an embodiment of the present application.

Fig. 3 is a schematic flow chart of a delay detection method according to an embodiment of the present application.

Fig. 4 is a schematic diagram of a delay detection method according to an embodiment of the present application.

Fig. 5 is a schematic flow chart of another delay detection method according to an embodiment of the present application.

Fig. 6 is a schematic block diagram of a delay detection device according to an embodiment of the present application.

FIG. 7 is a schematic block diagram of a computing device provided by an embodiment of the present application.

Detailed Description

The technical scheme of the application will be described below with reference to the accompanying drawings.

The present application will present various aspects, embodiments, or features about a system that may include a plurality of devices, components, modules, etc. It is to be understood and appreciated that the various systems may include additional devices, components, modules, etc. and/or may not include all of the devices, components, modules etc. discussed in connection with the figures. Furthermore, combinations of these schemes may also be used.

In addition, in the embodiments of the present application, words such as "exemplary," "for example," and the like are used to indicate an example, instance, or illustration. Any embodiment or design described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments or designs. Rather, the term use of an example is intended to present concepts in a concrete fashion.

The service scenario described in the embodiment of the present application is for more clearly describing the technical solution of the embodiment of the present application, and does not constitute a limitation on the technical solution provided by the embodiment of the present application, and as a person of ordinary skill in the art can know that, with the appearance of a new service scenario, the technical solution provided by the embodiment of the present application is applicable to similar technical problems.

Reference in the specification to "one embodiment" or "some embodiments" or the like means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the application. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," and the like in the specification are not necessarily all referring to the same embodiment, but mean "one or more but not all embodiments" unless expressly specified otherwise. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless expressly specified otherwise.

Fig. 1 is a schematic block diagram of an architecture of a switching network provided by an embodiment of the present application. Among them, the controller 110 is communicatively connected to a plurality of Network Interface Cards (NICs) 120, a switch 130, and a plurality of NICs 140. The plurality of NICs 120 are connected to the plurality of NICs 140 through the switch 130. Each NIC is connected to the switch 130 by a connection 150.

In some embodiments, NIC 120 may send a message to NIC 140 through switch 130. NIC 120 and NIC 140 may be the same NIC or a group of NICs, and NIC 140 may send messages to NIC 120 via switch 130.

In some embodiments, the controller 110 may control the time synchronization of the high precision clocks of the various portions of the switching network 100 to achieve that the various portions operate at the same cadence. In some embodiments, the controller 110 may also control the time at which the NIC 120 sends data and the switching time of the switch matrix in the switch 130.

The switch 130 may include a switch matrix. For example, the switch 130 may comprise an optical switch matrix, in which case the switch 130 may also be referred to as an optical switch or an optical switch matrix, and the connection lines 150 may be optical fibers. The optical switching matrix may perform the function of optical packet switching.

It should be noted that the present application is not limited to a specific type of switch, for example, the switch 130 may also include an electrical switch matrix, in which case the switch 130 may be referred to as an electrical switch.

The NIC may be used to interface with a user device or server to convert traffic data into optical signals for switching to the switch 110. The optical switch may include an optical switch matrix, and the corresponding optical switch is controlled to be turned on or off by a control signal input from the controller 110, so that different optical paths may be generated, thereby implementing many-to-many transmission according to the different optical paths.

The NIC may include a switch interface circuit (fabric interface circuit, FIC) and an optoelectronic module (optical/ELECTRICAL MODULE, OE). The FIC may enable communication between the user network interface to the switching network interface, and the FIC may include an upstream processing unit (iFIC) and a downstream processing unit (eFIC). The OE may convert optical signals on the transmission link into electrical signals, or electrical signals on the transmission link into optical signals. For example, in the context of an optical switch matrix, NIC 120 includes an ifec, an optical signal converted from an electrical signal at the iFIC output by an OE is sent to the optical switch matrix for optical switching, NIC 140 includes an eFIC, and an optical signal converted from an electrical signal at eFIC is sent out of switching network 100.

In order to prevent the messages of each transmission link from losing subsequent data due to the variation of the switch matrix when partially passing through the switch, it is required that the messages of all transmission links pass through the switch in one slice period. In other words, the slicing period needs to be set large enough to cover the time for each transmission link to transmit a message and the delay of each transmission link.

However, the delay of each transmission link is often different, if the message of the transmission link with high delay is sent later, the message of the transmission link with low delay is sent earlier, and when the two messages are transmitted in the links simultaneously, the slicing period needs to cover both the link which is sent earlier and transmitted faster and the link which is sent later and transmitted slower, so that the slicing period is increased. Conversely, the message of the transmission link with high delay is sent first, and the message of the transmission link with low delay is sent later, so that the slicing period can be reduced, and more messages can be sent in the same time.

Fig. 2 is a schematic diagram of a message transmission provided in an embodiment of the present application, and assuming that the lengths (i.e., data amounts) of the messages sent by the links are the same, the number of messages on a connection line 150 (not shown in fig. 2) between the NIC 120 and the switch 130 indicates that the NIC 120 may send the number of messages to the switch 130 in a period of time. As shown in fig. 2 (a), during this period, there are three slicing periods 210, and each transmission link may transmit one message in each slicing period 210. However, the delay of each transmission link is different, and each NIC 120 does not make any effective adjustment, so each slicing period 210 includes a time for waiting for other link delays in addition to the transmission of the message.

As shown in fig. 2 (b), by acquiring the delay of each link, the packets to be sent by each link may be "aligned", for example, the link with high control delay sends the packets first, and the link with low control delay sends the packets later. It can be seen that there are four slice periods 220 after alignment. That is, in the same time, only 3 messages can be transmitted by one link without message alignment, and after message alignment, 4 messages can be transmitted by one link, so that the efficiency of the communication system is remarkably improved. From another perspective, it is understood that the slicing period covers links that are sent first but transmitted slower, and links that are sent later but transmitted faster, thereby reducing the slicing period.

In some embodiments, the intervals between messages sent by the links are different, but the intervals between messages sent in one link are the same. So that as long as the first message is aligned, the following messages will be aligned.

To achieve the effect shown in fig. 2, however, it is necessary to accurately acquire the delays of the respective links first. Specifically, it is desirable to accurately detect the delay of each NIC 120 sending messages to the switch 130.

Related art approaches approximate the delay of the NIC 120 sending a message to the switch 130 to the delay of the measurement line 150 and measure the delay of the connection line 150 using a dedicated measurement instrument. However, the "off-line measurement" of the connection line 150 is intelligently implemented using a dedicated measuring instrument, and compensation for the link delay variation caused by the environmental variation cannot be implemented. Each measurement with a dedicated measuring instrument requires reconnecting the connection line 150 to the dedicated measuring instrument, affecting the efficiency of the measurement. In addition, in the case where the connection line 150 is an optical fiber, the delay of the switching network 100 is also affected by the individual boards (singleboard), optical modules, and optical fiber connectors, and the actual delay between the NIC 110 and the switch 130 in the switching network 100 cannot be simply replaced by the delay of the optical fiber.

Fig. 3 is a schematic flow chart of a delay detection method according to an embodiment of the present application. The method 300 shown in fig. 3 is capable of accurately detecting the delay between the NIC and the switch.

The method 300 may be performed by any device having a computing function (e.g., a delay detection device), such as by the controller 110 of fig. 1.

S310, the first NIC is controlled to continuously send a first detection code and a first detection message to the second NIC at a first moment through a switch matrix of the switch, wherein the first detection code is sent before the first detection message.

The first NIC may be a NIC of the transmitting end, and it will be appreciated that the transmitting end often has more than one NIC. The first NIC in the embodiment of the present application is only one NIC that the method 300 focuses on in performing delay detection, and it is obvious that repeating the method 300 may detect delays between multiple NICs to a switch. The second NIC may be a NIC of the receiving end, and it will be appreciated that the receiving end often has more than one NIC.

The first time is a point in time. For example, the delay detection device or the controller 110 may send control information to the first NIC, informing the first NIC to send the detection code and the detection message at the first time. The first NIC may parse the control information to extract the first time. In some embodiments, the first NIC may include a Real Time Clock (RTC), and when the RTC reaches the first time, the first NIC issues the first detection code and the first detection message. For example, the first NIC may include a serializer/deserializer (serializing/deserializing circuitry, serDes) interface through which the first NIC issues the first detection code and the first detection message.

The SerDes interface is a high-speed serial interface, and can send out a large amount of data bit by bit at a rate of up to tens to hundreds of Gbps, and after receiving the data, a receiving end can recover the data of a transmitting end bit by bit.

The first detection message may be a message of the first NIC structure, which is not limited in this disclosure, for example, the first detection message may also be a message indicated by the delay detection device or the controller 110.

The first detection message may include a header and a check bit. The message header may be used to identify the first detection message, and the check bit may be used to check the integrity of the first detection message. The first detection message may also include other fields. For example, the second NIC may identify the first test message by the header and may verify the integrity of the first test message by the check bit.

The first detection code is used to detect the delay, and a specific detection method will be described later. For example, the first detection code may be a number of binary digits, such as pseudo-random-random binary sequence (PRBS) or any other form of binary digits. For example, "010101 · can be used carrying out the same a similar sequence.

"Continuously transmitting" means that the first detection code and the first detection message are adjacent. It is also understood that there is no time interval between the transmission of the first detection code and the first detection message, nor other data.

In some embodiments, the first detection message may include an indication field for indicating a number of bits (or referred to as a number of bits) of the first detection code. For example, the number of bits of the first detection code may be encapsulated within the first detection message. For example, the indication field may be located after the header field. In some embodiments, the indication field may also be referred to as a message sequence number field. For example, the first detection message may be configured by the first NIC, and the number of bits of the first detection code may be 1. In this case, the first NIC may encapsulate the number of bits in the first detection message when constructing the first detection message. Thus, the second NIC may determine the number of bits of the first detection code by parsing the first detection message.

In some embodiments, the switch matrix comprises an optical switch matrix.

The meaning of the switch matrix may be found in the foregoing and is not described here in detail. In addition, the present application is not limited to a switch matrix, for example, the switch matrix may also include an electrical switch matrix.

In case the switch matrix comprises an optical switch matrix, the switch may also be referred to as an optical switch or an optical switch matrix. If the first NIC sends the first detection code and the first detection message in the form of an electrical signal, the optical module may be used to convert the electrical signal into an optical signal, and transmit the optical signal to the optical switching matrix.

The method provided by the embodiment of the application can be applied to the optical switch with the optical switch matrix, and the delay detection method has wide application scene and strong applicability.

S320, when a preset period is set from the first time, the switch matrix is turned on, wherein the switch matrix is turned off after the second NIC receives the first detection message.

The predetermined period may be a predetermined interval time. The first NIC sends a first detection code and a first detection message at a first moment, and the switch matrix is started at intervals of a preset period at the first moment. Therefore, the first detection code may not be able to be sent to the second NIC, and part of the first detection message may not be able to be sent to the second NIC. By setting the preset period appropriately, a larger delay can be made "artificially" and then by adjusting the detection code, the delay of the transmission link can be detected.

The switch matrix may be turned off after the second NIC receives the first detection message. For example, a certain time window may be set according to the length of the first detection packet, so that at least the first detection packet itself may pass through the switch completely. In other words, the time window is at least longer than the length of the first detection message. In some embodiments, the time window may be set larger, and in addition to enabling the first detection message to pass through the switch entirely, the first detection code portion before the first detection message may also be enabled to pass through the switch, or the padding data portion after the first detection message may also be enabled to pass through the switch. It will be appreciated that the fill data may be a sequence similar to "010101", a PRBS code or the like is also possible. The padding data may maintain the stability of the transmission link (e.g., a link with a SerDes port).

And S330, under the condition that the second NIC receives the incomplete first detection message, controlling the first network interface card NIC to continuously send a second detection code and a second detection message to the second NIC at a second moment through a switch matrix of the switch, wherein the bit number of the second detection code is larger than that of the first detection code, and the length of the second detection message is equal to that of the first detection message.

As described above, since the switch matrix is turned on at the first time interval by the preset period, the second NIC is likely to receive the incomplete first detection message. In some embodiments, the first detection message may include a check bit, and the second NIC determines whether the first detection message is complete by checking the check bit, and the second NIC transmits the result of the determination to the delay detection device or the controller 110. In other embodiments, the delay detection device may obtain the check bit of the first detection message, and the delay detection device determines whether the first detection message is complete.

The second time may be a time after the first time. It will be appreciated that the switch matrix is already closed at the second instant and therefore needs to be re-opened.

The process of controlling the first network interface card NIC to continuously send the second detection code and the second detection message to the second NIC at the second moment through the switch matrix of the switch may refer to the foregoing description, which is not repeated herein.

The length of the second detection message is equal to that of the first detection message. In some embodiments, the second detection message is substantially identical to the first detection message, such that the first NIC or delay detection device or controller 110 does not need to reconstruct the second detection message, reducing the burden on system operation. For example, in the case where the detection message may indicate the number of bits of the detection code, the second detection message and the first detection message may be distinguished only in an indication field, the indication field of the first detection message being used to indicate the number of bits of the first detection code, and the indication field of the second detection message being used to indicate the number of bits of the second detection code. For another example, in the case where the detection packet does not indicate the number of bits of the detection code, the data of each field in the second detection packet may be the same as the first detection packet.

The number of bits of the second detection code is greater than the number of bits of the first detection code. In other words, the second detection code may be longer than the first detection code, or the second detection code may have more bits than the first detection code.

In some embodiments, the second detection code may have one more user-side bit width than the first detection code. For example, the user side bit width of the SerDes may be 32 bits, with the number of bits of the second detection code being 32 bits greater than the number of bits of the first detection code. Thus, the number of bits of the second detection code can be adjusted at the user side of the SerDes, thereby increasing the applicability of the detection method.

In other embodiments, the difference between the number of bits of the second detection code and the number of bits of the first detection code is 1. In other words, the second detection code is 1bit more than the first detection code.

For example, assume that the rate of the SerDes port is 25Gbps and the user side bit width of SerDes is 32 bits. If the user side bit width of SerDes is used as granularity to adjust the number of bits of the detection code, the calculated delay is a multiple of 1.28 nanoseconds, so the delay can be accurate to nanoseconds. If 1 bit is adopted as granularity to carry out bit number adjustment of the detection code, the calculated delay is a multiple of 40 picoseconds, thereby realizing picosecond detection.

In the embodiment of the application, the bit number of the detection code added each time can be 1, thereby realizing picosecond detection and improving the accuracy and precision of delay detection.

In some embodiments, the second detection code may be any random sequence.

In other embodiments, the number of bits of 0 and 1 in the second detection code is similar.

For example, the second detection code may be a sequence similar to "010101.. About.", or may be a PRBS code.

In the embodiment of the application, the bit numbers of 0 and 1 in the detection code are similar, and the equalization of 0 and 1 in the link can be realized, thereby reducing the error rate of the NIC.

S340, when the preset period is set from the second time, the switch matrix is turned on, wherein the switch matrix is turned off after the second NIC receives the second detection message.

Note that the preset period here is the same as the preset period in S320. Since the second NIC does not receive the complete detection message, the number of bits of the detection code is increased, so that the second NIC is more likely to receive the complete detection message.

S350, under the condition that the second NIC receives the complete second detection message, determining the delay between the first NIC and the switch according to the number of bits of the second detection code and the preset period.

In the embodiment of the application, after the first NIC sends the detection code and the detection message, the switch matrix is started after a preset period, so that the second NIC initially receives the incomplete detection message. In the case that the second NIC receives an incomplete detection message, the first NIC sends a longer detection code, so that the second NIC is more likely to receive the complete detection message. When the second NIC receives the complete detection message, the delay between the first NIC and the switch can be obtained according to the number of bits of the detection code sent by the first NIC and the preset period. Compared with the scheme of a special measuring instrument, the embodiment of the application can realize delayed online detection and improve the detection efficiency and accuracy.

In some embodiments, the predetermined period may be converted into a number of bits according to how many bits of data can be transmitted in the predetermined period, and the delay between the first NIC and the switch may be determined according to the number of bits converted in the predetermined period and the number of bits of the detection code.

In other embodiments, determining the delay between the first NIC and the switch based on the number of bits of the second detection code and the predetermined period includes determining an additional delay resulting from adding the second detection code based on the number of bits of the second detection code, and determining the delay between the first NIC and the switch based on the additional delay and the predetermined period.

Fig. 4 is a schematic diagram of a delay detection method according to an embodiment of the present application. Arrows below the left and right diagrams in fig. 4 indicate time axes.

Referring to the left diagram in fig. 4, at a transmission time 410 (e.g., a first time), the first NIC may transmit a first detection code 430, a first detection message, and padding data 450 to the second NIC. Referring to the right hand diagram of fig. 4, at turn-on time 420, the switch matrix is turned on, and it can be seen that a portion of the data of the first detection message should have been "passed" through the switch matrix to the second NIC before turn-on time 420, but that this portion of the data did not reach the second NIC since turn-on time 420 was after this portion of the data. Therefore, the second NIC does not receive the complete first detection message.

It will be appreciated that the difference between the on time 420 and the transmit time 410 is the predetermined period described above. Fig. 4 is merely illustrative and not limiting of the application. Also, fig. 4 is for ease of understanding only, and does not mean that the first detection message and the second detection message are sent simultaneously at the sending time 410. In fact, before the first test message, there may be more test messages and test codes sent, and in case the second test message cannot reach the second NIC completely through the switch, there may also be more test messages and test codes sent after the second test message.

Referring to the left diagram in fig. 4, at a transmission time 410 (e.g., a second time), the first NIC may transmit a second detection code 440, a second detection message, and padding data 450 to the second NIC. Since the second detection code 440 is longer than the first detection code 430, the second detection message may pass completely through the switch to the second NIC.

Increasing the data sent causes a delay, which is referred to as an "extra delay". In some embodiments, the additional delay may be calculated based on the transmission rate of the data. For example, assuming a rate of 25Gbps for the SerDes port, an additional delay of 40 nanoseconds would be added for every 1bit of data added. The first detection code 430 in fig. 4 is shorter than the second detection code 440, which can intuitively indicate that the first detection code 430 corresponds to an additional delay that is smaller than the second detection code 440. It should be noted that the "increase" and "extra delay" are referred to herein with respect to not transmitting the detection code, but rather with respect to the shorter detection code.

For example, it may be determined that the delay between the first NIC and the switch is the difference between the preset period and the additional delay.

Further, determining the delay between the first NIC and the switch based on the number of bits of the second detection code and the preset period may include determining the delay between the first NIC and the switch based on the following formula:

T_delay＝ΔT_switch-ΔT_n;

Where T _delay is the delay between the first NIC and the switch, Δt _switch is the predetermined period, and Δt _n is the additional delay.

In the embodiment of the application, the accurate detection of the delay is realized according to the additional delay caused by sending the detection code and the preset period.

In some embodiments, determining the additional delay caused by adding the second detection code based on the number of bits of the second detection code includes determining the additional delay based on the number of bits of the second detection code and the rate at which the second detection code is sent by the first NIC.

For example, assuming that the rate at which the first NIC transmits the second detection code is 25Gbps and the number of bits of the second detection code is 10bit data, it can be determined that the additional delay is 400 nanoseconds.

According to the embodiment of the application, the extra delay can be determined according to the bit number of the detection code and the sending rate of the first NIC, so that the accurate detection of the delay between the first NIC and the switch is realized.

In some embodiments, the second detection message includes an indication field for indicating a number of bits of the second detection code, wherein the method further includes determining the number of bits of the second detection code based on the second detection message.

The detection message can comprise an indication field, the indication field can indicate the number of bits of the detection code before the detection message, delay calculation is convenient, and detection efficiency is improved.

In some embodiments, the controller 110 or the delay detection device may control the second NIC to determine the number of bits of the second detection code. In other embodiments, the controller 110 or the delay detection device may obtain the second detection message, thereby determining the number of bits of the second detection code.

It should be noted that, the above description describes the case where after the second NIC receives an incomplete detection message, the second NIC receives the complete detection message. In fact, before S310, the first NIC may also send a number of detection codes and detection messages, which are shorter than the first detection code, and which are as long as the first detection message. After the second NIC receives the incomplete first detection message, the second NIC may also receive the incomplete second detection message. The following describes a case where the second NIC receives an incomplete second detection message.

Alternatively, the method further comprises controlling the first NIC to send a third detection code and a third detection message to the second NIC through the switch matrix of the switch at a third moment when the second NIC receives the incomplete second detection message, wherein the bit number of the third detection code is larger than the bit number of the second detection code, the length of the third detection message is equal to the length of the first detection message, opening the switch matrix when the preset period is spaced from the third moment, wherein the switch matrix is closed after the second NIC receives the third detection message, and determining the delay between the first NIC and the switch according to the bit number of the third detection code and the preset period when the second NIC receives the complete third detection message.

That is, in the case that the second NIC receives the incomplete second detection message, the embodiment of the present application may control the first NIC to send the detection code and the detection message again longer, and if the detection message sent this time can be received completely by the second NIC, determine the delay according to the detection code sent this time.

It will be appreciated that if the detection message sent this time is still not completely received by the second NIC, the sending of the detection code and detection message may continue longer.

By continuously increasing the length of the detection code until the second NIC can receive the complete detection message, the detection method provided by the embodiment of the application can accurately detect the delay between the first NIC and the switch.

The method of detecting delay is described above, and the application of delay is described below by taking "message alignment" as an example.

Performing method 300 on multiple transmission links (e.g., multiple first NIC to switch links) may result in delays for the multiple transmission links. In some embodiments, a maximum delay of the delays of the plurality of transmission links may be taken as a reference point, and the delay of each transmission link is subtracted from the maximum delay to obtain a delay compensation for each of the plurality of transmission links. Message alignment may be achieved based on delay compensation for each of the plurality of transmission links.

For example, from a delay compensation of a transmission link, a number of data bits corresponding to the delay compensation may be determined. The corresponding number of data bits for delay compensation may be padded before each message is sent by the transmission link. The padding operation is performed on each of the plurality of transmission links, so that the alignment of the messages of the plurality of transmission links can be achieved.

In some embodiments, the plurality of second NICs may calculate the delay of the corresponding transmission link. The second NIC sends the delays of the transmission links to the controller 110, and the controller 110 determines the maximum delay (e.g., T _{Delay_max}) of the delays of the transmission links based on the delays of the respective transmission links (e.g., T _{Delay_1}～T_{Delay_n}). The controller 110 subtracts the delay of each transmission link from the maximum delay to obtain a delay compensation for each transmission link. The controller 110 transmits the delay offsets to the corresponding first NICs, respectively. Thus, before sending the message, the first NIC may perform message alignment according to the delay compensation sent by the controller 110, for example, fill the data with the corresponding bit number of the delay compensation before the message. The data that is populated may be a sequence that is "010101-", the PRBS code or the like is also possible, and any sequence is also possible.

The application is not limited to a specific method for aligning the message according to the delay compensation, for example, besides the foregoing data of the corresponding bit number of the delay compensation is filled in front of the message, the system clock of the field programmable gate array (field programmable GATE ARRAY, FPGA) can be used for adjustment (for example, the high-delay-compensation first-come-out and the low-delay-compensation later-come-out) and other ways can be used for adjustment. For example, the integer portion of the delay compensation greater than the FPGA system clock is adjusted using the system clock, and the remaining fraction portion is adjusted using data that fills the corresponding number of bits.

In some embodiments, the above-described delay detection and message alignment schemes may be performed periodically, so that the delay of the transmission link may be refreshed periodically, so that messages at the switch ingress are always aligned. Compared with the scheme of adopting a special measuring instrument, the embodiment provided by the application can effectively reduce the difficulty of networking and can compensate the change of the delay of the transmission link caused by the environmental change.

Under the condition that the delay detection and message alignment scheme is applied to the optical switching matrix, the delay of the transmission link can be corrected in real time according to the condition of the transmission link under the condition of no service interruption, and the data switching efficiency is improved.

Fig. 5 is a schematic flow chart of another delay detection method according to an embodiment of the present application. The method 500 may be performed by the delay detection device or the controller 110.

S510, the first NIC is controlled to continuously send detection codes and detection messages to the second NIC through a switch matrix of the switch, wherein the detection codes are sent before the detection messages.

S520, opening the switch matrix after a predetermined period.

S530, the second NIC is controlled to judge whether the detection message received by the second NIC is complete.

In the case that the second NIC receives the complete detection message, S540 is performed. In the case that the second NIC receives the incomplete detection message, S550 is performed.

S540, determining delay according to the preset period and the bit number of the detection code.

After performing S540, the method 500 may end.

S550, the number of bits of the detection code is increased.

For example, the number of bits can be increased by 1bit, or the number of bits can be increased by the user-side bit width of SerDes. For example 32 bits.

In some embodiments, since the delay detection device or the controller 110 may fail, the calculation is not performed S540 when the second NIC receives the complete detection message for the first time. In order to increase the robustness of the detection method provided by the embodiment of the present application, a determination may be added between S530 and S540.

For example, after the execution of S530, in the case where the second NIC receives the complete detection message, S540 is not executed, but it is determined whether the second NIC has received the complete detection message last time, and if the second NIC has not received the complete detection message last time, S540 is executed. If the second NIC also receives the complete detection message last time, the number of bits of the detection code is reduced, and steps S510, S520 are performed, that is, a cycle is re-entered.

The method embodiments of the present application are described in detail above. The following describes an embodiment of the apparatus according to the embodiment of the present application, where the embodiment of the apparatus corresponds to the embodiment of the method, so that a portion not described in detail may refer to the foregoing embodiments of the method, and the apparatus may implement any possible implementation manner of the foregoing method.

Fig. 6 shows a schematic block diagram of a delay detection device according to an embodiment of the present application.

As shown in fig. 6, the delay detection apparatus 600 includes a control module 610 configured to control a first NIC to continuously send a first detection code and a first detection message to a second NIC through a switch matrix of a switch at a first time, where the first detection code is sent before the first detection message, the control module 610 is further configured to turn on the switch matrix when a preset period is set from the first time, where the switch matrix is turned off after the second NIC receives the first detection message, and when the second NIC receives the first detection message that is incomplete, the control module 610 is further configured to control a first network interface card NIC to continuously send a second detection code and a second detection message to the second NIC through the switch matrix of the switch at a second time, where a bit number of the second detection code is greater than a bit number of the first detection code, and a length of the second detection message is equal to a length of the first detection message, and when the preset period is set from the second time, the control module 610 is further configured to turn on the switch matrix when the preset period is set from the second time, where the switch matrix is turned off, and after the second NIC receives the second detection message, the second detection message is determined to be turned off according to a preset period, and the second detection message is received by the second NIC.

The control module 610 and the processing module 630 may each be implemented by software, or may be implemented by hardware. Illustratively, the implementation of the control module 610 is described next with reference to the control module 610. Similarly, the implementation of the processing module 630 may refer to the implementation of the control module 610.

Module as an example of a software functional unit, the control module 610 may include code that runs on a computing instance. The computing instance may include at least one of a physical host (computing device), a virtual machine, and a container, among others. Further, the above-described computing examples may be one or more.

Module as an example of a hardware functional unit, the control module 610 may include at least one computing device, such as a server or the like. Alternatively, the control module 610 may be a device implemented using an application-specific integrated circuit (ASIC), a programmable logic device (programmable logic device, PLD), or the like. The PLD may be implemented as a complex program logic device (complex programmable logical device, CPLD), a field-programmable gate array (FPGA) GATE ARRAY, a general-purpose array logic (GENERIC ARRAY logic, GAL), or any combination thereof.

The present application also provides a computing device 700. As shown in fig. 7, computing device 700 includes a bus 702, a processor 704, a memory 706, and a communication interface 708. Communication between processor 704, memory 706, and communication interface 708 is via bus 702. Computing device 700 may be a server or a terminal device. It should be understood that the present application is not limited to the number of processors, memories in computing device 700.

Bus 702 may be a peripheral component interconnect standard (PERIPHERAL COMPONENT INTERCONNECT, PCI) bus, or an extended industry standard architecture (extended industry standard architecture, EISA) bus, among others. The buses may be divided into address buses, data buses, control buses, etc. For ease of illustration, only one line is shown in fig. 7, but not only one bus or one type of bus. Bus 702 may include a path for transferring information between various components of computing device 700 (e.g., memory 706, processor 704, communication interface 708).

The processor 704 may include any one or more of a central processing unit (central processing unit, CPU), a graphics processor (graphics processing unit, GPU), a Microprocessor (MP), or a digital signal processor (DIGITAL SIGNAL processor, DSP).

The memory 706 may include volatile memory (RAM), such as random access memory (random access memory). The memory 706 may also include non-volatile memory (ROM), such as read-only memory (ROM), flash memory, mechanical hard disk (HARD DISK DRIVE, HDD), or Solid State Disk (SSD) STATE DRIVE.

The memory 706 has stored therein executable program code that is executed by the processor 704 to implement the functions of the aforementioned control module 610 and processing module 630, respectively, to implement a delay detection method. That is, the memory 706 has instructions stored thereon for performing the delay detection method.

Communication interface 708 enables communication between computing device 700 and other devices or communication networks using a transceiver module such as, but not limited to, a network interface card, transceiver, or the like. For example, the first NIC, the switch matrix of the switch, and the second NIC may be controlled in accordance with the communication interface 708.

Embodiments of the present application also provide a computer program product comprising instructions. The computer program product may be software or a program product containing instructions capable of running on a computing device or stored in any useful medium. The computer program product, when run on at least one computing device, causes the at least one computing device to perform the delay detection method described above.

The embodiment of the application also provides a computer readable storage medium. The computer readable storage medium may be any available medium that can be stored by a computing device or a data storage device such as a data center containing one or more available media. The usable medium may be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid state disk), etc. The computer-readable storage medium includes instructions that instruct a computing device to perform the delay detection method described above.

The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any person skilled in the art will readily appreciate variations or alternatives within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.