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CN119232261A - Reset signal sending method, storage medium, electronic device, and computer program product - Google Patents

️Tue Dec 31 2024

Detailed Description

Embodiments of the present application will be described in detail below with reference to the accompanying drawings in conjunction with the embodiments.

It should be noted that the terms "first," "second," and the like in the description and the claims of the present application and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order.

The embodiment of the method for sending the reset signal provided in the embodiment of the application can be executed in a server device or a similar computing device. Taking the operation on the server device as an example, fig. 1 is a block diagram of a hardware structure of the server device of a method for sending a reset signal according to an embodiment of the present application. As shown in fig. 1, the server device may include one or more (only one is shown in fig. 1) processors 102 (the processor 102 may include, but is not limited to, a microprocessor MCU, a programmable logic device FPGA, or the like processing means) and a memory 104 for storing data, wherein the server device may further include a transmission device 106 for communication functions and an input-output device 108. It will be appreciated by those of ordinary skill in the art that the architecture shown in fig. 1 is merely illustrative and is not intended to limit the architecture of the server apparatus described above. For example, the server device may also include more or fewer components than shown in FIG. 1, or have a different configuration than shown in FIG. 1.

The memory 104 may be used to store a computer program, for example, a software program of application software and a module, such as a computer program corresponding to a method for transmitting a reset signal in an embodiment of the present application, and the processor 102 executes the computer program stored in the memory 104, thereby performing various functional applications and data processing, that is, implementing the above-mentioned method. Memory 104 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include memory remotely located with respect to the processor 102, which may be connected to the server device via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.

The transmission device 106 is used to receive or transmit data via a network. Specific examples of the network described above may include a wireless network provided by a communication provider of a server device. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, simply referred to as a NIC) that can connect to other network devices through a base station to communicate with the internet. In one example, the transmission device 106 may be a Radio Frequency (RF) module, which is configured to communicate with the internet wirelessly.

It should be noted that PCIe protocol is a data standard for high-speed serial high-bandwidth transmission, and is used for data transmission between expansion cards and computer boards. Along with the continuous increase of PCIe rate, the requirements of the protocol on PCIe signal quality are also continuously improved, and the transmission distance of PCIe signals on the traditional PCB or copper cable is also continuously shortened. In some PCIe long-range transmission applications, designers need to additionally add driving circuits to improve signal quality, increasing design difficulty and design cost. Compared with traditional PCIe copper cable transmission, the optical signal transmission PCIe signal has the advantages of low loss, low delay, high bandwidth, long distance and the like, but the PCIe protocol has no requirement of using the optical signal to transmit the PCIe signal, so that the PCIe optical transmission application has some differences with the traditional PCIe application.

The optical module is a photoelectric conversion device, and can convert an externally input electric signal into an optical signal to be sent out through an optical fiber line, and can also convert the optical signal received in the optical fiber line into an electric signal to be transmitted to a related processor. Compared with plug and play of a passive copper cable, the optical module is an active device, the optical module needs a period of time for internal initialization after power supply, in the process, the optical module reads the default configuration in the module and configures corresponding input and output links, meanwhile, an external processor can also change the parameters of the optical module in the secondary process and adjust the link characteristics of the input and output ports so as to ensure that the link initialization result meets the system working requirements, and because the optical modules manufactured by different manufacturers have different photoelectric conversion design schemes, different internal manufacturing processes and different port numbers, the duration of the initialization process is different. When the PCIe host sends out a reset signal to inform terminal equipment on a PCIe link to carry out link training, the PCIe signal and the reset signal can not be normally transmitted due to the uncertainty of the initialization time, and the PCIe terminal equipment can not stably receive the PCIe signal or the reset signal, so that the PCIe link training can not be normally carried out, the expected speed of the system design can not be reached, and the working state of the system is influenced.

In order to solve the problems, the embodiment of the application provides a method for sending a reset signal, which is applied to a communication scene of a host and equipment, wherein the communication scene is provided with the host, a first optical module of the host and the equipment, and a second optical module of the equipment, wherein an electric signal is transmitted between the host and the first optical module, an optical signal is transmitted between the first optical module and the second optical module, and an electric signal is transmitted between the second optical module and the equipment.

Optionally, in the case where the Host and the Device communicate based on PCIe links, as shown in fig. 2, one PCIe link may be composed of a Host Device, a Device, a Host optical module (i.e., a first optical module), a Device optical module (i.e., a second optical module), PCIe electrical signals transmitted between the Host Device and the Host optical module, PCIe electrical signals transmitted between the Device and the Device optical module, and PCIe optical signals transmitted between the Host optical module and the Device optical module. Taking the Host end as an example, the Host optical module is connected with a Host device to transmit PCIe signals, and also connected with a Host complex programmable logic device (Complex Programmable Logic Device, abbreviated as CPLD) and a baseboard management controller (Baseboard Management Controller, abbreviated as BMC) to transmit low-speed signals such as GPIO (General Purpose Input/Output), I2C (Inter-INTEGRATED CIRCUIT, namely an integrated circuit bus), PERST (PERIPHERAL RESET, peripheral reset signals) and the like for the reset control of a PCIe link. The Device end is connected in a similar manner to the Host end, and the difference is that a PERST Reset signal is sent from the Device end optical module to the Device end CPLD, and then the Device end CPLD sends the PERST Reset signal to the Device for notifying the Device to Reset the PCIe link, in addition, TX in fig. 2 is transmission (Transmit), RX is reception (Receive), RST is Reset signal (Reset), and MCU is a micro controller unit (Microcontroller Unit).

It should be noted that, the Host Device and the Host CPLD transmit two sets of reset signals, including a low-efficient PCIe link reset signal PERST (i.e., a first reset signal described below) that the Host Device actively sends to the Host CPLD and a low-efficient PCIe reset signal RST (i.e., a second reset signal described below) that the Host CPLD actively sends to the Host Device, where the Host Device automatically sends a PERST reset signal after power-up is completed, to reset a Device connected to a corresponding PCIe link in the present application, and the Host Device sends a PERST reset signal again when receiving a low-level RST signal sent by the Host CPLD, to notify the Device of PCIe link reset.

It should be noted that, there are five sets of signals between the Host optical module and the Host end CPLD, including:

(1) And LPmode, a signal sent by the CPLD to the optical module, and when the signal is high, the optical module enters a low-power consumption state.

(2) And the CPLD outputs a Reset signal to the optical module, and the Reset signal is externally pulled down for a period of time and then pulled up, and then is regarded as a Reset action for controlling the optical module to Reset.

(3) And the optical module sends an INT signal (namely an interrupt signal) to the CPLD, and when the signal is high, the optical module prompts the inside of the CPLD to be abnormal, and an external device is required to process the abnormal state.

(4) The Host optical module transmits an optical module in-place state signal PRSNT to the Host CPLD, when the optical module is installed, the PRSNT signal state is low, and otherwise, the PRSNT signal state is high.

(5) The Host optical module receives a PERST reset signal sent by the Host CPLD, converts the PERST reset signal into an optical signal through an internal photoelectric conversion part, and transmits the optical signal to the Device end through an optical fiber line, wherein the signal is an output signal of the Device optical module at the Device end, and the Device optical module converts the received reset optical signal into an electric signal and sends the electric signal to the Device CPLD.

The Host optical module and the Host end BMC are used for transmitting I2C signals, wherein (1) the optical module converts the I2C electrical signals into optical signals and transmits the optical signals to the Device end through the optical fiber line, and (2) the BMC reads the information of the Host end optical module state through the I2C and is used for judging whether the optical module works normally or not.

It should be noted that fig. 3 is a flowchart of a method for transmitting a reset signal according to an embodiment of the present application, including the following steps S302-S304:

step S302, determining the working state of the first optical module and the working state of the second optical module;

Step S304, according to the working state of the first optical module and the working state of the second optical module, a first reset signal sending condition of the host sends the first reset signal to the first optical module so as to send the first reset signal to the equipment through the first optical module and the second optical module, wherein the first reset signal is used for resetting the equipment and indicating the equipment to train a communication link between the equipment and the host.

Optionally, the main body of the method according to the embodiment of the present application is a programmable device of the host, for example, a CPLD of the host.

According to the working state of the first optical module of the main board and the working state of the second optical module of the equipment, the first reset signal sending condition of the host sends a first reset signal to the first optical module so as to send the first reset signal to the equipment through the first optical module and the second optical module. Because the working state of the optical module is considered when the reset signal is sent, the reset signal can be reasonably sent, by adopting the technical scheme, the problem that the host cannot reasonably send the reset signal under the condition that the host and the device perform data communication based on the optical signal is solved. The communication link can be stably transmitted at an expected speed through the optical module, and the host and the equipment can stably communicate, so that training of the communication link is completed.

In an exemplary embodiment, according to the working state of the first optical module and the working state of the second optical module, the first reset signal sending condition of the host sends the first reset signal to the first optical module, which is implemented by the following steps S11-S13:

Step S11, when the working state of the first optical module and the working state of the second optical module are both normal working states and the first reset signal sending condition is used for indicating that the host machine has sent the first reset signal, sending the first reset signal to the first optical module;

Step S12, waiting for the first reset signal sent by the host when the working state of the first optical module and the working state of the second optical module are both normal working states and the first reset signal sending condition is used for indicating that the host does not send the first reset signal, and sending the first reset signal to the first optical module when the first reset signal sent by the host is obtained;

And S13, prohibiting sending the first reset signal to the first optical module when the working state of the first optical module is not a normal working state or the working state of the second optical module is not a normal working state.

It should be noted that, the steps S11 to S13 are steps performed in different situations, and there is no execution sequence.

In this embodiment, the CPLD of the host analyzes and determines the received working state of the optical module of the host, the working state of the optical module of the device, and the first reset signal transmission condition of the host, and when the optical module of the host is in a normal working state and the optical module of the device is in a normal working state, the CPLD determines whether the host has transmitted the first reset signal, if the first reset signal has been transmitted, the CPLD of the host controls the first reset signal of the optical module connected to the host to generate a reset action, and if the first reset signal has not been received, the CPLD waits until the host transmits the first reset signal and then transmits the first reset signal to the outside. When the host has sent the first reset signal, but the optical module of the host or the optical module of the device is still not in the normal working state, the CPLD of the host needs to wait for the optical module of the host and the optical module of the device to be in the normal working state and then output the first reset signal to the optical module of the host.

It should be noted that the steps S11 to S13 have the following technical effects:

1. And S11 and S12, only when the first optical module and the second optical module are in a normal working state, transparent transmission of the reset signal is allowed, so that the optical modules at the two ends of the link can stably process and transmit the reset signal, and the problem of link training failure or unstable link working caused by abnormal optical module is avoided.

2. The accurate control of the reset action, namely the monitoring of the first reset signal sending condition in the steps S11 and S12, ensures the accurate transmission of the host reset signal, namely the synchronism of the reset action at the two ends of the link. When the host computer has sent the reset signal, it immediately transmits the signal to the optical module, and when the host computer has not sent the signal, it waits until it receives the signal, so that it can avoid unnecessary link reset and save reset time and system resource.

3. The fault prevention and safety mechanism, which is described in step S13, prohibits the transmission of the reset signal when the working state of any optical module is abnormal, provides a fault prevention mechanism, and prevents the optical module from being reset when the optical module fails to be initialized normally or fails, thereby avoiding the potential risk of link damage or data loss.

4. The whole system efficiency is improved, namely, the whole scheme avoids invalid or premature link resetting by precisely controlling the sending of the reset signal, reduces unnecessary initialization time and improves the working efficiency of PCIe optical interconnection links, thereby improving the whole performance of the system such as a server and the like.

5. The scheme enhances the compatibility and the interoperability of different optical modules by detecting and adapting to the working states of the optical modules as different optical modules possibly have respective initialization time and configuration requirements, and ensures that PCIe links based on the optical modules of different manufacturers can be stably reset and work.

6. The maintenance cost and time are reduced, namely, the occurrence of false alarms and faults is reduced by preventing the resetting under the abnormal state of the optical module, so that the maintenance cost and time are reduced, and the usability and the user satisfaction are improved.

In summary, by precisely controlling and synchronizing the transmission of the link reset signal, the above steps ensure the stability and efficiency of the optical module in the reset process, thereby enhancing the performance and reliability of the PCIe optical interconnection link based on the optical module, reducing the maintenance cost and improving the compatibility and interoperability.

In an exemplary embodiment, the method further comprises the steps of S21-S22:

Step S21, after the first reset signal is sent to the first optical module, detecting that the working state of the first optical module is switched from a normal working state to an abnormal working state within a preset time, and switching to the normal working state again, and/or sending a second reset signal to the host under the condition that the working state of the second optical module is switched from the normal working state to the abnormal working state within the preset time, and switching to the normal working state again, wherein the second reset signal is used for indicating the host to send the first reset signal again;

Step S22, when the first reset signal sent by the host is obtained and the working states of the first optical module and the second optical module are both normal working states, the first reset signal is sent to the first optical module.

That is, in this embodiment, when the CPLD of the Host has sent out a reset action (i.e. sent out the first reset signal) to the outside, the Host optical module or the Device optical module exits the normal working state (the optical module is pulled out or some abnormal state occurs), and when both the Host and the Device optical module recover to the normal working state, the Host CPLD sends out a reset action (i.e. sends out the second reset signal) to the Host Device, so as to notify the Host Device that the PCIe link needs to be initialized again, and the Host Device needs to send out a reset action (i.e. send out the first reset signal) again, so as to notify the Device to reset and then re-perform PCIe link training.

The Host CPLD sends a first reset signal to the Host optical module, and after the Host optical module, the optical fiber line and the Device optical module output the first reset signal to the Device end CPLD, device CPLD, and after detecting that the first reset signal sent from the Host end generates a reset action, the Device transmits the reset action to the Device, and the Host Device and the Device can stably transmit PCIe signals through the optical module to perform subsequent link training, so as to achieve the expected effect of PCIe optical interconnection, thereby completing one-time complete PCIe link reset.

That is, in this embodiment, PCIe link reset between the host and the device may be achieved by pulling out the first optical module or the second optical module. In addition, the self-detection and self-repair capabilities of the system are provided, the system can be automatically reset even if the optical module has a temporary fault, normal operation of the link is recovered, manual intervention is not needed, and the automation degree and self-healing capability of the system are improved.

In an exemplary embodiment, the method further comprises the steps of S31-S32:

Step S31, under the condition that the reset instruction information sent by the baseboard management controller of the host is obtained, a second reset signal is sent to the host, wherein the reset instruction information is used for instructing to reset the equipment and training a communication link between the host and the equipment, and the second reset signal is used for instructing the host to send the first reset signal again;

And step S32, when the first reset signal sent by the host is obtained and the working states of the first optical module and the second optical module are both normal working states, sending the first reset signal to the first optical module.

That is, in this embodiment, PCIe link reset between the host and the device may be implemented through the reset indication information sent by the baseboard management controller, so as to avoid manually plugging and unplugging the optical module to implement PCIe link reset between the host and the device.

In an exemplary embodiment, the method further comprises the steps of S41-S42:

Step S41, after the first reset signal is sent to the first optical module, a second reset signal is sent to the host when the working state of the equipment is detected to be switched from a normal working state to an abnormal working state within a preset time and is switched to the normal working state again, wherein the second reset signal is used for indicating the host to send the first reset signal again;

Optionally, the BMC of the device may detect the working state of the device, and then the BMC of the device sends the working state of the device to the BMC of the host, and then the BMC of the host sends the working state of the device to the CPLD of the host.

Alternatively, the BMC of the device may detect the operating state of the device, and then send the operating state to the CPLD of the host through the CPLD of the device.

Step S42, when the first reset signal sent by the host is obtained and the working states of the first optical module and the second optical module are both normal working states, the first reset signal is sent to the first optical module.

It should be noted that, the above steps S41 and S42 further enhance the stability and the recovery capability of the PCIe optical interconnection link based on the optical module when the device status fluctuates, and specific technical effects include:

1. in step S41, the CPLD of the host computer can actively detect the working state of the device after sending a first reset signal to the first optical module, and once the abnormal device state is found but recovered later, the CPLD of the host computer automatically sends a second reset signal to inform the host computer to reset again. This allows the CPLD of the host to react quickly to transient faults of the device, reducing the time for fault recovery, and enhancing the stability of the link.

2. The monitoring of the device state and the accurate control of the reset signal in steps S41 and S42 ensure that the PCIe optical interconnection link can be quickly restored to the normal working state even under the condition of the fluctuation of the device state, thereby improving the overall reliability of the communication scene and reducing the downtime caused by faults.

In an exemplary embodiment, the method further comprises steps S51-S53:

Step S51, detecting an in-place state signal of the first optical module;

step S52, controlling the first optical module to enter an initialization flow under the condition that the in-place state signal is used for indicating that the first optical module is in place;

And step S53, when the interrupt signal sent by the first optical module is obtained, the substrate management controller of the host is instructed to process the interrupt of the first optical module.

In the above steps, whether the optical module is correctly installed can be monitored in real time by detecting the in-place status signal of the first optical module. This helps to prevent link failure due to improper installation or removal of the optical module.

It should be noted that, after confirming that the first optical module is in place, the system starts to control the optical module to enter the initialization flow. The method avoids unnecessary initialization attempts to the optical module which does not exist or is not in place, reduces the waste of system resources, and ensures the accuracy and success rate of the initialization of the optical module, thereby improving the stability of the link.

It should be noted that, when the programmable device (such as the CPLD) receives the interrupt signal sent by the first optical module, the system can quickly instruct the Baseboard Management Controller (BMC) of the host to process the interrupt. The mechanism ensures that the abnormal state in the optical module can be found and processed in time, avoids the continuous influence of the abnormal state on the link performance, and improves the response speed to faults and the overall reliability.

In an exemplary embodiment, instructing the baseboard management controller of the host to process the interrupt of the first optical module includes instructing the baseboard management controller of the host to perform the following steps S61-S63:

step S61, determining an interrupt type of the interrupt of the first optical module, and determining a target parameter of a configuration register of the first optical module under the condition that the interrupt type is a first type, wherein the interrupt of the first type is generated after the first optical module enters an initialization flow and configures the configuration register according to a default configuration parameter of the configuration register;

Step S62, configuring the configuration register of the first optical module according to the target parameter;

and S63, clearing the interrupt state of the first optical module.

It should be noted that, in this embodiment, the BMC is capable of identifying the type of the interrupt, and further determining the target parameter of the configuration register when the interrupt type is the specific first type. The accurate recognition mechanism is helpful for rapidly positioning the root of the problem, avoids invalid processing of irrelevant interrupts, and improves the efficiency and accuracy of fault processing.

It should be noted that, once the interrupt type is determined to be the first type, the BMC may adjust the configuration register of the first optical module according to the target parameter. The mechanism allows the system to dynamically adjust configuration parameters according to the current state and the requirements of the optical module so as to cope with the problems of signal quality, power consumption or compatibility and the like possibly encountered in the initialization process, thereby improving the working performance of the optical module and the stability of a link.

It should be noted that, after the BMC completes the adjustment of the configuration parameters, the BMC may clear the interrupt state of the first optical module, and resume the normal operation thereof. The operation can timely eliminate the interrupt alarm in the system, avoid continuous interference of the interrupt state to subsequent communication operation, and ensure the continuity and high efficiency of the PCIe optical interconnection link.

In an exemplary embodiment, determining the target parameter of the configuration register of the first optical module includes determining a module type of the first optical module, and determining the target parameter from a configuration file according to the module type of the first optical module, where the configuration file has parameters of the configuration register corresponding to different module types.

It should be noted that, by determining the module type of the optical module, the configuration parameters matched with the optical module of the type are intelligently selected from the configuration file. The mechanism ensures the accuracy of configuration parameters, avoids initialization failure or link performance degradation caused by parameter mismatch, and improves the stability and efficiency of the link.

It should be noted that, because different optical modules may have different photoelectric conversion characteristics, power requirements or communication protocols, the ability to dynamically acquire the target parameters from the configuration file enables flexible adaptation to various types of optical modules, enhances interoperability and adaptability, and reduces risks when replacing or upgrading the optical modules.

It should be noted that, the target parameters are accurately and quickly obtained from the configuration file, so that blind attempts for configuring the optical module are reduced, and the parameter configuration time in the initialization process is shortened, thereby reducing the initialization time of the whole PCIe optical interconnection link and improving the response speed and the overall performance of the link.

In an exemplary embodiment, determining the target parameter of the configuration register of the first optical module includes determining a module type of the first optical module, and determining the stored parameter of the configuration register of the optical module of the motherboard detected last time as the target parameter when the module type of the first optical module is the same as the module type of the optical module of the motherboard detected last time by the baseboard management controller.

It should be noted that, when the module type of the first optical module is the same as the type of the optical module on the motherboard detected last time by the Baseboard Management Controller (BMC), the BMC may directly use the configuration register parameter stored previously as the target parameter, without re-reading or configuring the parameter, thereby greatly accelerating the initialization process of the optical module and reducing the waiting time of starting or restarting.

It should be noted that the above steps simplify the parameter configuration flow during initialization, avoid repeated parameter reading and configuration steps, and especially for a large server environment or a data center, can significantly improve the initialization efficiency of batch equipment, and reduce the operation and maintenance cost.

It should be noted that, the use of the configuration parameters that have been recorded last time and have been verified can ensure that the optical module can quickly enter a stable working state when being started this time, so as to reduce the risk of initialization failure or instability caused by improper parameter configuration.

It should be noted that, by determining the module type of the optical module and directly using the stored configuration parameters under the condition that the module types are consistent, the technical scheme effectively improves the initialization efficiency of the PCIe optical interconnection link device and reduces the resource consumption.

Step S71, determining an interrupt type of the interrupt of the first optical module, and determining the state of the first optical module by detecting a state register in the first optical module when the interrupt type is a second type, wherein the interrupt of the second type is generated after the first optical module configures a configuration register of the first optical module according to a target parameter determined by the baseboard management controller, and the first optical module updates the state of the first optical module in the state register to an active state after the first optical module configures the configuration register of the first optical module according to the target parameter determined by the baseboard management controller;

And S72, clearing the interrupt state of the first optical module.

In step S71, the BMC can identify the interrupt type, and when determining that the interrupt type is the second type, further detects the state of the optical module by reading the state register. This accurate state detection mechanism helps to quickly diagnose whether the light module has completed configuration according to the target parameters and enters an active state. This ensures that the configuration state of the light module is accurately tracked and any problems that have not reached the expected state after configuration can be timely found.

It should be noted that, after the first optical module configures its configuration register according to the target parameter determined by the BMC, the state of the optical module in the state register is updated to be an active state, which indicates that the optical module has already completed initialization and is ready for normal communication operation. This state update mechanism provides a reliable hardware state guarantee for subsequent link resets and data transmissions.

It should be noted that, through the processing of the second type interrupt, it can be quickly confirmed that the optical module has completed configuration according to the target parameter, and enters the active state, so that the waiting time in the initialization stage is reduced, and the starting speed of the whole PCIe optical interconnection link is accelerated.

By identifying and processing specific types of interrupts, the state change of the optical module can be automatically detected and confirmed, the self-recovery capability of solving the initialization problem is enhanced, the need of manual intervention is reduced, and the intelligent level is improved.

In an exemplary embodiment, the determining the working state of the first optical module includes determining that the working state of the first optical module is a normal working state when first indication information sent by a baseboard management controller of the host is obtained, where the first indication information is sent indication information when the baseboard management controller of the host determines that the first optical module is in an active state by detecting a status register in the first optical module.

In an exemplary embodiment, the determining the working state of the second optical module includes determining that the working state of the second optical module is a normal working state when second indication information sent by a baseboard management controller of the host is obtained, where the second indication information is indication information sent by the baseboard management controller of the host after obtaining third indication information sent by the first optical module, and the third indication information is information sent to the second optical module when the baseboard management controller of the device determines that the second optical module is in an activated state by detecting a status register in the second optical module.

In this embodiment, the Device end CPLD, the BMC, and the optical module are similar to the Host end in flow, and when the Device end BMC detects that the Device optical module is working normally, the Device end BMC transmits the status information to the Device end optical module through the I2C electrical signal, the Device end optical module converts the I2C electrical signal into the I2C optical signal and transmits the I2C optical signal to the Host end optical module through the optical fiber line, and converts the I2C optical signal transmitted from the Device end into the I2C electrical signal inside the Host optical module, and after the Host end BMC analyzes the I2C signal, the Device end optical module transmits the working status to the Host end CPLD for subsequent logic judgment.

In this embodiment, in order to better understand the above process, the following specific description is provided, where the BMC determines whether the optical module works normally by combining the CPLD, the BMC, and the optical module, and the determination flow is described as follows:

1. CPLD detects the PRSNT in-place signal (namely the in-place state signal) of the optical module, pulls up the Reset signal when the optical module is detected to be in place, and controls the optical module to enter a normal initialization flow;

2. the optical module reads the power-on default configuration to a related configuration register, the state enters LowPwr states from an initial Reset state, the state change is recorded to a state change register, the state is updated in the state register, and an INT interrupt signal is set to be high level;

3. The CPLD detects that the INT interrupt signal is High, and informs the BMC to detect an interrupt register related to the optical module so as to eliminate the interrupt state; after the actions are completed, the CPLD sets LPmode signals to be low level, and controls the optical module to enter into a High Power Mode in normal operation;

4. The optical module detects LPmode that the signal is in low level, the state is changed from LowPwr to ModuleReady, and the state is updated into a state register;

5. the optical module initializes each data link according to the set parameters in the configuration register, the state of the module enters Actived state after the completion, the state is updated into the state register, the state change is recorded into the state change register, and the INT interrupt signal is set to be high level;

6. the CPLD detects that the interrupt signal is changed to the high level again, informs the BMC to detect the related state change register and clears the optical module interrupt state, and reads the state register and detects that the optical module is changed to Actived states, and at the moment, the optical module is considered to be completely initialized normally and can work normally.

It should be noted that, fig. 4 illustrates a PCIe optical interconnect link reset flow based on an optical module, and detailed processes are shown in the foregoing embodiments, and the disclosure is not repeated here.

The Device CPLD detects the reset signal state of the Host Device, when the detected PERST signal state changes from high to low to high, the Host Device is regarded as sending out a reset action to the outside for the Device on the PCIe link, the Host CPLD continuously monitors whether the Host Device sends out the reset action for subsequent logic judgment, the Host CPLD detects the in-place state of the Host optical module, when the optical module is in place, the CPLD and the BMC control the optical module to enter a normal initialization flow, and judge whether the optical module enters a normal working state according to the above judgment flow, and after the Host BMC detects that the Host optical module works normally, the information is transmitted to the Host CPLD for subsequent logic judgment.

It should be noted that in the field of high-speed data communications, especially in the server and data center environments, the performance and stability of PCIe optical interconnect links are critical to system design. The optical module is used as a bridge for photoelectric signal conversion, and the working state and performance of the optical module directly influence the transmission rate and data integrity of a link. While the configuration parameters of the optical module are typically set during the initialization phase and remain fixed during subsequent operation, this may not be able to accommodate the performance requirements imposed by link load changes or environmental condition variations. Therefore, the application also provides a system capable of dynamically adapting the configuration parameters of the optical module according to the real-time state of the link, which has important significance for maintaining the optimal performance of the link.

The application provides an intelligent dynamic adaptation and performance optimization system of a PCIe optical interconnection link based on an optical module, which is characterized in that a real-time performance monitoring and dynamic parameter adaptation mechanism is introduced. The specific implementation steps are as follows:

1. And the real-time performance monitoring is to continuously monitor real-time performance indexes of the PCIe optical interconnection link, such as error rate, transmission delay, signal strength and the like through the CPLD, and transmit the data to the BMC for analysis.

2. And (3) intelligent analysis and decision, namely after the BMC receives the performance data, analyzing the link state through a preset algorithm, and judging whether the configuration parameters of the optical module need to be adapted. If the link performance drops below the preset threshold, the BMC will automatically trigger the parameter adaptation flow.

3. And the BMC sends an adaptation command to the optical module through the I2C bus according to the current state of the link and the adaptation strategy, and dynamically adjusts parameters in a configuration register, such as output optical power, receiving sensitivity, modulation mode and the like, so as to optimize the link performance.

4. And after the adaptation is finished, the performance monitoring module monitors the link performance again to confirm whether the optimization target is reached. If not, the BMC may continue to adjust until the performance improves to a satisfactory level.

5. And (3) recording parameter adaptation log, namely recording parameter change of each adaptation, link states and effects before and after the adaptation by the BMC in the whole adaptation process, and using the parameter adaptation log for subsequent performance analysis and adaptation strategy optimization.

By adopting the above development technical scheme, the performance stability and efficiency of the PCIe optical interconnection link based on the optical module can be remarkably improved, and the specific technical effects are as follows:

1. dynamic optimization of link performance, namely, through real-time monitoring and intelligent analysis, the system can dynamically adjust configuration parameters of the optical module to adapt to changing link conditions, ensure the optimal state of link performance, reduce error rate and delay of data transmission and improve the reliability of data transmission.

2. The self-adaptive capacity of the link is enhanced, the dynamic adapting mechanism enables the link to automatically respond to environmental changes and load fluctuation, the self-adaptability and the robustness of the system are improved, and the performance bottleneck of the link caused by fixed parameter setting is reduced.

3. The operation and maintenance efficiency and the intelligent level are improved, the automatic parameter adaptation and optimization flow reduces the manual intervention requirement, operation and maintenance work is simplified, and meanwhile, detailed performance adjustment history and effect evaluation are provided for operation and maintenance personnel through log recording, so that the operation and maintenance efficiency and the intelligent level of the system are improved.

In summary, by introducing the real-time performance monitoring and dynamic parameter adapting mechanism, the intelligent dynamic adapting and performance optimizing of the PCIe optical interconnection link based on the optical module are realized, and the intelligent operation and maintenance level of the system has remarkable technical effects for improving the stability and efficiency of the link, reducing the cost, and is an important direction for the development of future server and data center communication technologies.

The CPLD is used for judging the in-place state of the optical modules at the two ends of the optical fiber line, and the BMC, the CPLD and the internal state register combination of the optical modules are used for judging the working state of the optical modules, and the CPLD controls whether link resetting actions sent by the PCIe host are transmitted or not according to the working state of the optical modules at the two ends of the optical fiber line, so that when the PCIe link terminal equipment performs link resetting is controlled. When the PCIe link is reset, the problems that the PCIe rate cannot reach the expected rate and the system works in the speed-down and bandwidth-down state due to the fact that the configuration parameters of the optical module are unsuitable or the link is unstable because the optical module does not enter the normal working state are avoided.

In the technical scheme of the application, whether the optical module is in a normal working state can be accurately judged, when the PCIe optical interconnection link based on the transmission of the optical module is reset, the PCIe link can be stably transmitted at an expected speed through the optical module, and the PCIe host and the PCIe terminal equipment can be stably communicated, so that the PCIe link training is completed. The method can effectively solve the problems that when the PCIe optical interconnection link is reset, the PCIe link cannot be stably transmitted through the optical module due to the fact that the initialization time difference and the internal configuration parameter difference of the optical module are different, and when the PCIe link is reset, the optical module does not complete internal initialization, so that the PCIe link can be communicated in a speed-reducing and bandwidth-reducing state.

From the description of the above embodiments, it will be clear to a person skilled in the art that the method according to the above embodiments may be implemented by means of software plus the necessary general hardware platform, but of course also by means of hardware, but in many cases the former is a preferred embodiment. Based on such understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art in the form of a software product stored in a storage medium (e.g. ROM/RAM, magnetic disk, optical disk) comprising instructions for causing a terminal device (which may be a mobile phone, a computer, a server, or a network device, etc.) to perform the method according to the embodiments of the present application.

The embodiment also provides a device for sending a reset signal, which is used for implementing the foregoing embodiments and preferred embodiments, and is not described in detail. As used below, the term "module" may be a combination of software and/or hardware that implements a predetermined function. While the modules described in the following embodiments are preferably implemented in software, implementation in hardware, or a combination of software and hardware, is also possible and contemplated.

Fig. 5 is a block diagram of a configuration of a sending apparatus of a reset signal according to an embodiment of the present application, which is applied to a communication scenario between a host and a device, where the communication scenario includes the host, a first optical module of the host, the device, and a second optical module of the device, and electrical signals are transmitted between the host and the first optical module, optical signals are transmitted between the first optical module and the second optical module, and electrical signals are transmitted between the second optical module and the device, where the apparatus includes:

a determining module 52, configured to determine an operating state of the first optical module and an operating state of the second optical module;

and the sending module 54 is configured to send, according to the working state of the first optical module and the working state of the second optical module, the first reset signal sending condition of the host to send the first reset signal to the first optical module, so as to send the first reset signal to the device through the first optical module and the second optical module, where the first reset signal is used to reset the device and instruct the device to perform training of a communication link with the host.

According to the device, according to the working state of the first optical module of the main board and the working state of the second optical module of the equipment, the first reset signal is sent to the first optical module by the first reset signal sending condition of the host, so that the first reset signal is sent to the equipment through the first optical module and the second optical module. Because the working state of the optical module is considered when the reset signal is sent, the reset signal can be reasonably sent, by adopting the technical scheme, the problem that the host cannot reasonably send the reset signal under the condition that the host and the device perform data communication based on the optical signal is solved. The communication link can be stably transmitted at an expected speed through the optical module, and the host and the equipment can stably communicate, so that training of the communication link is completed.

In one exemplary embodiment, the sending module 54 is configured to send the first reset signal to the first optical module when the operating state of the first optical module and the operating state of the second optical module are both normal, the first reset signal sending condition is used to indicate that the host has sent the first reset signal, and to wait for the first reset signal sent by the host when the operating state of the first optical module and the operating state of the second optical module are both normal, the first reset signal sending condition is used to indicate that the host has not sent the first reset signal, and to send the first reset signal to the first optical module when the first reset signal sent by the host is acquired, and to prohibit sending the first reset signal to the first optical module when the operating state of the first optical module is not normal, or the operating state of the second optical module is not normal.

In an exemplary embodiment, the device further includes a processing module, configured to detect that, after the first reset signal is sent to the first optical module, the working state of the first optical module is switched from a normal working state to an abnormal working state within a preset time, and is switched to the normal working state again, and/or the working state of the second optical module is switched from the normal working state to the abnormal working state within the preset time, and is switched to the normal working state again, and send a second reset signal to the host, where the second reset signal is used to instruct the host to send the first reset signal again, and send the first reset signal to the first optical module when the first reset signal sent by the host is obtained and the working states of the first optical module and the second optical module are both in the normal working state.

In an exemplary embodiment, the processing module is further configured to send a second reset signal to the host when acquiring the reset instruction information sent by the baseboard management controller of the host, where the reset instruction information is used to instruct to reset the device and perform training of a communication link between the host and the device, and the second reset signal is used to instruct the host to send the first reset signal again, and send the first reset signal to the first optical module when acquiring the first reset signal sent by the host and the working states of the first optical module and the second optical module are both normal working states.

In an exemplary embodiment, the processing module is further configured to send, after sending the first reset signal to the first optical module, a second reset signal to the host when detecting that the operating state of the device is switched from a normal operating state to an abnormal operating state within a preset time and is switched to the normal operating state again, where the second reset signal is used to instruct the host to send the first reset signal again;

and under the condition that the first reset signal sent by the host is obtained and the working states of the first optical module and the second optical module are both normal working states, sending the first reset signal to the first optical module.

In an exemplary embodiment, the determining module 52 is further configured to determine, when first indication information sent by the baseboard management controller of the host is obtained, that the working state of the first optical module is a normal working state, where the first indication information is the sent indication information when the baseboard management controller of the host determines, by detecting a status register in the first optical module, that the first optical module is in an active state.

In an exemplary embodiment, the determining module 52 is further configured to determine, when second indication information sent by the baseboard management controller of the host is obtained, that the working state of the second optical module is a normal working state, where the second indication information is indication information sent by the baseboard management controller of the host after obtaining third indication information that the baseboard management controller of the device determines, by detecting a status register in the second optical module, that the second optical module is in an activated state, information sent to the second optical module.

In an exemplary embodiment, the processing module is further configured to detect an in-place status signal of the first optical module, control the first optical module to enter an initialization process when the in-place status signal is used to indicate that the first optical module is in place, and instruct a baseboard management controller of the host to process the interrupt of the first optical module when an interrupt signal sent by the first optical module is obtained.

In an exemplary embodiment, the processing module is further configured to instruct a baseboard management controller of the host to determine an interrupt type of an interrupt of the first optical module, and determine a target parameter of a configuration register of the first optical module if the interrupt type is a first type, where the first type of interrupt is an interrupt generated after the first optical module enters an initialization procedure and configures the configuration register according to a default configuration parameter of the configuration register, configure the configuration register of the first optical module according to the target parameter, and clear an interrupt state of the first optical module.

In an exemplary embodiment, the processing module is further configured to determine a module type of the first optical module, and determine the target parameter from a configuration file according to the module type of the first optical module, where the configuration file has parameters of configuration registers corresponding to different module types.

In an exemplary embodiment, the processing module is further configured to determine a module type of the first optical module, and if the module type of the first optical module is the same as the module type of the optical module of the motherboard detected last time by the baseboard management controller, determine a stored parameter of a configuration register of the optical module of the motherboard detected last time as the target parameter.

In an exemplary embodiment, the processing module is further configured to instruct a baseboard management controller of the host to determine an interrupt type of the interrupt of the first optical module, and determine a state of the first optical module by detecting a state register in the first optical module if the interrupt type is a second type, wherein the second type of interrupt is an interrupt generated after the first optical module configures a configuration register of the first optical module according to a target parameter determined by the baseboard management controller, and the first optical module updates the state of the first optical module in the state register to an active state after the first optical module configures the configuration register of the first optical module according to the target parameter determined by the baseboard management controller, and clears the interrupt state of the first optical module.

It should be noted that each of the above modules may be implemented by software or hardware, and the latter may be implemented by, but not limited to, the above modules all being located in the same processor, or each of the above modules being located in different processors in any combination.

Embodiments of the present application also provide a computer readable storage medium having a computer program stored therein, wherein the computer program is arranged to perform the steps of any of the method embodiments described above when run.

Alternatively, in the present embodiment, the above-described computer program may be configured to execute the following steps by the computer program:

S1, determining the working state of the first optical module and the working state of the second optical module;

s2, according to the working state of the first optical module and the working state of the second optical module, the first reset signal sending condition of the host sends the first reset signal to the first optical module so as to send the first reset signal to the equipment through the first optical module and the second optical module, wherein the first reset signal is used for resetting the equipment and indicating the equipment to train a communication link between the equipment and the host.

In an exemplary embodiment, the computer readable storage medium may include, but is not limited to, a U disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a removable hard disk, a magnetic disk, or an optical disk, etc. various media in which a computer program may be stored.

An embodiment of the application also provides an electronic device comprising a memory 602 and a processor 604, the memory 602 having stored therein a computer program, the processor 604 being arranged to perform the steps of any of the method embodiments described above by means of the computer program, as shown in fig. 6.

Alternatively, in the present embodiment, the processor 604 may be configured to execute the following steps by a computer program:

S1, determining the working state of the first optical module and the working state of the second optical module;

Specific examples in this embodiment may refer to the examples described in the foregoing embodiments and the exemplary implementation, and this embodiment is not described herein.

Alternatively, it will be appreciated by those of ordinary skill in the art that the configuration shown in fig. 6 is merely illustrative, and that fig. 6 is not intended to limit the configuration of the electronic device described above. For example, the electronic device may also include more or fewer components (e.g., network interfaces, etc.) than shown in FIG. 6, or have a different configuration than shown in FIG. 6.

The memory 602 may be used to store software programs and modules, such as program instructions/modules corresponding to the method for sending a reset signal and the device for sending a reset signal in the embodiment of the present application, and the processor 604 executes the software programs and modules stored in the memory 602, thereby performing various functional applications and data processing, that is, implementing the method for sending a reset signal. The memory 602 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, memory 602 may further include memory located remotely from processor 604, which may be connected to the terminal via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof. The memory 602 may be used to store, but is not limited to, information such as system configuration files. As an example, as shown in fig. 6, the memory 602 may include, but is not limited to, the determination module 52 and the transmission module 54 in the transmission apparatus including the reset signal. In addition, other module units in the above-mentioned transmitting device of the reset signal may be included, but are not limited to, and are not described in detail in this example.

Optionally, the transmission device 606 is used to receive or transmit data via a network. Specific examples of the network described above may include wired networks and wireless networks. In one example, the transmission device 606 includes a network adapter (Network Interface Controller, NIC) that can connect to other network devices and routers via a network cable to communicate with the internet or a local area network. In one example, the transmission device 606 is a Radio Frequency (RF) module for communicating wirelessly with the internet.

The electronic device further includes a display 608 and a connection bus 610 for connecting the various modular components of the electronic device.

Embodiments of the application also provide a computer program product comprising a computer program which, when executed by a processor, implements the steps of any of the method embodiments described above.

Embodiments of the present application also provide another computer program product comprising a non-volatile computer readable storage medium storing a computer program which, when executed by a processor, implements the steps of any of the method embodiments described above.

Embodiments of the present application also provide a computer program comprising computer instructions stored in a computer-readable storage medium, a processor of a computer device reading the computer instructions from the computer-readable storage medium, the computer instructions being executable by a burial device to cause the computer device to perform the steps of any of the method embodiments described above.

It will be appreciated by those skilled in the art that the modules or steps of the application described above may be implemented in a general purpose computing device, they may be concentrated on a single computing device, or distributed across a network of computing devices, they may be implemented in program code executable by computing devices, so that they may be stored in a storage device for execution by computing devices, and in some cases, the steps shown or described may be performed in a different order than that shown or described herein, or they may be separately fabricated into individual integrated circuit modules, or multiple modules or steps of them may be fabricated into a single integrated circuit module. Thus, the present application is not limited to any specific combination of hardware and software.

The above description is only of the preferred embodiments of the present application and is not intended to limit the present application, but various modifications and variations can be made to the present application by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the principle of the present application should be included in the protection scope of the present application.