CN202103633U - Analog-digital mixed clock duty cycle calibration circuit - Google Patents

本实用新型公开了一种数模混合模式时钟占空比校准电路，其特征在于：该电路包括脉冲发生器（1）、半周期延迟线（2）、RS触发器（3）、单端到差分转换电路（4）、数模混合电荷泵（5）和误差放大器（6）；其中，脉冲发生器（1）的输入端接待校准的原始输入时钟信号（CKI）；脉冲发生器（1）的输出端信号为缓冲后的输入时钟脉冲信号（CKB），该信号同时连接至半周期延迟线（2）的时钟输入端和RS触发器（3）的置位输入端（S）。本实用新型克服了传统的纯数字方式占空比校准电路调整所存在的离散型，实现占空比连续调整，且采用全数字工艺，在消耗更小的面积和功耗的情况下得到更高的调整精度。

The utility model discloses a digital-analog mixed mode clock duty cycle calibration circuit, which is characterized in that the circuit includes a pulse generator (1), a half-period delay line (2), an RS flip-flop (3), a single-ended to A differential conversion circuit (4), a digital-analog hybrid charge pump (5) and an error amplifier (6); wherein, the input terminal of the pulse generator (1) receives a calibrated original input clock signal (CKI); the pulse generator (1) The output signal of is the buffered input clock pulse signal (CKB), which is simultaneously connected to the clock input terminal of the half-period delay line (2) and the set input terminal (S) of the RS flip-flop (3). The utility model overcomes the discrete type existing in the adjustment of the duty ratio calibration circuit in the traditional pure digital mode, realizes the continuous adjustment of the duty ratio, and adopts an all-digital process to obtain higher efficiency while consuming less area and power consumption. adjustment accuracy.

数模混合模式时钟占空比校准电路Digital-analog mixed mode clock duty ratio calibration circuit

技术领域 technical field

本实用新型适用于各种高速通信传输中时钟占空比校准的应用场合，如高速数据存储器，流水线型处理器等，属于占空比校准电路设计的技术领域。 The utility model is suitable for the application occasions of clock duty ratio calibration in various high-speed communication transmissions, such as high-speed data memory, pipeline processor, etc., and belongs to the technical field of duty ratio calibration circuit design.

背景技术 Background technique

随着集成电路工艺的不断进步，芯片的工作速度不断的提高，并且已经开始广泛采用诸如双数据速率（Double Data Rate，DDR）、流水线（Pipeline）等技术来获取更大的数据吞吐率，这要求更为严格的时序精度，也即意味着对系统时钟的性能要求也更高，其中一个重要的性能指标就是时钟的占空比。一个50%占空比的时钟对于数据的传播最为有利，而对于采用双数据率、流水线工作方式的系统来说，50%的占空比能确保数据在传输过程中正确地建立和保持，保证系统正常稳定地工作。 With the continuous improvement of integrated circuit technology, the working speed of chips has been continuously improved, and technologies such as double data rate (Double Data Rate, DDR) and pipeline (Pipeline) have been widely used to obtain greater data throughput. More stringent timing accuracy is required, which means that the performance requirements of the system clock are also higher, and one of the important performance indicators is the duty cycle of the clock. A clock with a 50% duty cycle is most beneficial for data propagation, and for a system that adopts a double data rate and pipeline operation mode, a 50% duty cycle can ensure that the data is correctly established and maintained during transmission, ensuring The system works normally and stably.

在实际的应用中，系统的时钟往往通过锁相环（PLL）或者延迟锁相环（DLL）来产生，由于电路设计本身产生的失配和芯片制造过程中工艺与仿真模型的偏差，经过倍频、同步后产生的时钟往往不能保证50%的占空比。另外，在时钟的传播过程中，由于传播链路中同样存在着系统及工艺的偏差，也将会引起时钟的占空比失调。特别是在高频应用时，占空比的失调甚至会使时钟信号不能正常地翻转，从而造成严重的时序错误。因此，在对占空比要求严格的场合中，加入占空比校准电路是十分必须的。 In practical applications, the clock of the system is often generated by a phase-locked loop (PLL) or a delay-locked loop (DLL). The clock generated after frequency and synchronization often cannot guarantee a 50% duty cycle. In addition, during the propagation process of the clock, due to the deviation of the system and process also existing in the propagation link, the duty ratio of the clock will also be out of adjustment. Especially in high-frequency applications, the misadjustment of the duty cycle may even cause the clock signal to fail to flip normally, resulting in serious timing errors. Therefore, it is very necessary to add a duty cycle calibration circuit in occasions where the duty cycle is strictly required.

目前占空比校准方式主要分为两类：模拟方式和数字方式。模拟方式一般而言可以获得更高的占空比校正精度、工作在更高的频率、并获得更小的边沿抖动，但是模拟方式也存在着建立时间长，系统稳定性设计困难，以及受工艺-电压-温度（PVT）变化影响明显的缺点。纯数字方式的占空比校准可以做到快速建立、绝对稳定，以及PVT偏差影响不明显等优良特性。但由于数字方式受到最小延迟单元的限制，校准精度存在着离散性，往往不能获得精确地校准结果。而将两者结合起来可以实现快速建立和高校正精度。 At present, the duty cycle calibration methods are mainly divided into two categories: analog methods and digital methods. Generally speaking, the analog method can obtain higher duty cycle correction accuracy, work at a higher frequency, and obtain smaller edge jitter, but the analog method also has long settling time, difficulty in system stability design, and process constraints. -Voltage-temperature (PVT) variation affects obvious disadvantages. The purely digital duty cycle calibration can achieve excellent characteristics such as fast establishment, absolute stability, and no obvious influence of PVT deviation. However, because the digital method is limited by the minimum delay unit, the calibration accuracy is discrete, and it is often impossible to obtain accurate calibration results. Combining the two results in fast settling and high calibration accuracy.

发明内容 Contents of the invention

技术问题：本实用新型的目的是提供一种能够解决上述背景中提到的技术问题的数模混合模式时钟占空比校准电路，解决在高速系统中时钟的占空比校准问题。 Technical problem: The purpose of this utility model is to provide a digital-analog mixed-mode clock duty ratio calibration circuit that can solve the technical problems mentioned in the above background, and solve the problem of clock duty ratio calibration in high-speed systems.

技术方案：为解决上述技术问题，本实用新型提出一种数模混合模式时钟占空比校准电路，该电路包括脉冲发生器、半周期延迟线、RS触发器、单端到差分转换电路、数模混合电荷泵和误差放大器；其中， Technical solution: In order to solve the above technical problems, the utility model proposes a digital-analog hybrid mode clock duty ratio calibration circuit, which includes a pulse generator, a half-period delay line, an RS flip-flop, a single-ended to differential conversion circuit, a digital mixed-mode charge pump and error amplifier; where,

脉冲发生器的输入端接待校准的原始输入时钟信号；脉冲发生器的输出端信号为缓冲后的输入时钟脉冲信号，该信号同时连接至半周期延迟线的时钟输入端和RS触发器位输入端；半周期延迟线的输出端信号即半周期延迟时钟脉冲信号接RS触发器的复位输入端；RS触发器的输出端处信号即为校准后的时钟信号；该校准后的时钟信号输入至单端到差分转换电路的输入端；单端到差分转换电路输出端的输出信号为差分时钟正信号、差分时钟负信号；该差分时钟正信号、差分时钟负信号分别接至数模混合电荷泵的同名输入端，在数模混合电荷泵的第一输出端、第二输出端间产生差分电压；该差分电压输入至误差放大器的差分输入端，误差放大器的输出端为占空比微调控制电压，该占空比微调控制电压输入至半周期延迟线的延迟时间控制输入端。 The input of the pulse generator receives the calibrated raw input clock signal; the output signal of the pulse generator is the buffered input clock pulse signal, which is connected to both the clock input of the half-period delay line and the RS flip-flop bit input The signal at the output end of the half-period delay line, that is, the half-period delayed clock pulse signal, is connected to the reset input end of the RS flip-flop; the signal at the output end of the RS flip-flop is the calibrated clock signal; the calibrated clock signal is input to the single terminal to the input of the differential conversion circuit; the output signal from the single-ended to the output of the differential conversion circuit is a differential clock positive signal and a differential clock negative signal; the differential clock positive signal and differential clock negative signal are respectively connected to the digital-analog hybrid charge pump of the same name The input terminal generates a differential voltage between the first output terminal and the second output terminal of the digital-analog hybrid charge pump; the differential voltage is input to the differential input terminal of the error amplifier, and the output terminal of the error amplifier is a duty cycle fine-tuning control voltage, the The duty cycle fine-tuning control voltage is input to the delay time control input of the half-cycle delay line.

优选的，所述半周期延迟线HCDL由一个基本延迟单元和一至若干级半周期延迟线单元依次串联而成；其中，基本延迟单元的第一信号输入端即正向延迟线输入端接半周期延迟线输入端的输入时钟信号，基本延迟单元的第二信号输入端接高电平，基本延迟单元DLY的使能端接高电平，基本延迟单元的控制信号输入端接低电平，基本延迟单元的输出端接第一级半周期延迟线单元的第一信号输入端，第一级半周期延迟线单元的第二信号输入端即延迟线使能输入端接高电平，第一级半周期延迟线单元的第四信号输入端即边沿检测输入端接地，第一级半周期延迟线单元的第三信号输出端即反向延迟线的输出端，也即半周期延迟线的输出端；此后各级半周期延迟线单元的第一信号输入端即正向延迟线输入端接前一级半周期延迟线单元的第一信号输出端即正向延迟线输出端，第二信号输入端即延迟线使能输入端接前一级的第二信号输出端即延迟线使能输出端，第三信号输出端即反向延迟线输出端接前一级的第三信号输入端即反向延迟线输入端；最后一级半周期延迟线单元的第三信号输入端即反向延迟线输入端接低电平；各级半周期延迟单元的第五信号输入端即控制信号输入端与基本延迟单元的同名端口相接并接半周期延迟线的延迟时间控制输入端；除第一级外的各级半周期延迟线单元的第四信号输入端即边沿检测输入端接半周期延迟线输入端的输入时钟脉冲信号；半周期延迟线单元中上文未提及的信号输入和输出端悬空。 Preferably, the half-period delay line HCDL is formed by serially connecting a basic delay unit and one to several stages of half-period delay line units; wherein, the first signal input terminal of the basic delay unit, that is, the forward delay line input terminal, is connected to the half-period The input clock signal of the delay line input terminal, the second signal input terminal of the basic delay unit is connected to a high level, the enable terminal of the basic delay unit DLY is connected to a high level, the control signal input terminal of the basic delay unit is connected to a low level, and the basic delay The output terminal of the unit is connected to the first signal input terminal of the first-stage half-cycle delay line unit, the second signal input terminal of the first-stage half-cycle delay line unit, that is, the delay line enable input terminal is connected to a high level, and the first-stage half-cycle delay line unit is connected to a high level. The fourth signal input terminal of the periodic delay line unit is the edge detection input terminal grounded, and the third signal output terminal of the first-stage half-period delay line unit is the output terminal of the reverse delay line, that is, the output terminal of the half-period delay line; Afterwards, the first signal input end of the half-period delay line unit of each level is the forward delay line input end connected to the first signal output end of the previous stage half-period delay line unit, which is the forward delay line output end, and the second signal input end is the forward delay line output end. The delay line enable input terminal is connected to the second signal output terminal of the previous stage, which is the delay line enable output terminal, and the third signal output terminal, which is the reverse delay line output terminal, is connected to the third signal input terminal of the previous stage, which is the reverse delay Line input terminal; the third signal input terminal of the last half-cycle delay line unit, that is, the reverse delay line input terminal, is connected to a low level; the fifth signal input terminal of each half-cycle delay unit, that is, the control signal input terminal and the basic delay The port with the same name of the unit is connected and connected to the delay time control input end of the half-period delay line; the fourth signal input end of the half-period delay line unit of each stage except the first stage is the edge detection input end connected to the input end of the half-period delay line Input the clock pulse signal; the signal input and output ends of the half-period delay line unit not mentioned above are left floating.

优选的，所述的半周期延迟线中的基本延迟单元使用一个控制电压控制的压控电流不饱和型反相器来实现延迟时间连续可调；该基本延迟单元采用边沿触发自动刷新的动态结构，所产生的正脉冲宽度恒定。 Preferably, the basic delay unit in the half-period delay line uses a voltage-controlled current unsaturated inverter controlled by a control voltage to realize continuous adjustable delay time; the basic delay unit adopts a dynamic structure of edge-triggered automatic refresh , the resulting positive pulse width is constant.

    优选的，数模混合电荷泵和误差放大器构成了模拟闭环微调电路；所述数模混合电荷泵采用自偏置结构，该数模混合电荷泵将差分时钟正信号、差分时钟负信号的占空比偏差转化成数模混合电荷泵的第一输出端、第二输出端的差分输出电压；误差放大器由一个NMOS输入单级跨导放大器和一个PMOS输入单级跨导放大器并联而成互补放大器，该误差放大器将数模混合电荷泵差分输出电压放大，并将差分输入转化为单端输出控制电压，该输出控制电压反馈至半周期延迟线的延迟时间控制输入端，对半周期延迟线的延迟时间微调。 Preferably, the digital-analog hybrid charge pump and the error amplifier constitute an analog closed-loop fine-tuning circuit; the digital-analog hybrid charge pump adopts a self-bias structure, and the digital-analog hybrid charge pump converts the duty cycle of the differential clock positive signal and the differential clock negative signal The ratio deviation is converted into the differential output voltage of the first output terminal and the second output terminal of the digital-analog hybrid charge pump; the error amplifier is composed of an NMOS input single-stage transconductance amplifier and a PMOS input single-stage transconductance amplifier connected in parallel to form a complementary amplifier. The error amplifier amplifies the differential output voltage of the digital-analog hybrid charge pump and converts the differential input into a single-ended output control voltage. The output control voltage is fed back to the delay time control input of the half-cycle delay line, and the delay time of the half-cycle delay line fine-tuning.

有益效果：该电路综合数字模式和模拟模式的优点，将两者结合起来，采用数字开环结构实现粗校准和模拟闭环结构实现精细校准，提高了建立速度和校准精度，同时采用全数字工艺便于与数字系统集成。与现有技术相比，本实用新型的优点在于： Beneficial effect: the circuit integrates the advantages of digital mode and analog mode, combines the two, adopts digital open-loop structure to realize coarse calibration and analog closed-loop structure to realize fine calibration, improves the establishment speed and calibration accuracy, and adopts all-digital technology to facilitate Integrate with digital systems. Compared with the prior art, the utility model has the advantages of:

1、      相对于纯模拟占空比校准方式，本实用新型中所描述的占空比校准电路采用半周期延迟线进行粗校准，具有快速建立、更好的稳定性等优势。 1. Compared with the pure analog duty cycle calibration method, the duty cycle calibration circuit described in this utility model uses a half-cycle delay line for rough calibration, which has the advantages of rapid establishment and better stability.

2、      相对于纯数字占空比校准方式，本实用新型采用模拟反馈环路对半周期延迟线单元的延迟时间进行自动校正，具有更高的时钟占空比校准精度，并且克服了纯数字占空比校准的离散性，兼顾了调整精度与相位分辨率。 2. Compared with the pure digital duty cycle calibration method, the utility model uses an analog feedback loop to automatically correct the delay time of the half-cycle delay line unit, which has higher clock duty cycle calibration accuracy and overcomes the pure digital duty cycle calibration method. The discrete nature of space ratio calibration takes into account the adjustment accuracy and phase resolution.

3、      本实用新型对数字式占空比校准电路半周期延迟线的结构和其基本延迟单元进行了改进，使基本延迟单元延迟时间连续可调，并可节省匹配延迟线。负反馈结构使其能够更好的抵抗PVT偏差，在同等的工艺条件下工作更为可靠。 3. The utility model improves the structure of the half-cycle delay line of the digital duty cycle calibration circuit and its basic delay unit, so that the delay time of the basic delay unit can be continuously adjusted, and the matching delay line can be saved. The negative feedback structure enables it to better resist PVT deviation and work more reliably under the same process conditions.

4、      本实用新型采用连续可调的闭环微调电路，在相同的输入时钟频率范围下，需要更少的基本延迟单元，降低了面积和功耗。 4. The utility model adopts a continuously adjustable closed-loop fine-tuning circuit. Under the same input clock frequency range, fewer basic delay units are required, which reduces the area and power consumption.

本实用新型采用全数字工艺实现数模混合模式时钟占空比校准，便于与其他数字系统集成。 The utility model adopts an all-digital technology to realize the digital-analog mixed mode clock duty cycle calibration, which is convenient for integration with other digital systems.

附图说明 Description of drawings

图1为本实用新型的结构框图； Fig. 1 is a block diagram of the utility model;

图2为本实用新型的全局时序图； Fig. 2 is the global sequence diagram of the present utility model;

图3为脉冲发生器结构示意图； Fig. 3 is the structural schematic diagram of pulse generator;

图4为半周期延迟线结构示意图； Fig. 4 is a schematic diagram of a structure of a half-period delay line;

图5为半周期延迟线单元结构示意图； Fig. 5 is a structural schematic diagram of a half-period delay line unit;

图6为本实用新型的基本延迟单元电路结构示意图； Fig. 6 is a schematic diagram of the circuit structure of the basic delay unit of the present utility model;

图7为RS触发器结构示意图； FIG. 7 is a schematic structural diagram of the RS flip-flop;

图8为单端到差分转换电路结构示意图； Fig. 8 is a schematic structural diagram of a single-ended to differential conversion circuit;

图9为同相缓冲器结构示意图； FIG. 9 is a schematic structural diagram of a non-inverting buffer;

图10为本实用新型的数模混合结构电荷泵电路结构示意图。 FIG. 10 is a schematic structural diagram of a charge pump circuit with a digital-analog hybrid structure of the present invention.

图11为误差放大器电路结构示意图。 FIG. 11 is a schematic diagram of the circuit structure of the error amplifier.

其中有：脉冲发生器PG 1、原始输入时钟信号CKI、由脉冲发生器产生的缓冲时钟脉冲信号CKB，半周期延迟线HCDL 2、RS触发器3、半周期延迟时钟脉冲信号CKD、RS触发器合成的时钟信号CKG，校准后同向时钟信号CKO+、校准后反向时钟信号CKO-、半周期延迟线单元2-1正向延迟线输入端FDI、半周期延迟线单元延迟线使能输入端ENI、半周期延迟线单元反向延迟线输出端BDO、半周期延迟线单元反向延迟线输入端BDI、半周期延迟线单元延迟线使能输出端ENO、半周期延迟线单元正向延迟线输出端FDO、半周期延迟线延迟时间控制输入端VCR、半周期延迟线单元边沿检测输入端CI、传统基本延迟单元、改进基本延迟单元2-2，单端到差分转换电路STD 4，数模混合电荷泵CCP 5，误差放大器6。 Among them: pulse generator PG 1, original input clock signal CKI, buffered clock pulse signal CKB generated by the pulse generator, half-cycle delay line HCDL 2, RS flip-flop 3, half-cycle delayed clock signal CKD, RS flip-flop Synthesized clock signal CKG, calibrated co-directional clock signal CKO+, calibrated reverse clock signal CKO-, half-period delay line unit 2-1 forward delay line input FDI, half-period delay line unit delay line enable input ENI, half-period delay line unit reverse delay line output BDO, half-period delay line unit reverse delay line input BDI, half-period delay line unit delay line enable output ENO, half-period delay line unit forward delay line Output terminal FDO, half-period delay line delay time control input terminal VCR, half-period delay line unit edge detection input terminal CI, traditional basic delay unit, improved basic delay unit 2-2, single-ended to differential conversion circuit STD 4, digital-to-analog Hybrid charge pump CCP 5, error amplifier 6.

具体实施方式   Detailed ways

下面将参照附图对本实用新型的实施例进行说明。 Embodiments of the utility model will be described below with reference to the accompanying drawings.

本实用新型的目的在于，针对现有的数字方式占空比校准电路存在的不足，提出一种在指定工艺下能在更宽的频率、占空比范围内进行占空比校准的电路结构。除此之外，所提出的方案对工艺失配等现象也具有较好的抑制力。 The purpose of this utility model is to propose a circuit structure capable of performing duty cycle calibration in a wider frequency and duty cycle range under a specified process in view of the shortcomings of existing digital duty cycle calibration circuits. In addition, the proposed scheme also has a good suppression of process mismatch and other phenomena.

本实用新型全数字工艺数模混合模式时钟占空比校准电路，该电路包括脉冲发生器PG 1、半周期延迟线HCDL 2、RS触发器3、单端到差分转换电路STD 4，数模混合电荷泵CCP 5，误差放大器6。 The utility model presents an all-digital process digital-analog mixed mode clock duty cycle calibration circuit, which includes a pulse generator PG 1, a half-period delay line HCDL 2, an RS trigger 3, a single-end to differential conversion circuit STD 4, and a digital-analog hybrid Charge pump CCP 5, error amplifier 6.

该电路中脉冲发生器1的输入端接待校准的原始输入时钟信号CKI；脉冲发生器1的输出端信号为原始输入时钟信号缓冲后的具有固定脉宽的缓冲窄脉冲CKB，该信号被同时连接至半周期延迟线HCDL2的时钟输入端和RS触发器3的置位输入端S；半周期延迟线HCDL 2的输出端信号即相对于缓冲窄脉冲信号CKB延迟了半个时钟周期的半周期延迟信号CKD，该半周期延迟信号接RS触发器3的复位输入端R； RS触发器3的输出端Q处信号即为校准后的具有50%占空比校准时钟信号CKG，该信号接单端到差分转换电路STD 4的输入端，单端到差分转换电路STD 4的两个输出信号即为经过校准后的具有50%占空比的差分校准时钟信号CKO+、CKO-；同时，单端到差分转换电路STD 4的两个输出信号CKO+、CKO-分别连接至数模混合结构电荷泵CCP 5的差分同名输入端CKO+、CKO-；数模混合结构电荷泵CCP的第一输出信号FP和第二输出信号FN分别接至误差放大器5的反向输入端V-和同向输入端V+；误差放大器5的输出信号反馈至半周期延迟线HCDL 2的延迟时间控制输入端VCR，调整半周期延迟单元2-1的延迟时间，对占空比进行精细校正。脉冲产生器1的作用是对原始输入时钟信号进行缓冲，产生相对原始输入时钟信号上升有固定延迟的脉宽恒定的缓冲窄脉冲信号CKB，保障时钟信号对后续电路的扇出能力；半周期延迟线HCDL 2用来产生相对于缓冲窄脉冲信号CKB有半个时钟周期延迟的半周期延迟时钟信号CKD；RS触发器3使用上升沿相差恰为半个周期的缓冲窄脉冲信号CKB和半周期延迟信号CKD，利用上升沿触发原理，合成具有50%占空比的校准时钟信号CKG；单端到差分转换电路STD 4将单端信号转换为差分信号CKO+和CKO-；数模混合电荷泵CCP 5用来检测CKO+和CKO-占空比之差，并转换为FP与FN间电压差，该电压差经误差放大器6放大并反馈至半周期延迟线HCDL 2的延迟时间控制输入端VCR，调整基本延迟单元DLY 2-1-1的延迟时间，使半周期延迟线HCDL 2输出时钟信号相对其输入时钟的延迟时间精确为半个时钟周期，从而得到高校准精度的占空比均为50%的差分校准时钟信号CKO+和CKO-。 In this circuit, the input terminal of the pulse generator 1 receives the calibrated original input clock signal CKI; the output signal of the pulse generator 1 is the buffered narrow pulse CKB with a fixed pulse width buffered by the original input clock signal, and the signal is connected simultaneously To the clock input terminal of the half-period delay line HCDL2 and the set input terminal S of the RS flip-flop 3; the signal at the output terminal of the half-period delay line HCDL 2 is a half-period delay delayed by half a clock period relative to the buffered narrow pulse signal CKB Signal CKD, the half-cycle delay signal is connected to the reset input terminal R of RS flip-flop 3; the signal at the output terminal Q of RS flip-flop 3 is the calibrated clock signal CKG with a 50% duty cycle after calibration, and the signal is connected to single-ended to the input end of the differential conversion circuit STD 4, the two output signals of the single-ended to differential conversion circuit STD 4 are calibrated differential calibration clock signals CKO+ and CKO- with a 50% duty cycle; at the same time, the single-ended to differential The two output signals CKO+ and CKO- of the differential conversion circuit STD 4 are respectively connected to the differential input terminals CKO+ and CKO- of the digital-analog hybrid structure charge pump CCP 5 with the same name; the first output signal FP and the second output signal of the digital-analog hybrid structure charge pump CCP The two output signals FN are respectively connected to the inverting input terminal V- and the same input terminal V+ of the error amplifier 5; the output signal of the error amplifier 5 is fed back to the delay time control input terminal VCR of the half-period delay line HCDL 2 to adjust the half-period delay The delay time of unit 2-1, finely corrects the duty cycle. The function of pulse generator 1 is to buffer the original input clock signal, and generate a buffered narrow pulse signal CKB with a fixed pulse width and constant pulse width relative to the rise of the original input clock signal, so as to ensure the fan-out capability of the clock signal to subsequent circuits; half-cycle delay Line HCDL 2 is used to generate a half-period delayed clock signal CKD with a half clock cycle delay relative to the buffered narrow pulse signal CKB; RS flip-flop 3 uses the buffered narrow pulse signal CKB and the half-period delayed clock signal whose rising edges differ by exactly half a period Signal CKD, using the rising edge trigger principle, synthesizes a calibration clock signal CKG with a 50% duty cycle; single-ended to differential conversion circuit STD 4 converts single-ended signals into differential signals CKO+ and CKO-; digital-analog hybrid charge pump CCP 5 It is used to detect the difference between the duty cycle of CKO+ and CKO- and convert it into the voltage difference between FP and FN. The voltage difference is amplified by the error amplifier 6 and fed back to the delay time control input terminal VCR of the half-cycle delay line HCDL 2 to adjust the basic The delay time of the delay unit DLY 2-1-1 makes the delay time of the output clock signal of the half-period delay line HCDL 2 relative to its input clock accurate to half a clock cycle, thus obtaining a duty cycle of 50% with high calibration accuracy Differential calibration clock signals CKO+ and CKO-.

所述的脉冲发生器PG 1，如图1所示，为基本的脉冲产生电路，适当选择反相器101的尺寸可以改变输出脉冲宽度并足够的扇出驱动能力。 The pulse generator PG 1, as shown in FIG. 1, is a basic pulse generating circuit. Proper selection of the size of the inverter 101 can change the output pulse width and provide sufficient fan-out driving capability.

所述的半周期延迟线HCDL 2由一个基本延迟单元DLY 2-2与一至若干级半周期延迟线单元HCDLU 2-1依次串联而成，串联方法为：基本延迟单元DLY 2-2的第一信号输入端IN1即正向延迟线输入端接半周期延迟线HCDL 2输入端的输入时钟信号CKB，基本延迟单元DLY 2-2的第二信号输入端IN2接高电平，基本延迟单元DLY 2-2的使能端EN接高电平，基本延迟单元DLY 2-2的控制输入端VC接低电平，基本延迟单元DLY 2-2的输出端OUT接第一级半周期延迟线单元HCDLU 2-1的第一信号输入端FDI，第一级半周期延迟线单元HCDLU 2-1的第二信号输入端即延迟线使能输入端EDI接高电平，第一级半周期延迟线单元HCDLU 2-1的第四信号输入端即边沿检测输入端CI接地，第一级半周期延迟线单元HCDL 2-1的第三信号输出端即反向延迟线的输出端BDO信号即为半周期延迟线HCDL 2输出端半周期延时时钟信号；此后各级半周期延迟线单元HCDLU 2-1的第一信号输入端即正向延迟线输入端FDI接前一级半周期延迟线单元HCDLU 2-1的第一信号输出端即正向延迟线输出端FDO，第二信号输入端即延迟线使能输入端EDI接前一级的第二信号输出端即延迟线使能输出端EDO，第三信号输出端即反向延迟线输出端BDO接前一级的第三信号输入端即反向延迟线输入端BDI；最后一级半周期延迟线单元HCDLU 2-1的第三信号输入端即反向延迟线输入端BDI接低电平；各级半周期延迟单元HCDLU 2-1的第五信号输入端即控制信号输入端VC接HCDL 2的延迟时间控制输入端VCR；除第一级外的各级半周期延迟线单元HCDLU 2-1的第四信号输入端即边沿检测输入端CI接半周期延迟线HCDL 2输入端的输入时钟信号CKB；所有半周期延迟线单元HCDLU 2-1中上文未提及的信号输入和输出端悬空。 The half-period delay line HCDL 2 is composed of a basic delay unit DLY 2-2 and one to several stages of half-period delay line unit HCDLU 2-1 connected in sequence, and the series connection method is: the first delay unit DLY 2-2 of the basic delay unit The signal input terminal IN1 is the input terminal of the forward delay line connected to the input clock signal CKB of the input terminal of the half-period delay line HCDL 2, the second signal input terminal IN2 of the basic delay unit DLY 2-2 is connected to a high level, and the basic delay unit DLY 2- The enabling terminal EN of 2 is connected to high level, the control input terminal VC of basic delay unit DLY 2-2 is connected to low level, and the output terminal OUT of basic delay unit DLY 2-2 is connected to the first-stage half-cycle delay line unit HCDLU 2 The first signal input terminal FDI of -1, the second signal input terminal of the first-stage half-cycle delay line unit HCDLU 2-1, that is, the delay line enable input terminal EDI is connected to a high level, and the first-stage half-cycle delay line unit HCDLU The fourth signal input terminal of 2-1, that is, the edge detection input terminal CI is grounded, and the third signal output terminal of the first-stage half-period delay line unit HCDL 2-1, that is, the output terminal BDO signal of the reverse delay line is the half-period delay Line HCDL 2 output terminal half-period delay clock signal; Afterwards, the first signal input terminal of each level of half-period delay line unit HCDLU 2-1 is the forward delay line input terminal FDI connected to the previous stage half-period delay line unit HCDLU 2-1 The first signal output terminal of 1 is the forward delay line output terminal FDO, the second signal input terminal is the delay line enabling input terminal EDI connected to the second signal output terminal of the previous stage, namely the delay line enabling output terminal EDO, and the third The signal output terminal is the reverse delay line output terminal BDO connected to the third signal input terminal of the previous stage, namely the reverse delay line input terminal BDI; the third signal input terminal of the last stage half-period delay line unit HCDLU 2-1 is the reverse Connect the low level to the delay line input terminal BDI; the fifth signal input terminal of the half-cycle delay unit HCDLU 2-1 of each level is the control signal input terminal VC connected to the delay time control input terminal VCR of HCDL 2; except the first stage The fourth signal input terminal of the half-period delay line unit HCDLU 2-1 at all levels is the edge detection input terminal CI connected to the input clock signal CKB of the input terminal of the half-period delay line HCDL 2; all the above half-period delay line units HCDLU 2-1 Signal inputs and outputs not mentioned are floating.

所述的RS触发器3中，RS触发器的置位输入端S接第一反相器的输入端，RS触发器3的复位输入端R接第二反相器的输入端；第一、第二反相器的输出端分别接第一、第二与非门的第一信号输入端，第一、第二与非门的第二信号输入端分别接第二、第一与非门的输出端；第三反向器的输入端接第一与非门的输出端，第四反相器接第二与非门的输出端；第四反相器的输出端即为RS触发器3的输出端Q。 In the described RS flip-flop 3, the setting input end S of the RS flip-flop is connected to the input end of the first inverter, and the reset input end R of the RS flip-flop 3 is connected to the input end of the second inverter; the first, The output terminal of the second inverter is respectively connected to the first signal input terminal of the first and second NAND gates, and the second signal input terminals of the first and second NAND gates are respectively connected to the second and first NAND gates. Output terminal; the input terminal of the third inverter is connected to the output terminal of the first NAND gate, and the fourth inverter is connected to the output terminal of the second NAND gate; the output terminal of the fourth inverter is the RS flip-flop 3 The output terminal Q.

所述的单端到差分转换电路STD 4由同相缓冲器4-1和反相器构成，结构完全对称。该电路中单端输入信号CKG接第一、第二反相器和第一同相缓冲器4-1的输入端；第一反相器的输出端接第三反相器和第二同相缓冲器4-1的输入端；第一同相缓冲器4-1的输出端与第三反相器的输出端相连并与由第四、第五反相器首尾相连组成的锁存器的一端，同时连接到第六反相器的输入端；第二同相缓冲器4-1的输出端与第二反相器的输出端相连并与由第四、第五反相器首尾相连组成的锁存器的另一端，同时连接到第七反相器的输入端；第六、第七反相器的输出端即为差分输出信号端反向输出端CKO-和同向输出端CKO+。 The single-ended to differential conversion circuit STD 4 is composed of a non-inverting buffer 4-1 and an inverter, and the structure is completely symmetrical. In this circuit, the single-ended input signal CKG is connected to the input terminals of the first and second inverters and the first non-inverting buffer 4-1; the output terminal of the first inverter is connected to the third inverter and the second non-inverting buffer The input terminal of the device 4-1; the output terminal of the first non-inverting buffer 4-1 is connected with the output terminal of the third inverter and connected with one end of the latch composed of the fourth and fifth inverters end to end , simultaneously connected to the input terminal of the sixth inverter; the output terminal of the second non-inverting buffer 4-1 is connected to the output terminal of the second inverter and connected to the lock composed of the fourth and fifth inverters end to end The other end of the register is connected to the input end of the seventh inverter at the same time; the output ends of the sixth and seventh inverters are the differential output signal end inverting output end CKO- and the non-inverting output end CKO+.

所述的数模混合结构电荷泵CCP 5中第一、第二晶体管NM1、NM2的源极、漏极和衬底相接均接地，栅极分别接第三、第四晶体管NM3、NM4的栅极；第三、第四晶体管的源极和衬底接地，漏极相接并接第五、第六晶体管NM5、NM6的源极，；第五、第六晶体管的栅极分别与第七、第八晶体管PM1、PM2的栅极相接并分别接电荷泵同向输入端CKO+和反向输入端CKO-，第五、第六晶体管的漏极分别与第七、第八晶体管的漏极相接，第五、第六晶体管的衬底接地；第七、第八晶体管的源极相接并与第九、第十晶体管PM3、PM4的漏极相接，第七、第八晶体管的衬底接高电平； 第九、第十晶体管的源极与衬底均接高电平；第一、第三、第九晶体管的栅极和第五、第七晶体管的漏极相接并接至电荷泵CCP 5的反向输出端FN，第二、第四、第十晶体管的栅极和第六、第八晶体管的漏极相接并接至电荷泵CCP 5的同向输出端FP。 The sources, drains and substrates of the first and second transistors NM1 and NM2 in the digital-analog hybrid structure charge pump CCP 5 are connected to the ground, and the gates are respectively connected to the gates of the third and fourth transistors NM3 and NM4. pole; the source and substrate of the third and fourth transistors are grounded, and the drains are connected and connected to the source of the fifth and sixth transistors NM5 and NM6; the gates of the fifth and sixth transistors are respectively connected to the seventh and sixth transistors The gates of the eighth transistors PM1 and PM2 are connected to each other and are respectively connected to the same input terminal CKO+ and the reverse input terminal CKO- of the charge pump, and the drains of the fifth and sixth transistors are connected to the drains of the seventh and eighth transistors respectively. connected, the substrates of the fifth and sixth transistors are grounded; the sources of the seventh and eighth transistors are connected and connected with the drains of the ninth and tenth transistors PM3 and PM4, and the substrates of the seventh and eighth transistors connected to high level; the sources and substrates of the ninth and tenth transistors are connected to high level; the gates of the first, third and ninth transistors are connected to the drains of the fifth and seventh transistors and connected to The inverting output terminal FN of the charge pump CCP 5, the gates of the second, fourth and tenth transistors and the drains of the sixth and eighth transistors are connected and connected to the non-inverting output terminal FP of the charge pump CCP 5.

所述的误差放大器OTA 6由一个基本NMOS管差分输入、单端输出跨导放大器和一个基本PMOS管差分输入、单端输出跨导放大器并联而成，具有较宽的带宽和轨到轨输入输出电压摆幅。 The error amplifier OTA 6 is composed of a basic NMOS transistor differential input, single-ended output transconductance amplifier and a basic PMOS transistor differential input, single-ended output transconductance amplifier in parallel, and has a wide bandwidth and rail-to-rail input and output voltage swing.

本实用新型中半周期延迟线以及有其与数模混合电荷泵、误差放大器等组成的闭环电路是实现占空比校准的关键模块。如图4所示，输入到半周期延迟线中的缓冲窄脉冲信号CKB首先在由延迟时间Δ不可调的基本延迟单元的组成的正向延迟线中向右传播。当下一个外部时钟信号到来时，已经在正向延迟线中传播了一个时钟周期的时钟信号经一系列判决和选通电路进入反向延迟线中向左传播。电路设计时使得时钟信号在正弦延迟线中经过2N+1个基本延迟单元，而在反向延迟线中经过N个基本延迟单元。正向延迟线中基本延迟单元的控制输入端VC始终接地，其延迟时间固定为Δ；而反向延迟线中基本延迟单元的控制输入端接误差放大器的输出端，该输出电压由校准后的差分时钟信号CKO+、CKO-的占空比决定，使得反向延迟线中基本延迟单元的延迟时间可调，为Δ+δ。当环路稳定后，实现时钟信号经过正反向延迟线传播后总共恰好经历1.5个时钟周期时间，从而与经过缓冲的原始时钟信号产生精确的半周期相位差。RS触发器使用经过缓冲的原始输入时钟信号和该半周期延迟时钟信号使用边沿触发交替进行置位和复位，合成具有50%占空比的校准输出时钟信号CKG。单端到双端转换电路、数模混合电荷泵和误差放大器检测校准输出时钟信号CKG的占空比信息并反馈至半周期延迟线，调整反向延迟线的延迟时间，使校准输出时钟信号CKG的占空比逐渐逼近于50%。完成占空比校准电路工作波形如图2所示。 In the utility model, the half-period delay line and the closed-loop circuit composed of it, a digital-analog hybrid charge pump, and an error amplifier are key modules for realizing duty cycle calibration. As shown in FIG. 4 , the buffered narrow pulse signal CKB input to the half-period delay line first propagates to the right in the forward delay line composed of basic delay units whose delay time Δ is not adjustable. When the next external clock signal arrives, the clock signal that has propagated in the forward delay line for one clock period passes through a series of decision and gating circuits and enters the reverse delay line to propagate leftward. When the circuit is designed, the clock signal passes through 2N+1 basic delay units in the sinusoidal delay line, and passes through N basic delay units in the reverse delay line. The control input terminal VC of the basic delay unit in the forward delay line is always grounded, and its delay time is fixed as Δ; while the control input terminal of the basic delay unit in the reverse delay line is connected to the output terminal of the error amplifier, and the output voltage is determined by the calibrated The duty cycle of the differential clock signals CKO+ and CKO- is determined so that the delay time of the basic delay unit in the reverse delay line is adjustable, which is Δ+δ. When the loop is stable, the clock signal will experience a total of 1.5 clock cycles after propagating through the forward and reverse delay lines, so that an accurate half-period phase difference will be generated with the buffered original clock signal. The RS flip-flop uses the buffered original input clock signal and the half-period delayed clock signal to alternately set and reset using edge triggers to synthesize a calibrated output clock signal CKG with a 50% duty cycle. Single-ended to double-ended conversion circuit, digital-analog hybrid charge pump and error amplifier detect the duty cycle information of the calibration output clock signal CKG and feed it back to the half-cycle delay line, adjust the delay time of the reverse delay line, so that the calibration output clock signal CKG The duty cycle gradually approaches 50%. Complete duty cycle calibration circuit working waveform shown in Figure 2.

1、脉冲发生器 1. Pulse generator

由于半周期延迟线的要求时钟信号具有较大的驱动能力，并且要求输入时钟脉冲不能太宽也不能太窄以保证测量准确可靠，本实用新型脉冲发生器电路产生相对于输入时钟上升沿有一固定延迟的正窄脉冲信号，如图3所示，本实例中所使用的输出反相器尺寸较大，具有较强的负载能力，同时使得窄脉冲的宽度满足上述要求，约为2.5Δ。 Because the half-period delay line requires that the clock signal has a relatively large drive capability, and the input clock pulse is required to be neither too wide nor too narrow to ensure accurate and reliable measurement, the pulse generator circuit of the utility model generates a fixed frequency relative to the rising edge of the input clock. Delayed positive narrow pulse signal, as shown in Figure 3, the output inverter used in this example is larger in size and has a stronger load capacity, and at the same time makes the width of the narrow pulse meet the above requirements, which is about 2.5Δ.

2、半周期延迟线 2. Half-period delay line

所述的半周期延迟线由一个基本延迟单元与若干级半周期延迟线单元依次串联而成，如图4所示。其中，每一级半周期延迟线单元，图5中的正向延迟线输入端FDI和正向延迟线输出端FDO以及它们之间的两个基本延迟单元，共同组成输入时钟信号的正向延迟线单元。输入时钟信号CKB的每一个上升沿都将在正向延迟线中激发一个向右传播的正窄脉冲。而每一级半周期延迟线单元，图5中的反向延迟线输入端BDI和反向延迟线输出端BDO以及它们之间的一个基本延迟单元，共同组成输入时钟信号的反向延迟线单元。任何一个反向延迟线基本单元的输入端IN2获得一个正脉冲时，都将在反向延迟线中激发一个向左传播的正窄脉冲。 The half-period delay line is composed of a basic delay unit and several stages of half-period delay line units in series, as shown in FIG. 4 . Among them, the half-period delay line units of each stage, the forward delay line input terminal FDI and the forward delay line output terminal FDO in Figure 5 and the two basic delay units between them together form the forward delay line of the input clock signal unit. Each rising edge of the input clock signal CKB will excite a rightward propagating narrow pulse in the forward delay line. And each half-period delay line unit, the reverse delay line input terminal BDI and the reverse delay line output terminal BDO in Figure 5 and a basic delay unit between them together form the reverse delay line unit of the input clock signal . When the input terminal IN2 of any reverse delay line basic unit gets a positive pulse, a positive narrow pulse propagating to the left will be excited in the reverse delay line.

当下一个输入时钟信号CKB的上升沿到来时，假设在正向延迟线中由上一个输入时钟信号CKB上升沿激发的正窄脉冲传播到第k个半周期延迟线单元，此时，在第k级之前的各级半周期延迟单元中节点A的电压均为低电平，使能输出端ENO电压始终为高电平；而第k级半周期延迟线单元中节点A有一正窄脉冲，使能输出端ENO有一负脉冲；在第k级之后的各级半周期延迟单元中节点A的电压均为低电平，使能输出端ENO电压始终为低电平，该使能端信号禁止信号在其后各级半周期延迟单元中传播，避免多余的正脉冲继续在正向或反向延迟线中继续传播。第k级半周期延迟线单元中节点A处的正窄脉冲传递至该级反向基本延迟单元的第二输入端IN2，并在该级半周期延迟单元的反向延迟线输出端BDO处得到相对于结点A的窄脉冲延迟Δ+δ的正窄脉冲，该窄脉冲传递至第k-1级半周期延迟线的反向延迟输入端BDI，再经Δ+δ的延迟由第k-1级半周期延迟线的反向延迟输出端BDO输出，以此类推，反向传递直至第一级半周期延迟线的反向延迟输出端BDO输出，从而得到半周期延迟线的输出信号CKD。 When the rising edge of the next input clock signal CKB arrives, it is assumed that the positive narrow pulse excited by the rising edge of the previous input clock signal CKB in the forward delay line propagates to the kth half-period delay line unit, at this time, the kth The voltage of node A in the half-period delay units before the stage is all low level, and the voltage of the enable output end ENO is always high level; while the node A in the kth half-period delay line unit has a positive narrow pulse, so that There is a negative pulse at the enable output terminal ENO; the voltage of node A in each half-cycle delay unit after the kth stage is low level, and the voltage at the enable output terminal ENO is always low level, and the signal at the enable terminal prohibits the signal Propagate in the subsequent stages of half-cycle delay units to prevent redundant positive pulses from continuing to propagate in the forward or reverse delay lines. The positive narrow pulse at node A in the half-period delay line unit of the kth stage is transmitted to the second input terminal IN2 of the reverse basic delay unit of this stage, and is obtained at the reverse delay line output terminal BDO of the half-period delay unit of this stage Relative to the narrow pulse delay of node A, the positive narrow pulse is delayed by Δ+δ, and the narrow pulse is transmitted to the reverse delay input terminal BDI of the k-1th stage half-cycle delay line, and then is delayed by Δ+δ from the k-th The reverse delay output terminal BDO of the first-stage half-period delay line outputs, and so on, reversely transfers until the reverse delay output terminal BDO of the first-stage half-period delay line outputs, thereby obtaining the output signal CKD of the half-period delay line.

上述信号传播过程中，信号正向传输经过了最初一个基本延迟单元和其后k个半周期延迟单元，每个半周期延迟单元在正向传输路径上包含两个基本延迟单元，因而正向传播总延迟时间为（2k+1）Δ，约为1个时钟周期T。信号反向传输经过了k个半周期延迟单元，每个半周期延迟单元在反向传输路径上包含一个基本延迟单元，且反向延迟路径上的基本延迟单元延迟时间可调，因而反向传播总延迟时间为k（Δ+δ），其中δ的值由闭环回路控制，当占空比校准电路建立完成后，满足2k（Δ+δ）=T，此时占空比校准电路的输出信号为占空比为50%的时钟信号。 During the above signal propagation process, the forward transmission of the signal passes through the initial basic delay unit and the following k half-cycle delay units, and each half-cycle delay unit contains two basic delay units on the forward transmission path, so the forward propagation The total delay time is (2k+1)Δ, which is about 1 clock cycle T. The reverse transmission of the signal passes through k half-cycle delay units, and each half-cycle delay unit contains a basic delay unit on the reverse transmission path, and the delay time of the basic delay unit on the reverse delay path is adjustable, so the reverse propagation The total delay time is k(Δ+δ), where the value of δ is controlled by the closed-loop loop. When the duty cycle calibration circuit is established, 2k(Δ+δ)=T is satisfied. At this time, the output signal of the duty cycle calibration circuit A clock signal with a duty cycle of 50%.

基本延迟单元是半周期延迟线的关键单元。传统的基本延迟单元由与非门和非门串联而成。由于CMOS工艺中P管与N管性能失配的客观存在，时钟信号在这种基本延迟单元中传播时，其前后沿的传播速度并不相等。这种速度差异经过逐级积累轻则导致电路校准误差增大，性能劣化；重则导致在延迟线中传播的正窄脉冲或负窄脉冲消失，使电路无法工作。另外该传统的基本延迟单元其延迟时间不可控，不能满足要求。 The basic delay unit is the key unit of the half-period delay line. The traditional basic delay unit consists of NAND gates and NOT gates connected in series. Due to the objective existence of the performance mismatch between the P tube and the N tube in the CMOS process, when the clock signal propagates in this basic delay unit, the propagation speeds of the front and rear edges are not equal. The accumulation of this speed difference will lead to the increase of circuit calibration error and performance degradation; if it is serious, the positive narrow pulse or negative narrow pulse propagating in the delay line will disappear, making the circuit unable to work. In addition, the delay time of the traditional basic delay unit is uncontrollable and cannot meet the requirements.

本实用新型的基本延迟单元如图6所示, 初始时，基本延迟单元使能信号EN为无效电平（低电平），控制信号输入端VC为低电平，则PM1导通，NM1、PM2截止，PM4和NM6栅极为高电平。当第一延迟信号输入端IN1节点为低时，NM2的栅极被预充电到高。当第一延迟信号输入端IN1节点产生一个上升沿的瞬间，NM4的栅极被充电到高，此时NM2的栅极的预充电荷尚未被充分泄放，从而NM2和NM4同时导通。若此时基本延迟单元使能信号EN为有效电平（高电平），则NM1也导通，同时PM1截止，PM4和NM6栅极被放电至低电平。而在第一延迟信号输入端IN1信号的持续低电平或高电平阶段、第一延迟信号输入端IN1信号的下降沿时刻，或基本延迟单元使能信号EN的低电平阶段，均无法满足NM1、NM2、NM4同时导通的条件，此时PM4和NM6的栅极将由PM1或PM2逐渐充电至高电平。总体而言，当基本延迟单元使能信号EN为高电平，且控制信号输入端VC的电压足以使PM3导通时，第一延迟信号输入端IN1信号的一个上升沿将会在P4和N8栅极产生一个负脉冲。该负脉冲经过PM3、PM4和NM6组成的延迟时间可控反相器生成一个边沿较为理想的正脉冲作为此基本延迟单元的延迟输出信号。第二延迟信号输入端IN2与第一延迟信号输入端IN1相同，逻辑上与IN1相或。改进的基本延迟单元其优点在于，对于在由此构成的延迟线中传播的正脉冲，其脉宽可以稳定的维持在一个适当值，并且脉宽的具体宽度并不影响电路的性能。同时，在正反向延迟线中，均由脉冲的上升沿的传播延时作为整个延迟线的传播延迟，使正反向延迟线具有较好的一致性。此外，该基本单元使用一个电压控制的压控电流不饱和型反相器来实现基本延迟单元的延迟时间连续可调，控制电压的电压值越大，基本延迟单元延迟时间就越大，使得基本延迟单元的延迟时间为Δ+δ（δ可变），半周期延迟线的延迟时间精确为半个周期，消除了数字占空比校准电路所存在的离散型误差，使得校准精度更为精确。 The basic delay unit of the present utility model is shown in Figure 6. Initially, the enabling signal EN of the basic delay unit is at an inactive level (low level), and the control signal input terminal VC is at a low level, then PM1 is turned on, and NM1, PM2 cuts off, PM4 and NM6 gates are high level. When the first delayed signal input IN1 node is low, the gate of NM2 is precharged high. When the first delay signal input terminal IN1 node generates a rising edge, the gate of NM4 is charged to high, and the precharged charge of the gate of NM2 has not been fully discharged at this time, so NM2 and NM4 are turned on at the same time. If the enable signal EN of the basic delay unit is at an active level (high level) at this time, NM1 is also turned on, and at the same time PM1 is turned off, and the gates of PM4 and NM6 are discharged to low level. However, in the continuous low-level or high-level phase of the first delay signal input terminal IN1 signal, the falling edge moment of the first delay signal input terminal IN1 signal, or the low-level phase of the basic delay unit enable signal EN, all cannot Satisfying the condition that NM1, NM2, and NM4 are turned on at the same time, at this time, the gates of PM4 and NM6 will be gradually charged to a high level by PM1 or PM2. In general, when the enabling signal EN of the basic delay unit is at a high level, and the voltage of the control signal input terminal VC is sufficient to turn on PM3, a rising edge of the signal at the first delay signal input terminal IN1 will be at the P4 and N8 The gate generates a negative pulse. The negative pulse passes through the delay time controllable inverter composed of PM3, PM4 and NM6 to generate a positive pulse with a relatively ideal edge as the delayed output signal of the basic delay unit. The second delayed signal input terminal IN2 is the same as the first delayed signal input terminal IN1, and logically ORed with IN1. The advantage of the improved basic delay unit is that the pulse width of the positive pulse propagating in the resulting delay line can be stably maintained at an appropriate value, and the specific width of the pulse width does not affect the performance of the circuit. At the same time, in the forward and reverse delay lines, the propagation delay of the rising edge of the pulse is used as the propagation delay of the entire delay line, so that the forward and reverse delay lines have better consistency. In addition, the basic unit uses a voltage-controlled voltage-controlled current unsaturated inverter to realize the continuous adjustment of the delay time of the basic delay unit. The greater the value of the control voltage, the greater the delay time of the basic delay unit, so that the basic The delay time of the delay unit is Δ+δ (variable δ), and the delay time of the half-cycle delay line is accurate to half a cycle, which eliminates the discrete error existing in the digital duty cycle calibration circuit and makes the calibration accuracy more accurate.

3、RS触发器 3. RS trigger

合成具有50%占空比的校准时钟信号CKG的RS触发器的设计关键在于使从置位端S到输出端Q、以及从复位端R到输出端Q的路径延迟更精确地匹配。本实用新型使用如图7所示的结构来实现所需功能。本实用新型所采用由输入输出反相器和两个与非门组成，如图结构完全对称，保证置位输入端S和复位输入端R到RS触发器的输出端Q具有相同的延迟。另外，在该发明中，由于占空比失调可通过环路自动调节，降低了对RS触发器的要求，即使置位输入端S和复位输入端R到RS触发器的输出端Q具有延迟时间略有不同，环路也能将占空比校正为50%，也就提高了电路抗PVT变化的强度。 The key to the design of the RS flip-flop that synthesizes the calibration clock signal CKG with a duty cycle of 50% is to match the path delays from the set terminal S to the output terminal Q, and from the reset terminal R to the output terminal Q more precisely. The utility model uses the structure shown in Figure 7 to realize the required functions. The utility model adopts an input-output inverter and two NAND gates, as shown in the figure, the structure is completely symmetrical to ensure that the set input terminal S and the reset input terminal R have the same delay to the output terminal Q of the RS flip-flop. In addition, in this invention, since the duty cycle offset can be automatically adjusted through the loop, the requirements for the RS flip-flop are reduced, even if there is a delay time from the set input terminal S and the reset input terminal R to the output terminal Q of the RS flip-flop Slightly different, the loop can also correct the duty cycle to 50%, which increases the circuit's resistance to PVT changes.

4、单端到差分转换电路 4. Single-ended to differential conversion circuit

单端到差分转换电路STD将由RS触发器合成的输出时钟信号CKG转化为差分输出时钟CKO+和CKO-。本实用新型中所采用的STD电路结构完全对称，如图8所示，该电路可以减小差分时钟的扭斜以及由PVT变化所引起的输出时钟占空比失调，提高了电路的性能。 The single-ended to differential conversion circuit STD converts the output clock signal CKG synthesized by the RS flip-flop into differential output clocks CKO+ and CKO-. The structure of the STD circuit used in the utility model is completely symmetrical, as shown in Fig. 8, the circuit can reduce the skew of the differential clock and the duty cycle imbalance of the output clock caused by PVT changes, and improve the performance of the circuit.

5、模拟闭环微调电路 5. Analog closed-loop fine-tuning circuit

传统的纯数字方式的占空比校准电路的调整存在离散性，调整精度由基本延迟单元的延迟时间决定，因此在功耗/面积以及调整精度/相位分辨率方面难以兼顾。本实用新型所提出由占空比微调检测与控制和传统半周期延迟线所构成的闭环微调电路克服了上述缺点。本实用新型所提出的混合模式占空比校准电路通过在传统的纯数字方式的占空比校准电路基础上引入模拟的闭环微调电路来克服上述缺点。该闭环微调电路由数模混合电荷泵CCP 5（图10）和误差放大器OTA 6（图11）构成，完成占空比失调检测并产生占空比微调控制信号，调整半周期延迟线的延迟时间，实现占空比微调。 The adjustment of the traditional purely digital duty cycle calibration circuit is discrete, and the adjustment accuracy is determined by the delay time of the basic delay unit, so it is difficult to balance power consumption/area and adjustment accuracy/phase resolution. The utility model proposes a closed-loop fine-tuning circuit composed of a duty cycle fine-tuning detection and control and a traditional half-period delay line to overcome the above-mentioned shortcomings. The mixed-mode duty ratio calibration circuit proposed by the utility model overcomes the above-mentioned shortcomings by introducing an analog closed-loop fine-tuning circuit on the basis of a traditional purely digital duty ratio calibration circuit. The closed-loop fine-tuning circuit is composed of a digital-analog hybrid charge pump CCP 5 (Figure 10) and an error amplifier OTA 6 (Figure 11), which completes duty cycle offset detection and generates a duty cycle fine-tuning control signal to adjust the delay time of the half-cycle delay line , to achieve fine-tuning of the duty cycle.

差分输出时钟信号的占空比偏差由数模混合电荷泵（图10）检测并转化为电荷泵差分输出端FP和FN之间的电压差，本实用新型所提出数模混合电荷泵可以减小输出电压纹波，产生精确反映占空比信息的输出电压。在工作频率范围内，该占空比校准电路的调整精度基本上由模拟反馈环路的闭环增益决定，为了得到足够的校准精度，需要在电荷泵之后增加一误差放大器，即电荷泵差分输出端FP和FN之间的电压差经误差放大器放大得到占空比微调控制电压信号Vout。考虑到模拟闭环微调电路的稳定性与锁定时间正比于误差放大器带宽，反比于其增益，这就要求误差放大器在增益和带宽间折衷。本实用新型采用如图11所示的误差放大器，该误差放大器是由一个NMOS输入单级跨导放大器和一个PMOS输入单级跨导放大器并联而成互补放大器，具有更宽的带宽和轨到轨输入输出摆幅。上述数模混合电荷泵CCP 5和误差放大器OTA 6均省去了恒流源，节省了偏置电路，降低了功耗，便于全数字集成。 The duty cycle deviation of the differential output clock signal is detected by the digital-analog hybrid charge pump (Figure 10) and converted into the voltage difference between the differential output terminals FP and FN of the charge pump. The digital-analog hybrid charge pump proposed by the utility model can reduce output voltage ripple, resulting in an output voltage that accurately reflects duty cycle information. In the operating frequency range, the adjustment accuracy of the duty cycle calibration circuit is basically determined by the closed-loop gain of the analog feedback loop. In order to obtain sufficient calibration accuracy, it is necessary to add an error amplifier after the charge pump, that is, the differential output of the charge pump The voltage difference between FP and FN is amplified by the error amplifier to obtain the duty ratio fine-tuning control voltage signal Vout. Considering that the stability and locking time of the analog closed-loop fine-tuning circuit are proportional to the bandwidth of the error amplifier and inversely proportional to its gain, this requires the error amplifier to compromise between gain and bandwidth. The utility model adopts the error amplifier shown in Figure 11, the error amplifier is a complementary amplifier formed by parallel connection of an NMOS input single-stage transconductance amplifier and a PMOS input single-stage transconductance amplifier, and has wider bandwidth and rail-to-rail Input to output swing. The above-mentioned digital-analog hybrid charge pump CCP 5 and error amplifier OTA 6 both eliminate the constant current source, save the bias circuit, reduce power consumption, and facilitate full digital integration.

以上所述仅为本实用新型的较佳实施方式，本实用新型的保护范围并不以上述实施方式为限，但凡本领域普通技术人员根据本实用新型所揭示内容所作的等效修饰或变化，皆应纳入权利要求书中记载的保护范围内。 The above are only preferred embodiments of the present utility model, and the protection scope of the present utility model is not limited to the above-mentioned embodiments, but any equivalent modification or change made by those of ordinary skill in the art according to the content disclosed in the present utility model, All should be included in the scope of protection described in the claims.