CN202110462U - A LDO Based on Dynamic Zero-Pole Tracking Technology - Google Patents

The utility model belongs to the field of power source management and discloses an LDO (Low Dropout Regulator) based on dynamic zero-pole tracking techniques, aiming to solve the problem that the conventional LDO has poor loop stability. The LDO comprises an error amplifier, a buffer, and a slew rate intensifier circuit, and is characterized by further comprising a first capacitor, a second capacitor, and a variable resistor, wherein one end of the first capacitor is connected with the output end of the error amplifier, and the other end of the first capacitor is connected with one end of the variable resistor; and one end of the second capacitor is connected with the error amplifier, and the other end of the second capacitor is connected with the other end of the variable resistor, and serves as the output end of the LDO. In the LDO provided by the utility model, the first capacitor and the variable resistor form a compensating network to serve as the dynamic zero-pole of the system; and through adopting the second capacitor in current multiplication mode to compensate the phase margin of the LDO loop, the stability of the LDO loop is improved further.

一种基于动态零极点跟踪技术的LDOA LDO Based on Dynamic Zero-Pole Tracking Technology

技术领域 technical field

本实用新型属于电源管理领域，具体涉及一种低压差线性稳压器(LDO，Low DropoutRegulator)的设计。The utility model belongs to the field of power supply management, in particular to the design of a low dropout linear regulator (LDO, Low Dropout Regulator).

背景技术 Background technique

电源管理模块是芯片的基本单元电路，其设计在手持和便携设备领域尤为重要。无片外电容的低压差线性稳压器，是现在流行的典型线性稳压器结构。随着当前便携式设备的广泛使用，对LDO的性能也提出了新要求：更低的功耗，即更小的压差和更低的静态电流；更好的瞬态响应，即更优的补偿方式和拓扑结构。The power management module is the basic unit circuit of the chip, and its design is particularly important in the field of hand-held and portable devices. The low-dropout linear regulator without off-chip capacitors is a typical linear regulator structure that is popular now. With the widespread use of current portable devices, new requirements are put forward for the performance of LDO: lower power consumption, that is, smaller voltage drop and lower quiescent current; better transient response, that is, better compensation mode and topology.

环路稳定性是LDO的关键指标，传统的LDO采用输出电容上的ESR(Equivalent SeriesResistance)偿的方式。由于ESR容易受环境，如温度，工艺等的影响，变化较大，稳定提供的输出电流被限制在很小的范围内而显得不够优化。此外ESR的存在会在瞬时负载变化的时候恶化负载瞬时调整率(load transient regulation)。Loop stability is a key indicator of LDO. Traditional LDO uses ESR (Equivalent Series Resistance) compensation on the output capacitor. Because the ESR is easily affected by the environment, such as temperature, process, etc., and changes greatly, the output current provided stably is limited to a small range, which is not optimized enough. In addition, the existence of ESR will deteriorate the load transient regulation when the instantaneous load changes.

现在出现了多种新的拓扑和补偿方式：K.N.Leung提出的极点分裂技术和零极点抵消技术；Man提出的基于FVF的STC技术；Rincon-Mora提出的基于密勒倍增的零极点抵消技术以及K.N.Leung的阻尼因子校正技术(DFC)。但是它们都有一定的局限性：Leung提出的零极点抵消技术由工作在线性区的采样管跟踪工作在饱和区的功率管获取负载信息，跟踪负载不够精确；STC技术由于拓扑结构限制环路增益不可能很高，输出电压静态精度受限；Rincon-Mora提出的密勒倍增技术的电路实现由于其特殊工艺要求限制了在标准CMOS工艺中的应用；基于DFC技术的LDO补偿架构存在环路复杂性和较大静态电流的缺点。Now there are a variety of new topologies and compensation methods: K.N.Leung's pole splitting technology and zero-pole cancellation technology; Man's FVF-based STC technology; Rincon-Mora's Miller multiplication-based zero-pole cancellation technology and K.N. Leung's damping factor correction technique (DFC). But they all have certain limitations: the pole-zero cancellation technology proposed by Leung uses the sampling tube working in the linear region to track the power tube working in the saturation region to obtain load information, and the tracking load is not accurate enough; the STC technology limits the loop gain due to the topology It cannot be very high, and the static accuracy of the output voltage is limited; the circuit implementation of the Miller multiplication technology proposed by Rincon-Mora limits its application in the standard CMOS process due to its special process requirements; the LDO compensation architecture based on DFC technology has a complex loop Disadvantages of sex and large quiescent current.

实用新型内容 Utility model content

本实用新型的目的是为了解决现有的LDO环路稳定性的问题，提出了一种基于动态零极点跟踪技术的LDO。The purpose of the utility model is to solve the problem of loop stability of the existing LDO, and propose an LDO based on dynamic zero-pole tracking technology.

本实用新型的技术方案是：一种基于动态零极点跟踪技术的LDO，包括误差放大器，缓冲器，摆率增强电路，第一电容、第二电容和可变电阻，所述误差放大器的输出端与缓冲器的输入端相连接，缓冲器的输出端与摆率增强电路的输出端相连接，所述第一电容的一端接误差放大器输出端，另一端与可变电阻的一端相连接，所述第二电容的一端与误差放大器相连接，另一端与可变电阻的另一端相连接，并作为LDO的输出端。The technical scheme of the utility model is: a kind of LDO based on dynamic zero-pole tracking technology, including error amplifier, buffer, slew rate enhancement circuit, first capacitor, second capacitor and variable resistor, the output terminal of the error amplifier connected to the input end of the buffer, the output end of the buffer is connected to the output end of the slew rate enhancement circuit, one end of the first capacitor is connected to the output end of the error amplifier, and the other end is connected to one end of the variable resistor, so One end of the second capacitor is connected to the error amplifier, and the other end is connected to the other end of the variable resistor, which is used as the output end of the LDO.

所述误差放大器包括PMOS管M1、M2、Mb1、M7，M8，NMOS管M3，M4，M5，M6管，其中Mb1作为尾电流源；M1，M2作为输入对管；M7二极管连接；M8镜像M7的电流并作为负载P管；M3，M4二极管连接作为第一级负载；M5镜像M3的电流，M6镜像M4的电流，且M6管作为负载N管；M5与M7漏极相连；M6与M8漏极相连作为误差放大器输出端。The error amplifier includes PMOS tubes M1, M2, Mb1, M7, M8, NMOS tubes M3, M4, M5, and M6 tubes, wherein Mb1 is used as a tail current source; M1, M2 are used as input pair tubes; M7 diodes are connected; M8 mirrors M7 M3 and M4 diodes are connected as the first stage load; M5 mirrors the current of M3, M6 mirrors the current of M4, and the M6 tube is used as the load N tube; M5 is connected to the drain of M7; M6 is connected to the drain of M8 The pole is connected as the output terminal of the error amplifier.

所述缓冲器包括PMOS管Mb2、M9，其中，Mb2作为偏置电流管，M9作为源随器，Mb2的漏极与M9的源极相连接，并作为缓冲器的输出端；M9的栅极为缓冲器的输入端，漏极接地。The buffer includes PMOS transistors Mb2 and M9, wherein Mb2 is used as a bias current transistor, M9 is used as a source follower, the drain of Mb2 is connected to the source of M9, and is used as the output end of the buffer; the gate of M9 is Buffer input, drain grounded.

所述摆率增强电路包括PMOS管Ms、M16、M15，NMOS管M13、M14，其中，M16漏极和Ms的栅极接缓冲器的输出端，源极接LDO的输入电压，漏极接M14的漏极；M14二极管连接；M13镜像M14的电流，漏极接M15的漏极。The slew rate enhancement circuit includes PMOS transistors Ms, M16, M15, NMOS transistors M13, M14, wherein the drain of M16 and the gate of Ms are connected to the output end of the buffer, the source is connected to the input voltage of the LDO, and the drain is connected to M14 The drain of M14; M14 diode connection; M13 mirrors the current of M14, and the drain is connected to the drain of M15.

所述可变电阻由NMOS管M12、PMOS管M11、M10组成，其中，M12镜像所述摆率增强电路中NMOS管M14的电流；PMOS管M10栅极接NMOS管M12的漏极；PMOS管M11二极管连接，漏极接NMOS管M12的漏极，PMOS管M11源极和M10的源极相连接，并作为LDO的输出端。The variable resistor is composed of NMOS transistors M12, PMOS transistors M11 and M10, wherein M12 mirrors the current of the NMOS transistor M14 in the slew rate enhancement circuit; the gate of the PMOS transistor M10 is connected to the drain of the NMOS transistor M12; the PMOS transistor M11 The diode is connected, the drain is connected to the drain of the NMOS transistor M12, the source of the PMOS transistor M11 is connected to the source of the M10, and is used as the output terminal of the LDO.

本实用新型的有益效果：本实用新型的基于动态零极点跟踪技术的LDO，通过第一电容和可变电阻组成补偿网络，作为系统的动态零点；通过采用电流倍增模式的第二电容补偿LDO电路环路的相位裕度，从而提高了LDO环路稳定性。Beneficial effects of the utility model: The LDO based on the dynamic zero-pole tracking technology of the utility model forms a compensation network through the first capacitor and the variable resistor as the dynamic zero point of the system; the LDO circuit is compensated by the second capacitor in the current multiplication mode The phase margin of the loop improves the LDO loop stability.

附图说明 Description of drawings

图1为本实用新型的基于动态零极点跟踪技术的LDO系统框图。Fig. 1 is a block diagram of the LDO system based on the dynamic zero-pole tracking technology of the present invention.

图2为本实用新型的基于动态零极点跟踪技术的LDO的具体电路示意图。FIG. 2 is a specific circuit schematic diagram of the LDO based on the dynamic zero-pole tracking technology of the present invention.

图3为本实用新型电流模式电容倍增示意图，其中，图(a)为电路结构图，(b)为等效示意图。Fig. 3 is a schematic diagram of current mode capacitance multiplication according to the present invention, wherein (a) is a circuit structure diagram, and (b) is an equivalent schematic diagram.

图4为本实用新型实施例中相位超前补偿网络等效架构图。Fig. 4 is an equivalent structure diagram of the phase lead compensation network in the embodiment of the present invention.

具体实施方式 Detailed ways

下面结合附图和具体的实施例对本实用新型作进一步的阐述。Below in conjunction with accompanying drawing and specific embodiment, the utility model is further elaborated.

本实用新型LDO补偿结构思想如下：误差放大器采用单极对称结构的OTA，缓冲器用PMOS源极跟随器实现，增加对PMOS调整管的驱动能力，频率补偿采用miller电容和动态零点(可变MOS电阻+固定电容)相结合的方法。为提高LDO在负载突变时的瞬态响应，增加了摆率增强电路。The idea of the compensation structure of the utility model LDO is as follows: the error amplifier adopts the OTA of the unipolar symmetrical structure, the buffer is realized by the PMOS source follower, the driving ability to the PMOS adjustment tube is increased, and the frequency compensation adopts the miller capacitance and the dynamic zero point (variable MOS resistance + fixed capacitance) combined method. In order to improve the transient response of LDO when the load changes suddenly, a slew rate enhancement circuit is added.

图1是基于动态零极点跟踪技术的LDO的系统方框图，包括误差放大器Gain Stage，缓冲器Buffer，摆率增强电路SRE，第一电容C_c、第二电容C_m和可变电阻R_c，所述误差放大器Gain Stage的输出端与缓冲器Buffer的输入端相连接，缓冲器Buffer的输出端与摆率增强电路SRE的输出端相连接，所述第一电容C_c的一端接误差放大器Gain Stage输出端，另一端与可变电阻R_c的一端相连接，所述第二电容C_m的一端与误差放大器Gain Stage相连接，另一端与可变电阻R_c的另一端相连接，并作为LDO的输出端。Figure 1 is a system block diagram of an LDO based on dynamic pole-zero tracking technology, including an error amplifier Gain Stage, a buffer Buffer, a slew rate enhancement circuit SRE, a first capacitor C _c , a second capacitor C _m and a variable resistor R _c . The output end of the error amplifier Gain Stage is connected to the input end of the buffer Buffer, the output end of the buffer Buffer is connected to the output end of the slew rate enhancement circuit SRE, and one end of the first capacitor C _c is connected to the error amplifier Gain Stage The output terminal, the other end is connected to one end of the variable resistor _Rc , one end of the second capacitor _Cm is connected to the error amplifier Gain Stage, and the other end is connected to the other end of the variable resistor _Rc , and used as an LDO output terminal.

图2为所述的LDO的具体电路示意图。误差放大器Gain Stage包括PMOS管M1、M2、Mb1、M7，M8，NMOS管M3，M4，M5，M6，其中Mb1作为尾电流源；M1，M2作为输入对管；M7二极管连接；M8镜像M7的电流并作为负载P管；M3，M4均二极管连接作为第一级负载；M5镜像M3的电流，M6镜像M4的电流，且M6管作为负载N管；M5与M7漏极相连；M6与M8漏极相连作为误差放大器的输出端。FIG. 2 is a specific schematic circuit diagram of the LDO. The error amplifier Gain Stage includes PMOS tubes M1, M2, Mb1, M7, M8, NMOS tubes M3, M4, M5, M6, where Mb1 is used as a tail current source; M1, M2 are used as input pair tubes; M7 diode connection; M8 mirror M7 The current is used as the load P tube; M3 and M4 are diode-connected as the first stage load; M5 mirrors the current of M3, M6 mirrors the current of M4, and M6 tube is used as the load N tube; M5 is connected to the drain of M7; M6 and M8 drain The pole is connected as the output terminal of the error amplifier.

缓冲器Buffer包括PMOS管Mb2、M9，其中，Mb2作为偏置电流管，M9作为源随器，Mb2的漏极与M9的源极相连接，并作为缓冲器Buffer的输出端；M9的栅极为缓冲器Buffer的输入端，漏极接地。The buffer Buffer includes PMOS transistors Mb2 and M9, wherein Mb2 is used as a bias current transistor, M9 is used as a source follower, the drain of Mb2 is connected to the source of M9, and is used as the output end of the buffer Buffer; the gate of M9 is The input terminal of the buffer Buffer, the drain is grounded.

摆率增强电路SRE包括PMOS管Ms、M16、M15，NMOS管M13、M14，其中，M16漏极和Ms的栅极一起接Buffer的输出端，源极接LDO的输入电压，漏极接M14的漏极；M14二级管连接；M13镜像M14的电流，漏极接二极管连接的M15的漏极。M16管镜像M15的电流。The slew rate enhancement circuit SRE includes PMOS transistors Ms, M16, M15, NMOS transistors M13, M14, wherein, the drain of M16 and the gate of Ms are connected to the output end of Buffer together, the source is connected to the input voltage of LDO, and the drain is connected to M14 Drain; M14 diode connection; M13 mirrors the current of M14, and the drain is connected to the drain of M15 connected to the diode. The M16 tube mirrors the current of the M15.

可变电阻Rc由NMOS管M12、PMOS管M11、M10组成，其中，M12镜像所述摆率增强电路中NMOS管M14的电流；PMOS管M11二极管连接，漏极接NMOS管M12的漏极，PMOS管M11源极和M10的源极相连接，并作为LDO的输出端；PMOS管M10栅极接NMOS管M12的漏极。The variable resistor Rc is composed of NMOS transistors M12, PMOS transistors M11, and M10, wherein M12 mirrors the current of the NMOS transistor M14 in the slew rate enhancement circuit; the PMOS transistor M11 is diode-connected, and its drain is connected to the drain of the NMOS transistor M12. The source of the transistor M11 is connected to the source of the M10, and serves as the output end of the LDO; the gate of the PMOS transistor M10 is connected to the drain of the NMOS transistor M12.

这里，二极管连接指的是MOS管的栅极与漏极直接连接在一起。Here, the diode connection means that the gate and the drain of the MOS transistor are directly connected together.

本实用新型利用的电流模式电容倍增示意图如图3所示。图(a)为电路结构图，V_n端的小信号电压变化在第一电容C_c上的电流为V_nC_cS，通过电流镜的低阻抗点(1/gm)收集流经电容的小信号电流并比例镜像放大，返回输入端V_n。图(b)为等效示意图，等效电容C_eq＝(1+K_x)C_c，进而实现了电容的密勒倍增。The schematic diagram of current mode capacitance multiplication utilized in the present invention is shown in FIG. 3 . Figure (a) is a circuit structure diagram. The small signal voltage change at the V _n terminal causes the current on the first capacitor C _c to be V _n C _c S, and the small signal flowing through the capacitor is collected by the low impedance point (1/gm) of the current mirror. The signal current is proportionally mirrored and amplified, and returned to the input terminal V _n . Figure (b) is an equivalent schematic diagram, and the equivalent capacitance C _eq =(1+K _x )C _c , thereby realizing the Miller multiplication of the capacitance.

图1中，第二电容C_m作为电流模式的密勒倍增电容，R_c是工作在线性区、包含负载信息的MOS电阻。第一电容C_c与可变电阻R_c跨接在EA增益级的输出与功率管输出，产生动态零点跟踪补偿输出极点。Buffer隔离大电容和大电阻，并起摆率增强作用。C_f与反馈电阻R_f1，R_f2组成高通滤波器，产生一对零极对，实现相位超前补偿从而改善环路稳定性。摆率增强电路SRE可以根据负载电流情况，改变对功率管栅电容Cp的瞬时充电电流。In FIG. 1 , the second capacitor C _m is used as a Miller multiplier capacitor in current mode, and R _c is a MOS resistor working in a linear region and containing load information. The first capacitor C _c and the variable resistor R _c are connected across the output of the EA gain stage and the output of the power tube to generate a dynamic zero tracking compensation output pole. Buffer isolates large capacitors and large resistors, and acts as a slew rate enhancer. C _f and feedback resistors R _f1 and R _f2 form a high-pass filter to generate a pair of zero poles to realize phase lead compensation and improve loop stability. The slew rate enhancement circuit SRE can change the instantaneous charging current to the power transistor gate capacitance Cp according to the load current condition.

由图1可知，LDO的稳态输出电压：It can be seen from Figure 1 that the steady-state output voltage of the LDO is:

V out = R f 1 + R f 2 R f 1 V ref 公式(1) V out = R f 1 + R f 2 R f 1 V ref Formula 1)

系统环路传输函数：System loop transfer function:

H 1 ( s ) = H 1 ( 0 ) ( 1 + s / Z 1 ) ( 1 + s / Z 2 ) ( 1 + s / P 1 ) ( 1 + s / P 2 ) ( 1 + s / P 3 ) 公式(2) h 1 ( the s ) = h 1 ( 0 ) ( 1 + the s / Z 1 ) ( 1 + the s / Z 2 ) ( 1 + the s / P 1 ) ( 1 + the s / P 2 ) ( 1 + the s / P 3 ) Formula (2)

公式(2)中，低频环路增益：In formula (2), the low frequency loop gain is:

H 1 ( 0 ) = A v g mp [ r op / / ( R f 1 + R f 2 ) / / R L ] R f 1 R f 1 + R f 2 公式(3) h 1 ( 0 ) = A v g mp [ r op / / ( R f 1 + R f 2 ) / / R L ] R f 1 R f 1 + R f 2 Formula (3)

零极点分别为：The poles and zeros are:

PP 11 == 11 (( KK xx CC mm ++ CC cc )) gg mpmp rr opop RR oeqoeq ;;

P 2 = g mb C p ; P 3 = g mp C L 公式(4) P 2 = g mb C p ; P 3 = g mp C L Formula (4)

Z 1 ≈ 1 R ds _ mos C c = u p C ox ( W / L ) 1 ( V gs - V tp ) C c = u p C ox ( W / L ) 1 C c 2 I 0 K 1 K 2 u p C ox ( W / L ) 2 公式(5) Z 1 ≈ 1 R ds _ mos C c = u p C ox ( W / L ) 1 ( V gs - V tp ) C c = u p C ox ( W / L ) 1 C c 2 I 0 K 1 K 2 u p C ox ( W / L ) 2 Formula (5)

Z 2 = Z f = 1 R f 1 C f 公式(6) Z 2 = Z f = 1 R f 1 C f Formula (6)

其中，A_v为误差放大器的直流增益，g_mp为调整管Mp的跨导，r_op为调整管Mp的导通电阻，K_x为M3与M5的镜像比例，g_mb为Mb2的跨导，R_oeq为误差放大器的等效输出电阻，μ_p为空穴的迁移率，C_ox为单位面积的栅氧化层电容，W为栅的宽度，L为栅的长度，V_gs为栅源两极之间的电压，V_tp为PMOS管的阈值电压。Among them, A _v is the DC gain of the error amplifier, g _mp is the transconductance of the pass tube Mp, r _op is the on-resistance of the pass tube Mp, K _x is the mirror image ratio between M3 and M5, g _mb is the transconductance of Mb2, R _oeq is the equivalent output resistance of the error amplifier, μ _p is the mobility of holes, C _ox is the capacitance of the gate oxide layer per unit area, W is the width of the gate, L is the length of the gate, V _gs is the distance between the two poles of the gate and source The voltage between, V _tp is the threshold voltage of the PMOS tube.

公式(5)中Z₁为动态零点，用来跟踪补偿输出动态极点P₃，其中K₁，K₂为负载电流采样网络的采样比例；Z_f为相位超前补偿网络产生的增益带宽乘积(GBW，Gain-Bandwidthproduct)之内的零点，用来改善环路相位裕度。对应的P_f在GBW之外，上面未予给出，具体分析将在下面给出。由此可知该LDO为单极点系统，具有很好的稳定性。In formula (5), Z ₁ is the dynamic zero point, which is used to track and compensate the output dynamic pole P ₃ , where K ₁ and K ₂ are the sampling ratios of the load current sampling network; Z _f is the gain-bandwidth product (GBW , Gain-Bandwidthproduct) within the zero point, used to improve the loop phase margin. The corresponding P _f is outside the GBW, which is not given above, and the specific analysis will be given below. It can be seen that the LDO is a single-pole system with good stability.

图4相位超前补偿网络等效架构图，电容C_f与反馈网络电阻R_f1，R_f2组成高通滤波网络，从而改善系统稳定性，并能提高瞬态响应和PSRR，减小输出噪声。其传输函数表达式如下：Figure 4 is the equivalent architecture diagram of the phase lead compensation network. The capacitor C _f and the feedback network resistors R _f1 and R _f2 form a high-pass filter network, thereby improving system stability, improving transient response and PSRR, and reducing output noise. Its transfer function expression is as follows:

H 2 ( s ) = V fb V out = ( R f 1 R f 1 + R f 2 ) [ 1 + s C f R f 2 1 + s C f ( R f 1 / / R f 2 ) ] 公式(7) h 2 ( the s ) = V fb V out = ( R f 1 R f 1 + R f 2 ) [ 1 + the s C f R f 2 1 + the s C f ( R f 1 / / R f 2 ) ] Formula (7)

P f = 1 ( R f 1 / / R f 2 ) C f = 1 + R f 2 R f 1 R f 2 C f ; Z f = 1 R f 2 C f 公式(8) P f = 1 ( R f 1 / / R f 2 ) C f = 1 + R f 2 R f 1 R f 2 C f ; Z f = 1 R f 2 C f Formula (8)

从公式(8)可以得出：

即Z_f相对Pf处在更低频率，将Z_f放在略低于GBW附近，P_f在GBW之外，可以补偿环路频率特性。但是零极点的分隔间距越大，需要

越大，一方面存在电阻的layout的失配，更为重要的是，误差放大器输入端的噪声和失配会以更大的倍数放大到输出端，所以

的设计存在折衷，在这里取

From formula (8), it can be concluded that:

That is, Z _f is at a lower frequency than Pf, Z _f is placed slightly lower than GBW, and P _f is outside GBW, which can compensate the loop frequency characteristics. However, the larger the separation distance between zero and pole points, the more

The larger it is, on the one hand there is a mismatch in the layout of the resistors, and more importantly, the noise and mismatch at the input of the error amplifier will be amplified to the output at a greater multiple, so

There are trade-offs in the design of

在图2中，V_in为未调整的电源电压，MB1、MB2、MB3是静态偏置管；M1～M8为误差放大器增益级；M9为缓冲级；负载电流采样网络Ms，M13，M14采样功率管电流以获得负载信息；M10为工作在线性区的MOS电阻，其过驱动电压(|V_gs|-|V_tp10|)包含负载电流的信息(如公式(5))，第一电容C_c与M10的电阻形成零点，跟踪补偿输出极点；第二电容C_m利用负载电流镜M3、M5的镜像比例，实现电流模式的密勒电容倍增。C_c与C_m在误差放大器输出端的等效值为(K_xC_m+C_c)g_mpr_op。In Figure 2, Vin _is the unadjusted power supply voltage, MB1, MB2, and MB3 are static bias tubes; M1~M8 are error amplifier gain stages; M9 is a buffer stage; the load current sampling network Ms, M13, and M14 sample power tube current to obtain load information; M10 is a MOS resistor operating in the linear region, and its overdrive voltage (|V _gs |-|V _tp10 |) contains load current information (such as formula (5)), the first capacitor C _c It forms a zero point with the resistance of M10 and tracks and compensates the output pole; the second capacitor C _m utilizes the mirror image ratio of the load current mirror M3 and M5 to realize Miller capacitance multiplication in current mode. The equivalent of C _c and C _m at the output of the error amplifier is (K _x C _m +C _c ) g _mp r _op .

为了提高环路GBW，避免寄生极点的影响，以及电流模式密勒倍增的需要，设计的误差放大器为单极点系统的对称的非闭环的跨导放大器(OTA，Operational TransconductanceAmplifier)，除了输出端其他节点均为低阻抗节点。缓冲器Buffer为P型缓冲器，起电平位移和隔离缓冲的作用。由于缓冲器Buffer中Mb2的恒定偏置电流为Ib2，使得将功率管Mp栅极充电电流限制在Ib2之内，却限制不了功率管Mp栅极的放电电流。这就使得在V_out突然减小时，使得功率管Mp栅极的放电电流增大。低功耗的设计使得Mb2的静态偏置电流不可能很大，在V_out突然增大时，限制了上冲调节性能，这也是P型Buffer的固有缺陷。本实用新型采用摆率增强网络M15～M16根据负载状况改变对功率管栅极寄生电容的充电电流值，提升瞬态调整性能。In order to improve the loop GBW, avoid the influence of parasitic poles, and the need for current mode Miller multiplication, the designed error amplifier is a symmetrical non-closed-loop transconductance amplifier (OTA, Operational Transconductance Amplifier) of a single-pole system, except for other nodes at the output end Both are low impedance nodes. Buffer Buffer is a P-type buffer, which acts as a level shift and isolation buffer. Since the constant bias current of Mb2 in the buffer Buffer is Ib2, the grid charging current of the power transistor Mp is limited within Ib2, but the discharge current of the grid of the power transistor Mp cannot be limited. This makes the discharge current of the gate of the power transistor Mp increase when V _out suddenly decreases. The design of low power consumption makes it impossible for the static bias current of Mb2 to be very large. When V _out suddenly increases, it limits the overshoot regulation performance, which is also an inherent defect of P-type Buffer. The utility model adopts the slew rate enhancing network M15-M16 to change the charging current value of the parasitic capacitance of the grid of the power tube according to the load condition, so as to improve the transient adjustment performance.

此外，根据静态功耗和摆率增强的效果以及M10的MOS阻值补偿需要的综合考虑，负载电流采样网络采样比例设计：In addition, according to the comprehensive consideration of static power consumption and the effect of slew rate enhancement and the MOS resistance compensation of M10, the sampling ratio design of the load current sampling network is as follows:

KK 11 == (( WW // LL )) Mm SS (( WW // LL )) Mm PP == 11 :: 13001300 ,, KK 22 == Mm 1212 Mm 1414 == 11 :: 88

因此，在较低负载范围内，M10包含的负载信息可能都低于噪声信号。为此，Mb3引入一路偏置电流，将动态零点固定设置在低负载范围内的输出动态极点变化范围内。Therefore, in the lower load range, the load information contained in M10 may be lower than the noise signal. For this reason, Mb3 introduces a bias current, and the dynamic zero point is fixedly set within the range of the output dynamic pole change range in the low load range.

可以看出，本实用新型的基于动态零极点跟踪技术的LDO，通过第一电容和可变电阻组成补偿网络，作为系统的动态零点；通过采用电流倍增模式的第二电容补偿LDO的环路的相位裕度，提高LDO的环路稳定性。It can be seen that the LDO based on the dynamic zero-pole tracking technology of the utility model forms a compensation network through the first capacitor and the variable resistor as the dynamic zero point of the system; the loop of the LDO is compensated by the second capacitor of the current multiplication mode phase margin, improving the loop stability of the LDO.

本领域的普通技术人员将会意识到，这里所述的实施例是为了帮助读者理解本实用新型的原理，应被理解为本实用新型的保护范围并不局限于这样的特别陈述和实施例。本领域的普通技术人员可以根据本实用新型公开的这些技术启示做出各种不脱离本实用新型实质的其它各种具体变形和组合，这些变形和组合仍然在本实用新型的保护范围内。Those skilled in the art will appreciate that the embodiments described here are to help readers understand the principle of the utility model, and it should be understood that the protection scope of the utility model is not limited to such specific statements and examples. Those skilled in the art can make various other specific modifications and combinations based on the technical revelations disclosed in the utility model without departing from the essence of the utility model, and these variations and combinations are still within the protection scope of the utility model.