CN202230152U - A general automatic test device for multi-bus processor modules - Google Patents

The utility model provides a general automatic testing arrangement of multibus processor module, including the power supply unit, the power supply unit all with the industrial computer, programme-controlled oscilloscope, programme-controlled power and signal acquisition sub-device are connected, the industrial computer links to each other with equipment access box, equipment switching box links to each other with multimeter and digital IO control panel respectively, equipment switching box link to each other with programme-controlled power, the industrial computer and programme-controlled oscilloscope, programme-controlled power and communication board link to each other, programme-controlled oscilloscope and programme-controlled power link to each other with equipment switching box, the utility model discloses test system mainly realizes the portable machinery loading to the different bus processor module of different models, the automatic loading of interior test program, the automatic test of performance and the disconnected short nature test of all pins of module. The testing hardware of the system is matched with developed testing software, so that the functions of automatic identification of the processor module, automatic loading of the internal testing program, real-time display of the performance testing result, report output and the like can be realized.

一种多总线处理器模块通用自动测试装置A general automatic test device for multi-bus processor modules

技术领域 technical field

本实用新型测试系统涉及一种多型、多总线模块的测试装置，特别涉及一种基于虚拟仪器技术设计而成的一种多总线处理器模块通用自动测试装置。The utility model test system relates to a multi-type, multi-bus module test device, in particular to a multi-bus processor module universal automatic test device designed based on virtual instrument technology.

背景技术 Background technique

目前对于处理器模块的生产厂家来说，在处理器的设计和生产过程当中，采用的手段是一种总线的处理器模块设计一个主板。测试时根据被测模块总线的不一样，来选择不同总线的主板。这种设计方案缺乏通用性，同时它要求处理器模块的生产厂家熟悉处理器的总线的时序关系，而对一些厂家来说，由于文件档案的保存问题，很多原始的有关主板的资料都已经找不见了，如果现有的主板出现问题，则无法对生产的处理器模块进行性能测试。At present, for processor module manufacturers, in the design and production process of the processor, the method adopted is to design a motherboard for the processor module of a bus. During the test, the motherboards with different buses are selected according to the different buses of the modules under test. This design scheme lacks versatility, and it requires the manufacturer of the processor module to be familiar with the timing relationship of the bus of the processor. For some manufacturers, due to the preservation of files and files, many original information about the motherboard have been found. Gone, performance testing of production processor modules is not possible if there is a problem with the existing motherboard.

另一方面，现在对处理器性能的测试采用的手段是把连接有处理器的主板上的RS-232接口通过连接电缆连接到计算机的RS-232接口，且每次测试时先在windows98下安装IDE386软件，然后在IDE386下加载处理器的内测程序，最后启动Windows操作系统自带的超级终端来完成对处理器的测试。这种方式的缺点是当更换不同总线的处理器时，一方面必须更换处理器的连接盒，另外一方面由于处理器的测试程序不能自动加载，因此每次只能测试一个模块，测试结果也没办法自动输出报表。On the other hand, the means used to test the performance of the processor is to connect the RS-232 interface on the motherboard connected with the processor to the RS-232 interface of the computer through a connecting cable, and install it under windows98 each time it is tested. IDE386 software, then load the internal test program of the processor under IDE386, and finally start the HyperTerminal that comes with the Windows operating system to complete the test of the processor. The disadvantage of this method is that when replacing processors with different buses, on the one hand, the connection box of the processor must be replaced; There is no way to automatically output the report.

发明内容 Contents of the invention

为了克服上述现有技术的缺陷，本实用新型测试系统提供一种多总线处理器模块通用自动测试装置，能够实现对多型、多总线处理器模块的便携式机械加载、自动内测程序加载，所有引脚的通断性测试、自动性能测试和输出报表的功能。In order to overcome the defects of the above-mentioned prior art, the utility model test system provides a general automatic test device for multi-bus processor modules, which can realize portable mechanical loading and automatic internal test program loading of multi-type and multi-bus processor modules, all Functions of pin continuity test, automatic performance test and report output.

为了达到上述目的，本实用新型通用自动测试系统的技术方案是这样实现的：In order to achieve the above object, the technical scheme of the utility model general automatic test system is realized in this way:

一种多总线处理器模块通用自动测试装置，包括供电单元4，供电单元4均与工控机1、程控示波器2、程控电源3和信号获取子装置7的电源输入端相连接。工控机1的RS-232接口与设备接入盒5的RS-232接口相连，通讯板8、矩阵开关9、万用表10、和数字I/O控制板11则通过PXI总线插入信号获取子装置7的主板上，设备转接盒5的信号输入输出接口分别与信号获取子装置7的万用表10和数字I/O控制板11相连，设备转接盒5的电源输入端与程控电源3的电源输出端相连，工控机1的USB接口分别与程控示波器2和程控电源3的USB接口相连，工控机1通过插在其PCI总线的通讯卡的通讯口与信号获取子装置7的通讯板8的通讯口相连，程控示波器2的信号输入端与设备转接盒5的信号输出端相连，程控电源3的电源信号输出端与设备转接盒5的电源信号输入端相连。A general automatic test device for multi-bus processor modules, including a power supply unit 4, and the power supply unit 4 is connected to an industrial computer 1, a program-controlled oscilloscope 2, a program-controlled power supply 3 and a power input terminal of a signal acquisition sub-device 7. The RS-232 interface of the industrial computer 1 is connected to the RS-232 interface of the equipment access box 5, and the communication board 8, the matrix switch 9, the multimeter 10, and the digital I/O control board 11 are inserted into the signal acquisition sub-device 7 through the PXI bus On the main board of the device transfer box 5, the signal input and output interfaces of the device transfer box 5 are respectively connected to the multimeter 10 and the digital I/O control board 11 of the signal acquisition sub-device 7, and the power input terminal of the device transfer box 5 is connected to the power output of the program-controlled power supply 3 The USB interface of the industrial computer 1 is connected with the USB interface of the program-controlled oscilloscope 2 and the program-controlled power supply 3 respectively, and the industrial computer 1 communicates with the communication board 8 of the signal acquisition sub-device 7 through the communication port of the communication card inserted in its PCI bus. The signal input end of the program-controlled oscilloscope 2 is connected with the signal output end of the equipment adapter box 5, and the power signal output end of the program-controlled power supply 3 is connected with the power signal input end of the equipment adapter box 5.

上面所述的信号获取子装置7包括通讯板8、矩阵开关9、万用表10和数字I/O控制板11。通讯板8、矩阵开关9、万用表10和数字I/O控制板11的板卡都是基于PXI总线的，插于信号获取子装置所在的PXI机箱的背板。矩阵开关9的信号输入端和万用表10的信号输出端通过连接电缆相连，矩阵开关9的信号输入端与数字I/O控制板11的信号输出端相连。The above-mentioned signal acquisition sub-device 7 includes a communication board 8 , a matrix switch 9 , a multimeter 10 and a digital I/O control board 11 . The boards of the communication board 8, the matrix switch 9, the multimeter 10 and the digital I/O control board 11 are all based on the PXI bus, and are inserted into the backplane of the PXI case where the signal acquisition sub-device is located. The signal input end of the matrix switch 9 is connected with the signal output end of the multimeter 10 through a connecting cable, and the signal input end of the matrix switch 9 is connected with the signal output end of the digital I/O control board 11 .

上面所述的设备接入盒5包括总线插座10。被测处理器模块插入总线插座10内，通过总线插座10的输入输出端与信号转接板12相连。The device access box 5 described above includes a bus socket 10 . The processor module under test is inserted into the bus socket 10 and connected to the signal adapter board 12 through the input and output ends of the bus socket 10 .

本实用新型的特点、优点为：Features and advantages of the utility model are:

(1)可以实现对被测处理器模块内测程序的自动加载；(1) It can realize the automatic loading of the internal test program of the processor module under test;

(2)不同种类的被测处理器模块的检测仅需通过更换不同的设备转接盒、便可实现对其的测试；(2) The detection of different types of processor modules under test can be tested only by replacing different equipment adapter boxes;

(3)可以通过所设计的自动测试软件实现对各型处理器模块性能的测试；(3) The performance test of various processor modules can be realized through the designed automatic test software;

(4)该装置可实现对被测处理器模块所有信号引脚的通断和粘连性测试。(4) The device can realize continuity and adhesion testing of all signal pins of the processor module under test.

(5)该装置还可实现对测试结果的录入和历史信息的查询以及测试报表的输出功能。(5) The device can also realize the input of test results, the query of historical information and the output of test reports.

附图说明 Description of drawings

图1是本实用新型系统的组成框图Fig. 1 is the composition block diagram of the utility model system

图2是本实用新型系统中的内测程序的加载流程框图。Fig. 2 is a block diagram of the loading process of the internal testing program in the system of the utility model.

图3是本实用新型系统的覆盖性测试的实现方法。Fig. 3 is the realization method of the coverage test of the utility model system.

具体实施方式 Detailed ways

下面结合附图对本实用新型系统的结构原理和工作原理作详细叙述。Below in conjunction with accompanying drawing, structural principle and working principle of the utility model system are described in detail.

参照图1，一种多总线处理器模块通用自动测试装置，包括供电单元4。供电单元4均与工控机1、程控示波器2、程控电源3和信号获取子装置7的电源输入端相连接，工控机1的RS-232接口与设备接入盒5的RS-232接口相连，通讯板8、矩阵开关9、万用表10、和数字I/O控制板11则通过PXI总线插入信号获取子装置7的主板上。设备转接盒5的信号输入输出接口通过连接电缆6分别与信号获取子装置7的万用表10和数字I/O控制板11相连，设备转接盒5的电源输入端与程控电源3的电源输出端相连，工控机1的USB接口分别与程控示波器2和程控电源3的USB接口相连，工控机1通过插在其PCI总线的通讯卡的通讯口与信号获取子装置7的通讯板8的通讯口相连，程控示波器2的信号输入端与设备转接盒5的信号输出端相连，程控电源3的电源信号输出端与设备转接盒5的电源信号输入端相连。Referring to FIG. 1 , a general automatic test device for a multi-bus processor module includes a power supply unit 4 . The power supply unit 4 is all connected with the power input end of the industrial computer 1, the program-controlled oscilloscope 2, the program-controlled power supply 3 and the signal acquisition sub-device 7, and the RS-232 interface of the industrial computer 1 is connected with the RS-232 interface of the equipment access box 5, The communication board 8, the matrix switch 9, the multimeter 10, and the digital I/O control board 11 are inserted into the main board of the signal acquisition sub-device 7 through the PXI bus. The signal input and output interfaces of the equipment transition box 5 are respectively connected to the multimeter 10 and the digital I/O control board 11 of the signal acquisition sub-device 7 through the connecting cable 6, and the power input terminal of the equipment transition box 5 is connected to the power output of the programmable power supply 3 The USB interface of the industrial computer 1 is connected with the USB interface of the program-controlled oscilloscope 2 and the program-controlled power supply 3 respectively, and the industrial computer 1 communicates with the communication board 8 of the signal acquisition sub-device 7 through the communication port of the communication card inserted in the PCI bus. The signal input end of the program-controlled oscilloscope 2 is connected with the signal output end of the equipment adapter box 5, and the power signal output end of the program-controlled power supply 3 is connected with the power signal input end of the equipment adapter box 5.

上面所述的信号获取子装置7包括通讯板8、矩阵开关9、万用表10和数字I/O控制板11。通讯板8、矩阵开关9、万用表10和数字I/O控制板11的板卡都是基于PXI总线的，插在信号获取子装置所在的PXI机箱的背板上。矩阵开关9的信号输入端和万用表10的信号输出端通过连接电缆相连，矩阵开关9的信号输入端与数字I/O控制板11的信号输出端通过连接电缆13相连。The above-mentioned signal acquisition sub-device 7 includes a communication board 8 , a matrix switch 9 , a multimeter 10 and a digital I/O control board 11 . The boards of the communication board 8, the matrix switch 9, the multimeter 10 and the digital I/O control board 11 are all based on the PXI bus, and are inserted into the backboard of the PXI case where the signal acquisition sub-device is located. The signal input end of the matrix switch 9 is connected with the signal output end of the multimeter 10 through a connection cable, and the signal input end of the matrix switch 9 is connected with the signal output end of the digital I/O control board 11 through a connection cable 13 .

上面所述的设备接入盒5包括总线插座10，被测处理器模块插入总线插座10内，通过总线插座10的输入输出端与信号转接板12相连。The above-mentioned device access box 5 includes a bus socket 10 , the processor module under test is inserted into the bus socket 10 , and connected to the signal adapter board 12 through the input and output ends of the bus socket 10 .

本实用新型的工作原理包括以下步骤：The working principle of the present utility model comprises the following steps:

步骤一：按照上述连接关系保证装置中的所有模块正确连接。Step 1: Ensure that all modules in the device are correctly connected according to the above connection relationship.

步骤二：给供电单元4上电，然后接通供电单元4上的开关，以给程控示波器2、信号获取子装置7供电；然后把被测的处理器模块插于总线插座10；Step 2: power on the power supply unit 4, and then turn on the switch on the power supply unit 4 to supply power to the program-controlled oscilloscope 2 and the signal acquisition sub-device 7; then insert the tested processor module into the bus socket 10;

步骤三：启动工控机1，待工控机的操作系统正常运行后，启动被测处理器的测试软件；Step 3: start the industrial computer 1, after the operating system of the industrial computer runs normally, start the test software of the processor under test;

步骤四：在测试软件中，首先运行该装置的模块自检程序，以实现对通讯板8、矩阵开关9、万用表10、数字I/O控制板11的自检，查看这些模块是否正常工作，本部分属于可选项，不一定每一次测试都需要执行该操作；Step 4: In the test software, first run the module self-inspection program of the device to realize the self-inspection of the communication board 8, the matrix switch 9, the multimeter 10, and the digital I/O control board 11, and check whether these modules are working normally. This part is optional and not necessarily required for every test;

步骤五：给程控电源3供电，打开程控电源3上的面板开关，然后加载被测处理器模块的内测程序，当提示加载成功后，再运行被测处理器模块的性能测试程序，自动判断被测处理器模块是否正常工作；Step 5: Supply power to the program-controlled power supply 3, turn on the panel switch on the program-controlled power supply 3, and then load the internal test program of the processor module under test. Whether the processor module under test works normally;

步骤六：被测处理器模块的测试结果一方面可录入到本系统所带的数据库，同时也可以把测试结果作为报表输出。Step 6: On the one hand, the test results of the tested processor module can be entered into the database of the system, and at the same time, the test results can also be output as a report.

步骤七：在测试软件中，选择“覆盖性测试”，则依据本实用新型的方法执行测试过程，然后把测试结果实时显示在屏幕上。Step 7: In the test software, select "coverage test", then execute the test process according to the method of the utility model, and then display the test result on the screen in real time.

本实用新型中设备接入盒的设计原理The design principle of the equipment access box in the utility model

在上述实用新型方案中，设备接入盒5内的各硬件板卡通过螺丝与金属上盖板紧密连接，其间隙约半个插座的高度。该电路主要实现对被测处理器的I/O线的匹配、过流/过压保护、电源和信号线转接等功能。由于被测的处理器类型较多，设备接入盒5与被测处理器采用电缆连接，更换被测处理器时，只需连接相应的设备接入盒5即可。连接电缆的一端与设备接入盒5的接口设有自动识别芯线，另外一端与被测件相连。当把处理器模块接入所设计的通用设备接入盒5后，首先对测试设备进行自检和自校准。在确认测试设备工作正常后，给处理器加电，然后进行内测程序的加载，待加载成功后，再运行内测程序的测试子程序，并把测试结果回读回来。In the above-mentioned utility model solution, each hardware board in the equipment access box 5 is tightly connected with the metal upper cover through screws, and the gap is about half the height of the socket. The circuit mainly realizes the matching of the I/O line of the processor under test, overcurrent/overvoltage protection, power supply and signal line switching and other functions. Since there are many types of processors to be tested, the device access box 5 is connected to the processor under test by a cable. When replacing the processor under test, only the corresponding device access box 5 needs to be connected. One end of the connecting cable is provided with an automatic identification core wire at the interface of the equipment access box 5, and the other end is connected with the device under test. After the processor module is connected to the designed universal device access box 5, the test device is firstly self-checked and self-calibrated. After confirming that the test equipment is working normally, power on the processor, and then load the internal test program. After the loading is successful, run the test subroutine of the internal test program and read back the test results.

设备接入盒5的前面板上布有七个指示灯和一个自检航插头和三个DB9接头。“电源”、“故障”指示灯分别指示设备接入盒5供电状况和工作的状态情况，“模块1”到“模块5”指示灯分别指示测试模块所安插的测试插座号。The front panel of the equipment access box 5 is provided with seven indicator lights, a self-inspection aviation plug and three DB9 connectors. The "power supply" and "fault" indicator lights respectively indicate the power supply status and working status of the equipment access box 5, and the "module 1" to "module 5" indicator lights respectively indicate the number of the test socket where the test module is inserted.

设备接入盒5在其上设计了模块测试插座，通常情况下，每个设备接入盒5上的测试插座与某个特定的被测处理器模块对应，处理器模块从上向下插入，并有防止插错的标记。每个模块上有电源指示灯、模块故障指示灯和模块指示灯。当某一个处理器模块正常插入时，模块指示灯会亮。The device access box 5 is designed with a modular test socket on it. Usually, the test socket on each device access box 5 corresponds to a specific processor module to be tested, and the processor module is inserted from top to bottom. And there is a mark to prevent wrong insertion. Each module has a power indicator, a module fault indicator and a module indicator. When a processor module is inserted normally, the module indicator light will be on.

(1)处理器内测程序的加载与通讯方法(1) Loading and communication methods of the internal test program of the processor

处理器的内测程序放置在活存，每次在处理器上电后，先需要把内测程序加载到活存中，但是下电后，内测程序也随之自动卸载。以前每次进入IDE 386的运行环境，通过加载IDE 386程序来下载程序，该程序运行结束后，会提示加载成功。但是由于IED386程序只能在Windows 98下运行(而目前多数电脑未安装windows 98操作系统)，同时IDE 386程序也没有办法融合到测试软件中去。The internal test program of the processor is placed in the live storage. Every time the processor is powered on, the internal test program needs to be loaded into the live storage. However, after the power is turned off, the internal test program is also automatically uninstalled. In the past, every time I entered the operating environment of IDE 386, I downloaded the program by loading the IDE 386 program. After the program finished running, it would prompt that the loading was successful. However, because the IED386 program can only run under Windows 98 (and most computers do not have the Windows 98 operating system installed at present), the IDE 386 program cannot be integrated into the test software at the same time.

在本专利申请中首先通过程控电源给处理器供电，在LabVIEW环境下设计了一种下载Intel指令的方法，接下来通过串口把这些指令下载到活存中。In this patent application, the processor is first powered by a programmable power supply, and a method for downloading Intel instructions is designed in the LabVIEW environment, and then these instructions are downloaded to the live memory through the serial port.

指令下载流程如图2所示。在图2中，先对串口进行初始化，然后设置串口的缓存器大小，并发送指令“BWC”，从串口读取6个字节的字符，如何读取的字符正确，则向串口发送数据，如何发送完毕，则结束本次发送数据的过程。The command download process is shown in Figure 2. In Figure 2, initialize the serial port first, then set the buffer size of the serial port, and send the command "BWC" to read 6-byte characters from the serial port. If the read character is correct, send data to the serial port. If the sending is completed, the process of sending data this time ends.

(2)基本性能测试的实现方法(2) Implementation method of basic performance test

处理器的测试内容比较多，有处理器测试、在板RAM测试、在板Flash测试等测试项。对这些信息的获取可通过内测程序来实现，而基本性能测试则是把内测程序的运行结果回读过来。由于处理器模块都有RS-232串口信号线，因此本专利的做法是在LabVIEW下通过VISA的串口函数把测试结果进行回读。There are many test items for the processor, including processor test, on-board RAM test, and on-board Flash test. The acquisition of these information can be realized through the internal test program, and the basic performance test is to read back the running results of the internal test program. Since the processor modules all have RS-232 serial port signal lines, the method of this patent is to read back the test results through the serial port function of VISA under LabVIEW.

所述的覆盖性测试的方法，具体如下：The method of the coverage test is as follows:

一、测试原理1. Test principle

在处理器模块的测试过程中，需要进行处理器模块的覆盖性测试，也就是测试处理器模块各个引脚是否有短路和断路情况，并把出现故障的引脚号标记出来，最终存储在故障数据库中。在本测试设备中采用分组法来测试处理器模块各引脚的粘连性和通断性。不管是LBE总线处理器模块、还是VME总线处理器模块，其信号引脚都可分为以下几组：地址线组、数据线组、控制线组、空引脚组、电源组和地线组。During the testing process of the processor module, it is necessary to carry out the coverage test of the processor module, that is, to test whether each pin of the processor module is short-circuited or open-circuited, and to mark the pin number of the fault, and finally store it in the fault in the database. In this test equipment, the grouping method is used to test the adhesion and continuity of each pin of the processor module. Regardless of whether it is an LBE bus processor module or a VME bus processor module, its signal pins can be divided into the following groups: address line group, data line group, control line group, empty pin group, power supply group and ground wire group .

二、测试基本步骤2. Basic steps of testing

第一步：组内的通断性测试Step 1: Continuity test within the group

通断性测试主要针对电源组和地线组，组内测试是为了保证所有的引脚是连通的。The continuity test is mainly for the power group and the ground group, and the test within the group is to ensure that all pins are connected.

第二步：组间的粘连性测试Step 2: Adhesion test between groups

按照上述的分组原则，顺序执行组间的测试，以保证所有的组间信号没有粘连。According to the above-mentioned grouping principle, the tests between the groups are performed sequentially to ensure that there is no adhesion between all the signals between the groups.

三、覆盖性测试的实现方法3. Implementation method of coverage test

在本系统中采用2×256开关模块配合万用表模块执行覆盖性测试。In this system, 2×256 switch modules and multimeter modules are used to perform coverage tests.

在执行组内信号的通断性测试时把组内的信号分成两组，这两组分别挂到开关模块的两个行上，在如图3所示的系统实现原理图中，R0，R1代表矩阵开关的行，C0，C1，C2…C255代表列。“HI和“R0”指的是万用表模块10的输入接口需要连接的信号端。当把每一组信号挂在开关模块的列上，然后用万用表测试两个行“R0”和“R1”之间的电阻值，如果测试出的阻值大于设定的阻值，则认为该组信号内部通断正常。When performing the continuity test of the signals in the group, the signals in the group are divided into two groups, and these two groups are respectively hung on the two rows of the switch module. In the schematic diagram of the system realization shown in Figure 3, R0, R1 Rows represent matrix switches, C0, C1, C2...C255 represent columns. "HI and "R0" refer to the signal terminals that the input interface of the multimeter module 10 needs to be connected to. When each group of signals is hung on the column of the switch module, then use a multimeter to test the difference between the two rows "R0" and "R1" If the tested resistance value is greater than the set resistance value, it is considered that the internal continuity of the group of signals is normal.

在执行组间信号的粘连性测试时，把组内的信号分成两组，这两组分别挂到开关模块的两个行“R0”和“R1”上。然后用万用表测试两个行之间的电阻值。如果测试出的阻值大于设定的阻值，则认为没有信号粘连，程序继续执行下一组的组间测试；如果测试出的阻值小于设定的阻值，则认为有信号粘连，于是把其中一组的每一个信号和目前测试的组再进行多次测试，循环执行上述过程，直到找见两个粘连的信号组。When performing the adhesion test of signals between groups, divide the signals in the group into two groups, and these two groups are connected to the two rows "R0" and "R1" of the switch module respectively. Then test the resistance value between the two rows with a multimeter. If the tested resistance value is greater than the set resistance value, it is considered that there is no signal adhesion, and the program continues to perform the next group of inter-group tests; if the tested resistance value is less than the set resistance value, it is considered that there is signal adhesion, so Perform multiple tests on each signal in one of the groups and the currently tested group, and execute the above process in a loop until two cohesive signal groups are found.