CN203444380U - Output voltage control circuit - Google Patents
- ️Wed Feb 19 2014
CN203444380U - Output voltage control circuit - Google Patents
Output voltage control circuit Download PDFInfo
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- CN203444380U CN203444380U CN201320564036.3U CN201320564036U CN203444380U CN 203444380 U CN203444380 U CN 203444380U CN 201320564036 U CN201320564036 U CN 201320564036U CN 203444380 U CN203444380 U CN 203444380U Authority
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Abstract
The utility model discloses an output voltage control circuit. By means of the magnitude of currents fed back to voltage stabilizing chips by an input logic signal control circuit, the magnitude of voltage output by a voltage stabilizing circuit is controlled so as to provide stable output voltage. Besides, different output voltages are provided for a system on different situations according to whether the two voltage stabilizing chips in the input logic signal control circuit works. Normal operation of the system is guaranteed, and the electricity quantity of a power supply is saved for the system. Besides, the circuit is simple in structure, easy to achieve and capable of controlling converting of the output voltages accurately.
Description
Technical field
The utility model relates to circuit engineering field, relates in particular to a kind of output voltage controlling circuit.
Background technology
At present, along with the renewal day by day of product, efficient power management has become one of key factor of circuit design.
Because system is under different operating state, to the demand of voltage, be different.For example, when needs are processed mass data, the voltage that use amplitude is higher, when calculated amount is little, or in holding state lower time, can be used the voltage that amplitude is lower.
If power supply provides high voltage always, may cause the waste of electric weight.If low voltage is provided always, can affect system operation, cannot carry out extensive calculation process.
Therefore, on the design field of power-efficient, one of them is exactly to provide different output voltages for the different operating situation of system now, to realize in the normal operation of assurance system, for system is saved electric quantity of power supply.
Utility model content
The utility model embodiment provides a kind of output voltage controlling circuit, for realizing in the normal operation of assurance system, for system is saved electric quantity of power supply.
A kind of output voltage controlling circuit, comprise: the first voltage input end mouth (101), Voltage-output port (102), the first logic input terminal mouth (103), the second logic input terminal mouth (104), the 3rd logic input terminal mouth (105), second voltage input port (106), tertiary voltage input port (107), the first mu balanced circuit (108), feedback circuit (109), the first logic control circuit (110), the second mu balanced circuit (111), the second logic control circuit (112), the 3rd mu balanced circuit (113) and the 3rd logic control circuit (114),
Wherein, described the first mu balanced circuit (108) one end is connected with described voltage input end mouth (101), and the other end of described the first mu balanced circuit (108) is connected with described the second mu balanced circuit (111);
Described feedback circuit (109) one end is connected with described the second mu balanced circuit (111), and described feedback circuit (109) other end is connected with described the first mu balanced circuit (108);
The first logic control circuit (110) one end is connected with described the first logic input terminal mouth (103), and the other end of described the first logic control circuit (110) is connected with feedback circuit (109);
The first logic control circuit (110), according to from the first logic control signal of receiving of the first logic input terminal mouth (103), control the size that described feedback circuit (109) feeds back to the feedback current of described the first mu balanced circuit (108); Described the first mu balanced circuit (108) varies in size according to the feedback current receiving, exports the voltage of corresponding size to described the second mu balanced circuit (111);
One end of described the second mu balanced circuit (111) is connected with described feedback circuit (109) with described the first mu balanced circuit (108), and the other end of described the second mu balanced circuit (111) is connected with the second logic control circuit (112); One end again of described the second mu balanced circuit (111) is connected with described Voltage-output port (102);
Described the second logic control circuit (112) is connected with described the second logic input terminal mouth (104), second voltage input port (106) and tertiary voltage input port (107) respectively;
One end of described the 3rd mu balanced circuit (113) is connected with described tertiary voltage input port (107), and the other end of described the 3rd mu balanced circuit (113) is connected with the 3rd logic control circuit (114); One end again of described the second mu balanced circuit (113) is connected with described Voltage-output port (102);
Described the second logic control circuit (114) is connected with described the 3rd logic input terminal mouth (105), second voltage input port (106) and tertiary voltage input port (107) respectively;
Wherein, described the second logic control circuit (112) receives the second logic control signal by the second logic input terminal mouth (104), according to the second logic control signal receiving, controls whether conducting of described the second mu balanced circuit (111); Described the 3rd logic control circuit (114) receives the 3rd logic control signal by the 3rd logic input terminal mouth (105), according to the 3rd logic control signal receiving, controls the whether conducting of described the 3rd mu balanced circuit (113); When described the second mu balanced circuit (111) or described the 3rd mu balanced circuit (113) conducting, output voltage is to described voltage output end (102).
Preferably, described the first mu balanced circuit (108) comprises the first voltage stabilizing chip (1081) and inductance (1082); Described feedback circuit (109) comprises the first resistance (1091), the second resistance (1092) and the 3rd resistance (1092); Described the first logic control circuit (110) comprises the first triode (1101) and the 4th resistance (1102);
Wherein, the first port of described the first voltage stabilizing chip (1081) is connected with described the first voltage input end mouth (101); The second port of described the first voltage stabilizing chip (1081) is connected with described the second mu balanced circuit (111) by described inductance (1082);
Described the first resistance (1091), the second resistance (1092) and the 3rd resistance (1092) are connected between described the second mu balanced circuit (111) and ground, and the 3rd port of described the first voltage stabilizing chip (1081) is connected between described the first resistance (1091) and the second resistance (1092);
The collector of described the first triode (1101) is connected between described the second resistance (1092) and the 3rd resistance (1093); The grounded emitter of described the first triode (1101); The base stage of described the first triode (1101) is by the 4th resistance (1102) ground connection, and meanwhile, the base stage of described the first triode (161) is connected with described the first logic input terminal mouth (103).
Preferably, described the second mu balanced circuit (111) comprises the second voltage stabilizing chip (1111); Described the second logic control circuit (112) comprising: the 5th resistance (1121), the 6th resistance (1122), the 7th resistance (1123) and the second triode (1124);
The first port of described the second voltage stabilizing chip (1111) is connected with described the first resistance (1091) with described inductance (1082); The 3rd port of described the second voltage stabilizing chip (1111) is connected with described Voltage-output port (102);
Described the 5th resistance (1121) one end is connected with described second voltage input port (106), and described the 5th resistance (1121) other end is connected with the second port of described the second voltage stabilizing chip (1111);
Described the 6th resistance (1122) one end is connected with described the second logic input terminal mouth (104), and described the 6th resistance (1122) other end is connected with the base stage of described the second triode (1124);
One end of described the 7th resistance (1123) is connected with described tertiary voltage input port (107), and described the 7th resistance (1123) other end is connected with described the second logic input terminal mouth (104);
The collector of described the second triode (1124) is connected with the second port of described the second voltage stabilizing chip (1111), the grounded emitter of described the first triode (1124).
Preferably, described the 3rd mu balanced circuit (113) comprises the 3rd voltage stabilizing chip (1131); Described the 3rd logic control circuit (114) comprising: the 8th resistance (1141), the 9th resistance (1142), the tenth resistance (1143) and the 3rd triode (1144);
The first port of described the 3rd voltage stabilizing chip (1131) is connected with described tertiary voltage input port (107); The 3rd port of described the 3rd voltage stabilizing chip (1111) is connected with described Voltage-output port (102);
Described the 8th resistance (1141) one end is connected with described second voltage input port (106), and described the 8th resistance (1141) other end is connected with the second port of described the 3rd voltage stabilizing chip (1131);
Described the 9th resistance (1142) one end is connected with described the 3rd logic input terminal mouth (105), and described the 9th resistance (1142) other end is connected with the base stage of described the 3rd triode (1144);
One end of described the tenth resistance (1143) is connected with described tertiary voltage input port (107), and described the tenth resistance (1143) other end is connected with described the 3rd logic input terminal mouth (105);
The collector of described the 3rd triode (1144) is connected with the second port of described the 3rd voltage stabilizing chip (1131), the grounded emitter of described the 3rd triode (1144).
The output voltage controlling circuit of the present embodiment, by feeding back to the size of the electric current of voltage stabilizing chip in input logic signal control circuit, and then controls the size of the voltage of described mu balanced circuit output, so that stable output voltage to be provided.In addition, by two voltage stabilizing chips in input logic signal control circuit, whether work, take under different situations as system provides different output voltages.Realization is in the normal operation of assurance system, for system is saved electric quantity of power supply.And circuit structure is simple, realize easily, can control comparatively exactly the conversion of output voltage.
Other features and advantages of the utility model will be set forth in the following description, and, partly from instructions, become apparent, or understand by implementing the utility model.The purpose of this utility model and other advantages can be realized and be obtained by specifically noted structure in the instructions write, claims and accompanying drawing.
Below by drawings and Examples, the technical solution of the utility model is described in further detail.
Accompanying drawing explanation
Accompanying drawing is used to provide further understanding of the present utility model, and forms a part for instructions, is used from explanation the utility model with embodiment mono-of the present utility model, does not form restriction of the present utility model.In the accompanying drawings:
Fig. 1 is the structural representation of output voltage controlling circuit in the utility model embodiment;
Fig. 2 is the electrical block diagram of output voltage controlling circuit in the utility model embodiment.
Embodiment
Below in conjunction with accompanying drawing, preferred embodiment of the present utility model is described, should be appreciated that preferred embodiment described herein is only for description and interpretation the utility model, and be not used in restriction the utility model.
Because system is under different operating state, to the demand of voltage, be different.The utility model provides a kind of can realize the conversion to electric power output voltage simply, quickly and accurately.
As shown in Figure 1, the output voltage controlling circuit of the utility model embodiment, comprising:
The first voltage
input end mouth101, Voltage-
output port102, the first logic
input terminal mouth103, the second logic
input terminal mouth104, the 3rd logic
input terminal mouth105, second
voltage input port106, tertiary
voltage input port107, the first mu balanced circuit 108, feedback circuit 109, the first logic control circuit 110, the second mu balanced circuit 111, the second logic control circuit 112, the 3rd mu balanced circuit 113 and the 3rd logic control circuit 114.
Wherein, first mu balanced circuit 108 one end are connected with voltage
input end mouth101, and the other end of the first mu balanced circuit 108 is connected with the second mu balanced circuit 111.
Feedback circuit 109 one end are connected with the second mu balanced circuit 111, and feedback circuit 109 other ends are connected with the first mu balanced circuit 108.
First logic control circuit 110 one end are connected with the first logic
input terminal mouth103, and the other end of the first logic control circuit 110 is connected with feedback circuit 109.
The first logic control circuit 110, according to from the first logic control signal of receiving of the first logic
input terminal mouth103, feedback control circuit 109 feeds back to the size of the feedback current of the first mu balanced circuit 108; The first mu balanced circuit 108 varies in size according to the feedback current receiving, exports the voltage of corresponding size to the second mu balanced circuit 111.
One end of the second mu balanced circuit 111 is connected with feedback circuit 109 with the first mu balanced circuit 108, and the other end of the second mu balanced circuit 111 is connected with the second logic control circuit 112; One end again of the second mu balanced circuit 111 is connected with Voltage-
output port102.
The second logic control circuit 112 is connected with the second logic
input terminal mouth104, second
voltage input port106 and tertiary
voltage input port107 respectively.
One end of the 3rd mu balanced circuit 113 is connected with tertiary
voltage input port107, and the other end of the 3rd mu balanced circuit 113 is connected with the 3rd logic control circuit 114; One end again of the second mu balanced circuit 113 is connected with Voltage-
output port102.
The second logic control circuit 114 is connected with the 3rd logic
input terminal mouth105, second
voltage input port106 and tertiary
voltage input port107 respectively.
Wherein, the second logic control circuit 112 is by the second logic input
terminal mouth104 receive logic control signals, according to the second logic control signal receiving, controls the whether conducting of the second mu balanced circuit 111; The 3rd logic control circuit 114 receives the 3rd logic control signals by the 3rd logic
input terminal mouth105, according to the 3rd logic control signal receiving, controls the whether conducting of the 3rd mu balanced circuit 113; When the second mu balanced circuit 111 or the 3rd mu balanced circuit 113 conducting, output voltage is to
voltage output end102.
Preferably, as shown in Figure 2, the first mu balanced circuit 108 comprises the first
voltage stabilizing chip1081 and
inductance1082; Feedback circuit 109 comprises the
first resistance1091, the
second resistance1092 and the
3rd resistance1092; The first logic control circuit 110 comprises the
first triode1101 and the
4th resistance1102.
Wherein, the first port IN of the first
voltage stabilizing chip1081 is connected with the first voltage
input end mouth101; The second port OUT of the first
voltage stabilizing chip1081 is connected with the second mu balanced circuit 111 by
inductance1082.
The
first resistance1091, the
second resistance1092 and the
3rd resistance1092 are connected between the second mu balanced circuit 111 and ground, and the 3rd port FB of the first
voltage stabilizing chip1081 is connected between the
first resistance1091 and the
second resistance1092.
The collector of the
first triode1101 is connected between the
second resistance1092 and the
3rd resistance1093; The grounded emitter of the
first triode1101; The base stage of the
first triode1101 is by the
4th resistance1102 ground connection, and meanwhile, the base stage of the first triode 161 is connected with the first logic
input terminal mouth103.
Preferably, as shown in Figure 2, the second mu balanced circuit 111 comprises the second
voltage stabilizing chip1111; The second logic control circuit 112 comprises: the
5th resistance1121, the
6th resistance1122, the
7th resistance1123 and the
second triode1124.
The first port S2 of the second
voltage stabilizing chip1111 is connected with the
first resistance1091 with
inductance1082; The 3rd port D2 of the second
voltage stabilizing chip1111 is connected with Voltage-
output port102.
The
5th resistance1121 one end are connected with second
voltage input port106, and the
5th resistance1121 other ends are connected with the second port Q2 of the second
voltage stabilizing chip1111.
The
6th resistance1122 one end are connected with the second logic
input terminal mouth104, and the
6th resistance1122 other ends are connected with the base stage of the
second triode1124.
One end of the
7th resistance1123 is connected with tertiary
voltage input port107, and the
7th resistance1123 other ends are connected with the second logic
input terminal mouth104.
The collector of the
second triode1124 is connected with the second port of the second
voltage stabilizing chip1111, the grounded emitter of the
first triode1124.
Preferably, as shown in Figure 2, the 3rd mu balanced circuit 113 comprises the 3rd
voltage stabilizing chip1131; The 3rd logic control circuit 114 comprises: the
8th resistance1141, the
9th resistance1142, the
tenth resistance1143 and the 3rd triode 1144.
The first port S3 of the 3rd
voltage stabilizing chip1131 is connected with tertiary
voltage input port107; The 3rd port D3 of the 3rd
voltage stabilizing chip1111 is connected with Voltage-
output port102.
The
8th resistance1141 one end are connected with second
voltage input port106, and the
8th resistance1141 other ends are connected with the second port Q3 of the 3rd
voltage stabilizing chip1131.
The
9th resistance1142 one end are connected with the 3rd logic
input terminal mouth105, and the
9th resistance1142 other ends are connected with the base stage of the 3rd triode 1144.
One end of the
tenth resistance1143 is connected with tertiary
voltage input port107, and the
tenth resistance1143 other ends are connected with the 3rd logic
input terminal mouth105.
The collector of the 3rd triode 1144 is connected with the second port of the 3rd
voltage stabilizing chip1131, the grounded emitter of the 3rd triode 1144.
Below the specific works principle of the output voltage controlling circuit of the utility model embodiment is described.
Under different operating state, system is different to the demand of voltage.System can be operated in two kinds of voltage modes, and 3.3V and 5V, when needs are processed mass data, are used 5V voltage, when calculated amount is little, or in holding state lower time, uses 3.3V voltage.
The first logic control signal that the first logic input terminal mouth input is set is 0 or 1.By controlling the closure or openness as the
first triode1101 of switch, make the
3rd resistance1093 places in circuit in feedback circuit 109 or by short circuit, change the feedback current that offers the first
voltage stabilizing chip1081, to change the output voltage of the first mu balanced circuit 108.
In the present embodiment, can, by the first logic control signal receiving, control the stably output 5V voltage of the first mu balanced circuit 108.
When the first stabilized circuit outputting voltage hour, it is 0 that the first logic control signal can be set, being equivalent to provides a low level in the
first triode1101 base stages, the
first triode1101 is opened, and the
3rd resistance1093 is linked in circuit.At this moment, due to the
first resistance1091, the
second resistance1092 and the
3rd resistance1092 series connection, feedback circuit 109 resistances increase, electric current on this series circuit reduces, thereby the feedback current that the 3rd port FB of the first
voltage stabilizing chip1081 obtains also reduces, the voltage of the second port OUT output of the first
voltage stabilizing chip1081 increases, the voltage of the output terminal output 5V making at the first mu balanced circuit 108.
When the first stabilized circuit outputting voltage is when larger, it is 1 that the first logic control signal can be set, and being equivalent to provides a high level in the
first triode1101 base stages, and the
first triode1101 closures make the
3rd resistance1093 by short circuit.At this moment, due to the
first resistance1091 and the
second resistance1092 series connection, feedback circuit 109 resistances reduce, electric current on this series circuit increases, thereby the feedback current that the 3rd port FB of the first
voltage stabilizing chip1081 obtains also increases, the voltage of the second port OUT output of the first
voltage stabilizing chip1081 reduces, the voltage of the output terminal output 5V making at the first mu balanced circuit 108.
In the present embodiment, second
voltage input port106 input voltages are 5V, and tertiary
voltage input port107 input voltages are 3.3V.
The second logic control signal that the second logic
input terminal mouth104 inputs are set is that the 3rd logic control signal of 0 or 1, the three logic
input terminal mouth105 inputs is 0 or 1.By second and third logic control signal, control the second voltage stabilizing chip or the 3rd voltage stabilizing chip conducting, make the voltage in the different amplitudes of Voltage-
output port102 output.
As shown in table 1 below, when the second logic
input terminal mouth104 receives the second logic control signals, be that to receive the 3rd logic control signal be 1 to 0, the three logic input terminal mouth 105.Being equivalent to provides a low level in the base stage of the
second triode1124, the
second triode1124 is opened, collector, the emitter current of the
second triode1124 are 0, are equivalent to the off-state of switch between collector and emitter, and the
second triode1124 works in cut-off region.Base stage at the 3rd triode 1144 provides a high level, the 3rd triode 1144 closures, the collector and emitter of the 3rd triode 1144 has electric current, is equivalent to the conducting state of switch between collector and emitter, and the 3rd triode 1144 works in saturation region.
Because the
second triode1124 works in cut-off region, at the second port Q2 of the second
voltage stabilizing chip1111, by the
5th resistance1121, obtain a high level, make the second
voltage stabilizing chip1111 conductings; And the 3rd triode 1144 works in saturation region, due to the shunting of triode, the second port Q3 making at the 3rd
voltage stabilizing chip1131 obtains a low level, and the 3rd
voltage stabilizing chip1131 is closed.Therefore, the voltage in 102 outputs of Voltage-output port is 5V.
In like manner, when the second logic
input terminal mouth104 receives the second logic control signal, be 1, the 3rd logic control signal that the 3rd logic
input terminal mouth105 receives is 0 o'clock, and being equivalent to provides a high level in the base stage of the
second triode1124, the
second triode1124 closures; Base stage at the 3rd triode 1144 provides a low level, and the 3rd triode 1144 is opened.The second
voltage stabilizing chip1111 is closed, the 3rd
voltage stabilizing chip1131 conductings, the voltage of exporting at Voltage-
output port1102 is 3.3V.
Table 1
| The second logic control signal | The 3rd logic control signal | Voltage output end |
| 0 | 1 | 5V |
| 1 | 0 | 3.3V |
The output voltage controlling circuit of the utility model embodiment, by feeding back to the size of the electric current of voltage stabilizing chip in input logic signal control circuit, and then controls the size of the voltage of described mu balanced circuit output, so that stable output voltage to be provided.In addition, by two voltage stabilizing chips in input logic signal control circuit, whether work, take under different situations as system provides different output voltages.Realization is in the normal operation of assurance system, for system is saved electric quantity of power supply.And circuit structure is simple, realize easily, can control comparatively exactly the conversion of output voltage.
Obviously, those skilled in the art can carry out various changes and modification and not depart from spirit and scope of the present utility model the utility model.Like this, if within of the present utility model these are revised and modification belongs to the scope of the utility model claim and equivalent technologies thereof, the utility model is also intended to comprise these changes and modification interior.
Claims (4)
1. an output voltage controlling circuit, it is characterized in that, comprise: the first voltage input end mouth (101), Voltage-output port (102), the first logic input terminal mouth (103), the second logic input terminal mouth (104), the 3rd logic input terminal mouth (105), second voltage input port (106), tertiary voltage input port (107), the first mu balanced circuit (108), feedback circuit (109), the first logic control circuit (110), the second mu balanced circuit (111), the second logic control circuit (112), the 3rd mu balanced circuit (113) and the 3rd logic control circuit (114),
Wherein, described the first mu balanced circuit (108) one end is connected with described voltage input end mouth (101), and the other end of described the first mu balanced circuit (108) is connected with described the second mu balanced circuit (111);
Described feedback circuit (109) one end is connected with described the second mu balanced circuit (111), and described feedback circuit (109) other end is connected with described the first mu balanced circuit (108);
Described the first logic control circuit (110) one end is connected with described the first logic input terminal mouth (103), and the other end of described the first logic control circuit (110) is connected with feedback circuit (109);
Described the first logic control circuit (110), according to from the first logic control signal of receiving of the first logic input terminal mouth (103), control the size that described feedback circuit (109) feeds back to the feedback current of described the first mu balanced circuit (108); Described the first mu balanced circuit (108) varies in size according to the feedback current receiving, exports the voltage of corresponding size to described the second mu balanced circuit (111);
One end of described the second mu balanced circuit (111) is connected with described feedback circuit (109) with described the first mu balanced circuit (108), and the other end of described the second mu balanced circuit (111) is connected with the second logic control circuit (112); One end again of described the second mu balanced circuit (111) is connected with described Voltage-output port (102);
Described the second logic control circuit (112) is connected with described the second logic input terminal mouth (104), second voltage input port (106) and tertiary voltage input port (107) respectively;
One end of described the 3rd mu balanced circuit (113) is connected with described tertiary voltage input port (107), and the other end of described the 3rd mu balanced circuit (113) is connected with the 3rd logic control circuit (114); One end again of described the second mu balanced circuit (113) is connected with described Voltage-output port (102);
Described the 3rd logic control circuit (114) is connected with described the 3rd logic input terminal mouth (105), second voltage input port (106) and tertiary voltage input port (107) respectively;
Wherein, described the second logic control circuit (112) receives the second logic control signal by the second logic input terminal mouth (104), according to the second logic control signal receiving, controls whether conducting of described the second mu balanced circuit (111); Described the 3rd logic control circuit (114) receives the 3rd logic control signal by the 3rd logic input terminal mouth (105), according to the 3rd logic control signal receiving, controls the whether conducting of described the 3rd mu balanced circuit (113); When described the second mu balanced circuit (111) or described the 3rd mu balanced circuit (113) conducting, output voltage is to described voltage output end (102).
2. circuit according to claim 1, is characterized in that, described the first mu balanced circuit (108) comprises the first voltage stabilizing chip (1081) and inductance (1082); Described feedback circuit (109) comprises the first resistance (1091), the second resistance (1092) and the 3rd resistance (1092); Described the first logic control circuit (110) comprises the first triode (1101) and the 4th resistance (1102);
Wherein, the first port of described the first voltage stabilizing chip (1081) is connected with described the first voltage input end mouth (101); The second port of described the first voltage stabilizing chip (1081) is connected with described the second mu balanced circuit (111) by described inductance (1082);
Described the first resistance (1091), the second resistance (1092) and the 3rd resistance (1092) are connected between described the second mu balanced circuit (111) and ground, and the 3rd port of described the first voltage stabilizing chip (1081) is connected between described the first resistance (1091) and the second resistance (1092);
The collector of described the first triode (1101) is connected between described the second resistance (1092) and the 3rd resistance (1093); The grounded emitter of described the first triode (1101); The base stage of described the first triode (1101) is by the 4th resistance (1102) ground connection, and meanwhile, the base stage of described the first triode (161) is connected with described the first logic input terminal mouth (103).
3. circuit according to claim 2, is characterized in that, described the second mu balanced circuit (111) comprises the second voltage stabilizing chip (1111); Described the second logic control circuit (112) comprising: the 5th resistance (1121), the 6th resistance (1122), the 7th resistance (1123) and the second triode (1124);
The first port of described the second voltage stabilizing chip (1111) is connected with described the first resistance (1091) with described inductance (1082); The 3rd port of described the second voltage stabilizing chip (1111) is connected with described Voltage-output port (102);
Described the 5th resistance (1121) one end is connected with described second voltage input port (106), and described the 5th resistance (1121) other end is connected with the second port of described the second voltage stabilizing chip (1111);
Described the 6th resistance (1122) one end is connected with described the second logic input terminal mouth (104), and described the 6th resistance (1122) other end is connected with the base stage of described the second triode (1124);
One end of described the 7th resistance (1123) is connected with described tertiary voltage input port (107), and described the 7th resistance (1123) other end is connected with described the second logic input terminal mouth (104);
The collector of described the second triode (1124) is connected with the second port of described the second voltage stabilizing chip (1111), the grounded emitter of described the first triode (1124).
4. according to the arbitrary described circuit of claim 1-3, it is characterized in that, described the 3rd mu balanced circuit (113) comprises the 3rd voltage stabilizing chip (1131); Described the 3rd logic control circuit (114) comprising: the 8th resistance (1141), the 9th resistance (1142), the tenth resistance (1143) and the 3rd triode (1144);
The first port of described the 3rd voltage stabilizing chip (1131) is connected with described tertiary voltage input port (107); The 3rd port of described the 3rd voltage stabilizing chip (1111) is connected with described Voltage-output port (102);
Described the 8th resistance (1141) one end is connected with described second voltage input port (106), and described the 8th resistance (1141) other end is connected with the second port of described the 3rd voltage stabilizing chip (1131);
Described the 9th resistance (1142) one end is connected with described the 3rd logic input terminal mouth (105), and described the 9th resistance (1142) other end is connected with the base stage of described the 3rd triode (1144);
One end of described the tenth resistance (1143) is connected with described tertiary voltage input port (107), and described the tenth resistance (1143) other end is connected with described the 3rd logic input terminal mouth (105);
The collector of described the 3rd triode (1144) is connected with the second port of described the 3rd voltage stabilizing chip (1131), the grounded emitter of described the 3rd triode (1144).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320564036.3U CN203444380U (en) | 2013-09-11 | 2013-09-11 | Output voltage control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320564036.3U CN203444380U (en) | 2013-09-11 | 2013-09-11 | Output voltage control circuit |
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|---|---|
| CN203444380U true CN203444380U (en) | 2014-02-19 |
Family
ID=50095413
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| CN201320564036.3U Withdrawn - After Issue CN203444380U (en) | 2013-09-11 | 2013-09-11 | Output voltage control circuit |
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Cited By (2)
* Cited by examiner, † Cited by third party| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103488223A (en) * | 2013-09-11 | 2014-01-01 | 天脉聚源(北京)传媒科技有限公司 | Output voltage control circuit |
| CN107168436A (en) * | 2017-06-20 | 2017-09-15 | 合肥威艾尔智能技术有限公司 | A kind of dual voltage-stabilized power supply circuit adjusted based on two close cycles |
-
2013
- 2013-09-11 CN CN201320564036.3U patent/CN203444380U/en not_active Withdrawn - After Issue
Cited By (3)
* Cited by examiner, † Cited by third party| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103488223A (en) * | 2013-09-11 | 2014-01-01 | 天脉聚源(北京)传媒科技有限公司 | Output voltage control circuit |
| CN103488223B (en) * | 2013-09-11 | 2015-11-25 | 天脉聚源(北京)传媒科技有限公司 | A kind of output voltage controlling circuit |
| CN107168436A (en) * | 2017-06-20 | 2017-09-15 | 合肥威艾尔智能技术有限公司 | A kind of dual voltage-stabilized power supply circuit adjusted based on two close cycles |
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| Date | Code | Title | Description |
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| 2014-02-19 | C14 | Grant of patent or utility model | |
| 2014-02-19 | GR01 | Patent grant | |
| 2015-11-25 | AV01 | Patent right actively abandoned |
Granted publication date: 20140219 Effective date of abandoning: 20151125 |
| 2015-11-25 | C25 | Abandonment of patent right or utility model to avoid double patenting |