CN204597988U - The AFDX terminal test equipment of Based PC PCI interface - Google Patents

The utility model discloses a kind of AFDX terminal test equipment of Based PC PCI interface, comprising: PCI communication module, for realizing the exchanges data between host computer and programmable chip; Programmable chip, data for being passed down by host computer carry out AFDX protocol code to be given to tested AFDX aviation ethernet standard equipment, and the data that tested AFDX aviation ethernet standard equipment is uploaded are carried out verify, traffic shaping and Redundancy Management to be to be given to host computer; AFDX terminal test equipment interface module, for realizing the exchanges data between programmable chip and tested AFDX aviation ethernet standard equipment; Power module, powers for giving whole testing equipment.The utility model achieves sampling, the function such as queue and error injection/detection of AFDX aviation ethernet standard equipment.

基于PCI接口的AFDX终端测试设备AFDX Terminal Test Equipment Based on PCI Interface

技术领域technical field

本实用新型涉及测试设备技术领域，具体涉及一种基于PCI接口的AFDX终端测试设备。The utility model relates to the technical field of testing equipment, in particular to an AFDX terminal testing equipment based on a PCI interface.

背景技术Background technique

AFDX全称为航空电子全双工交换式以太网(Avionics Full DuplexSwitched Ethernet，AFDX)，它是为在航空子系统之间进行数据交换而定义的一种协议(IEEE802.3和ARINC664Part7)标准，是基于ARINC429和1553B基础之上的一种总线通信协议规范(ARINC664)。AFDX是目前世界上较先进的航空电子网络数据传输技术之一，它是以成熟的高带宽以太网技术和广泛应用的TCP/IP协议为基础，因此其研发、部署和实施与传统的航电系统相比会更加容易，成本更低。但是与常规以太网相比，它又具有实时性好、可靠性高等特点。目前，AFDX航空以太网在大中型运输机和客机等航空电子网络应用中表现出很强的适应性，隐藏着有着巨大应用潜力。因此，该类航空电子设备(AFDX航空以太网标准设备)的测试和维护就显得日益重要了。另外，由于PCI总线传输速度快，而且支持热插拔、电源管理等功能，不但能满足多路AFDX航空以太网的高速数据传输，而且体积小、价格低、使用方便、应用范围广，而且PCI总线是处于主流的航电工控计算机总线，因此，将PCI技术和TCP/IP技术应用到AFDX航空以太网中，设计一种基于PCI接口的AFDX航空以太网终端测试设备，将给人们带来许多更多方便。The full name of AFDX is Avionics Full Duplex Switched Ethernet (AFDX), which is a protocol (IEEE802.3 and ARINC664Part7) standard defined for data exchange between aviation subsystems, based on A bus communication protocol specification (ARINC664) based on ARINC429 and 1553B. AFDX is one of the more advanced avionics network data transmission technologies in the world. It is based on mature high-bandwidth Ethernet technology and widely used TCP/IP protocol. Therefore, its development, deployment and implementation are different from traditional avionics system will be easier and less costly. But compared with conventional Ethernet, it has the characteristics of good real-time performance and high reliability. At present, AFDX Aviation Ethernet has shown strong adaptability in avionics network applications such as large and medium-sized transport aircraft and passenger aircraft, and has huge application potential hidden. Therefore, the testing and maintenance of this type of avionics equipment (AFDX aviation Ethernet standard equipment) is becoming more and more important. In addition, due to the fast transmission speed of the PCI bus and the support for hot swapping, power management and other functions, it can not only meet the high-speed data transmission of multi-channel AFDX aviation Ethernet, but also has small size, low price, convenient use, and wide application range. The bus is the mainstream avionics industrial control computer bus. Therefore, applying PCI technology and TCP/IP technology to AFDX aviation Ethernet and designing an AFDX aviation Ethernet terminal test equipment based on PCI interface will bring many benefits to people. More convenient.

实用新型内容Utility model content

本实用新型目的在于提供一种基于PCI接口的AFDX终端测试设备。The purpose of the utility model is to provide an AFDX terminal testing device based on the PCI interface.

上述目的通过以下技术方案实现：Above-mentioned purpose realizes through following technical scheme:

一种基于PCI接口的AFDX终端测试设备，其特征在于，包括：PCI通讯模块，用于实现上位机与下述可编程芯片之间的数据交换；可编程芯片，实现AFDX协议栈特有的全部功能，用于将所述上位机下传的数据进行AFDX协议编码以给到被测的AFDX航空以太网标准设备，及将所述被测的AFDX航空以太网标准设备上传的数据进行校验、流量整形和冗余管理以给到所述上位机；AFDX终端测试设备接口模块，用于实现所述可编程芯片与所述被测的AFDX航空以太网标准设备之间的数据交换；电源模块，用于给整个测试设备供电。A kind of AFDX terminal testing equipment based on PCI interface, it is characterized in that, comprises: PCI communication module, is used for realizing the data exchange between upper computer and following programmable chip; Programmable chip, realizes all functions peculiar to AFDX protocol stack , for performing AFDX protocol encoding on the data downloaded from the host computer to the tested AFDX aviation Ethernet standard equipment, and performing verification and flow of the data uploaded by the tested AFDX aviation Ethernet standard equipment Shaping and redundancy management are given to the host computer; the AFDX terminal test equipment interface module is used to realize the data exchange between the programmable chip and the tested AFDX aviation Ethernet standard equipment; the power module is used for for powering the entire test setup.

作为具体的技术方案，所述PCI通讯模块包括相互连接的PCI接口和PCI桥接芯片，所述PCI桥接芯片与可编程芯片连接，所述PCI接口与所述上位机连接。As a specific technical solution, the PCI communication module includes a PCI interface and a PCI bridge chip connected to each other, the PCI bridge chip is connected to a programmable chip, and the PCI interface is connected to the host computer.

作为具体的技术方案，所述PCI通讯模块采用PCI9056接口芯片。As a specific technical solution, the PCI communication module adopts a PCI9056 interface chip.

作为具体的技术方案，所述可编程芯片内包括：处理器单元，用于控制所述可编程芯片内部各模块及芯片外部各部件工作；发送通道，用于设定逻辑来将经编码或并注入错误的数据发送给所述AFDX终端测试设备接口模块；接收通道，用于设定逻辑来接收所述AFDX终端测试设备接口模块的数据以待解码和校验；PCI接口模块，用于实现所述可编程芯片与PCI通讯模块之间的数据交换。As a specific technical solution, the programmable chip includes: a processor unit, used to control the work of each module inside the programmable chip and each component outside the chip; The wrong data is sent to the AFDX terminal test equipment interface module; the receiving channel is used to set the logic to receive the data of the AFDX terminal test equipment interface module to be decoded and checked; the PCI interface module is used to realize the described AFDX terminal test equipment interface module. Data exchange between the programmable chip and the PCI communication module.

作为具体的技术方案，所述发送通道包括依次连接的：流量整形模块，用于控制所述可编程芯片内部AFDX端口发出的消息流进行规范化，使其输出的数据流是规整的、没有时延抖动的、且满足下述的虚拟链路调度模块的BAG参数的消息流；虚拟链路调度模块，用于对来自不同的虚拟电路中的消息进行调度，决定发送消息的顺序，以满足实时性的要求；发送冗余管理模块，用于在发送消息时，将所发送的消息复制发送到2个独立的冗余网络中；所述接收通道包括依次连接的：完整性检查模块，用于将AFDX的MAC层接收端所接收到的数据进行完整性检查，即检查接收帧是否具有虚拟链路所期待的SN序列号；接收冗余管理模块，在接收消息时，将经过完整性检查后的消息进行相同检验，以滤除冗余消息。As a specific technical solution, the sending channel includes sequentially connected: a traffic shaping module, which is used to control the message flow sent by the AFDX port inside the programmable chip to be standardized, so that the output data flow is regular and has no time delay A message flow that is jittering and satisfies the following BAG parameters of the virtual link scheduling module; the virtual link scheduling module is used to schedule messages from different virtual circuits and determine the order of sending messages to meet real-time requirements Requirements; Sending redundancy management module, used to copy and send the sent message to two independent redundant networks when sending a message; The receiving channel includes sequentially connected: an integrity check module, used to send The data received by the receiving end of the MAC layer of AFDX performs an integrity check, that is, checks whether the received frame has the SN sequence number expected by the virtual link; the receiving redundancy management module, when receiving a message, will pass the integrity check Messages undergo the same check to filter out redundant messages.

作为具体的技术方案，所述可编程芯片型号为EP3C55F484I型FPGA。As a specific technical solution, the programmable chip model is EP3C55F484I FPGA.

作为具体的技术方案，所述AFDX终端测试设备接口模块为与所述可编程芯片连接的双冗余以太网PHY物理层接口。As a specific technical solution, the AFDX terminal test equipment interface module is a dual redundant Ethernet PHY physical layer interface connected to the programmable chip.

作为具体的技术方案，所述双冗余以太网PHY物理层接口包括2个相互独立的以太网PHY物理层接口。As a specific technical solution, the dual redundant Ethernet PHY physical layer interface includes two mutually independent Ethernet PHY physical layer interfaces.

作为具体的技术方案，所述AFDX终端测试设备接口模块采用88E1111接口芯片。As a specific technical solution, the AFDX terminal test equipment interface module adopts 88E1111 interface chip.

本实用新型提供的基于PCI接口的AFDX终端测试设备的有益效果在于：由于PCI接口支持热插拔，通过充分利用常规以太网数据传输带宽高和PCI总线传输速度快而且支持热插拔的特点，使得本实用新型能满足双冗余AFDX航空以太网的高速数据传输，实现了AFDX航空以太网标准设备的取样(sampling)、队列(queuing)和错误注入/检测等功能，能模拟与AFDX航空以太网标准设备之间进行错误测试和协议分析等功能；同时，本实用新型体积相对较小，方便携带和使用。The beneficial effects of the AFDX terminal test equipment based on the PCI interface provided by the utility model are: because the PCI interface supports hot plugging, by making full use of the characteristics of high data transmission bandwidth of the conventional Ethernet and fast transmission speed of the PCI bus and supporting hot plugging, The utility model can satisfy the high-speed data transmission of dual redundant AFDX aviation Ethernet, realize the functions of sampling (sampling), queue (queuing) and error injection/detection of AFDX aviation Ethernet standard equipment, and can simulate and AFDX aviation Ethernet Perform error testing and protocol analysis between network standard equipment; at the same time, the utility model is relatively small in size and convenient to carry and use.

附图说明Description of drawings

图1为本实用新型实施例提供的基于PCI接口的AFDX终端测试设备的结构框图。Fig. 1 is a structural block diagram of the AFDX terminal test equipment based on the PCI interface provided by the embodiment of the present invention.

图2为本实用新型实施例提供的基于PCI接口的AFDX终端测试设备的内部结构框图。Fig. 2 is a block diagram of the internal structure of the AFDX terminal test equipment based on the PCI interface provided by the embodiment of the present invention.

具体实施方式Detailed ways

如图1所示，本实施例提供的基于PCI接口的AFDX终端测试设备为测试板卡，包括PCI通讯模块、可编程芯片、AFDX终端测试设备接口模块及电源模块。其中可编程芯片与PCI通讯模块及AFDX终端测试设备接口模块连接，电源模块给整个测试设备供电。As shown in FIG. 1 , the PCI-based AFDX terminal test equipment provided in this embodiment is a test board, including a PCI communication module, a programmable chip, an AFDX terminal test equipment interface module, and a power supply module. The programmable chip is connected with the PCI communication module and the AFDX terminal test equipment interface module, and the power supply module supplies power to the entire test equipment.

如图2所示，PCI通讯模块连接于上位机与可编程芯片之间，用于实现上位机与可编程芯片之间的数据交换。PCI通讯模块包括相互连接的PCI接口和PCI桥接芯片，PCI接口与上位机(图中未示出)连接，PCI桥接芯片与可编程芯片的PCI接口模块连接。As shown in Figure 2, the PCI communication module is connected between the host computer and the programmable chip, and is used to realize data exchange between the host computer and the programmable chip. The PCI communication module includes a PCI interface and a PCI bridge chip connected to each other, the PCI interface is connected to a host computer (not shown in the figure), and the PCI bridge chip is connected to the PCI interface module of the programmable chip.

继续参看图2，可编程芯片包括处理器单元、发送通道、接收通道及PCI接口模块。处理器单元与发送通道、接收通道及PCI接口模块连接，用于控制可编程芯片内部各模块及芯片外部各部件工作。Continuing to refer to FIG. 2 , the programmable chip includes a processor unit, a sending channel, a receiving channel and a PCI interface module. The processor unit is connected with the sending channel, the receiving channel and the PCI interface module, and is used to control the work of each module inside the programmable chip and each component outside the chip.

发送通道，用于设定逻辑来将经编码或并注入错误的数据发送给所述AFDX终端测试设备接口模块。发送通道包括依次连接的发送缓存模块、流量整形模块、虚拟链路调度模块、发送冗余管理模块及MAC1。其中，流量整形模块，用于控制可编程芯片内部AFDX端口发出的消息流进行规范化，使其输出的数据流是规整的、没有时延抖动的、且满足下述的虚拟链路调度模块的BAG参数的消息流；虚拟链路调度模块，用于对来自不同的虚拟电路中的消息进行调度，决定发送消息的顺序，以满足实时性的要求；发送冗余管理模块，用于在发送消息时，将所发送的消息复制发送到2个独立的冗余网络中。The sending channel is used to set the logic to send the coded or error-injected data to the AFDX terminal test equipment interface module. The transmission channel includes a transmission buffer module, a traffic shaping module, a virtual link scheduling module, a transmission redundancy management module and MAC1 which are sequentially connected. Among them, the traffic shaping module is used to control the message flow sent by the AFDX port inside the programmable chip to standardize, so that the output data flow is regular, has no delay and jitter, and satisfies the BAG of the following virtual link scheduling module The message flow of parameters; the virtual link scheduling module is used to schedule messages from different virtual circuits, and determines the order of sending messages to meet the real-time requirements; the sending redundancy management module is used to send messages , to copy and send the sent message to 2 independent redundant networks.

接收通道，用于设定逻辑来接收所述AFDX终端测试设备接口模块的数据以待解码和校验。接收通道包括依次连接的MAC2、接收缓存模块、完整性检查模块及接收冗余管理模块。其中，完整性检查模块，用于将AFDX的MAC层接收端所接收到的数据进行完整性检查，即检查接收帧是否具有虚拟链路所期待的SN序列号；接收冗余管理模块，在接收消息时，将经过完整性检查后的消息进行相同检验，以滤除冗余消息。The receiving channel is used to set the logic to receive the data of the interface module of the AFDX terminal test equipment to be decoded and verified. The receiving channel includes MAC2 connected in sequence, a receiving buffer module, an integrity checking module and a receiving redundancy management module. Among them, the integrity check module is used to check the integrity of the data received by the receiving end of the MAC layer of AFDX, that is, to check whether the received frame has the SN serial number expected by the virtual link; When sending a message, the same check will be performed on the message after the integrity check to filter out redundant messages.

PCI接口模块，用于实现可编程芯片与PCI通讯模块之间的数据交换。The PCI interface module is used to realize the data exchange between the programmable chip and the PCI communication module.

继续参看图2，AFDX终端测试设备接口模块连接于可编程芯片与被测的AFDX航空以太网标准设备之间，用于实现可编程芯片与被测的AFDX航空以太网标准设备之间的数据交换。AFDX终端测试设备接口模块为双冗余以太网PHY物理层接口，包括2个相互独立的以太网PHY物理层接口，2个相互独立的以太网PHY物理层接口分别与可编程芯片的发送通道及接收通道连接，另一端分别通过RJ45接口与被测的AFDX航空以太网标准设备连接(图中未示出)。Continue to refer to Figure 2, the AFDX terminal test equipment interface module is connected between the programmable chip and the AFDX aviation Ethernet standard equipment under test, and is used to realize the data exchange between the programmable chip and the AFDX aviation Ethernet standard equipment under test . The AFDX terminal test equipment interface module is a dual-redundant Ethernet PHY physical layer interface, including 2 mutually independent Ethernet PHY physical layer interfaces, and the 2 mutually independent Ethernet PHY physical layer interfaces are respectively connected to the transmission channel of the programmable chip and the The receiving channel is connected, and the other end is respectively connected to the AFDX aviation Ethernet standard equipment (not shown in the figure) through the RJ45 interface.

电源模块，其输入为+12V/-12V/+5V/+3.3V直流，输出有+2.5V、-5V和1.2V。The power supply module, its input is +12V/-12V/+5V/+3.3V DC, and the output has +2.5V, -5V and 1.2V.

在本实施例中，PCI桥接芯片具体型号为PCI9056，通过该芯片可以使多种局部总线快速转换到PCI总线上。可编程芯片为FPGA芯片，型号为EP3C55F484I，可以实现AFDX协议栈和MAC链路层的所有功能。AFDX的双冗余物理层PHY芯片采用88E1111，能实现10M/100M以太网物理层的数据链路及传输。In this embodiment, the specific model of the PCI bridge chip is PCI9056, through which various local buses can be quickly converted to the PCI bus. The programmable chip is FPGA chip, the model is EP3C55F484I, which can realize all functions of AFDX protocol stack and MAC link layer. The dual redundant physical layer PHY chip of AFDX adopts 88E1111, which can realize the data link and transmission of 10M/100M Ethernet physical layer.

本实用新型实施例提供的基于PCI接口的AFDX终端测试设备的工作时，其PCI接口与PC机连接，其双冗余以太网PHY物理层接口的RJ45网线接口与被测的AFDX航空以太网标准设备连接，实现被测的AFDX航空以太网标准设备与运行检测软件的PC机之间的数据交换，其工作流程具体包括发送数据工作流程和接收数据工作流程。During the work of the AFDX terminal test equipment based on the PCI interface provided by the embodiment of the utility model, its PCI interface is connected with a PC, and the RJ45 network cable interface of its dual redundant Ethernet PHY physical layer interface is connected with the AFDX aviation Ethernet standard tested. The equipment connection realizes the data exchange between the tested AFDX aviation Ethernet standard equipment and the PC running the detection software, and its workflow specifically includes the workflow of sending data and the workflow of receiving data.

发送数据工作流程：Send data workflow:

首先在PC机上运行上层测试软件，通过它来设置发送通道的相应参数，该信息通过PCI接口传送至可编程芯片，可编程芯片内的处理器单元根据PC机下传的参数来设置发送通道的相关寄存器参数，同时该消息经过流量整形模块，进行规划化处理，使其输出的数据帧是规整的、没有时延抖动的。来自流量整形模块的数据帧由虚拟调度模块添加序列号(SN)后，发往发送冗余管理模块。冗余管理模块将需要发送消息复制发送到2个独立的冗余MAC链路层中。MAC模块对数据帧添加帧序列校验，发往AFDX终端测试设备接口模块。AFDX终端测试设备接口模块的以太网PHY物理层接口将可编程芯片内的MAC层的数据帧进行电平转换后传送至被测的AFDX航空以太网标准设备中。First, run the upper layer test software on the PC, and use it to set the corresponding parameters of the sending channel. The information is transmitted to the programmable chip through the PCI interface, and the processor unit in the programmable chip sets the sending channel according to the parameters downloaded from the PC. Relevant register parameters, and at the same time, the message is processed through the traffic shaping module, so that the output data frame is regular and has no delay jitter. The data frame from the traffic shaping module is sent to the sending redundancy management module after being added with a sequence number (SN) by the virtual scheduling module. The redundant management module copies the message to be sent to two independent redundant MAC link layers. The MAC module adds a frame sequence check to the data frame and sends it to the AFDX terminal test equipment interface module. The Ethernet PHY physical layer interface of the AFDX terminal test equipment interface module converts the data frame of the MAC layer in the programmable chip and then transmits it to the AFDX aviation Ethernet standard equipment under test.

接收数据工作流程：Receive data workflow:

首先在PC机上运行上层测试软件，通过它来设置接收通道的相应参数，该信息通过PCI接口传送至可编程芯片，处理器单元根据上位机下传的参数来设置接收通道的相应参数，完成接收通道的初始化操作。然后，AFDX终端测试设备接口模块检测到物理链路上有数据帧后，将数据帧取出，送至可编程芯片内MAC模块，MAC模块对数据帧进行CRC校验。之后送至接收模块。接收模块将MAC模块传来的数据存入自身缓存中，直至数据帧接收完毕后，对数据帧进行完整检查和冗余管理，完整性检查时检查接收帧是否具有虚拟链路所期待的SN序列号，冗余管理用于将经过完整性检查后的消息进行相同检验，以滤除冗余消息。可编程芯片内的处理器单元控制将接收到的正确的消息通过PCI接口上传至上位机，上位机测试软件将对这些消息进行数据验证与分析。First, run the upper-layer test software on the PC, and use it to set the corresponding parameters of the receiving channel. The information is transmitted to the programmable chip through the PCI interface, and the processor unit sets the corresponding parameters of the receiving channel according to the parameters downloaded from the upper computer to complete the receiving process. Channel initialization operation. Then, after the AFDX terminal test equipment interface module detects the data frame on the physical link, it takes out the data frame and sends it to the MAC module in the programmable chip, and the MAC module performs CRC check on the data frame. Then sent to the receiving module. The receiving module stores the data transmitted by the MAC module in its own cache until the data frame is received, and performs a complete check and redundancy management on the data frame. During the integrity check, check whether the received frame has the SN sequence expected by the virtual link number, and redundancy management is used to perform the same check on the message after the integrity check to filter out redundant messages. The processor unit in the programmable chip controls and uploads the received correct messages to the host computer through the PCI interface, and the host computer test software will perform data verification and analysis on these messages.

本实用新型不局限于上述实施例，基于上述实施例的、未做出创造性劳动的简单替换，应当属于本实用新型揭露的范围。The utility model is not limited to the above-mentioned embodiments, and simple replacements based on the above-mentioned embodiments without creative efforts shall belong to the disclosed scope of the utility model.