CN213069787U - Read-write control system of memory card - Google Patents

Referring to FIG. 1, a block diagram of a read/write control system according to a first embodiment of the present invention is shown. The read/write control system is used for a

host system

103 to read/write data of a

memory card

100. The read/write control system includes a

memory card interface

101, a

host system interface

102, and a

control device

106.

As shown in fig. 1, the

memory card interface

101 is used to connect to the

memory card

100. The

host system interface

102 is electrically connected to the

memory card interface

101, and the

host system

103 is connected to the

host system interface

102. The

control device

106 includes a

bridge device

109 and a

selector

114, the

bridge device

109 is electrically connected to the

host system interface

102 and the

memory card interface

101, and the

selector

114 is electrically connected to the

host system interface

102, the

memory card interface

101 and the

bridge device

109. When the

memory card

100 operates according to the first communication protocol, the

memory card interface

101 is electrically connected to the

host system interface

101 through the

selector

114 and the

bridge device

109. When the

memory card

100 operates according to the second communication protocol, the

memory card interface

101 is electrically connected to the

host system interface

101 through the

selector

114, and the

memory card interface

101 is also electrically connected to the

host system interface

102 through the

bridge device

109.

As shown in fig. 1, in an embodiment, the

host system

103 detects that the

memory card interface

101 is electrically connected to the

host system interface

102 via the

control device

106, and defaults to connect to the

memory card

100 with the first communication protocol, so as to initialize or start (initiate process) the

memory card

100 with the first communication protocol. The initialization is, for example, the

host system interface

102 provides the

memory card

100 with the power required for operation, the

host system interface

102 transmits the operation and access commands to the

memory card

100, and the

memory card interface

101 establishes the bidirectional communication between the

host system interface

102 and the

memory card

100.

As shown in fig. 1, in an embodiment, the

bridge device

109 includes a

first interface

110 and a

second interface

112. The

first interface

110 is electrically connected to the

memory card interface

101 and the

host system interface

102, and the

second interface

112 is electrically connected to the

memory card interface

101 and the

selector

114. In one embodiment, the

first interface

110 is, for example, a control interface or a controller. The

second interface

112 is, for example, a control interface or a controller.

As shown in fig. 1, in one embodiment, when the

memory card

100 operates in the first communication protocol, when the first communication protocol of the

memory card

100 is Secure Digital (SD) mode, the

memory card interface

101 is electrically connected to the

host system interface

102 via the

selector

114, the

second interface

112 and the

first interface

110, wherein the transmission path among the

memory card interface

101, the

second interface

112, the

first interface

110 and the

host system interface

102 is defined as a first transmission path P1, the transmission path among the

memory card interface

101, the

selector

114, the

second interface

112, the

first interface

110, and the

host system interface

102 is defined as a second transmission path P2, such that the

host system

103 communicates with the

memory card interface

101 through the first transmission path P1 and reads and writes the data of the

memory card

100 through the second transmission path P2 with the first communication protocol. In one embodiment, the

host system

103 detects that the

memory card interface

101 is electrically connected to the

host system interface

102 through the

host system interface

102 via the first transmission path P1. The

host system

103 initializes the

memory card

100 with the first communication protocol via the

host system interface

102 via the first transmission path P1. In a preferred embodiment, during the process of detecting the connection of the

memory card

100, the

host system

103 initializes or boots the

memory card

100 according to the first communication protocol, for example, through the

host system interface

102 and the

first interface

110, the non-volatile memory express (NVMe)

controller

200 and the

second interface

112 of the

bridge device

109.

As shown in fig. 1, in one embodiment, when the

memory card

100 operates in the second communication protocol, for example, when the second communication protocol of the

memory card

100 is a secure digital (SD Express) mode, the

memory card interface

101 is electrically connected to the

host system interface

102 via the

selector

114, the

memory card interface

102 is electrically connected to the

host system interface

102 via the

first interface

110 of the

bridge device

109, wherein the transmission path among the

memory card interface

101, the

selector

114 and the

host system interface

102 is defined as a third transmission path P3, the transmission path among the

memory card interface

101, the

first interface

110 and the

host system interface

102 is defined as a fourth transmission path P4, such that the

host system

103 communicates with the

memory card interface

101 through the third transmission path P3 and reads and writes the data of the

memory card

100 through the fourth transmission path P4 according to the second communication protocol. After determining that the

memory card

100 supports the second communication protocol, the embodiment, for example, initializes or starts (initiates) the

memory card

100 according to the second communication protocol, so as to perform subsequent communication or read/write operations.

As shown in FIG. 1, in an embodiment, the

memory card interface

101 conforms to, for example, a secure digital memory card (secure digital memory card) protocol, such as, but not limited to, protocol versions SD-UHS I, SD-UHS II, SD-UHS III, and SD 7.0. In one embodiment, the first communication protocol of the

memory card

100 is defined as a Secure Digital (SD) mode, such as SD-UHS I, SD-UHS II, SD-UHS III protocol versions. The second communication protocol of the

memory card

100 is defined as secure digital (SD Express) mode. The secure digital mode is a previous protocol version of a secure digital mode, and the secure digital mode is a Secure Digital (SD)7.0 protocol version, such as a version supporting the Secure Digital (SD)7.0 protocol version or a later updated protocol version. The data transmission rate of the first communication protocol of the

memory card

100 is smaller than the data transmission rate of the second communication protocol. The

host system interface

102 is, for example, a peripheral component interconnect express (PCIe) root complex (PCIe) component, which is used to connect a processor and a memory to a PCIe switch fabric composed of one or more switch devices, and may be disposed in a notebook computer, a mobile phone, a tablet computer, or other electronic devices with a processor and a memory connected thereto. The

control device

106 is, for example, but not limited to, a control chip or a control circuit of the card reader.

As shown in fig. 1, in one embodiment, the

host system interface

102 includes a

first sub-interface

102a and a

second sub-interface

102 b. For example, the

first sub-interface

102a includes a PCI Express Reset (PERST #) signal, a clock request run signal (CLKREQ #), and a reference clock differential pair signal (REFCLK, REFCLK +, REFCLK-), wherein the PERST #) signal is used for managing the Reset operation of the

second sub-interface

102 b; a frequency request operation signal (clock request, CLKREQ #) for requesting a reference frequency operation; the reference frequency differential pair signal (reference clock, REFCLK +, REFCLK-) is used to provide the reference frequency. The

first sub-interface

102a is electrically connected to the

first interface

110 of the

bridge device

109 and the

selector

114 for transmitting the 4 signals, including the PERST #, CLKREQ #, REFCLK +, REFCLK-4 signals. The

second sub-interface

102b is used for performing data transmission/reception (TX/RX) between the

host system interface

102 and the

memory card interface

101. The

second sub-interface

102b supports the pci 1.0, pci 2.0 and pci 3.0 protocol versions. For example, the transmission bandwidth of PCIe1.0 is 2.5GHz, the transmission bandwidth of PCIe2.0 is 5.0GHz, and the transmission bandwidth of PCIe3.0 is 8.0 GHz. In one embodiment, the

memory card interface

101 is electrically connected to the

second sub-interface

102b of the

host system interface

102 through the

bridge device

109, and the

memory card interface

101 is also electrically connected to the

first sub-interface

102a of the

host system interface

102 through the

selector

114.

As shown in fig. 1, in one embodiment, when the

memory card

100 operates in the second communication protocol, the

second interface

112 triggers the

selector

114 with a trigger signal TS, so that the

memory card interface

101 is electrically connected to the

first sub-interface

102a of the

host system interface

102 through the

selector

114, and the

memory card interface

101 is electrically connected to the

second sub-interface

102b of the

host system interface

102 through the

first interface

110.

As shown in fig. 1, in one embodiment, the

host system

103 communicates with the

memory card

100 through the

host system interface

102, the

bridge device

109 and the

selector

114 to determine whether the

memory card

100 supports protocol versions of the

host system

103, including the protocol versions pcie1.0, pcie2.0 and pcie 3.0. When the

host system

103 confirms through the

host system interface

102 that the first communication protocol of the

memory card

100 supports the pci 1.0 protocol version or the pci 2.0 protocol version of the

host system

103, the

host system

103 reads and writes the data of the

memory card

100 through the

host system interface

102, the

first interface

110, the

second interface

112 and the

selector

114, and when the

host system

103 confirms through the

host system interface

102 that the second communication protocol of the

memory card

100 supports the pci 3.0 protocol version of the

host system

103, the

host system

103 reads and writes the data of the

memory card

100 through the

host system interface

102 and the

first interface

110 of the

bridge device

109.

As shown in fig. 1, in an embodiment, the

second interface

112 of the

bridge device

109 includes a control interface 112a and a

transceiver interface

112b, the control interface 112a is connected to the

memory card interface

101, the

transceiver interface

112b is connected to the

selector

114, and the

second interface

112 is used for the operations of the control interface 112a and the

transceiver interface

112 b. The control interface 112a includes signals such as secure digital command (SD CMD) and secure digital clock (SD CLK) for establishing a communication link between the

second interface

112 and the

memory card interface

101. The

transceiving interface

112b includes secure digital data (SD DAT), such as SD DAT 0-3, which includes 4 bits for transceiving data between the

second interface

112 and the

memory card interface

101. The control interface 112a and the

transceiving interface

112b of the

second interface

112 are respectively used for converting the communication and data transmission formats between the

first sub-interface

102a and the

second sub-interface

102b of the

host system interface

102 and the first communication protocol. In one embodiment, the

selector

114 is a multiplexer, but is not limited to this, such as a selector composed of circuit elements or logic elements. In one embodiment, the

second interface

112 is, for example, a SD-UHS I host controller. In one embodiment, the

first interface

110 is used for switching between a first communication protocol and a second communication protocol, or the

first interface

110 receives commands through the

first sub-interface

102a and the

second sub-interface

102b of the

host system interface

102 to switch between the first communication protocol and the second communication protocol.

As shown in fig. 1, in an embodiment, the

bridge device

109 further includes an

NVMe controller

200 electrically connected to the

second sub-interface

102b of the

host system interface

102 through the

first interface

110, when the

memory card

100 does not support the operation of the second communication protocol, a non-volatile memory express (NVMe) protocol driver of the

host system

103 accesses data of the

memory card

100 through the

host system interface

102, the

first interface

110, the

NVMe controller

200, the

second interface

112 and the

selector

114 by using the

NVMe controller

200, and when the

memory card

100 supports the operation of the second communication protocol, the non-volatile memory express (NVMe) protocol driver of the

host system

103 accesses data of the

memory card

100 through the

host system interface

102 and the

first interface

110.

According to the above, the read/write control system of the present invention, by means of the

bridge device

109 and the

selector

114 of the

control device

106, the

host system

103 can support different communication protocols to read/write the data of the

memory card

100 only by using a non-volatile memory express (NVMe) protocol driver, thereby solving the problem of compatibility between the

memory card

100 and the read/write control system, improving the flexibility of the

memory card

100, and reducing the production cost of the read/write control system.

1. A read-write control system for a host system to read and write data of a memory card, the read-write control system comprising:

a memory card interface for connecting the memory card;

a host system interface electrically connected to the memory card interface and connected to the host system; and

a control device electrically connected to the memory card interface and the host system interface, comprising:

a bridge device electrically connected to the host system interface and the memory card interface; and

a selector electrically connected to the host system interface, the memory card interface and the bridge device;

when the memory card operates with a first communication protocol, the memory card interface is electrically connected with the host system interface through the selector and the bridge device;

when the memory card operates with a second communication protocol, the memory card interface is electrically connected with the host system interface through the selector, and the memory card interface is also electrically connected with the host system interface through the bridge device.

2. The read-write control system of claim 1, wherein the control device detects that the memory card is electrically connected to the memory card interface and defaults to connecting with the memory card with the first communication protocol, so as to activate the memory card with the first communication protocol.

3. The read-write control system of claim 1, wherein the bridge device comprises:

a first interface electrically connected to the memory card interface and the host system interface; and

a second interface electrically connected to the memory card interface and the selector;

when the memory card operates with the first communication protocol, the memory card interface is electrically connected with the host system interface through the selector, the second interface and the first interface, wherein a transmission path among the memory card interface, the second interface, the first interface and the host system interface is defined as a first transmission path, and a transmission path among the memory card interface, the selector, the second interface, the first interface and the host system interface is defined as a second transmission path, so that the host system communicates with the memory card interface through the first transmission path and reads and writes the data of the memory card through the second transmission path by the first communication protocol;

when the memory card operates with the second communication protocol, the memory card interface is electrically connected with the host system interface through the selector, and the memory card interface is electrically connected with the host system interface through the first interface of the bridge device, wherein a transmission path among the memory card interface, the selector and the host system interface is defined as a third transmission path, and a transmission path among the memory card interface, the first interface and the host system interface is defined as a fourth transmission path, so that the host system communicates with the memory card interface through the third transmission path and reads and writes the data of the memory card through the fourth transmission path with the second communication protocol.

4. The read-write control system of claim 3, wherein the host system interface includes a first sub-interface and a second sub-interface, the memory card interface is electrically connected to the second sub-interface of the host system interface through the bridge device, and the memory card interface is also electrically connected to the first sub-interface of the host system interface through the selector.

5. The read-write control system of claim 4, wherein the second interface triggers the selector with a trigger signal when the memory card operates according to the second communication protocol, so that the memory card interface is electrically connected to the first sub-interface of the host system interface through the selector, and the memory card interface is electrically connected to the second sub-interface of the host system interface through the first interface.

6. The write/read control system of claim 4, wherein the host system communicates with the memory card through the host system interface, the bridge device and the selector to determine whether the memory card supports protocol versions of the host system, the protocol versions including PCIe1.0, PCIe2.0 and PCIe3.0.

7. The read-write control system of claim 6, wherein when the host system determines via the host system interface that the first communication protocol of the memory card supports the pci e1.0 protocol version or the pci e2.0 protocol version of the host system, the host system reads and writes the data of the memory card via the host system interface, the first interface, the second interface and the selector, and when the host system determines via the host system interface that the second communication protocol of the memory card supports the pci e3.0 protocol version of the host system, the host system reads and writes the data of the memory card via the host system interface and the first interface of the bridge device.

8. The read-write control system of claim 4, wherein the bridge device further includes an NVMe controller electrically connected to the second sub-interface of the host system interface via the first interface, when the memory card does not support the operation of the second communication protocol, a non-volatile memory express (NVMe) protocol driver of the host system accesses data of the memory card via the host system interface, the first interface, the NVMe controller, the second interface and the selector, and when the memory card supports the operation of the second communication protocol, the non-volatile memory express (NVMe) protocol driver of the host system accesses data of the memory card via the host system interface and the first interface.

9. The read-write control system of claim 8, wherein the second interface is electrically connected to the first interface via the NVMe controller.

10. The read/write control system of claim 1, wherein the first communication protocol of the memory card is defined as Secure Digital (SD) mode, and the second communication protocol of the memory card is defined as secure digital Express (SD) mode.

11. The read-write control system of claim 1, wherein the data transmission rate of the first communication protocol of the memory card is smaller than the data transmission rate of the second communication protocol.