CN214069897U - GaN transistor driver modules, switching circuits and electronic equipment - Google Patents

本实用新型提供了一种GaN晶体管的驱动模块、开关电路与电子设备，包括：第一下拉晶体管与反向过冲抑制单元，所述第一下拉晶体管的第一端直接或间接连接至所述GaN晶体管的栅极，所述反向过冲抑制单元连接于所述第一下拉晶体管的第二端与地之间，所述反向过冲抑制单元还直接或间接连接至所述GaN晶体管的栅极；所述GaN晶体管连接于第一电压源与地之间；所述反向过冲抑制单元用于：在所述GaN晶体管的栅极电压下降时，若所述栅极电压高于指定阈值时，以第一阻抗控制所述GaN晶体管栅极电荷的释放；若所述栅极电压低于所述指定阈值时，以第二阻抗控制所述GaN晶体管栅极电荷的释放；所述第一阻抗小于所述第二阻抗。

The utility model provides a driving module, a switch circuit and an electronic device of a GaN transistor, comprising: a first pull-down transistor and a reverse overshoot suppression unit, wherein the first end of the first pull-down transistor is directly or indirectly connected to The gate of the GaN transistor, the reverse overshoot suppression unit is connected between the second end of the first pull-down transistor and the ground, and the reverse overshoot suppression unit is also directly or indirectly connected to the the gate of the GaN transistor; the GaN transistor is connected between the first voltage source and the ground; the reverse overshoot suppression unit is used for: when the gate voltage of the GaN transistor drops, if the gate voltage When the voltage is higher than the specified threshold, the release of the gate charge of the GaN transistor is controlled by a first impedance; if the gate voltage is lower than the specified threshold, the release of the gate charge of the GaN transistor is controlled by a second impedance; The first impedance is smaller than the second impedance.

Drive module, switching circuit and electronic equipment of GaN transistor

Technical Field

The utility model relates to a drive field of gaN transistor especially relates to a drive module, switch circuit and electronic equipment of gaN transistor.

Background

The GaN transistor may be a transistor formed on the basis of GaN material, such as an NMOS transistor formed on the basis of GaN material, which can be turned on and off by the driving module.

In the related art, the gate of the GaN transistor may be grounded through the pull-down transistor, and when the pull-down transistor is driven to be turned on, the gate of the GaN transistor may be pulled down, thereby performing a turn-off operation of the GaN transistor.

However, GaN has a very high switching speed, so the rate of change of the gate current is slow (it can be understood that di/dt is large), and a large reverse overshoot voltage is generated under the influence of the gate parasitic inductance (mainly the parasitic inductance caused by the PCB and the package), and the reverse overshoot voltage obviously affects the stability of the GaN transistor.

SUMMERY OF THE UTILITY MODEL

The utility model provides a drive module, switch circuit and electronic equipment of gaN transistor to solve the problem that reverse voltage of overshooting influences gaN transistor stability.

According to a first aspect of the present invention, there is provided a driving module of a GaN transistor, comprising: a first pull-down transistor and an overshoot suppression unit, a first end of the first pull-down transistor is directly or indirectly connected to the gate of the GaN transistor, the overshoot suppression unit is connected between a second end of the first pull-down transistor and ground, and the overshoot suppression unit is also directly or indirectly connected to the gate of the GaN transistor; the GaN transistor is connected between a first voltage source and the ground;

the inverse overshoot suppression unit is configured to:

when the grid voltage of the GaN transistor is reduced and if the grid voltage is higher than a specified threshold value, controlling the discharge of the grid charge of the GaN transistor by using first impedance; if the grid voltage is lower than the designated threshold value, controlling the discharge of the GaN transistor grid charge by second impedance; the first impedance is less than the second impedance.

Optionally, the reverse overshoot suppression unit includes a second pull-down transistor and a pull-down resistor;

the first end of the pull-down resistor is connected with the second end of the first pull-down transistor, the second end of the pull-down resistor is connected to the ground, the first end of the second pull-down transistor is connected with the second end of the first pull-down transistor, the second end of the second pull-down transistor is connected to the ground, and the grid electrode of the second pull-down transistor is connected to the grid electrode of the GaN transistor.

Optionally, the first pull-down transistor and the second pull-down transistor are both NMOS transistors, the first end of the first pull-down transistor is a drain of the first pull-down transistor, and the second end of the first pull-down transistor is a source of the first pull-down transistor; the first end of the second pull-down transistor is a drain electrode of the second pull-down transistor, and the second end of the second pull-down transistor is a source electrode of the second pull-down transistor.

Optionally, the specified threshold is matched to zero volts.

Optionally, the driving module further includes: a driving unit and a pull-up transistor;

the input side of the driving unit is used for accessing a control signal of the GaN transistor, the first end of the pull-up transistor is used for accessing a second voltage source, the second end of the pull-up transistor is directly or indirectly connected with the grid electrode of the GaN transistor, and the grid electrode of the pull-up transistor and the grid electrode of the first pull-down transistor are both connected to the output side of the driving unit;

and the driving unit is used for selecting and controlling the pull-up transistor and the first pull-down transistor to be opened according to the control signal.

Optionally, the driving unit includes a logic driver, and an input side of the logic driver is used for directly or indirectly accessing the control signal; the output side of the logic driver is connected with the grid electrode of the pull-up transistor and the grid electrode of the first pull-down transistor:

the logical driver is to:

when the control signal is a first control signal, controlling the pull-up transistor to be turned on, and controlling the first pull-down transistor to be turned off;

and when the control signal is a second control signal, controlling the pull-up transistor to be turned off, and controlling the first pull-down transistor to be turned on.

Optionally, the driving unit further includes a noise reduction unit, an input side of the noise reduction unit is configured to access the control signal, an output side of the noise reduction unit is connected to an input side of the logic driver, and the noise reduction unit is configured to reduce the noise of the control signal and input the reduced noise to the logic driver.

Optionally, the control signal includes a forward input signal and a reverse input signal;

the noise reduction part comprises a first Schmitt trigger and a second Schmitt trigger;

the input end of the first Schmitt trigger is used for accessing the forward input signal, the input end of the second Schmitt trigger is used for accessing the reverse input signal, and the output end of the first Schmitt trigger and the output end of the second Schmitt trigger are both connected with the input side of the logic driver.

Optionally, the pull-up transistor is a PMOS transistor, the first end of the pull-up transistor is a source electrode of the pull-up transistor, and the second end of the pull-up transistor is a drain electrode of the pull-up transistor.

Optionally, the driving module is disposed on the same chip.

According to a second aspect of the present invention, there is provided a switching circuit comprising the driving module according to the first aspect and its alternatives, and the GaN transistor.

According to a third aspect of the present invention, there is provided an electronic device including the switching circuit according to the second aspect and the alternatives thereof.

The utility model provides an among drive module, switch circuit and the electronic equipment of gaN transistor, in the in-process that utilizes drive module drive gaN transistor to turn off, the utility model discloses can realize the grid charge release under two kinds of different impedances, wherein, when the grid voltage of gaN transistor descends, if when the grid voltage is higher than appointed threshold value, with the release of first impedance control gaN transistor grid charge; if the grid voltage is lower than the specified threshold value, controlling the discharge of the GaN transistor grid charge by a second impedance higher than the first impedance; furthermore, the larger second impedance can slow down the current change rate, so that di/dt is reduced, the reverse overshoot voltage is avoided or relieved, and the stability of the GaN transistor is guaranteed.

Meanwhile, in the process, the release of the GaN transistor gate charge is controlled by the second impedance only when the GaN transistor gate voltage is low, namely, the falling speed is reduced only when the GaN transistor gate voltage is reduced to be close to a specified threshold (for example, 0V), further, the falling speed of the GaN transistor gate voltage which is just started is not influenced, the reverse overshoot is restrained, the falling speed is not reduced obviously, the suppression of the reverse overshoot is effectively considered, and the change rate of the gate current is effectively considered.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without inventive exercise.

Fig. 1 is a first schematic structural diagram of a GaN transistor and a driving module thereof according to an embodiment of the present invention;

fig. 2 is a schematic structural diagram of a GaN transistor and a driving module thereof according to an embodiment of the present invention;

fig. 3 is a third schematic structural diagram of a GaN transistor and a driving module thereof according to an embodiment of the present invention;

fig. 4 is a fourth schematic structural diagram of a GaN transistor and a driving module thereof according to an embodiment of the present invention;

fig. 5 is a circuit diagram of a GaN transistor and a driving module thereof according to an embodiment of the present invention.

Description of reference numerals:

1-a drive module;

11-a first pull-down transistor;

12-an inverse overshoot suppression unit;

121-a second pull-down transistor;

13-a pull-up transistor;

14-a drive unit;

141-a logic driver;

142-a noise reduction section;

1421 — first schmitt trigger;

1422 — second schmitt trigger;

3-chip;

NMOS1 — first pull-down transistor;

NMOS2 — second pull-down transistor;

NMOS_GaN-a GaN transistor;

PMOS-pull-up transistors;

r1 — pull-down resistor;

r2-pull-up connecting resistor;

R3-Pull-down connection resistance.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.

The terms "first," "second," "third," "fourth," and the like in the description and in the claims, as well as in the drawings, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

The technical solution of the present invention will be described in detail with specific examples. The following several specific embodiments may be combined with each other, and details of the same or similar concepts or processes may not be repeated in some embodiments.

The first impedance and the second impedance can be understood as any impedance value or impedance range value which enables the current change rate to change, and the second impedance is larger than the first impedance, so that when the second impedance is adopted to release charges, the current is decreased faster, and when the first impedance is adopted to release charges, the current is decreased slower. Simultaneously, the mode that changes impedance wantonly can all regard as the utility model discloses an implementation mode of embodiment, can realize through the change of access resistance with not access resistance for example, also can realize through the mode of inserting different resistances, quantity resistance, still can realize through the mode of inserting different transistors (for example the transistor of different size, model, quantity).

In the above scheme, at the in-process that utilizes drive module drive GaN transistor to turn off, the utility model discloses can realize the grid charge release under two kinds of different impedances, wherein, great second impedance can slow down the current change rate for di/dt diminishes, avoids or has alleviateed reverse overshoot voltage, ensures the stability of GaN transistor.

Meanwhile, in the process, the release of the GaN transistor gate charge is controlled by the second impedance only when the GaN transistor gate voltage is low, namely, the falling speed is reduced only when the GaN transistor gate voltage is reduced to be close to a specified threshold (for example, 0V), further, the falling speed of the GaN transistor gate voltage which is just started is not influenced, the reverse overshoot is restrained, the falling speed is not reduced obviously, the suppression of the reverse overshoot is effectively considered, and the change rate of the gate current is effectively considered.

Furthermore, the inventive contribution of the embodiments of the present invention is not only reflected in the switching of the first impedance and the second impedance, but also reflected in: the negative effects of the parasitic inductance of the GaN transistor and its reverse overshoot voltage were creatively discovered. Any solution that is not searched for based on the influence cannot be suggested to obtain the solution of the embodiment of the present invention.

In a specific example, the specified threshold may be matched to a voltage of zero volts, for example, the specified threshold may be zero volts, or may be a voltage close to zero volts.

When GaN transistor NMOS_GaNWhen the GaN transistor NMOS is turned off from the on state to the off state (i.e. when the GaN transistor NMOS is turned off by pulling down)_GaNMay drop from a high level to 0V.

When GaN transistor NMOS_GaNWhen the gate voltage has not dropped to 0V, the second pull-down transistor NMOS2 remains on, and the GaN transistor NMOS remains on_GaNThe gate charge is discharged through the first pull-down transistor NMOS1 and the second pull-down transistor NMOS2, and the pull-down resistor R1 is very small and does not affect the falling speed.

When GaN transistor NMOS_GaNWhen the gate voltage of the second pull-down transistor NMOS2 drops to 0V, the second pull-down transistor NMOS2 is turned off, and the GaN transistor NMOS_GaNThe grid charge is released through the pull-down resistor R1, and the lower resistor R1 can slow down the change of di/dt, so that the suppression of the reverse overshoot is realized.

In this scheme, the initial falling speed of the GaN gate voltage is not affected, and only in the GaN transistor NMOS_GaNStarts to slow down the falling speed when the grid voltage falls to the vicinity of 0, thereby not only inhibiting the reverse overshoot, but also not obviously reducing the falling speed.

And the driving unit is used for selecting and controlling the pull-up transistor and the first pull-down transistor to be opened according to the control signal.

when the control signal is a first control signal, controlling the pull-up transistor to be turned on, and controlling the first pull-down transistor to be turned off;

and when the control signal is a second control signal, controlling the pull-up transistor to be turned off, and controlling the first pull-down transistor to be turned on.

The control signal may be, for example, associated with a PWM signal, when the PWM signal is high, the control signal is a first control signal, when the PWM signal is low, the control signal is a second control signal, or: when the PWM signal is high, the control signal is the second control signal, and when the PWM signal is low, the control signal is the first control signal.

The logic driver can adopt the required logic gate to realize the processes based on the types of the transistors, the first control signal and the second control signal, and further can be realized by a hardware mode of selecting and combining devices. In one example, the logic driver may be an and gate, for example.

In addition, if the factors to be considered in driving are changed, the logic driver may also integrate more complex logic gates, or may be implemented by using a plurality of logic gates (such as and gates, not gates, nand gates, nor gates, or a combination of at least two of the above logic gates).

In one embodiment, the control signal comprises a forward input signal and a reverse input signal; in one example, the forward input signal and/or the reverse input signal may form a PWM signal, and if the PWM signal is formed by only the forward input signal, then: the inverting input may be, for example, an enable signal or other signal associated with the enable signal.

The noise reduction unit (for example, schmitt trigger) described above can reduce the influence of the input noise on the system. In other alternatives, other circuit configurations besides schmitt triggers may be used to achieve noise reduction (e.g., capacitors, inductors, etc. may be used to achieve noise reduction).

the reverse overshoot suppression unit 12 (e.g., the gate of the second pull-down transistor NMOS2 therein) may be connected to the GaN transistor NMOS through the VFB pin of the chip 3_GaNA gate electrode of (1);

The embodiment of the utility model provides an electronic equipment is still provided, including above related switch circuit, and then, this electronic equipment can be for the arbitrary equipment that needs to use the GaN transistor, and the effect of this GaN transistor in equipment can dispose wantonly according to the demand, and no matter how to dispose, all do not break away from the utility model discloses the scope of embodiment.

To sum up, in the driving module, the switching circuit and the electronic device of the GaN transistor provided by the embodiments of the present invention, in the process of using the driving module to drive the GaN transistor to turn off, the present invention can realize the gate charge release under two different impedances, wherein, when the gate voltage of the GaN transistor decreases, if the gate voltage is higher than a specified threshold, the release of the gate charge of the GaN transistor is controlled by the first impedance; if the grid voltage is lower than the specified threshold value, controlling the discharge of the GaN transistor grid charge by a second impedance higher than the first impedance; furthermore, the larger second impedance can slow down the current change rate, so that di/dt is reduced, the reverse overshoot voltage is avoided or relieved, and the stability of the GaN transistor is guaranteed.

Meanwhile, in the process, the release of the GaN transistor gate charge is controlled by the second impedance only when the GaN transistor gate voltage is low, namely, the falling speed is reduced only when the GaN transistor gate voltage is reduced to be close to a specified threshold (for example, 0V), further, the falling speed of the GaN transistor gate voltage which is just started is not influenced, the reverse overshoot is restrained, the falling speed is not reduced obviously, the suppression of the reverse overshoot is effectively considered, and the change rate of the gate current is effectively considered.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the present invention.