CN222262495U - A power supply control system for laser radar - Google Patents

The utility model discloses a power supply control system of a laser radar, wherein a first output end of a conversion module in the power supply control system is respectively and electrically connected with a power supply end of a first awakening module and an input end of a power switch module, an output end of the power switch module is electrically connected with a power supply end of a system power supply, and a second output end of the conversion module is electrically connected with a power supply end of a second awakening module. The output end of the first awakening module is electrically connected with the first control end of the power switch module, and the output end of the second awakening module is electrically connected with the second control end of the power switch module. The power switch module is used for supplying power to the system power supply module when at least one of the first awakening module or the second awakening module outputs a first level signal, so that the first awakening module, the second awakening module and the system power supply module are all powered through the total power supply module, a plurality of independent power supplies are not required to be arranged, the cost is further reduced, the power consumption is reduced, and the low-power-consumption operation of the laser radar is realized.

Power supply control system of laser radar

Technical Field

The utility model relates to the technical field of laser radars, in particular to a power supply control system of a laser radar.

Background

The laser radar, also called optical radar (LIght Detection AND RANGING), is a short term of laser detection and ranging system, and analyzes information such as the reflected energy, the amplitude, the frequency and the phase of the reflection spectrum and the like on the surface of a target object by measuring the propagation distance between a sensor emitter and the target object, and outputs point cloud, so that accurate three-dimensional structure information of the target object is presented. The laser radar generally comprises PHY (Physical Layer) chip circuits and CAN (Controller Area Network) chip circuits, wherein the PHY chip circuits are mainly responsible for transmitting point cloud data, and the CAN chip circuits are mainly responsible for transmitting state chips of the laser radar. When the laser radar is in the working mode, the power consumption is relatively large. If the laser radar is not required to work, the laser radar is still in a working mode, a large amount of electricity is consumed, and therefore, the laser radar is required to be in a sleep state when the laser radar is not required to work.

The existing laser radar sleep wake-up circuit generally adopts an independent power supply mode, namely adopts a plurality of different power supply modules to respectively supply power to different wake-up modules and systems. The multiple power supplies occupy a larger space and are costly.

Disclosure of utility model

The utility model provides a power supply control system of a laser radar, which is characterized in that a main power supply module and a conversion module are used for respectively supplying power to a first awakening module, a second awakening module and a system power supply module, so that a plurality of independent power supplies are not required to be arranged, the cost is reduced, the power consumption is reduced, and the low-power-consumption operation of the laser radar is realized.

In a first aspect, an embodiment of the present utility model provides a power supply control system for a laser radar, where the power supply control system includes a main power module, a conversion module, a first wake-up module, a second wake-up module, a power switch module, and a system power supply module;

The output end of the main power supply module is electrically connected with the input end of the conversion module, the first output end of the conversion module is electrically connected with the power supply end of the first wake-up module and the input end of the power switch module respectively, and the second output end of the conversion module is electrically connected with the power supply end of the second wake-up module;

The output end of the first wake-up module is electrically connected with the first control end of the power switch module, and the output end of the second wake-up module is electrically connected with the second control end of the power switch module;

The output end of the power switch module is electrically connected with the power supply end of the system power supply module, and the power switch module is used for being conducted when at least one of the first awakening module or the second awakening module outputs a first level signal so as to provide power for the system power supply module, wherein the first level signal is larger than a preset level signal.

Optionally, the conversion module includes a first conversion circuit and a second conversion circuit;

The input end of the first conversion circuit is electrically connected with the output end of the main power supply module, the output end of the first conversion circuit is electrically connected with the power supply end of the first wake-up module and the input end of the power switch module respectively, and the first conversion circuit is used for converting the main power supply output by the main power supply module into a first power supply so as to provide the first power supply for the first wake-up module and the system power supply module;

The input end of the second conversion circuit is electrically connected with the output end of the first conversion circuit, the output end of the second conversion circuit is electrically connected with the power supply end of the second wake-up module, and the second conversion circuit is used for converting the first power supply output by the first conversion circuit into a second power supply so as to provide the second power supply for the second wake-up module.

Optionally, the first conversion circuit includes a conversion chip, an input filter unit and an output filter unit;

a plurality of input pins of the conversion chip are electrically connected with the output end of the total power supply module through the input filtering unit;

and a plurality of output pins of the conversion chip are electrically connected with the output end of the first conversion circuit through the output filter unit.

Optionally, the second conversion circuit includes a zener diode and a first resistor;

The first end of the first resistor is electrically connected with the output end of the first conversion circuit;

The first end of the zener diode is electrically connected with the second end of the first resistor and the power supply end of the second wake-up module respectively;

The second end of the zener diode is electrically connected with the grounding end.

Optionally, the resistance value of the first resistor satisfies:

wherein R is the resistance value of the first resistor, U1 is the voltage value of the first power supply, U2 is the regulated voltage of the zener diode, and I is the current value flowing through the first resistor.

Optionally, the power switch module includes a first switch unit, a second switch unit, and an or gate logic unit;

The first input end of the OR gate logic unit is electrically connected with the output end of the first awakening module, the second input end of the OR gate logic unit is electrically connected with the output end of the second awakening module, the OR gate logic unit is used for outputting a first level signal when at least one of the first awakening module and the second awakening module outputs the first level signal, and outputting a second level signal when the first awakening module and the second awakening module both output the second level signal, and the second level signal is smaller than a preset level signal;

The control end of the first switch unit is electrically connected with the output end of the OR gate logic unit, the input end of the first switch unit is electrically connected with the ground end, the output end of the first switch unit is electrically connected with the control end of the second switch unit, and the first switch unit is used for being turned on when the output end of the OR gate logic unit outputs the first level signal and turned off when the output end of the OR gate logic unit outputs the second level signal;

The control end of the second switch unit is electrically connected with the output end of the first switch unit, the input end of the second switch unit is electrically connected with the first output end of the conversion module, the output end of the second switch unit is electrically connected with the power supply end of the system power supply module, and the second switch unit is used for being turned off when the first switch unit is turned on and being turned on when the first switch unit is turned off.

Optionally, the first switching unit includes a first transistor, and the second switching unit includes a second transistor;

The OR gate logic unit comprises a first anti-reflection diode and a second anti-reflection diode;

The first end of the first anti-reflection diode is electrically connected with the output end of the first wake-up module, the first end of the second anti-reflection diode is electrically connected with the output end of the second wake-up module,

The second end of the first anti-reflection diode and the second end of the second anti-reflection diode are electrically connected with the grid electrode of the first transistor, the source electrode of the first transistor is electrically connected with the grounding end, the drain electrode of the first transistor is electrically connected with the grid electrode of the second transistor, the source electrode of the second transistor is electrically connected with the first output end of the conversion module, and the drain electrode of the second transistor is electrically connected with the system power supply module.

Optionally, the first transistor includes an N-type metal oxide semiconductor transistor, and the second transistor includes a P-type metal oxide semiconductor transistor.

Optionally, the first conversion circuit further includes an output voltage adjusting unit;

The output voltage adjusting unit is arranged between the output end of the first conversion circuit and the feedback pin of the conversion chip.

Optionally, the first conversion circuit further includes an enable current limiting unit;

The enabling current limiting unit is arranged between a plurality of input pins of the conversion chip and an enabling pin of the conversion chip.

In summary, in the utility model, the output end of the main power module is electrically connected with the input end of the conversion module, the first output end of the conversion module is electrically connected with the power supply end of the first wake-up module and the input end of the power switch module respectively, and the second output end of the conversion module is electrically connected with the power supply end of the second wake-up module. The output end of the first awakening module is electrically connected with the first control end of the power switch module, and the output end of the second awakening module is electrically connected with the second control end of the power switch module. The output end of the power switch module is electrically connected with the power supply end of the system power supply module, and the power switch module is used for being conducted when at least one of the first awakening module or the second awakening module outputs a first level signal so as to provide power for the system power supply module. Therefore, the first awakening module, the second awakening module and the system power supply module are powered through the main power supply module, a plurality of independent power supplies are not required to be arranged, the cost is further reduced, the power consumption is reduced, the integration of a power supply control system is facilitated, and the low-power-consumption operation of the laser radar is realized.

Drawings

FIG. 1 is a block diagram of a power supply control system for a laser radar according to an embodiment of the present utility model;

fig. 2 is a block diagram of an overall circuit of a power supply control system of a lidar according to an embodiment of the present utility model;

Fig. 3 is a partial circuit diagram of a power switch module according to an embodiment of the present utility model.

Detailed Description

In order to make the objects, technical solutions and advantages of the present utility model more apparent, the technical solutions of the present utility model will be fully described below by way of specific embodiments with reference to the accompanying drawings in the examples of the present utility model. It is apparent that the described embodiments are some, but not all, embodiments of the present utility model, and that all other embodiments, which a person of ordinary skill in the art would obtain without making inventive efforts, are within the scope of this utility model.

It should be noted that the terms "first," "second," and the like in the description and the claims of the present utility model and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the utility model described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

Fig. 1 is a block diagram of a power supply control system of a laser radar according to an embodiment of the present utility model, where, as shown in fig. 1, the power supply control system includes a main power module 10, a conversion module 20, a first wake-up module 30, a second wake-up module 40, a power switch module 50, and a system power supply module 60. The output end of the total power module 10 is electrically connected with the input end of the conversion module 20, the first output end of the conversion module 20 is electrically connected with the power supply end of the first wake-up module 30 and the input end of the power switch module 50 respectively, and the second output end of the conversion module 20 is electrically connected with the power supply end of the second wake-up module 40. The output end of the first wake-up module 30 is electrically connected to the first control end of the power switch module 50, and the output end of the second wake-up module 40 is electrically connected to the second control end of the power switch module 50. The output end of the power switch module 50 is electrically connected to the power supply end of the system power supply module 60, and the power switch module 50 is configured to be turned on when at least one of the first wake-up module 30 or the second wake-up module 40 outputs a first level signal, so as to provide power for the system power supply module 60, where the first level signal is greater than a preset level signal.

Specifically, as shown in fig. 1, the output end of the total power module 10 is electrically connected to the output end of the conversion module 20, and the total power provided by the total power module 10 is converted into a first power source and a second power source by the conversion module 20. The voltage value of the first power supply is different from the voltage value of the second power supply. For example, the voltage value of the first power source may be 5V, the voltage value of the second power source may be 3.3V, the first wake-up module 30 may be a CAN sleep wake-up module, and the second wake-up module 40 may be a PHY sleep wake-up module, where the working voltage of the first wake-up module 30 and the working voltage of the system power supply module 60 are the same as each other and are both 5V, so that the first output end of the conversion module 20 is electrically connected with the power supply end of the first wake-up module 30 and the input end of the power switch module 50, and the output end of the power switch module 50 is electrically connected with the power supply end of the system power supply module 60, so that the total power module 10 supplies power to the first wake-up module 30 and the system power supply module 60 through the first output end of the conversion module 20.

The working voltage of the second wake-up module 40 is different from the working voltage of the first wake-up module 30, for example, the working voltage of the second wake-up module 40 is 3.3V, and then the second output end of the conversion module 20 is electrically connected with the power supply end of the second wake-up module 40, and the converted second power supply is output to the second wake-up module 40 through the second output end of the conversion module 20 so as to supply power to the second wake-up module 40, so that the total power supply module supplies power to the first wake-up module 30 and the system power supply module 60 through the first output end of the conversion module 20, and the second output end of the conversion module 20 supplies power to the second wake-up module 40, namely, the power supply of a plurality of modules in the power supply control system can be realized through one power supply.

In addition, the first wake-up module 30 outputs a first level signal when the first power source is in a wake-up state, and outputs a second level signal when the first power source is in a sleep state, wherein the first level signal is greater than the preset level signal, and the second level signal is less than the preset level signal, i.e. the first level signal is a high level signal, and the second level signal is a low level signal. The same second wake-up module 40 outputs the first level signal when the second power is in the wake-up state and outputs the second level signal when the second power is in the sleep state. The output end of the first wake-up module 30 is electrically connected to the first control end of the power switch module 50, and the output end of the second wake-up module 40 is electrically connected to the second control end of the power switch module 50. The power switch module 50 is turned on when at least one of the first wake-up module 30 or the second wake-up module 40 outputs the first level signal, in other words, the power switch module 50 is turned on when at least one of the first wake-up module 30 or the second wake-up module 40 is in a wake-up state, so that the overall power module 10 supplies power to the system power module 60 through the conversion module 20. And when the first wake-up module 30 and the second wake-up module both output the second level signal (i.e. both in the sleep state), the power switch module 50 is turned off, and the voltage of the power supply end of the system power supply module 60 is 0V, so that the low-power-consumption operation of the laser radar is realized.

In summary, in the utility model, the output end of the main power module is electrically connected with the input end of the conversion module, the first output end of the conversion module is electrically connected with the power supply end of the first wake-up module and the input end of the power switch module respectively, and the second output end of the conversion module is electrically connected with the power supply end of the second wake-up module. The output end of the first awakening module is electrically connected with the first control end of the power switch module, and the output end of the second awakening module is electrically connected with the second control end of the power switch module. The output end of the power switch module is electrically connected with the power supply end of the system power supply module, and the power switch module is used for being conducted when at least one of the first awakening module or the second awakening module outputs a first level signal so as to provide power for the system power supply module. Therefore, the first awakening module, the second awakening module and the system power supply module are powered through the main power supply module, a plurality of independent power supplies are not required to be arranged, the cost is further reduced, the power consumption is reduced, the integration of a power supply control system is facilitated, and the low-power-consumption operation of the laser radar is realized.

Optionally, with continued reference to fig. 1 based on the above embodiments, the conversion module 20 includes a first conversion circuit 210 and a second conversion circuit 220. The input end of the first conversion circuit 210 is electrically connected to the output end of the main power module 10, the output end of the first conversion circuit 210 is electrically connected to the power supply end of the first wake-up module 30 and the input end of the power switch module 50, and the first conversion circuit 210 is configured to convert the main power output by the main power module 10 into a first power to provide the first power for the first wake-up module 30 and the system power module 60. The input end of the second conversion circuit 220 is electrically connected to the output end of the first conversion circuit 210, the output end of the second conversion circuit 220 is electrically connected to the power supply end of the second wake-up module 40, and the second conversion circuit 220 is configured to convert the first power source output by the first conversion circuit 210 into the second power source, so as to provide the second power source for the second wake-up module 40.

Illustratively, the operating voltage of the first wake-up module 30 is the same as the operating voltage of the system power module 60, but is different from the operating voltage of the second wake-up module 40, so that multiple switching of the total power provided by the total power module 10 is required. Specifically, the conversion module 20 includes a first conversion circuit 210 and a second conversion circuit 220, where the first conversion circuit 210 is configured to convert the total power provided by the total power module 10 into a first power, and an output end of the first conversion circuit 210 is electrically connected to a first output end of the conversion module 20, so as to supply power to the first wake-up module 30 and the system power supply module 60 through the first conversion circuit 210 respectively. The second conversion circuit 220 is configured to convert the first power source output by the first conversion circuit 210 into a second power source, and an output end of the second conversion circuit 220 is electrically connected with a second output end of the conversion module 20, so that the second wake-up module 30 is powered by the second conversion circuit 220, and thus, the first wake-up module 30 and the system power supply module 60 with the same operating voltage are powered by the same conversion circuit, which can simplify the circuit and make the control mode of power supply simple.

It should be noted that, in the embodiment of the present utility model, the operation voltage of the first wake-up module 30 is the same as the operation voltage of the system power supply module 60, but is different from the operation voltage of the second wake-up module 40, but this is not limited thereto, and in other embodiments, there may be cases where the operation voltage of the first wake-up module 30, the operation voltage of the second wake-up module 40, and the operation voltage of the system power supply module 60 are different. At this time, the conversion module may further include a first conversion circuit, a second conversion circuit, and a third conversion circuit, where an input end of the first conversion circuit is electrically connected to an output end of the main power module, and an output end of the first conversion circuit is electrically connected to an input end of the second conversion circuit, an input end of the third conversion circuit, and a power supply end of the system power supply module, and an output end of the second conversion circuit is electrically connected to a power supply end of the second wake-up module, and an output end of the third conversion circuit is electrically connected to a power supply end of the first wake-up module, so as to supply power to the first wake-up module, the second wake-up module, and the system power supply module, respectively.

Optionally, fig. 2 is an overall circuit diagram of a power supply control system according to an embodiment of the present utility model, as shown in fig. 2, the first conversion circuit 210 includes a conversion chip U1, an input filter unit (not shown in the figure), and an output filter unit (not shown in the figure). The plurality of input pins VIN of the conversion chip U1 are electrically connected to the output terminal of the total power module 10 through the input filter unit. The plurality of output pins SW of the conversion chip U1 are electrically connected to the output terminals of the first conversion circuit 210 through the output filter unit.

Specifically, as shown in fig. 2, the conversion chip U1 may be a DCDC conversion chip for converting one direct current into another direct current. The plurality of input pins VIN of the conversion chip U1 are electrically connected to the output end of the total power module 10, and the plurality of output pins SW of the conversion chip U1 are electrically connected to the output end of the first conversion circuit 210, so that the total power output by the total power module 10 is converted into the first power through the conversion chip U1, and the first power is output to the output end of the first conversion circuit 210. In addition, an input filter unit is further disposed between the output end of the total power module 10 and the plurality of input pins VIN of the conversion chip U1, the input filter unit includes a first capacitor C1 and a second capacitor C2, the first capacitor C1 and the second capacitor C2 are disposed in parallel between the plurality of input pins VIN of the conversion chip U1 and the plurality of ground pins GND1 of the conversion chip U1, the first plates of the first capacitor C1 and the second capacitor C2 are electrically connected with the output end of the total power module 10, and the second plates of the first capacitor C1 and the second capacitor C2 are electrically connected with the ground end GND, so that the total power output by the total power module 10 is filtered by the input filter unit, so that the power output to the conversion pins U1 is smooth direct current.

An output filter power supply is further disposed between the output ends of the first conversion circuit 210 of the plurality of output pins SW of the conversion chip U1. The output filter unit includes an inductor L1, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6, and a seventh capacitor C7. The first end of the inductor L1 is electrically connected to the plurality of output pins SW of the conversion chip U1, the second end of the inductor L1 is electrically connected to the output end of the first conversion circuit 210, the first plates of the third capacitor C3, the fourth capacitor C4, the fifth capacitor C5, the sixth capacitor C6 and the seventh capacitor C7 are all disposed between the second end of the inductor L1 and the output end of the first conversion circuit 210, and the second plates of the third capacitor C3, the fourth capacitor C4, the fifth capacitor C5, the sixth capacitor C6 and the seventh capacitor C7 are all electrically connected to the ground end GND, so that the first power source output by the conversion chip U1 is filtered and stored through the inductor L1, the third capacitor C3, the fourth capacitor C4, the fifth capacitor C5, the sixth capacitor C6 and the seventh capacitor C7. In this way, the total power supply input to the conversion chip U1 and the first power supply output from the conversion chip U1 are filtered by the input filtering unit and the output filtering unit, respectively, so as to improve the reliability of the first power supply output from the conversion chip U1.

Optionally, with continued reference to fig. 1 and 2, the second conversion circuit 220 includes a zener diode D1 and a first resistor R1. The first end of the first resistor R1 is electrically connected to the output end of the first conversion circuit 210. The first end of the zener diode D1 is electrically connected to the second end of the first resistor R1 and the power supply end AVDD of the second wake-up module 40, and the second end of the zener diode D1 is electrically connected to the ground end GND.

Specifically, the first power supply output by the first conversion circuit 210 is converted into the second power supply through the first resistor R1 and the zener diode D1, the first end of the zener diode D1 and the second end of the first resistor R1 are electrically connected with the power supply end AVDD of the second wake-up module 40, and then the second power supply is output to the power supply end AVDD of the second wake-up module 40 to supply power to the second wake-up module 40. Since the zener diode D1 has lower power consumption and cost, the second wake-up module 40 is further powered by the zener diode D1, which can further reduce the cost and power consumption.

For example, the operating voltage of the second wake-up module 40 is 3.3V, and the second power source converted by the second converting circuit 220 is 3.3V, so that a zener diode with a regulated voltage of 3.3V is required to supply power to the second wake-up module 40. It will be appreciated that, in order for the second wake-up module 40 to ensure low power operation based on normal operation, a suitable resistance value of the first resistor R1 needs to be selected for current limiting. Specifically, the resistance value of the first resistor R1 satisfies: Wherein, R is the resistance value of the first resistor R1, U1 is the voltage value of the first power supply, U2 is the stable voltage of the zener diode D1, and I is the current value flowing through the first resistor R1. For example, if the voltage value of the first power supply is 5V, the regulated voltage of the zener diode D1 is 3.3V, and the power consumption of the second wake-up module 40 is 40 μa to ensure the low power consumption operation of the second wake-up module 40, the first resistor R1 having the resistance value of 42.5kΩ needs to be selected.

It should be noted that, the type of the zener diode D1 may be AD-BZT52C3V3S, but the embodiment of the present utility model is not limited thereto, and those skilled in the art may set the type according to the need.

Optionally, fig. 3 is a partial circuit diagram of a power switch module according to an embodiment of the present utility model, and with continued reference to fig. 1-3, the power switch module 50 includes a first switch unit 510, a second switch unit 520, and an or gate logic unit 530. The first input end of the or gate logic unit 530 is electrically connected to the output end CAN-OUT of the first wake-up module 30, the second input end of the or gate logic unit 530 is electrically connected to the output end PHY-OUT of the second wake-up module 40, and the or gate logic unit 530 is configured to output a first level signal when at least one of the first wake-up module 30 and the second wake-up module 40 outputs the first level signal, and to output a second level signal when both the first wake-up module 30 and the second wake-up module 40 output the second level signal, where the second level signal is smaller than the preset level signal. The control terminal of the first switch unit 510 is electrically connected to the output terminal of the or gate logic unit 530, the input terminal of the first switch unit 510 is electrically connected to the ground terminal GND, the output terminal of the first switch unit 510 is electrically connected to the control terminal of the second switch unit 520, and the first switch unit 510 is configured to be turned on when the output terminal of the or gate logic unit 530 outputs the first level signal, and turned off when the output terminal of the or gate logic unit 530 outputs the second level signal. The control end of the second switch unit 520 is electrically connected to the output end of the first switch unit 510, the input end of the second switch unit 520 is electrically connected to the first output end of the conversion module 20, the output end of the second switch unit 520 is electrically connected to the power supply end SYS of the system power supply module 60, and the second switch unit 520 is configured to be turned off when the first switch unit 510 is turned on and turned on when the first switch unit 510 is turned off.

Specifically, the first wake-up module 30 outputs a first level signal when the first power supply is in a wake-up state, and outputs a second level signal when the first power supply is in a sleep state, wherein the first level signal is a high level signal and the second level signal is a low level signal. The same second wake-up module 40 outputs the first level signal when the second power is in the wake-up state and outputs the second level signal when the second power is in the sleep state. The first input terminal and the second input terminal of the or gate logic unit 530 are electrically connected to the output terminal CAN-OUT of the first wake-up module 30 and the output terminal PHUY-OUT of the second wake-up module 40, respectively, and the on conditions of the first switch unit 510 and the second switch unit 520 are different, so that the on and off of the power switch module 50 are controlled together through the first switch unit 510, the second switch unit 520 and the or gate logic unit 530.

For example, when at least one of the first wake-up module 30 and the second wake-up module 40 is in the wake-up state, the or gate logic unit 530 outputs a high level signal, under the high level signal, the first switch unit 510 is turned on, the input end of the first switch unit 510 is electrically connected to the ground GND, the output end of the first switch unit 510 is electrically connected to the control end of the second switch unit 520, that is, the control end of the second switch unit 520 is a low level signal, under the low level signal, the second switch unit 520 is turned on, at this time, the first power output by the first conversion circuit 210 may be output to the power supply end of the system power supply module 60 through the second switch unit 520 to supply power to the system power supply module 60. When the first wake-up module 30 and the second wake-up module 40 are both in the sleep state, the or gate logic unit 530 outputs a low-level signal, under the low-level signal, the first switch unit 510 is turned off, the output end of the first switch unit 510 is a high-level signal, that is, the control end of the second switch unit 520 is a high-level signal, under the high-level signal, the second switch unit 520 is turned off, at this time, the output end of the first conversion circuit 210 is disconnected from the power supply end of the system power supply module 60, thereby realizing the low-power consumption operation of the laser radar.

Alternatively, with continued reference to fig. 1-3, the first switching unit 510 includes a first transistor Q1 and the second switching unit 520 includes a second transistor Q2. The or gate logic unit 530 includes a first anti-reflection diode D2 and a second anti-reflection diode D3. The first end of the first anti-reflection diode D2 is electrically connected to the output CAN-OUT of the first wake-up module 30, and the first end of the second anti-reflection diode D3 is electrically connected to the output PHY-OUT of the second wake-up module 40. The second end of the first anti-reflection diode D2 and the second end of the second anti-reflection diode D3 are electrically connected to the gate of the first transistor Q1, the source of the first transistor Q1 is electrically connected to the ground GND, the drain of the first transistor Q1 is electrically connected to the gate of the second transistor Q2, the source of the second transistor Q2 is electrically connected to the first output of the conversion module 20, and the drain of the second transistor Q2 is electrically connected to the system power supply module 60.

Specifically, the first end of the anti-reflection diode is the positive end, the second end of the anti-reflection diode is the negative end, the anti-reflection diode has the characteristic of unidirectional conduction, when at least one of the first wake-up module 30 or the second wake-up module 40 outputs a high level signal, the first anti-reflection diode D2 and/or the negative end of the second anti-reflection diode is the high level signal, that is, the grid electrode of the first transistor Q1 is the high level signal, the first transistor Q1 is conducted, the source electrode of the first transistor Q1 is electrically connected with the ground end GND, the output end of the first transistor Q1 is electrically connected with the control end of the second transistor Q2, that is, the low level signal of the source electrode of the first transistor Q1 is transmitted to the grid electrode of the second transistor Q2, the second transistor Q2 is conducted under the low level signal, and at this time, the first power output by the first conversion circuit 210 can be output to the power supply end of the system power supply module 60 through the second transistor Q2 to supply power to the system power supply module 60. When the first wake-up module 30 and the second wake-up module 40 are both in the sleep state, the negative terminals of the first anti-reflection diode D2 and the second anti-reflection diode are low-level signals, the first transistor Q1 is turned off under the low-level signals, the output terminal of the first transistor Q1 is a high-level signal, that is, the control terminal of the second transistor Q2 is a high-level signal, the second transistor Q2 is turned off under the high-level signal, at this time, the output terminal of the first conversion circuit 210 is disconnected from the power supply terminal of the system power supply module 60, and thus the low-power consumption operation of the laser radar is realized.

It should be noted that, the power switch module 50 further includes a plurality of resistors for ensuring the normal operation of the first transistor Q1 and the second transistor Q2 based on the above embodiments. The plurality of resistors includes, for example, a second resistor R2, a third resistor R3, a fourth resistor R4, and a fifth resistor R5. The first end of the second resistor R2 is electrically connected with the second end of the first anti-reflection diode D2, the second end of the second resistor R2 is electrically connected with the gate of the first transistor Q1, the first end of the third resistor R3 is electrically connected with the second end of the second resistor R2, the second end of the third resistor R3 is electrically connected with the ground end GND, and the first transistor Q1 is further protected by the second resistor R2 and the third resistor R3, so that the first transistor Q1 is prevented from being damaged by unexpected heavy current. In addition, the first end of the fourth resistor R4 is electrically connected to the source of the second transistor Q2, the second end of the fourth resistor R4 is electrically connected to the gate of the second transistor Q2, and the fifth resistor R4 is connected between the drain of the first transistor Q1 and the gate of the second transistor Q2, so that the second transistor Q2 is protected by the fourth resistor R4 and the fifth resistor R5, and the reliability of the power switch module 50 is ensured.

Alternatively, the first transistor Q1 includes an N-type metal oxide semiconductor transistor, and the second transistor Q2 includes a P-type metal oxide semiconductor transistor. Specifically, the N-type metal oxide semiconductor transistor is turned on when the voltage between the source and the gate is greater than or equal to the threshold voltage, which can be understood that the gate of the N-type metal oxide semiconductor transistor is turned on under a high-level signal, and the N-type metal oxide semiconductor transistor has the characteristics of high input impedance, small driving power and the like. The P-type metal oxide semiconductor transistor is turned on when the voltage between the gate and the source is smaller than a certain value, which can be understood that the P-type metal oxide semiconductor transistor is turned on at a low level, and the P-type metal oxide semiconductor transistor has the characteristics of low power consumption, high switching speed and the like, and further the power consumption of the power switch module 50 can be reduced on the basis of ensuring the normal operation of the power switch module 50 by arranging the first transistor Q1 comprising the N-type metal oxide semiconductor transistor and the second transistor Q2 comprising the P-type metal oxide semiconductor transistor.

Optionally, with continued reference to fig. 2, the first conversion circuit 210 further includes an output voltage adjusting unit (not shown in the figure) based on the above embodiment. The output voltage adjusting unit is disposed between the output end of the first converting circuit 210 and the feedback pin FB of the converting chip Y1.

Specifically, as shown in fig. 2, the output voltage adjusting unit includes a sixth resistor R6 and a seventh resistor R7, a first end of the sixth resistor R6 is electrically connected to the output end of the first conversion circuit 210, a second end of the sixth resistor R6 and a first end of the seventh resistor R7 are both electrically connected to the feedback pin FB of the conversion chip Y1, and a second end of the seventh resistor R7 is electrically connected to the ground GND. When the first power supply output by the first conversion circuit 210 changes, the output voltage of the first conversion circuit 210 can be adjusted by adjusting the resistance values of the sixth resistor R6 and the seventh resistor R7, so as to realize precise control.

Optionally, with continued reference to fig. 2, the first conversion circuit 210 further includes an enable current limiting unit (not shown). The enabling current limiting unit is disposed between the plurality of input pins VIN of the conversion chip U1 and the enabling pin EN of the conversion chip U1.

Specifically, the enabling current limiting unit includes an eighth resistor R8, a first end of the eighth resistor R8 is electrically connected to a plurality of input pins VIN of the conversion chip U1, a second end of the eighth resistor R8 is electrically connected to an enable end EN of the conversion chip U1, and when the total power module 10 outputs the total power, the conversion chip U1 is in a working state, and in addition, the switching-on voltage and the switching-off voltage of the conversion chip U1 can be adjusted by adjusting the resistance value of the eighth resistor R8, so that the power consumption enabled by the conversion chip U1 is reduced.

It should be noted that, the first conversion circuit 210 further includes a ninth resistor R9, the ninth resistor R9 is a MODE setting resistor, a first end of the ninth resistor R9 is electrically connected to the MODE setting pin MODE of the conversion chip U1, a second end of the ninth resistor R9 is electrically connected to the ground GND, and further, an operating MODE of the conversion chip U1 is set through the ninth resistor R9, so that the static power consumption of the conversion chip U1 is minimized. Further, the first conversion circuit 210 further includes a tenth resistor R10, an eleventh resistor R11, and an eighth capacitor C8. The tenth resistor R10 is a switching frequency setting resistor, a first end of the tenth resistor R10 is electrically connected to the operating frequency setting pin RT of the conversion chip U1, a second end of the tenth resistor R10 is electrically connected to the ground GND, and the switching frequency of the conversion chip U1 is set through the tenth resistor R10. The eleventh resistor R11 is an output state indicating resistor, a first end of the eleventh resistor R11 is electrically connected to the state indicating pin PG of the conversion chip U1, and a second end of the eleventh resistor R11 is electrically connected to the output end of the first conversion circuit 210. The eighth capacitor C8 is a soft start setting capacitor, a first polar plate of the eighth capacitor C8 is electrically connected with a soft start pin TR/SS of the conversion chip U1, a second polar plate of the eighth capacitor C8 is electrically connected with the grounding end GND, and then the power-on time of the conversion chip U1 for outputting the first power supply can be set through the eighth capacitor C8. In addition to the above, the first conversion circuit 210 further includes other electrical components for ensuring the normal operation of the conversion chip U1, which is not described in detail in the embodiment of the present utility model.

Note that the above is only a preferred embodiment of the present utility model and the technical principle applied. It will be understood by those skilled in the art that the present utility model is not limited to the particular embodiments described herein, and that various obvious changes, rearrangements, combinations, and substitutions can be made by those skilled in the art without departing from the scope of the utility model. Therefore, while the utility model has been described in connection with the above embodiments, the utility model is not limited to the embodiments, but may be embodied in many other equivalent forms without departing from the spirit or scope of the utility model, which is set forth in the following claims.