EP1490906A1 - Beol process for cu metallizations free from al-wirebond pads - Google Patents

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Definitions

• the present invention relates to preparing FBEOL (FAR-BACK-END-OF-LINE) copper metallizations for use in semiconductors without relying on additional Al-wirebond pads by: a process of probing, bonding, and fusing with only one patterning step for the final passivation opening; or a process of probing, bonding, fusing and flip chip bumping with two patterning steps - wherein both processes eliminate the Al-via + Al-pad patterning.
• FBEOL FAR-BACK-END-OF-LINE
• a fabricated integrated circuit (IC) device is assembled into a package for use on a printed circuit board as part of a larger circuit .
• IC integrated circuit
• a metal bond is formed to make a connection between the bonding pad of the IC device and a lead extending to the package lead frame, or a solder ball connection to a ceramic or polymeric chip carrier.
• Al and Al alloys are used as conventional chip wiring materials. However, it is desirous to replace Al wiring material with Cu and Cu alloys since Cu wiring would provide improved chip performance and superior reliability compared to Al and alloys of Al . Nevertheless, the packaging of IC devices utilizing copper wiring presents a considerable number of technical issues and challenges related to the reaction of copper with material used in the solder-ball process and/or the susceptibility of copper to attack and corrosion.
• U.S. Patent 6,187,680 disclose a method for creating aluminum wirebound pad on a copper BEOL. The process comprises:
• the method of making the interconnection structure for the semiconductor circuit comprises: providing a substrate having coplanar damascene non-self passivating conductors embedded in a first insulator defining a first electrical interconnect layer; forming a second electrical interconnect layer comprising coplanar self-passivating conductors in a second insulator, the second electrical interconnect layer over-lying the first electrical interconnect layer and the second interconnect self- passivating conductors contacting the non-self passivating conductors ; and depositing a final passivation layer over the second electrical interconnect layer.
• One of the non-self passivating conductors forms part of a Controlled, Collapse Chip Connection (C4) barrier structure, the method further comprising the steps of: etching the final passivation layer above the C4 barrier structure; and depositing pad limiting and C4 metallurgies.
• C4 Controlled, Collapse Chip Connection
• U.S. Patent 6,054,380 disclose a method an apparatus for integrating low dielectric constant materials into a multilevel metallization and interconnect structure.
• the method comprises: forming a metal line upon a surface of a substrate, where the metal line has a top surface and sidewalls; depositing a barrier layer over the metal line and the surface of said substrate; removing a portion of the barrier layer where the barrier layer remains deposited on at least the sidewalls of the metal line; depositing a first insulative layer over said metal line, the surface of the substrate and the barrier layer, where the insulative layer is a material that, but for the barrier layer protecting the sidewalls of the metal line, would react with a material of the same metal line; depositing a second insulative layer over the first insulative layer; and forming a via that contacts a top surface of the metal line .
• One object of the present invention is to provide a process for fabricating a semiconductor device of a Cu far-back-end-of- the-line (FBEOL) structure comprising Cu metallizations wherein probing, bonding and fusing is accomplished with only one patterning step for the final passivation opening.
• FBEOL far-back-end-of- the-line
• Another object of the present invention is to provide a process for fabricating a semiconductor device of a Cu front- back-end-of-the-line (FBEOL) structure comprising Cu metallization wherein probing, bonding, and fusing is accomplished together with flip chip bumping with two patterning steps .
• FBEOL Cu front- back-end-of-the-line
• a further object of the present invention is to provide a process for preparing Cu front-back-end-of-the-line (FBEOL) structures of Cu metallizations that eliminate the Al-via + Al- pad patterning.
• FIG. 1 depicts an integrated scheme for preparing the semiconductors of the invention in which there is probing, bonding and fusing utilizing only one patterning step for the final passivation opening in preparing i-Au passivated Cu-pads and Cu-laser fuses.
• FIG. 2 depicts an integration scheme of the invention process in which there is probing, bonding and fusing, but also flip chip bumping utilizing two patterning steps to obtain Cu pads and fuses with i-Au finish.
• the invention will now be described in more detail with reference to the accompanying drawings, starting from a point where there is a multi-level Cu metallization either in combination with a conventional oxide or nitride or with low k- dielectrics such as Silk, Flare, Coral, SiCOH, or a porous low k material.
• a mechanically hard dielectric e.g., oxide or FSG [fluorinated silicon glass]
• the last Cu layer must be thick enough to support the wire bonding process (approximately 500nm or more) .
• Cu-wirings including the fuse-lengths are manufactured by state of the art damascene or dual damascene processes (i.e., patterning of the trenches and vias in the dielectric and filling it with liner, Cu seed layer, Cu-fill followed by an anneal and Cu CMP [chemical mechanical polishing] ) .
• the process sequence of the first embodiment is as follows: providing a substrate having embedded copper wires and copper pads ; selectively depositing a first metallic passivation layer on the top copper surfaces sufficient to prevent Cu oxidation and/or Cu out diffusion; depositing a final passivation layer; employing lithography and etching of the final passivation layer to affect pad opening and opening of the fuses by exposing the passivated Cu in the bond pad area and in the fuse area; and affecting an additional passivation of open pad and open fuse areas by selective immersion deposition of Au.
• the process sequence of the second embodiment of the invention entails: providing a substrate of a damascene copper pad and copper fuse embedded in a dielectric with a dielectric cap layer thereon; depositing a final passivation layer and affecting final passivation opening and fuse patterning with a lithographic and etching step; deposition of a liner (diffusion barrier) and copper seed layer, followed by Cu electroplating; immersion plating Au on top of Cu pads to create a surface sufficient for probing and bonding; and providing a dielectric layer sufficient to protect the fuses, but thin enough that the fuse can be blown through it.
• the integration scheme for preparing the semiconductor of the invention process commences with a multi-level Cu metallization in which a Cu or Cu alloy (MxCu) pad 10 and Cu fuse 11 are embedded in a dielectric substrate, the requirement being that at least the last Cu-layer must be embedded in the mechanically hard dielectric (e.g. oxide, FSG) .
• MxCu Cu or Cu alloy
• the multi-level Cu metallization may be in combination with a conventional oxide or nitride or a low k-dielectric (Silk, Flare, Coral, SiCOH, or other porous low K materials) .
• the last Cu layer must also be thick enough to support the wirebonding process (approximately 500nm or more) .
• the last Cu- wiring including the fuse-link may be manufactured in a state- of-the-art damascene or dual damascene process (i.e. patterning of the trenches and vias in the dielectric and filling it with liner, Cu-seed layer, Cu-fill followed by an anneal and Cu CMP) .
• the top Cu surface is passivated against oxidation or Cu out diffusion by depositing a metallic passivation layer of either CoWP cap layer as shown in FIG. 1 or a layer of CoP or Ru.
• a metallic passivation layer of either CoWP cap layer as shown in FIG. 1 or a layer of CoP or Ru.
• deposition of a dielectric cap or etch stop layer such as SiN or Blok may be made at this point, whereupon the final passivation (using conventional PECVD oxide or nitride layers) is deposited.
• a conventional patterning sequence utilizing lithography and etching is next employed on the final passivation to obtain the pad opening and the opening of the fuses.
• the passivated Cu is exposed in the bond pad area and also is the fuse area.
• the metallic passivation layer is needed on top of the Cu surface .
• each individual fuse link gets its individual opening in the final passivation.
• One large opening of the whole fuse area (which is the state of the art today) should be avoided. This is so because, during the laser fusing process, the splattered material should be redeposited at the vertical side wall of the final passivation in order to avoid a short of the neighboring fuse .
• the integration scheme of this first embodiment can be combined with the realization of inductors in the last Cu-level and also with a MIM-cap scheme.
• an additional thin ( ⁇ 200nm because of fusing) layer of dielectric e.g. oxide, nitride, photosensitive (low k or other) dielectric
• dielectric e.g. oxide, nitride, photosensitive (low k or other) dielectric
• Final passivation is accomplished using an oxide or nitride, formed by final passivation opening and fuse patterning (on the whole fuse) with a single lithographic and etching step.
• deposition of a liner (diffusion barrier) and a Cu seed layer is performed followed by a conventional Cu electroplating and CMP of the excess Cu and liner.
• Immersion deposition of Au (I-Au) is used to cause plating on top of the Cu pads to create a surface sufficient for probing and bonding.
• a thin layer of a dielectric ⁇ 200nm
• the packing of the thin dielectric layer is followed by a patterning step to affect the pad opening.
• a thin photosensitive low k dielectric may be deposited for exposure and development to enable alleviating an etch process for the pad opening .
• the process is very well suited for providing inductors (because thickening of the last Cu provides low resistance) and MIM can be easily integrated with a C4 or Flip Chip type of process (because the fuses are protected during the UBM and bumping process) .
• the probing and fusing may be done after bumping.
• An additional benefit of the of the second embodiment of the invention is that all of the unblown fuses are protected by the last dielectric layer.

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• Physics & Mathematics (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Design And Manufacture Of Integrated Circuits (AREA)
• Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
• Wire Bonding (AREA)

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• 2002
  • 2002-04-02 WO PCT/US2002/010409 patent/WO2003085735A1/en not_active Application Discontinuation
  • 2002-04-02 EP EP02719422A patent/EP1490906A1/en not_active Withdrawn
  • 2002-04-02 JP JP2003582819A patent/JP2005522055A/en not_active Abandoned
  • 2002-04-02 AU AU2002250505A patent/AU2002250505A1/en not_active Abandoned

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