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GB2265479A - Reference current generating circuit - Google Patents

️Wed Sep 29 1993

GB2265479A - Reference current generating circuit - Google Patents

Reference current generating circuit Download PDF

Info

Publication number

GB2265479A

GB2265479A GB9209400A GB9209400A GB2265479A GB 2265479 A GB2265479 A GB 2265479A GB 9209400 A GB9209400 A GB 9209400A GB 9209400 A GB9209400 A GB 9209400A GB 2265479 A GB2265479 A GB 2265479A Authority

United Kingdom

Prior art keywords

voltage

electrode connected

reference current

mos transistor

generating circuit

Prior art date

1992-03-20

Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)

Withdrawn

Application number

GB9209400A

Other versions

GB9209400D0 (en

Inventor

Jae-Hyeong Lee

Dong-Jae Lee

Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

Samsung Electronics Co Ltd

Original Assignee

Samsung Electronics Co Ltd

Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)

1992-03-20

Filing date

1992-04-30

Publication date

1993-09-29

1992-04-30 Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd

1992-06-17 Publication of GB9209400D0 publication Critical patent/GB9209400D0/en

1993-09-29 Publication of GB2265479A publication Critical patent/GB2265479A/en

Status Withdrawn legal-status Critical Current

Classifications

- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is DC
- G05F3/10—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
- G05F3/24—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only
- G05F3/242—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage
- G05F3/245—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage producing a voltage or current as a predetermined function of the temperature
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is DC
- G05F3/10—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
- G05F3/24—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only
- G05F3/242—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage
- G05F3/247—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage producing a voltage or current as a predetermined function of the supply voltage
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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Engineering & Computer Science (AREA)
Physics & Mathematics (AREA)
Microelectronics & Electronic Packaging (AREA)
Radar, Positioning & Navigation (AREA)
Electromagnetism (AREA)
General Physics & Mathematics (AREA)
Nonlinear Science (AREA)
Automation & Control Theory (AREA)
Computer Hardware Design (AREA)
Computing Systems (AREA)
General Engineering & Computer Science (AREA)
Mathematical Physics (AREA)
Control Of Electrical Variables (AREA)
Dram (AREA)
Amplifiers (AREA)

Description

2265479 REFERENCE CURRENT GENERATING CIRCUIT The present invention relates

to a semiconductor device, and more particularly to a reference current generating circuit of a semiconductor device.

Reference current generating circuits employed in semiconductor devices must output constant current regardless of the external environment. Accordingly, the requisite characteristics of a reference current generating circuit are largely two: first, constant current should be sent out as an output within a desired range free from the fluctuation of a supplied voltage, and second, constant current should also be sent out as an output within a desired range free from changes in external temperature and/or process conditions.

FIG. 1 of the accompanying drawings illustrates a reference current generating circuit of a conventional semiconductor device, wherein reference current Iref flowing through a PMOS transistor MP2 is expressed by, in amperes, V 11ML R, Here., "Vm," designates the threshold voltage of an NMOS transistor MN1. That is, it can be noted that reference current Iref is in proportion to threshold voltage Vt of NMOS transistor MN1.

Therefore, the conventional circuit is disadvantageous in that reference current Iref is varied in accordance with the threshold voltage of MOS transistor MN1 which is susceptible to temperature and process condition changes.

Accordingly, it is an object of the present invention to provide a reference current generating circuit which is 2 insusceptible to variations in temperature and manufacturing process.

According to the present invention, there is provided a reference current generating circuit comprising voltage generating means having resistance means and a MOS transistor between f irst and second voltages, f or outputting a constant voltage, and MOS diode means and a resistor connected between the constant voltage and the second voltage, whereby constant current is output in the amount obtained by dividing a value which is obtained by subtracting the threshold voltage of the MOS diode means from the constant voltage, by the resistance value of the resistor.

Embodiments of the present invention will now be described by way of example with reference to the accompanying drawings in which:

FIG. 1 shows a reference current generating circuit of a conventional semiconductor device; FIG. 2 illustrates a reference current generating circuit of a semiconductor device according to an embodiment of the present invention; FIG. 3 shows a reference current generating circuit of a semiconductor device according to another embodiment of the present invention; and FIG. 4 shows a reference current generating circuit of a semiconductor device according to a further embodiment of the present invention.

Referring to FIG. 1, a conventional reference current generating circuit includes: a PMOS transistor MP1 for limiting 3 current which has its source electrode connected to a power source Vcc, and its gate electrode connected to ground (Vss); a PMOS transistor MP2 for limiting current which has its source electrode connected to power source Vcc, and its drain electrode commonly connected to its gate electrode; an NMOS transistor MN2 which has its gate electrode connected to the drain electrode of PMOS transistor MP1, and its drain electrode connected to the drain electrode of PMOS transistor MP2; an NMOS transistor MN1 which has its drain electrode connected to the gate electrode of NMOS transistor MN2, its gate electrode connected to the source electrode of NMOS transistor MN2, and its source electrode connected to ground (Vss); and a resistor R, connected between the gate electrode of NMOS transistor MN1 and ground (Vss).

Here, reference current Iref flowing through PMOS transistor MP2 can be defined as the following equation.

Iref = VtmN, (1) R, From the above equation (1), it is noted that reference current Iref is in proportion to the threshold voltage of NMOS transistor MN1. Accordingly, reference current Iref is liable to be changed according to variations in temperature and the manufacturing process.

FIG. 2 illustrates an embodiment of a reference current generating circuit according to the present invention.

The circuit of FIG. 2 when compared with that of Fig. 1 also includes an NMOS transistor MN3 which has its gate and drain electrodes connected to resistor R,, and its source electrode connected to ground.

4 Here, a reference current Iref flowing through pmos transistor MP2 can be written as below.

Iref VtmN, - VtmN3 (2) R, 04 From the above equation (2), ref erence current Iref is in proportion to the value obtained by subtracting the threshold voltage of NMOS transistor MN3 from the threshold voltage of NMOS transistor MN1. Therefore, reference current Iref is insusceptible to variations in temperature and manufacturing process.

FIG. 3 illustrates another embodiment of the reference current generating circuit according to the present invention.

The circuit of FIG. 3, in order to make the threshold voltages of NMOS transistor MN1 and NMOS transistor MN3 different, a back-bias voltage VBB is supplied to the substrate of NMOS transistor MN1 and NMOS transistor MN2 to increase the threshold voltage. Fig. 3 also differs from Fig. 2 in that the source electrode of NMOS transistor MN3 and the substrate are connected to ground (Vss).

Here, reference current Iref flowing through PMOS transistor MP2 can be defined as:

Iref = VmN, - V04N3 (3) R, From the above equation (3), it is noted that a desired reference current Iref can be obtained by adjusting resistor R,.

FIG. 4 illustrates another embodiment of the reference current generating circuit according to the present invention. As compared with the circuit of FIG. 1, the circuit shown in FIG.

4 further includes an NMOS transistor MN5 which has its drain and gate electrodes connected to resistor R,, and its source electrode connected to the substrate; and a PMOS transistor MP3 which has its source electrode connected to the substrate and to iq the source electrode of NMOS transistor MN5, and its gate and drain electrodes connected to ground. In the case of NMOS transistor MN1, the source voltage becomes higher than the ground potential, by as much as the threshold voltage of the PMOS transistor MP3, and the substrate is grounded, thereby obtaining an inverse bias effect. Thus, since the current flowing through PMOS transistor MP2 is in proportion to the threshold voltage difference between NMOS transistors MN1 and MN5, a reference current generating circuit which is insusceptible to the temperature and manufacturing process variations, can be provided.

At this time, changes in the reference current, in accordance with the temperature of the conventional circuit shown in FIG. 1 and the circuit of an embodiment of the present invention shown in FIG. 4, are compared in the following table.

temperature conventional circuit Fig. 4 circuit CC) Iref (MA) Iref (liA) -5 1.6285 1.5492 +25 1.4653 1.5097 +50 1.3364 1.4772 +100 1.0887 1.4277 In the above table, it can be. noted that the change of the reference current with temperature variation in the circuit of Fig. 4, is less than that of the conventional circuit. As a 6 result, the reference current generating circuit of the present invention has a good reference current characteristic, so that product reliability can be enhanced by its adoption in semiconductor devices employing a reference current generating 04 circuit.

Claims (9)

CLAIMS:

1. A reference current generating circuit comprising voltage generating means having resistance means and a MOS to transistor between first and second voltages, for outputting a constant voltage, and MOS diode means and a resistor connected between said constant voltage and said second voltage, whereby constant current is output in the amount obtained by dividing a value which is obtained by subtracting the threshold voltage of said MOS diode means from said constant voltage, by the resistance value of said resistor.

2. A reference current generating circuit as claimed in claim 1, wherein said voltage generating means comprises: a first MOS transistor which has its source electrode connected to said f irst voltage, and its gate electrode connected to said second voltage; a second MOS transistor which has its drain electrode connected to the drain electrode of said first MOS transistor, and its source electrode connected to said second voltage; a third MOS transistor which has its source electrode connected to said first voltage, and its gate and drain electrodes connected to each other; and a fourth MOS transistor which has its drain electrode connected to the gate electrode of said third MOS transistor, its gate electrode connected to the drain electrode of said second MOS transistor, and its source electrode connected to the gate electrode of said second MOS transistor.

3. A reference current generating circuit as claimed in claim 1 or 2, wherein said MOS diode means comprises a drain electrode and a gate electrode connected to said resistor, and a source electrode connected to said second voltage.

4. A reference current generating circuit as claimed in any preceding claim, wherein said MOS diode means comprises: an NMOS transistor having its drain and gate electrodes connected to said resistor, its source electrode connected to its substrate; and a PMOS transistor having its source electrode connected to the source of said NMOS transistor and said substrate, and its drain and gate electrodes connected to said second voltage.

5. A reference current generating circuit as claimed in any preceding claim, wherein said constant voltage is greater than said threshold voltage of said MOS diode means.

6. A reference current generating circuit as claimed in any preceding claim, wherein said constant voltage adjusts the threshold voltage difference of said MOS diode means using back bias voltage difference.

7. A reference current generating circuit as claimed in claim 1, wherein said voltage generating means comprises:

a first MOS transistor which has its source electrode connected to said first voltage, and its gate electrode connected to said second voltage; 9 0, (h a second MOS transistor which has its drain electrode connected to the drain electrode of said first MOS transistor, its source electrode connected to said second voltage, and its substrate applied with a third voltage; a third MOS transistor which has its source electrode connected to said first voltage, and its gate and drain electrodes connected to each other; and a fourth MOS transistor which has its drain electrode connected to the gate electrode of said third MOS transistor, its gate electrode connected to the drain electrode of said second MOS transistor, its source electrode connected to the gate electrode of said second MOS transistor, and its substrate applied with said third voltage.

8. A reference current generating circuit as claimed in claim 7, wherein said MOS diode means comprises drain and gate electrodes connected to said resistor, and a source electrode connected to said second voltage and a substrate.

9. A reference current generating circuit substantially as hereinbefore described with reference to Figure 2 with or without reference to either of Figures 3 and 4 of the accompanying drawings.

GB9209400A 1992-03-20 1992-04-30 Reference current generating circuit Withdrawn GB2265479A (en)

Applications Claiming Priority (1)

Application Number	Priority Date	Filing Date	Title
KR1019920004658A KR940005510B1 (en)	1992-03-20	1992-03-20	Reference current generating circuit

Publications (2)

Publication Number	Publication Date
GB9209400D0 GB9209400D0 (en)	1992-06-17
GB2265479A true GB2265479A (en)	1993-09-29

Family

ID=19330693

Family Applications (1)

Application Number	Title	Priority Date	Filing Date
GB9209400A Withdrawn GB2265479A (en)	1992-03-20	1992-04-30	Reference current generating circuit