JPS63307759A - Semiconductor integrated circuit - Google Patents

PURPOSE:To shorten a design period and prevent a design error by a method wherein the uppermost metal wiring is used only for a power supply wire, an inner element using the power is covered with the uppermost metal wiring, and the power is supplied to the element through the intermediary of a through hole and a contact without providing a lower wiring. CONSTITUTION:A semiconductor integrated circuit is provided with, at least two layered wiring layers, for instance, three-layered wiring layers 3-5 formed on a semiconductor substrate 1, where the metal wiring layers 3-5 are formed to cover an inner element region 2 and structured to contain the uppermost metal wiring 5 composed of only a power supply wiring. That is to say, a potential Vss of the third layer metal wiring 5 is directed to the first and the second layer metal wirings 3 and 4 through the intermediary if through holes 10 and 9 and a contact 8, wherefore an additional circuit is not necessary to be provided. Thus, a wiring design can be facilitated and also accomplished in a short period without committing errors.

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体集積回路に関し、特に多層金属配線を有
する半導体集積回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit having multilayer metal wiring.

〔従来の技術〕[Conventional technology]

従来の多層金属配線構造を有する半導体集積回路、例え
ば、ゲートアレーで用いられている３層の金属配線を用
いろ半導体集積回路では、否定績（ＮＡＮＤ）及び否定
和（ＮＯＲ）等を基本論理セル内の配線を第１層（最下
層）金属配線で行ない、基本論理セル間の配線を第２層
及び第３層金属配線で行ない、電源線の配線を第１層、
第２層及び第３層金属配線で行なっていた。Semiconductor integrated circuits with conventional multilayer metal wiring structures, such as the three-layer metal wiring used in gate arrays, use basic logic cells such as NAND and NOR. The internal wiring is done with the first layer (bottom layer) metal wiring, the wiring between basic logic cells is done with the second and third layer metal wiring, and the power supply line wiring is done in the first layer,
This was done using second and third layer metal wiring.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来の半導体集積回路は、多層金属配線の設計
をチップ面積最小化の必要性から人手設計せざるを得な
い汎用の１チツプマイクロコンピユータ及びマイクロプ
ロセッサ等に適用する場合、各層の金属配線が電源線と
信号線を共有する為、複数の電源線の配線と信号線の配
線を各々考慮して両方の配線の最適設計をすることは現
実的には不可能であり、従って設計の複雑化をもたらし
、融通性に欠けるので、設計工期の長期化及び設計誤り
を招くという欠点がある。When the above-mentioned conventional semiconductor integrated circuit is applied to general-purpose one-chip microcomputers and microprocessors, etc., where multilayer metal wiring must be designed manually due to the need to minimize chip area, the metal wiring in each layer is Since the power supply line and the signal line are shared, it is practically impossible to design the optimum wiring by considering the wiring of multiple power supply lines and the wiring of the signal line separately, thus making the design more complicated. This results in a lack of flexibility, which has the drawback of prolonging the design period and causing design errors.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は、半導体基板Ｅに形成された少くとも２層の金
属配線層を有する半導体集積回路において、前記金属配
線層は内部素子領域を覆って形成されかつ電源配線のみ
から成る最上層の金属配線層を含んで構成される。The present invention provides a semiconductor integrated circuit having at least two metal wiring layers formed on a semiconductor substrate E, in which the metal wiring layer is formed to cover an internal element region, and the metal wiring in the uppermost layer consists only of power supply wiring. It is composed of layers.

〔実施例〕〔Example〕

次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.

第１図は本発明の第１の実施例の平面図である。FIG. 1 is a plan view of a first embodiment of the invention.

第１図に示すように、半導体基板１上に形成された内部
素子領域２を覆って最上層の第１層金属配ｖＡ５が形成
され、内部素子１域２の周囲のポンディングパッド領域
６には信号用のポンディングパッド１１と■５ｓ電源用
ポンディングパッド１２と■６゜電源用ポンディングパ
ッド１３とが形成される。As shown in FIG. 1, an uppermost first layer metal interconnection layer A5 is formed to cover an internal element area 2 formed on a semiconductor substrate 1, and a bonding pad area 6 around the internal element area 2 is formed. A bonding pad 11 for a signal, a bonding pad 12 for a 5s power supply, and a bonding pad 13 for a 6° power supply are formed.

第３層金属配線５はポンディングパッド１２を介して供
給されるＶｓｓ電源により、Ｖｓｓ電位に保たれる。The third layer metal wiring 5 is maintained at the Vss potential by the Vss power supply supplied via the bonding pad 12.

第２図は第１図のＡ部の内部素子領域の一部切欠き平面
図である。FIG. 2 is a partially cutaway plan view of the internal element region of section A in FIG. 1. FIG.

第２図に示すように、半導体基板１上に形成されたトラ
ンジスタを形成するための拡散層領域２１〜２４と、第
１層金属配線３と、第２層金属配線４と第３層金属配線
５と、多結晶シリコン層７と、コンタクト８と、第１層
金属配線３と第２層金属配線４間のスルーホール９と、
第２層金属配線４と第３層金属配線５間のスルーホール
１０とを含む。As shown in FIG. 2, diffusion layer regions 21 to 24 for forming transistors formed on a semiconductor substrate 1, a first layer metal interconnect 3, a second layer metal interconnect 4, and a third layer metal interconnect 5, a polycrystalline silicon layer 7, a contact 8, a through hole 9 between the first layer metal wiring 3 and the second layer metal wiring 4,
It includes a through hole 10 between the second layer metal wiring 4 and the third layer metal wiring 5.

このように構成して、スルーホール１０．スルーホール
９及びコンタクト８を介し第３屑金属配線５のＶ５５電
位は第１層金属配線３及び第２層金属配線４へ導かれる
ため、別の配線を用いる必要が生じない。With this configuration, the through hole 10. Since the V55 potential of the third scrap metal interconnect 5 is guided to the first layer metal interconnect 3 and the second layer metal interconnect 4 via the through hole 9 and the contact 8, there is no need to use a separate interconnect.

従って、配線設計が容易になり短期間に誤りなし行なう
ことができる。Therefore, wiring design becomes easy and can be done in a short period of time without errors.

第３図は本発明の第２の実施例の平面図である。FIG. 3 is a plan view of a second embodiment of the invention.

第３図に示すように、第２の実施例では半導体基板１上
に第１の内部素子領域２１と第２の内部素子領域２ｂと
を設け、内部素子領域２１上を覆う第３層金属配線５ａ
と内部素子領域２ｂ上を覆う第３層金属配線５ｂを形成
している。As shown in FIG. 3, in the second embodiment, a first internal element region 21 and a second internal element region 2b are provided on a semiconductor substrate 1, and a third layer metal wiring covering the internal element region 21 is provided. 5a
A third layer metal wiring 5b is formed to cover the internal element region 2b.

内部素子領域２．はＶｓｓｌ電源及び■。Ｃ７電源と用
い、内部素子領域２ｂはＶｓｓ２電源及びＶＣＣ２電源
を用いる。Internal element area 2. is the Vssl power supply and ■. The internal element region 2b uses the Vss2 power source and the VCC2 power source.

半導体基板１の外周上のポンディングパッド領域６上に
形成したポンディングパッド１２．、からＶｓｓ１電源
、ポンディングパッド１３．、からＶｃｃ１電源が第３
層金属配線５１に供給され、ポンディングパッド１２ｂ
から■＝、ｓ２電源、ポンディングパッド１３．からＶ
ｃｃ２電源が第３層金属配線５ｂに供給される。A bonding pad 12 formed on the bonding pad region 6 on the outer periphery of the semiconductor substrate 1. , to Vss1 power supply, bonding pad 13. , the Vcc1 power supply is the third
layer metal wiring 51 and bonding pad 12b
From ■=, s2 power supply, bonding pad 13. from V
The cc2 power supply is supplied to the third layer metal wiring 5b.

第２の実施例では、完全２電源を用いる半導体集積回路
に適用できる利点がある。The second embodiment has the advantage that it can be applied to a semiconductor integrated circuit using two complete power supplies.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、最上層の金属配線を電源
線のみに使用し、その電源を使用する内部素子上を最上
層の金属配線で覆い、下層の配線を引回すことなしにス
ルーホール及びコンタクトで素子に電源を供給すること
により、チップ面積を縮少でき、又、設計の融通性が大
きくなるので、設計工期を短縮し設計誤りの発生を防止
できるという効果がある。更に、第３層金属配線はほぼ
矩形の大きなパターンになるので下地の段差による段切
れに注意を払うことを要せず、製造プロセスの簡略化を
図れるという副次的効果もある。As explained above, the present invention uses the top layer metal wiring only as a power supply line, covers the internal elements that use the power supply with the top layer metal wiring, and uses through-holes without routing the lower layer wiring. By supplying power to the element through contacts and contacts, the chip area can be reduced and design flexibility is increased, which has the effect of shortening the design period and preventing the occurrence of design errors. Furthermore, since the third layer metal wiring has a large, substantially rectangular pattern, there is no need to pay attention to step breaks due to differences in the underlying layer, which has the secondary effect of simplifying the manufacturing process.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の第１の実施例の平面図、第２図は第１
図のＡ部の内部素子領域の一部切欠き平面図、第３図は
本発明の第２の実施例の平面図である。FIG. 1 is a plan view of the first embodiment of the present invention, and FIG. 2 is a plan view of the first embodiment of the present invention.
FIG. 3 is a partially cutaway plan view of the internal element region of section A in the figure, and FIG. 3 is a plan view of a second embodiment of the present invention.