KR0140811B1 - Fabrication method of transistor - Google Patents

Classifications

• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
  • G06V30/00—Character recognition; Recognising digital ink; Document-oriented image-based pattern recognition
  • G06V30/10—Character recognition
  • G06V30/16—Image preprocessing
  • G06V30/168—Smoothing or thinning of the pattern; Skeletonisation
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/60—Electrodes characterised by their materials
  • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
  • H10D64/661—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
  • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
  • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
  • H01L21/0274—Photolithographic processes
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
  • H01L21/28008—Making conductor-insulator-semiconductor electrodes
  • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
  • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
  • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
  • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
  • H01L21/321—After treatment
  • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
  • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/01—Manufacture or treatment
  • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
  • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
  • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 

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• Engineering & Computer Science (AREA)
• General Physics & Mathematics (AREA)
• Physics & Mathematics (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• Manufacturing & Machinery (AREA)
• Computer Hardware Design (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Power Engineering (AREA)
• Multimedia (AREA)
• Theoretical Computer Science (AREA)
• Computer Vision & Pattern Recognition (AREA)
• Insulated Gate Type Field-Effect Transistor (AREA)
• Semiconductor Memories (AREA)

Abstract

Description

Claims (3)

트랜지스터 제조방법에 있어서; 반도체 기판 상에 게이트 절연막, 폴리실리콘막 및 희생막을 차례로 형성하는 제1단계; 상기 희생막을 선택식각하여 상기 폴리실리콘막을 제1선폭으로 노출시키는 제2단계; 상기 희생막의 측벽에 절연막스페이서를 형성하여 상기 폴리실리콘막을 상기 제1선폭보다 적은 제2선폭으로 노출시키는 제3단계; 상기 제2선폭으로 노출된 폴리실리콘막 상에 불순물 이온 주입을 실시하는 제4단계; 상기 희생막 및 상기 희생막과 오버랩된 상기 폴리실리콘막을 차례로 선택식각하는 제5단계; 및 소오스/드레인 영역의 형성을 위한 이온주입을 실시하는 제6단계를 포함하여 이루어지는 것을 특징으로 하는 트랜지스터 제조 방법.In the transistor manufacturing method; A first step of sequentially forming a gate insulating film, a polysilicon film, and a sacrificial film on the semiconductor substrate; Selectively etching the sacrificial layer to expose the polysilicon layer in a first line width; A third step of forming an insulating film spacer on sidewalls of the sacrificial film to expose the polysilicon film to a second line width less than the first line width; A fourth step of implanting impurity ions onto the polysilicon film exposed to the second line width; A fifth step of sequentially etching the sacrificial layer and the polysilicon layer overlapping the sacrificial layer; And a sixth step of performing ion implantation to form source / drain regions. 제1항에 있어서, 상기 제2단계는 상기 희생막 상에 역(Reverse) 게이트 마스크를 사용하여 제1감광막 패턴을 형성하는 단계; 상기 제1감광막 패턴을 식각 장벽으로 하여 희생막을 식각하는 단계; 및 상기 제1감광막 패턴을 제거하는 단계를 포함하여 이루어지는 것을 특징으로 하는 트랜지스터 제조 방법.The method of claim 1, wherein the second step comprises: forming a first photoresist pattern on the sacrificial layer using a reverse gate mask; Etching the sacrificial layer using the first photoresist pattern as an etch barrier; And removing the first photoresist pattern. 제1항에 있어서; 상기 제5단계는 게이트 마스크를 사용하여 제2감광막 패턴을 형성하는 단계; 및 상기 제2감광막 패턴을 식각장벽으로 하여 희생막 및 폴리실리콘막을 차례로 식각하는 단계를 포함하여 이루어지는 것을 특징으로 하는 트랜지스터 제조 방법.The method of claim 1; The fifth step may include forming a second photoresist pattern using a gate mask; And etching the sacrificial film and the polysilicon film in sequence by using the second photoresist pattern as an etch barrier.

Priority Applications (1)

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Publications (2)

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ID=19385793

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• 1994
  • 1994-06-21 KR KR1019940014086A patent/KR0140811B1/en not_active IP Right Cessation

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