KR101647559B1 - Method of manufactuing semiconductor package and semiconductor package - Google Patents

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• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
• Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
• Mechanical Treatment Of Semiconductor (AREA)
• Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

Description

Claims (14)

다수의 다이 패드가 형성된 반도체 다이 상에 패시베이션층을 형성하는 단계;
상기 패시베이션층 상에 형성되고, 상기 패시베이션층을 관통하여 상기 다이 패드와 전기적으로 연결되는 재배선층을 형성하는 단계;
상기 재배선층 상에 범프용 임시패턴부재를 배치하고, 소잉할 위치에 소잉용 임시패턴부재를 배치하는 단계;
상기 패시베이션층, 상기 재배선층, 상기 범프용 임시패턴부재 및 상기 소잉용 임시패턴부재가 덮이도록 몰딩부를 형성하는 단계;
상기 범프용 임시패턴부재 및 상기 소잉용 임시패턴부재가 노출되도록 상기 몰딩부를 그라인딩하는 단계;
노출된 상기 범프용 임시패턴부재 및 소잉용 임시패턴부재를 제거하고, 상기 소잉용 임시패턴부재가 제거되어 소잉라인을 형성하는 단계; 및
상기 범프용 임시패턴부재가 제거된 빈 공간을 통해 도전성 범프를 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 패키지의 제조 방법.Forming a passivation layer on a semiconductor die having a plurality of die pads formed therein;
Forming a redistribution layer formed on the passivation layer and electrically connected to the die pad through the passivation layer;
Disposing a temporary pattern member for bumps on the re-wiring layer and disposing a temporary pattern member for thinning at a position to be sown;
Forming a molding portion such that the passivation layer, the re-wiring layer, the temporary pattern member for bump, and the temporary pattern member for covering are covered;
Grinding the molding part to expose the temporary pattern member for bump and the temporary pattern member for ingoing;
Removing the exposed bump temporary pattern member and the exposed temporary pattern member, and removing the temporary temporary pattern member to form a sawing line; And
And forming the conductive bump through an empty space from which the temporary pattern member for bump is removed. 삭제delete 제 1 항에 있어서,
상기 도전성 범프를 형성하는 단계 이후 상기 소잉라인을 따라 상기 반도체 다이를 소잉하는 단계를 더 포함하는 것을 특징으로 하는 반도체 패키지의 제조 방법.The method according to claim 1,
Further comprising sawing the semiconductor die along the sawing line after forming the conductive bump. ≪ RTI ID = 0.0 > 11. < / RTI > 제 1 항에 있어서,
상기 소잉용 임시패턴부재는 포토레지스트 또는 드라이필름을 포함하는 것을 특징으로 하는 반도체 패키지의 제조 방법.The method according to claim 1,
Wherein the temporary pattern member for scribing comprises a photoresist or a dry film. 다수의 다이 패드가 형성된 반도체 다이 상에 패시베이션층을 형성하는 단계;
상기 패시베이션층 상에 형성되고, 상기 패시베이션층을 관통하여 상기 다이 패드와 전기적으로 연결되는 재배선층을 형성하는 단계;
상기 재배선층 상에 범프용 임시패턴부재를 배치하고, 범프용 임시패턴부재가 형성되지 않은 위치에 기준마크용 임시패턴부재를 배치하는 단계;
상기 패시베이션층, 상기 재배선층 및 상기 범프용 임시패턴부재 및 상기 기준마크용 임시패턴부재가 덮이도록 몰딩부를 형성하는 단계;
상기 범프용 임시패턴부재 및 상기 기준마크용 임시패턴부재가 노출되도록 상기 몰딩부를 그라인딩하는 단계;
노출된 상기 범프용 임시패턴부재 및 상기 기준마크용 임시패턴부재를 제거하고, 상기 기준마크용 임시패턴부재가 제거되어 기준마크를 형성하는 단계; 및
상기 범프용 임시패턴부재가 제거된 빈 공간을 통해 도전성 범프를 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 패키지의 제조 방법.Forming a passivation layer on a semiconductor die having a plurality of die pads formed therein;
Forming a redistribution layer formed on the passivation layer and electrically connected to the die pad through the passivation layer;
Disposing a temporary pattern member for a bump on the re-wiring layer and disposing a temporary pattern member for a reference mark at a position where the temporary pattern member for a bump is not formed;
Forming a molding portion such that the passivation layer, the re-wiring layer, the temporary pattern member for the bump, and the temporary pattern member for the reference mark are covered;
Grinding the molding part to expose the temporary pattern member for the bump and the temporary pattern member for the reference mark;
Removing the exposed temporary pattern member for a bump and the temporary pattern member for a reference mark, and removing the temporary pattern member for a reference mark to form a reference mark; And
And forming the conductive bump through an empty space from which the temporary pattern member for bump is removed. 제 5 항에 있어서,
상기 기준마크용 임시패턴부재는 포토레지스트 또는 드라이필름을 포함하는 것을 특징으로 하는 반도체 패키지의 제조 방법.6. The method of claim 5,
Wherein the reference mark temporary pattern member includes a photoresist or a dry film. 제 1 항에 있어서,
상기 범프용 임시패턴부재는 포토레지스트 또는 드라이필름을 포함하는 것을 특징으로 하는 반도체 패키지의 제조 방법.The method according to claim 1,
Wherein the temporary pattern member for bumps includes a photoresist or a dry film. 제 1 항에 있어서,
상기 몰딩부를 그라인딩하는 단계에서 상기 범프용 임시패턴부재의 일부분을 그라인딩하여 상기 몰딩부의 두께를 조절하는 것을 특징으로 하는 반도체 패키지의 제조 방법.The method according to claim 1,
Wherein the thickness of the molding part is adjusted by grinding a part of the temporary pattern member for bump in the step of grinding the molding part. 제 1 항에 있어서,
상기 도전성 범프 및 상기 몰딩부의 접촉면은 상기 도전성 범프의 노출면과 상이한 형태로 이루어진 것을 특징으로 하는 반도체 패키지의 제조 방법.The method according to claim 1,
Wherein the contact surface of the conductive bump and the molding part is different from the exposed surface of the conductive bump. 제 9 항에 있어서,
상기 도전성 범프 및 상기 몰딩부의 접촉면은 상기 범프용 임시패턴부재에 의해 평면으로 형성되는 것을 특징으로 하는 반도체 패키지의 제조 방법.10. The method of claim 9,
Wherein the contact surface of the conductive bump and the molding part is formed in a plane by the temporary pattern member for bump. 제 9 항에 있어서,
상기 도전성 범프의 노출면은 구면으로 형성되는 것을 특징으로 하는 반도체 패키지의 제조 방법.10. The method of claim 9,
Wherein the exposed surface of the conductive bump is formed of a spherical surface. 반도체 다이;
상기 반도체 다이 상에 형성된 패시베이션층;
상기 패시베이션층 상에 형성되고, 상기 패시베이션층을 관통하여 상기 반도체 다이와 전기적으로 연결된 재배선층;
상기 재배선층 상에 배치된 범프용 임시패턴부재;
소잉할 위치에 배치된 소잉용 임시패턴부재; 및
상기 패시베이션층, 상기 재배선층, 상기 범프용 임시패턴부재, 상기 소잉용 임시패턴부재를 덮도록 형성된 몰딩부를 포함하는 것을 특징으로 하는 반도체 패키지.A semiconductor die;
A passivation layer formed on the semiconductor die;
A rewiring layer formed on the passivation layer and electrically connected to the semiconductor die through the passivation layer;
A temporary pattern member for bumps disposed on the re-wiring layer;
A provisional temporary pattern member disposed at a position to be sowed; And
And a molding portion formed to cover the passivation layer, the re-wiring layer, the temporary pattern member for bump, and the temporary pattern member for thinning. 반도체 다이;
상기 반도체 다이 상에 형성된 패시베이션층;
상기 패시베이션층 상에 형성되고, 상기 패시베이션층을 관통하여 상기 반도체 다이와 전기적으로 연결된 재배선층;
상기 재배선층 상에 배치된 범프용 임시패턴부재;
상기 범프용 임시패턴부재가 형성되지 않은 위치에 배치된 기준마크용 임시패턴부재; 및
상기 패시베이션층, 상기 재배선층, 상기 범프용 임시패턴부재, 상기 기준마크용 임시패턴부재를 덮도록 형성된 몰딩부포함하는 것을 특징으로 하는 반도체 패키지.A semiconductor die;
A passivation layer formed on the semiconductor die;
A rewiring layer formed on the passivation layer and electrically connected to the semiconductor die through the passivation layer;
A temporary pattern member for bumps disposed on the re-wiring layer;
A temporary mark temporary pattern member disposed at a position where the temporary bump pattern member is not formed; And
And a molding portion formed to cover the passivation layer, the re-wiring layer, the temporary pattern member for the bump, and the temporary pattern member for the reference mark. 삭제delete

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