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SG10201407347RA - Vias and conductive routing layers in semiconductor substrates - Google Patents

  • ️Tue Dec 30 2014

SG10201407347RA - Vias and conductive routing layers in semiconductor substrates - Google Patents

Vias and conductive routing layers in semiconductor substrates

Info

Publication number
SG10201407347RA
SG10201407347RA SG10201407347RA SG10201407347RA SG10201407347RA SG 10201407347R A SG10201407347R A SG 10201407347RA SG 10201407347R A SG10201407347R A SG 10201407347RA SG 10201407347R A SG10201407347R A SG 10201407347RA SG 10201407347R A SG10201407347R A SG 10201407347RA Authority
SG
Singapore
Prior art keywords
vias
routing layers
semiconductor substrates
conductive routing
dielectric
Prior art date
2009-08-21
Application number
SG10201407347RA
Inventor
Kyle K Kirby
Sarah A Niroumand
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
2009-08-21
Filing date
2010-07-28
Publication date
2014-12-30
2010-07-28 Application filed by Micron Technology Inc filed Critical Micron Technology Inc
2014-12-30 Publication of SG10201407347RA publication Critical patent/SG10201407347RA/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05025—Disposition the internal layer being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13025—Disposition the bump connector being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

VIAS AND CONDUCTIVE ROUTING LAYERS IN SEMICONDUCTOR SUBSTRATES Abstract Through vias and conductive routing layers in semiconductor substrates and associated methods of manufacturing are disclosed herein. In one embodiment, method a for processing a semiconductor substrate includes forming an aperture in a semiconductor substrate and through a dielectric on the semiconductor substrate. The aperture has a first end open at the dielectric and a second end opposite the first end. The method can also include forming a plurality of depressions in the dielectric, and simultaneously depositing a conductive material into the aperture and at least some of the depressions. FIG. 1A -18-

SG10201407347RA 2009-08-21 2010-07-28 Vias and conductive routing layers in semiconductor substrates SG10201407347RA (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US12/545,196 US9799562B2 (en) 2009-08-21 2009-08-21 Vias and conductive routing layers in semiconductor substrates

Publications (1)

Publication Number Publication Date
SG10201407347RA true SG10201407347RA (en) 2014-12-30

Family

ID=43604670

Family Applications (3)

Application Number Title Priority Date Filing Date
SG10201407347RA SG10201407347RA (en) 2009-08-21 2010-07-28 Vias and conductive routing layers in semiconductor substrates
SG2012011094A SG178473A1 (en) 2009-08-21 2010-07-28 Vias and conductive routing layers in semiconductor substrates
SG10201805279PA SG10201805279PA (en) 2009-08-21 2010-07-28 Vias and conductive routing layers in semiconductor substrates

Family Applications After (2)

Application Number Title Priority Date Filing Date
SG2012011094A SG178473A1 (en) 2009-08-21 2010-07-28 Vias and conductive routing layers in semiconductor substrates
SG10201805279PA SG10201805279PA (en) 2009-08-21 2010-07-28 Vias and conductive routing layers in semiconductor substrates

Country Status (7)

Country Link
US (3) US9799562B2 (en)
EP (2) EP2467874B1 (en)
KR (1) KR101427015B1 (en)
CN (1) CN102484095B (en)
SG (3) SG10201407347RA (en)
TW (1) TWI541937B (en)
WO (1) WO2011022180A2 (en)

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US9911693B2 (en) * 2015-08-28 2018-03-06 Micron Technology, Inc. Semiconductor devices including conductive lines and methods of forming the semiconductor devices
US11056443B2 (en) 2019-08-29 2021-07-06 Micron Technology, Inc. Apparatuses exhibiting enhanced stress resistance and planarity, and related methods
US20210335660A1 (en) * 2020-04-24 2021-10-28 Nanya Technology Corporation Semiconductor structure having void between bonded wafers and manufacturing method tehreof
TWI778406B (en) * 2020-08-26 2022-09-21 矽品精密工業股份有限公司 Electronic package and manufacturing method thereof
TWI800977B (en) * 2020-11-11 2023-05-01 南韓商Ｎｅｐｅｓ股份有限公司 Semiconductor package and method for manufacturing the same

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Also Published As

Publication number Publication date
TW201133708A (en) 2011-10-01
SG10201805279PA (en) 2018-07-30
CN102484095B (en) 2017-05-10
US20170372961A1 (en) 2017-12-28
KR101427015B1 (en) 2014-08-05
US9799562B2 (en) 2017-10-24
CN102484095A (en) 2012-05-30
WO2011022180A2 (en) 2011-02-24
TWI541937B (en) 2016-07-11
KR20120068007A (en) 2012-06-26
EP2467874A2 (en) 2012-06-27
EP3792966A1 (en) 2021-03-17
WO2011022180A3 (en) 2011-05-19
SG178473A1 (en) 2012-04-27
US10600689B2 (en) 2020-03-24
EP2467874A4 (en) 2014-10-29
US20110042821A1 (en) 2011-02-24
US20200294854A1 (en) 2020-09-17
EP2467874B1 (en) 2020-11-04

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