201208004 六、發明說明： •【發明所屬之技術領域】 • 本發明内容是關於一個形成面板型態封裝之晶粒埋入 式（embedded dice inside)基板結構；更特別的是擴散式面 板型態封裝（fan-out panei levei package)具有覆蓋於雙面 之重佈層，以增加可靠度和降低此元件的大小（特別是在厚 度方面）。 【先前技術】 在半導體元件的領域中，隨著元件尺寸不斷地縮小， 元件密度也不斷地提高。在封裝或是内部連線方面的技術 需求也必須要提高以符合上述情況。傳統上，在覆晶連接 方法（flip-chip attachment method)中，一焊料凸塊陣列形成 於上述晶粒的表面。上述焊料凸塊的形成可以藉由使用— 焊接複合材料（solder composite material)，經過一焊接點遮 罩（solder mask)來製造出所要的焊料凸塊圖案。晶片封裝 的功旎包含功率傳送（power distributi〇n)、訊號傳送⑻抑U distribution)、散熱（heat dissipation)、保護與支撐等等。备 半導體變的更複雜，傳統的封裝技術，例如導線架封裝 (lead frame package)、收縮式封裝（flex package)、硬式封 裝技術（rigid package technique)，已無法滿足在一個更小 的晶片上製造高密度元件之需求。 再者，因為傳統的封裝技術將晶圓上大的晶粒分成小 的晶粒後，再分別加以封裝。因此，這些技術的製程是耗 時的。至此晶片封裝技術高度地被積體電路的發展所影 201208004 響；所以，隨著電路大小之需求，也產生封裝技術之需求。 依據上述理由’今日的封裝技術的發展趨勢是朝向球狀矩 •陣排列、覆晶、晶片尺寸封裝和晶圓級封裝。“晶圓級封 裝”如同字面上的解釋，就是整個封裝與所有的内部連線 跟其他製程-樣，都是在晶圓在㈣成小晶粒之前被完 成。一般來說，在完成所有組裝與封裝程序後，個別的半 導體封包將從-個晶圓被分成複數個半導體晶粒。此晶圓 級封裝具有極小尺寸與極優電性的結合。 〜藉由晶粒在完整的晶圓上製造與測試，晶圓級封裝技 術是-個先進的封裳技術。之後，上述晶圓被切割成晶粒， 以依照表面鑲嵌線（surf跡m_ Hne)裂配。因為上述 晶圓級封裝技術將整片晶圓當成一個物件來利用，而非利 用二晶片或是晶粒，因此在進行切割程序（scribing 之前，就已經完成封裝與測試。更者，由於晶圓級封裝是 如此先進的技術’所以可以省略打線⑽e bQnding)，黏晶 _咖誠），覆膠（molding)及/或底膠填充（under姻)之技 術。藉由使用晶圓級封裝技術，可以節省成本與製程時間； 且此技術之最終結構與此晶粒一樣；因此，此技術可以滿 足電子元件小型化之需求。 雖然晶圓級封裝技術用有上述的優點，仍有一些存在 的問題，影響著此技術的可接受度。例如，晶圓級封裝技 術中其結構中一材料與主機板此兩材料間之熱膨澡係數差 異；此者成為結構機械性不穩定（mechanical instabiHty)的 關鍵性因素。上述結構之總終端陣列數被晶片大小所限 201208004 制。在切割此晶圓之前，無法使用整片晶圓封裝中曰 I >4 曰日 片及系統級封裝。美國專利6,239,482B1(圖十五）揭露一具 -有機械性彎曲問題之封裝。這是因為前述先前技術將矽晶 片12埋入於上述基板18或是核心區域，而且只用黏著材 料20來支撐上述晶粒12。眾所週知，在機械性彎曲 (mechanical bending)的過程中，由於矽晶粒與基板材料18 以及黏著材料20的硬度（hardness)與材料性質皆有所不 同，此彎曲效應（bending effect)將造成材料邊界破裂，使 重佈層金屬線（RDL)32遭到損壞，可靠度測試㈣咖吻 test)也因此於機械應力項目失效。更者，由於介電層太厚 (*介電層22與16)，以及介電層22、16、金屬3〇與材 等等之間的熱膨滿係數不匹酉己，亦造成不#的可靠度與良 率。-揭露於美國專利6,506,632B1(圖十六）的封褒也面臨 到同樣機構之問題。 ，更者，前述先前技術在形成面板型態封裝時需要複雜 的製程。上述製程需要封裝用覆膠工具（m〇ld t〇〇i)，以及 封裝材料的注射或是注射上述黏著材料的點膠機 (chspenser)。纟於封裝化合物或環氧樹醋㈣〇χγ)在熱固化 之後會翹曲’晶粒與上述化合物的表面難以控制在相同的 水平面，所以需要化學機械研磨製程來研磨此不平的表 面°成本也因此而提高。 【發明内容】 ^發明提供—具有應力緩衝性f與尺讀小化的晶粒 里入式基板結構，來解決上述的問題，並且提供一個較佳 201208004 的主機板級（BGard Level)可靠度測試，例如彎曲、振動測 試等等。 本發明内容之-目的為提供一具有極佳的熱膨漲係數 匹配性能與縮小化尺寸的擴散式面板型態封裝。 本發明之另-目的為提供一擴散式面板型態封裝，其 基板具有晶粒容納開口以改善機械可靠度與縮小元件的尺 寸。 本發明之又-目的為提供—形成面㈣態基板之方 法，以簡易方式將晶粒埋人以重新分配晶粒/晶片與基板， 並填充黏著材料以形成應力緩衝層以黏接數種材料來形成 面板型態基板的結構。 本發明之又一目的為提供一擴散式面板型態封裝，其 具有一重佈層（Redistribution Layers _ RDL)來增加擴散式 導線（fan-out trace)的數目，並且提供系統級封裝（System & Package- SIP)解決方案。因此，透過重佈層來重新分配連 接塾的間距（the pitch of pads)與導電連接線的大小 (dimension of conductive trace) ’本發明可以改善散熱的能 力。 本發明内容揭露一基板結構，包含：一第一基板具有一 晶粒金屬墊（它可以是一墊區域，而且不須要是金屬），導 線圖案形成於兩面（上表面與底表面），一晶粒其背側有黏 著材料，藉此來與上述第一基板中的晶粒金屬墊黏接；一 第二基板具有晶粒容納開口，且其兩面皆有導線圖案；一 黏著材料（應力缓衝材料）被填入於上述晶粒背面與上述 201208004 第一基板上表面之間的間隙；以及上述晶粒側壁與上述晶 •粒容納開口的側壁之間的間隙；以及上述第二基板的背 -侧。本發明更包含形成於基板兩面的重佈層，其中上述基 板的兩面亦包含凸塊底層金屬結構；接下來進行表面鑲嵌 製程，將晶圓級晶片尺寸封裝、晶片尺寸封裝、球狀矩陣 排列/基板陣列矩陣，覆晶等等，與其它被動元件焊接至 上述基板的上表面’形成系統級封裝結構。 前述基板材料包含具環氧樹酯的耐高溫玻璃纖維板， 玻璃纖維板（FR4, FR5)，雙馬來醯亞胺三氮雜苯樹脂 (BT) ’矽’印刷電路板材料，玻璃，或是陶瓷。上述基板 可選擇性地包含合金或金屬。此基板以使用雙馬來醯亞胺 三氮雜苯樹脂（BT)為佳，因為其具有薄細與高玻璃轉換溫 度的材料特性。此材料内含玻璃纖維，所以具有較佳的製 程容許度（process window)。上述材料之熱膨漲係數亦與主 機板相近，大約落在14至17附近。上述黏著材料以使用 矽橡膠為佳，藉由填充來具有較高的延展性、低介電常數、 降低溼度的攝取，以具備應力緩衝特性。上述介電層材料 包含一彈性介電層（elastic dielectric layer)、一感光層 (photosensitive layer)、一矽基介電層（silic〇ne based layer)、一矽氧烷聚合物層（sil〇xane p〇lymer layer)、 一聚醯亞胺層（pi)、一矽樹脂層（Silic〇ne resin layer)。 本發明内容更揭露一形成半導體元件裝的方法，包括： 提供一具有對準標記之工具’而暫時圖案膠形成於上述工 具之上表面；藉由上述對準標記，將一第二基板對準與附 201208004 著於上述暫時圖案膠上面；再次藉由上述對準標記，將一 晶粒對準與附著於上述暫時圖轉上面，配置於上述第二 -基板内部的通道區域。從上述晶粒的背側與上述第二基板 的底側將黏著材料印刷上去；將一第一基板與黏著材料連 接在-起，以形成-面板型態基板（須要靠著對準來使上述 第-基板與晶粒塾的背側相配-通常這可以利用上述第一 與第二基板上的對準目標完成對準的動作）；最後移在除暫 時圖案膠之後，將上述面板型基板與上述工具分開。 上述方法更包含在上述晶粒與上述第二基板的上表面 形成至少一增層，及/或在上述第一基板的底表面。本方法 更包含形成導電穿孔來連接上述第二基板上表面與底表面 的導線，及上述第-基板上表面與底表面的導線。上述晶 粒的連線墊與上述第二基板的孔洞墊利用上述暫時圖案膠 上面的圖案來與其附著。上述對準標記包含一單晶粒對準 標記以及上述第二基板之對準目標。上述晶粒藉由使用一 挑選與放置微對準製程（pick and pIace fine process)來與暫時圖案膠附著。上述面板型態基板藉由一薄 型機械刀片以及或許在加熱條件下（高溫環境）來與上述工 具分開。 本發明揭露一種半導體元件封裝結構，包含一具有一 曰曰粒金屬墊之第一基板，一第一導線電路位於所述第一基 板之上表面和一第二導線電路位於所述第一基板之底表 面，其中所述晶粒金屬墊包含一對準標記；一晶粒配置於 所述晶粒金屬墊之上；一第二基板具有一晶粒容納開口來 201208004 谷納所述晶粒，一第三導線電路位於所述第二基板之上表 面和一第四導線電路位於所述第二基板之底表面，其中所 述晶粒之厚度等於所述第二基板之厚度；以及一黏著層， 填入於所述第一基板之上表面及所述第二基板及所述晶粒 之底表面；以及一第一介電層位於所述晶粒及所述第二基 板之上及所述晶粒側壁及所述晶粒容納開口側壁之間。 本發明更揭露一種形成半導體元件封裝的方法，包含 準備一第一基板及一第二基板，其中所述第一基板包含一 上方具有對準標記之一晶粒金屬墊；使用雷射或沖壓方法 形成晶粒容納開口貫穿於所述第二基板；準備一黏著材 料，利用所述黏著材料將所述第一基板黏著於所述第二基 板上；使用晶粒金屬墊之對準標記將晶粒對準，並以所述 黏著材料將晶粒黏著於晶粒金屬墊上；形成一第一介電層 於第一基板及晶粒之上表面，且將第一介電層推壓入所述 晶粒側壁及所述晶粒容納開口側壁間之間隙於真空狀態； 於第一介電層中形成複數個孔洞區域；以及形成重佈層於 才旻數個孔洞區域及於第*—介電層之上。 【實施方式】 本發明現在將以大量的參考用發明實施例與附加圖示 來加以描述。然而必須要知道是，這些參考用發明實施例 僅供圖示之用。除了這裡提到的參考實施例，本發明可以 在這裡沒有詳細提及之處，以其它廣大範圍的實施例來執 行。而且本發明概念將不被申請專利範圍的說明所侷限。 本發明揭露一個晶粒或多晶片埋入式基板結構；上述 201208004 基板/、有覆盖於一側表面之建構層（dual built up layers)。 圖十二圖示一系統級封裝（system in package)結構的截面 -圖，上述基板具有晶粒埋入式結構、雙邊增層(Rouble side build up layers)、以及被動元件、晶圓級晶片尺寸封裝 (wafer level chip scale package ’ WL-CSP)、晶片尺寸封裝 (chip scale package ’ csp)、球狀矩陣排列（baU gri(J array， BGA)、覆晶（flip_chip)等等。根據本發明内容，表面鑲嵌 位於上部增層，而終端接腳位於對侧。上述封裝結構包含 一具有晶粒金屬墊101 a(以利於傳熱）之第一基板1〇〇，一 導線圖案101位於第一基板1〇〇之上表面，而另一導線圖 案102位於第一基板1〇〇之底表面。一連接導電穿孔i 形成以穿過第一基板丨00來連接導線圖案1〇1、1〇2，此配 置為當作接地或是散熱器（heat sink)之用。一晶粒/晶片j2〇 其责面有黏著材料122，藉此來和第一基板1 〇〇上的晶粒 金屬墊101a附著。上述晶粒12〇其上有鋁墊（輸出/輸入墊） 121。晶粒120配置於第二基板1 〇4之晶粒容納開口，並 且與黏著材料122附著。一第二基板1 〇4位於第一基板j 〇〇 之上’其中晶粒容納開口與一導線圖案105位於第二基板 104之上表面’而另一導線圖案則位於上述第二基板 1 〇4之底表面。上述黏著材料（應力緩衝材料）丨22被填入於 a曰粒120背面與第一基板100上表面之間的間隙；以及晶 粒120侧壁與晶粒容納開口之側壁間的間隙；以及第二基 板104的背側。於晶粒120的底表面印刷、塗膜、或是喷 流黏著材料122 ’藉此將晶粒120密封。在一實施例中， 11 201208004 .黏著材料122覆蓋於第二基板1〇4的上表面、晶粒i2〇除 了鋁墊121 11域之外的表®、第二基板104的孔洞以及增 •層的下方。藉由黏著材料122，晶粒12〇的表面水平面^ 第二基板104的表面水平面是在同一個水平面。一導電穿 孔159貫穿於第一基板1〇〇與第二基板1〇4，以連接第二 基板104上表面與底表面的導線（1〇5與1〇6)及第一基板 1〇〇上表面與底表面的導線（101與1〇2)。在一實施例中， 上述導電穿孔159連接上述晶粒墊1〇la與上述第一基板 1〇〇之底表面導線102，此配置為當作接地和散熱之用。 一第一介電層161形成於晶粒12〇與第二基板1〇4之上， 並且具有一孔洞區域使得孔洞160能形成於其上。以獲得 較佳可靠度為考量，第一介電層161能越薄越好。一重佈 層（RDL)162形成於孔洞16〇與第一介電層161之上以 和孔洞160耦合。第一增層形成於晶粒12〇電路側之上方 與第二基板104表面之上方。一第二（上）介電層163形成 於第一介電層161與重佈層金屬導線162之上，而第二介 電層163具有孔洞區域使得凸塊底層金屬164形成於其 内。第二增層可以形成於第一基板100之底側，或是附蓋 於第一增層之上。這表示第三介電層400形成於第一基板 底表面之導線電路上，而第三介電層具有孔洞區域使得重 佈層形成於其上。焊接金屬墊165形成於金屬凸塊底座201208004 VI. Description of the Invention: • Technical Field of the Invention: The present invention relates to an embedded dice inside substrate structure forming a panel type package; more particularly, a diffused panel type package (fan-out panei levei package) has a double layer covering the double sided to increase reliability and reduce the size of the component (especially in terms of thickness). [Prior Art] In the field of semiconductor elements, as the size of components continues to shrink, the density of components continues to increase. The technical requirements for packaging or internal wiring must also be increased to meet the above conditions. Conventionally, in a flip-chip attachment method, a solder bump array is formed on the surface of the above-described crystal grains. The solder bumps described above can be formed into a desired solder bump pattern by using a solder composite material through a solder mask. The power of the chip package includes power distribution, signal transmission (8), heat dissipation, protection and support. Semiconductors are becoming more complex, and traditional packaging techniques, such as lead frame packages, flex packages, and rigid package techniques, are no longer sufficient for manufacturing on a smaller wafer. The need for high density components. Furthermore, because the conventional packaging technology divides the large crystal grains on the wafer into small crystal grains, they are separately packaged. Therefore, the process of these technologies is time consuming. At this point, the chip packaging technology is highly affected by the development of integrated circuits 201208004; therefore, with the demand for circuit size, there is also a need for packaging technology. For the above reasons, today's packaging technology trends toward spherical matrices, flip-chips, wafer-scale packages, and wafer-level packages. “Wafer-level packaging” is literally explained, that is, the entire package and all internal wiring and other processes are completed before the wafer is (4) into small grains. In general, after completing all assembly and packaging procedures, individual semiconductor packages will be divided into a plurality of semiconductor dies from a wafer. This wafer-level package combines a very small size with excellent electrical properties. ~ Wafer-level packaging technology is an advanced sealing technology by manufacturing and testing die on a complete wafer. Thereafter, the wafer is diced into dies to be split according to surface inlaid lines (surf traces m_Hne). Because the above wafer-level packaging technology uses the entire wafer as an object instead of using two wafers or dies, the packaging process has been completed before the scribing process. Moreover, due to the wafer Level packaging is such an advanced technology 'so that it is possible to omit the technique of wire bonding (10) e bQnding), die bonding, molding and/or underfill. By using wafer-level packaging technology, cost and process time can be saved; and the final structure of this technology is the same as this die; therefore, this technology can meet the needs of miniaturization of electronic components. Although wafer-level packaging technology has the above advantages, there are still some problems that affect the acceptability of this technology. For example, in a wafer-level packaging technology, the thermal expansion coefficient between a material in a structure and a motherboard is different; this is a critical factor in the mechanical instabiHty of the structure. The total number of terminal arrays of the above structure is limited by the size of the chip 201208004. It is not possible to use a full-wafer package with 曰 I > 4 曰 day and system-in-package before cutting this wafer. U.S. Patent 6,239,482 B1 (Fig. 15) discloses a package having mechanical bending problems. This is because the aforementioned prior art embeds the germanium wafer 12 in the above substrate 18 or the core region, and only supports the crystal grains 12 with the adhesive material 20. It is well known that in the mechanical bending process, since the hardness and material properties of the germanium crystal grain and the substrate material 18 and the adhesive material 20 are different, the bending effect will cause the material boundary. The rupture causes the redistribution metal wire (RDL) 32 to be damaged, and the reliability test (4) the kiss test is also invalid in the mechanical stress project. Moreover, since the dielectric layer is too thick (* dielectric layers 22 and 16), and the thermal expansion coefficients between the dielectric layers 22, 16, the metal, the metal, and the like are not comparable, Reliability and yield. - The closures disclosed in U.S. Patent 6,506,632 B1 (Fig. 16) also face problems with the same institutions. Moreover, the aforementioned prior art requires a complicated process in forming a panel type package. The above process requires a coating tool (m〇ld t〇〇i) for encapsulation, and an injection or encapsulation of the encapsulating material or a chspenser for injecting the above-mentioned adhesive material.封装 The encapsulating compound or Epoxy vinegar (IV) 〇χ γ) warps after thermal curing. The surface of the above-mentioned compound is difficult to control at the same level, so a chemical mechanical polishing process is required to grind the uneven surface. Therefore, it is improved. SUMMARY OF THE INVENTION The present invention provides a die-in-substrate structure with stress buffering f and scale reading to solve the above problems, and provides a better board-level (BGard Level) reliability test of 201208004. Such as bending, vibration testing, and the like. SUMMARY OF THE INVENTION It is an object of the present invention to provide a diffused panel type package having excellent thermal expansion coefficient matching performance and reduced size. Another object of the present invention is to provide a diffused panel type package having a substrate having a die receiving opening to improve mechanical reliability and reduce the size of the component. Still another object of the present invention is to provide a method of forming a planar (tetra) substrate by burying the die in a simple manner to redistribute the die/wafer to the substrate and filling the adhesive material to form a stress buffer layer for bonding several materials. To form the structure of the panel type substrate. It is yet another object of the present invention to provide a diffused panel type package having a Redistribution Layers (RDL) to increase the number of fan-out traces and to provide system level packaging (System & Package-SIP) solution. Therefore, the present invention can improve the ability to dissipate heat by redistributing the pitch of pads and the dimension of conductive trace through the redistribution layer. The present invention discloses a substrate structure comprising: a first substrate having a die pad (which may be a pad region and not necessarily a metal), and a wire pattern formed on both sides (upper surface and bottom surface), a crystal The back side has an adhesive material for bonding with the die metal pad in the first substrate; a second substrate has a die receiving opening, and both sides have a wire pattern; an adhesive material (stress buffer a material) is filled in a gap between the back surface of the die and the upper surface of the first substrate of the above 201208004; and a gap between the sidewall of the die and the sidewall of the crystal grain receiving opening; and the back of the second substrate side. The invention further comprises a redistribution layer formed on both sides of the substrate, wherein the two sides of the substrate also comprise a bump underlying metal structure; the surface damascene process is followed by wafer level wafer size packaging, wafer size packaging, spherical matrix arrangement / The substrate array matrix, flip chip, etc., and other passive components are soldered to the upper surface of the substrate to form a system level package structure. The foregoing substrate material comprises a high temperature resistant glass fiber board with epoxy resin, a glass fiber board (FR4, FR5), a bismaleimide triazabenzene resin (BT) '矽' printed circuit board material, glass, or ceramic . The above substrate may optionally comprise an alloy or a metal. This substrate is preferably a bismaleimide triazine resin (BT) because of its material properties of thinness and high glass transition temperature. This material contains glass fibers and therefore has a better process window. The thermal expansion coefficient of the above materials is also similar to that of the main plate, which falls approximately 14 to 17. It is preferable that the above-mentioned adhesive material is made of ruthenium rubber, and has high ductility, low dielectric constant, and reduced humidity uptake by filling to have stress buffering properties. The dielectric layer material comprises an elastic dielectric layer, a photosensitive layer, a silicane based layer, and a siloxane polymer layer. P〇lymer layer), a polyimine layer (pi), a silicon resin layer. The present invention further discloses a method of forming a semiconductor device package, comprising: providing a tool having an alignment mark and temporarily patterning a glue on an upper surface of the tool; and aligning a second substrate by the alignment mark And attached to the above-mentioned temporary pattern glue; and by the alignment mark, a die is aligned and attached to the top surface of the temporary pattern, and is disposed in the channel region inside the second substrate. Printing the adhesive material from the back side of the die and the bottom side of the second substrate; connecting a first substrate and the adhesive material to form a panel type substrate (need to be aligned by the above The first substrate is matched with the back side of the die - - generally this can be done by using the alignment targets on the first and second substrates described above; and finally, after the temporary pattern glue is removed, the above-mentioned panel type substrate is The above tools are separate. The method further includes forming at least one buildup layer on the upper surface of the die and the second substrate, and/or on a bottom surface of the first substrate. The method further includes forming a conductive via to connect the wires of the upper surface and the bottom surface of the second substrate, and the wires of the upper surface and the bottom surface of the first substrate. The wiring pad of the crystal grain and the hole pad of the second substrate are attached thereto by using a pattern on the temporary pattern glue. The alignment mark includes a single-die alignment mark and an alignment target of the second substrate. The die is adhered to the temporary pattern by using a pick and pIace fine process. The above-described panel type substrate is separated from the above tool by a thin mechanical blade and perhaps under heating conditions (high temperature environment). A semiconductor device package structure includes a first substrate having a metal pad, a first wire circuit on an upper surface of the first substrate and a second wire circuit on the first substrate a bottom surface, wherein the die metal pad comprises an alignment mark; a die is disposed on the die metal pad; a second substrate has a die receiving opening to the 201208004 grain, the die a third wire circuit is located on the upper surface of the second substrate and a fourth wire circuit is located on a bottom surface of the second substrate, wherein a thickness of the die is equal to a thickness of the second substrate; and an adhesive layer, Filling the upper surface of the first substrate and the second substrate and the bottom surface of the die; and a first dielectric layer on the die and the second substrate and the crystal The grain sidewall and the die receive the sidewall between the openings. The present invention further discloses a method of forming a semiconductor device package, comprising preparing a first substrate and a second substrate, wherein the first substrate comprises a die metal pad having an alignment mark thereon; using a laser or stamping method Forming a die accommodating opening penetrating the second substrate; preparing an adhesive material, bonding the first substrate to the second substrate by using the adhesive material; and using the alignment mark of the die metal pad to mark the die Aligning, and bonding the die to the die pad with the adhesive material; forming a first dielectric layer on the first substrate and the upper surface of the die, and pushing the first dielectric layer into the die a gap between the sidewall of the grain and the sidewall of the die receiving opening is in a vacuum state; forming a plurality of holes in the first dielectric layer; and forming a redistribution layer in the plurality of holes and the *-dielectric layer Above. [Embodiment] The present invention will now be described with a large number of referenced embodiments of the invention and additional figures. However, it must be understood that these reference embodiments of the invention are for illustrative purposes only. In addition to the reference embodiments mentioned herein, the invention may be practiced in other broad scope embodiments without the details of the invention. Moreover, the inventive concept is not limited by the description of the scope of the claims. The present invention discloses a die or multi-wafer buried substrate structure; the above-mentioned 201208004 substrate/ has a built-in layer covering the one side surface. Figure 12 illustrates a cross-sectional view of a system in package structure having a die buried structure, a double layer build up layers, and a passive component, wafer level wafer size. Wafer level chip scale package ' WL-CSP), chip scale package ' csp ', spherical matrix arrangement (ba gri (J array, BGA), flip chip, etc. according to the present invention The surface inlay is located on the upper build-up layer, and the terminal pin is on the opposite side. The package structure comprises a first substrate 1 having a die pad 101 a (to facilitate heat transfer), and a wire pattern 101 is located on the first substrate 1 〇〇 upper surface, and another wire pattern 102 is located on the bottom surface of the first substrate 1 . A connecting conductive via 1 is formed to connect the wire patterns 1 〇 1 , 1 〇 2 through the first substrate 丨 00, This configuration is used as a grounding or heat sink. A die/wafer j2 has its adhesive material 122, thereby adhering to the die metal pad 101a on the first substrate 1 The above die 12 has an aluminum pad thereon Output/input pad 121. The die 120 is disposed on the die receiving opening of the second substrate 1 〇4 and attached to the adhesive material 122. A second substrate 1 〇4 is located on the first substrate j ' The particle accommodating opening and a wire pattern 105 are located on the upper surface of the second substrate 104 and the other wire pattern is located on the bottom surface of the second substrate 1 。 4. The adhesive material (stress buffer material) 丨 22 is filled in a a gap between the back surface of the particle 120 and the upper surface of the first substrate 100; and a gap between the sidewall of the die 120 and the sidewall of the die receiving opening; and a back side of the second substrate 104. Printed on the bottom surface of the die 120 , the coating film, or the spray adhesive material 122 ' thereby sealing the die 120. In one embodiment, 11 201208004. The adhesive material 122 covers the upper surface of the second substrate 1 〇 4, the grain i2 〇 except aluminum The surface of the pad 121 11 outside the field, the hole of the second substrate 104, and the underside of the layer. The surface level of the die 12 is the same horizontal plane by the adhesive material 122. a conductive via 159 extends through the first base 1〇〇 and the second substrate 1〇4 to connect the wires (1〇5 and 1〇6) of the upper surface and the bottom surface of the second substrate 104 and the wires of the upper surface and the bottom surface of the first substrate 1 (101 and In an embodiment, the conductive vias 159 are connected to the die pad 1A1a and the bottom surface conductors 102 of the first substrate 1b, which are configured for grounding and heat dissipation. A first dielectric layer 161 is formed over the die 12 〇 and the second substrate 〇 4 and has a hole region such that the hole 160 can be formed thereon. In order to obtain better reliability, the thinner the first dielectric layer 161, the better. A redistribution layer (RDL) 162 is formed over the via 16 〇 and the first dielectric layer 161 to couple with the via 160. The first build-up layer is formed over the side of the die 12 〇 circuit and above the surface of the second substrate 104. A second (upper) dielectric layer 163 is formed over the first dielectric layer 161 and the redistribution metal conductor 162, and the second dielectric layer 163 has a void region such that the bump underlayer metal 164 is formed therein. The second build-up layer may be formed on the bottom side of the first substrate 100 or attached to the first build-up layer. This means that the third dielectric layer 400 is formed on the wiring circuit of the bottom surface of the first substrate, and the third dielectric layer has a hole region on which the redistribution layer is formed. A solder metal pad 165 is formed on the metal bump base
Under bump metallurgy)l64 上。焊膏（solder paste)或是焊 接點（導電凸塊）18〇形成於金屬墊丨&上。複數個晶片尺 寸封裝·、晶圓級晶片尺寸封裝、球狀矩陣排列、覆晶以及 12 201208004 被動元件181、182、183藉由焊球㈣丨如^丨⑴⑽焊接於 .金屬墊上；上述金屬墊為增層之電路側（終端金屬墊之對邊） • 之金屬凸塊底座。 "電材料161與163和黏著材料122作為應力緩衝區 域，來吸收晶粒120與第二基板104或是第一基板1〇〇之 間的熱機械應力（thermal mechanical stress);而上述應力是 在溫度循環（temperature cycling)過程中，或是由介電材料 之彈性性質導致之彎曲所造成。上述之系統級封裝建構了 一柵格陣列（land grid array package- LGA)式封裝。 第一基板100與第二基板104之材料以有機基板例如 環氧樹脂（耐高溫玻璃纖維板（FR5)、雙馬來醯亞胺三氮雜 笨樹脂（BT))以及印刷電路板為佳。第一基板1〇〇與第二基 板104之熱膨脹係數與主機板（印刷電路板）一樣為佳。上 述有機基板以具有高玻璃轉換溫度（Tg)之環氧樹脂（耐高 溫玻璃纖維板、雙馬來醯亞胺三氮雜苯樹脂）為佳，上述材 料可以輕易地形成電路圖案以及内部連線穿孔中。金屬銅 之熱膨脹係數大約為16，也可應用於第一與第二基板材料 之中。而玻璃、陶瓷以及矽也可用來當作基板。上述黏著 材料122以矽橡膠基彈性材料為佳。 上述環氧樹脂（对高溫玻璃纖維板、雙馬來醢亞胺三氮 雜本樹脂）之有機基板的熱膨脹係數在X/Y方向約為 14〜17,在Z方向約為30〜60,因此可以選擇熱膨脹係數與 上述基板相近之晶粒重新分佈工具；如此可以降低黏著材 料在溫度固化過程中晶粒位移問題。如果溫度循環的高溫 13 201208004 階段接近玻璃轉換溫度，上述耐高溫玻璃纖維板/雙馬來酿 亞胺三氮雜苯樹脂在溫度循環之後似乎無法回到原先的位 置。在面板型態封裝的製程中需使用到幾個高溫製程，例 如介電材料與黏著材料的溫度固化製程等等；如果使用材 料的熱膨脹係數不匹配，則會造成面板形式中的晶粒位移。 上述第一與第二基板可以為圓形，例如晶圓形式，其 直徑可以是200mm、30〇mm或是更高。上述第一與第二基 板也可以是矩形例如面板的形式。其尺寸最好為基板/軟^ 電路板（flexible printed circuit)製程時的大小，因為如此可 以完全地使用到上述基板/軟性電路板製造機台，同時亦可 降低單位成本。 在本發明之一實施例中，第一與第二介電層（161和 163)以彈性介電材料為佳’彈性介電材料為碎氧烧聚合 物、dow corning wl5000系列及其組合所構成之矽橡膠基 介電材料。在另-實施例中，第—與第二介電層（161和163) 由聚醯亞胺（polyimides)或石夕膠基樹脂⑽ic〇ne 所構成。第-與第二介電層⑽# 163)以簡單製程所形成 之感光層為佳。 在本發明之-實施例中，彈性介電層為一種材料其熱 膨脹係數大於l〇〇(ppm/QC)，延展率大約為百分之四十（在 百刀之二十至百分之五十之間為佳），而上述材料的硬度界 於塑膠與橡敎fa1。上述彈性介電層的厚度端視溫度循環 測試時累積於重佈層/介電層介面之應力而定。 在本發明之-實施例中，上述重佈層材料包含欽_ 14 201208004 金合金或是鈦/銅/鎳/金合金，而重佈層之厚度在2um至 15um之間的範圍（如果有需要，可以增加厚度至25um)。 Ti/Cu合金係利用濺鍍（sputtering)技術所形成，可做為種晶 金屬層；而Cu/Au合金或是Cu/Ni/Au合金則是利用電鍍 技術所形成。使用電鍍製程來形成重佈層可使其具有足夠 的厚度與較佳的機械性質，以抵抗在溫度循環和機械彎曲 的過輊中的熱膨係數不匹配。上述金屬墊可以為金屬鋁或 金屬銅或其組合。 本發明内容中形成具有埋入式晶粒基板結構之製程， 包含：準備一第一基板100與一第二基板1〇4(以玻璃纖維 板（FR4)/时高溫玻璃纖維板（FR5)/雙馬來醯亞胺三氮雜苯 樹脂（BT)之原料為佳）；及用來#料線電路圖案分別形 成於第一基板1〇〇之上與底表面之接觸金屬墊1〇1、1〇2; 以及用來當料線電路，分卿成第三基板iQ4之上與底 表面之接觸金屬* 1G5、1()6,如圖—所示。接觸金屬塾 101 102 105、106和基板之晶粒金屬墊i J a可以用電 鑛銅/鎳/金結構的方法來形成。上述連結導電穿孔⑻可 以形成以貫穿第-基板i⑼，連接晶粒金屬墊⑻&與接觸 金屬塾1G2,以利於接地與散熱器（其可在製作基板之過程 被預先製造）。晶粒容納開口 1〇7利用雷射切割或是機械沖 床(多晶粒沖床)製做為每邊稍大於晶粒大小加上大約 100um至200um，如圖二所示。上述開口之深度與晶粒厚 度相近（或多厚約為25um)。 步為提ί、工具11 〇，為了對晶粒/基板作定位與 15 201208004 對準’ S具有對準標記（alignmentkey)ln(位於單一晶粒之 上）與暫時圖案膠（temp〇rary pattern以㈣川2形成於工具 • 110之上表面，如圖三所示。上述工具11〇之對準標記lu 包含單晶粒對準標記與第二基板刚之對準目#。暫時圖 案膠112以覆蓋於紹墊與基板之金屬孔洞為佳但其須要 平衡設計以維持晶粒在一平坦之水準。暫時圖案膠ιΐ2被 印刷（或點膠）於工纟11〇之上以黏著晶粒與第二基板之表 面。暫時圖案膠具有圖案以附著晶粒】2〇之鋁焊墊12!以 及第二基板104之孔洞金屬墊丨〇5。 之後，本發明之製程包含第二基板1〇4與工具11〇之 暫時圖案膠112之對準與附著，舉例而言，接觸金屬墊1〇5 可藉由對準與暫時圖案膠112附著，如圖四所示。接下來， 晶粒依據接下來的步驟製備，包含晶背研磨至所要的厚 度，舉例而言為127或200微米；透過藍膠膜152(biuetape) 將晶圓附著於一框架15〇上，再沿著切割線153將框架15〇 上之晶粒151切割，最後以映像⑼邛口“㈡的方式將晶圓加 以區分，如圖九所示。具有晶粒墊121之晶粒12〇對準（藉 由對準標記111)並附著至其面朝下工具11〇之暫時圖案膠 112之上；其中晶粒藉由使用挑選與放置微對準系統，被 對準與放置到工具上；上述挑選與微對準系統具有覆晶的 功能，能將晶粒以期望的間距重新分配至工具上，如圖五 所示。上述暫時圖案膠U2黏附第二基板1〇4晶粒容納開 口内之晶粒120(於主動表面側）於工具丨丨〇之上。接下來， 印刷一黏者材料（填充材料）122，例如彈性核心膠體材料 201208004 (elashc core paste materia〇至晶粒12〇之背侧與第二基板 之底侧。上述填充材料122被填充於晶粒l2〇之間之空間 (間隙）’覆蓋於晶12〇晶粒背側以及第二基板之底側，如 圖六所不。黏著材料122以能夠覆蓋接觸金屬墊之表面為 佳105。接下來，第一基板1〇〇真空附著至黏著材料122， 如圖七所示。固化製程利用紫外線或熱固化法，將黏著材 料122固化，以連接第一基板1〇〇。面板焊接（B〇ndin幻機 為用來將第一基板100焊接至第二基板1〇4與晶粒12〇之 背侧，以形成一部件。上述部件之厚度13〇可以被控制。 完成真空焊接後，接著移除暫時圖案膠112，再將工具1〇〇 從上述部件中分開，以形成面板基板（具有内埋式晶粒 120、第一基板100、第二基板以及黏著材料122)，如圖八 所不。上述面板基板分離方法包含將上述物件放置於加熱 板上或是烤箱中，當烤箱的溫度約於1〇〇〇c時，上述暫時 圖案膠112會變得柔軟並且喪失黏著性，然後施加一外力 於上述面板基板之邊緣，同時使用一薄型機械刀片14〇來 將面板基板相同邊緣之暫時圖案膠丨12到除；因此面板基 板與工具110分開，如圖七A所示。此外，可以使用溶劑 來清除面板基板以移除暫時圖案膠殘留物。在一實施例 中’暫時圖案膠之材料包含聚二曱基矽氧烷樹脂 (polydimethy-siloxane gum)和樹脂分散劑（resin dispersion) ° 上述面板基板與工具110分開之後，執行一清潔势 程；藉由施加一濕式及/或乾式（電漿）清潔來清洗晶粒之表 17 201208004 面。在上述面板基板形成後，接下來的製程為在晶粒 二基板104之上表面形成增層結構，如圖十所示。也 •取另-種選擇，在第-基板i⑽之底侧形成增層結構；可 以在利用基板/軟性電路板製程的同時形成上層與底層辦 層結構。形成增層結構的第一步為利用旋轉/喷霧的方曰式: 塗膜或是形成一第一介電層於電路側。第一介電層於 是形成於晶粒120與第二基板1〇4之上方，第一介胃電層16;! 具有孔洞160形成於其中，利用曝光、顯影、固化步驟之 微影製程可以暴露出紹連接塾121(晶粒輸入/輸出塾）和接 觸金屬墊105(基板輸入/輸出墊），在某些例子中，需要蝕 刻製程。隨後執行電漿清潔步驟來清洗孔洞與鋁墊之表 面。接下來執行電腦數值控制（c〇mputer numedeai coiitro卜CNC)鑽孔或是雷射鑽孔，在第二基板1〇4之上 接觸金屬墊105至第一基板100之下接觸金屬墊1〇6之間 形成穿孔；接著填充導電材料，例如銅（Cu)於上述穿孔， 以形成導電穿孔159。上述導電穿孔159為形成以連接第 二基板104之上與下導線電路和第一基板1〇〇之上與下導 線電路。下一步再濺鍍上鈦/銅作為種子金屬層16〇於第一 介電層161、孔洞及穿孔之上。之後，在第一介電層i6l 與種晶金屬層160之上塗佈光阻（可以使用乾膜層），接著 再對光阻加以曝光、顯影，以形成重佈金屬層之圖案。然 後，再執行電鍍製程以形成銅/金或銅/鎳/金之重佈層金 屬。最後，利用剝除上述光阻以及濕蝕刻法形成重佈層金 屬線162於種晶金屬層160上。一般而言，上述製程可以 18 201208004 同時建構出上述導電穿孔159與重佈層。 接著，是將一第二（上）介電層塗膜、印刷、或壓膜於 -上述第一介電層161與重佈層金屬線162上。上述第二介 電層163因此形成於第一介電層ι61與重佈層金屬線ι62 上，並且其中具有金屬凸塊底座孔洞。利用曝光、顯影、 固化步驟之微影製程可以暴露重佈層金屬線162，在某些 例子中需要蝕刻製程。下一步再濺鍍鈦/銅（〇 〇5/〇 3um)作 為種晶金屬層164於第二介電層i63及金屬凸塊底座孔洞 之上。接著，在第二介電層163與種晶金屬層164塗佈上 光阻（乾膜壓層）’接著再對上述光阻加以曝光、顯影以形 成焊接金屬墊之圖案。然後，再執行電鍍製程，以在種晶 金屬層（種晶金屬層）164上形成銅/鎳/金（3/3/0.2um)之焊接 金屬墊165。最後，再剝除上述光阻，以金屬濕蝕刻法來 清洗焊接金屬墊165。可重複上述之種晶層、光阻及電鍍 或剝除/1虫刻製程’以在面板基板之單面及/或兩面形成多 層重佈層與介電層。 之後’可將面板型態基板切割成子面板型態基板以進 行最終測試。舉例而言，將二十英吋大小之面板丨7〇切割 成四片十英吋大小之子面板171，如圖十一所示。接下來， 將焊接球植入或焊接點18〇印刷於焊接金屬墊165上。印 刷元知接球植入或是焊接膠（s〇lder paste)後，在焊接球側 (對球狀矩陣型封裝而言）執行一熱回流（heat refl〇w)製 程。接著’利用傳統焊接製程，將用於晶圓級晶片尺寸封 裝、晶片尺寸封裝、球狀矩陣排列、覆晶等封裝之被動元 19 201208004 件如電容182、電阻183以及其他晶粒181附著於晶粒120 之電路之上（重佈層之上）之焊接點18〇,如圖十二所示。上 述之子面板171可再被切割成複數個單元。接下來，執行 測試。模組化最終測試可以藉由使用垂直的或環氧樹脂探 針卡接觸該終端金屬墊102來執行。在一實施例中，為了 電磁抗擾（EMI)之目的，可在電容182、電阻183與其它晶 粒181上方覆蓋金屬覆蓋物184，如圖十三所示。上述面 板型基板200之單元基板結構可以參考圖十四，其包含晶 粒201，第一基板203，其上側與底侧具有導線電路；一 第一基板202，其具有晶粒容納開口、上側與底側之導線 電路，和黏著材料（應力緩衝層）2〇4。測試結束後，上述封 裝分別被挑選與放置於托盤（Tray)、膠帶式滾筒（Tape& Reel)。 本發明之另一實施例係一球狀矩陣排列封裝之最終終 端形式，如圖十七與圖十八所示。圖十七與圖十八中的封 裝結構皆包含上侧增層與底側增層。上述上側增層與底侧 增層之形成皆與圖十和圖十三相其述描述之細節在此 被省略。上述底側增層包含一介電層4〇〇、孔洞樹、重佈 層4〇2、一介電層403、孔洞（金屬凸塊底座）404以及焊 接球405。上述焊接球405為藉由印刷的方式形成於上述 孔/同（金屬凸塊底座）404之上。 本發明之另-實施例係堆疊至少兩個具有埋入式晶粒 (可以為多晶粒)之基板’其具有導電穿孔以内連接電信 號’如圖十九所示。圖十九的封裝結構包含一晶粒12〇、 20 201208004 曰曰粒600具有一 |g焊接墊6〇3、上側增層、中增層以及 底側增層，上述上侧增層、中增層以及底側增層之形成與 圖十與圖十—相似’其描述之細節在此被省略0上側增層 包含一介電層606、孔洞604、重佈層6〇5及一介電層6〇7S。 上述晶粒/晶片600之背侧具有黏著材料（應力緩衝 層）601，並附著於第二基板丨〇4之晶粒墊丨之上。介電 層607上可以選擇性地形成一上核心膠體62〇。上述導電 穿孔159可以藉由電腦數值控制鑽孔或是雷射鑽孔來形 成0 請參考圖二十，係為本發明之另一實施例。所述半導 體兀件封裝包含一第一基板700，所述第一基板7〇〇具有 一導線電路7 01及一具有對準標記之晶粒金屬墊7 〇丨a位於 其上表面，另具有一導線電路7〇2位於其底表面。一連接 導電穿孔703係設置於第一基板700，以連接晶粒金屬墊 701 a及導線電路702，用以接地及散熱。此外，半導體元 件封裝包含一第二基板7〇4。所述第二基板7〇4具有一導 線電路705位於其上表面，及一導線電路7〇6於其底表面， 及具有一容納晶粒720之晶粒容納開口。晶粒720之上表 面設置有連接墊721。連接墊721之材料可使用銘 (aluminum)。於本發明之一實施例中，晶粒720之厚度可 實質上約等於第二基板704之厚度。 一黏著材料722係設置於第一基板700之上表面，以 及第一基板704與晶粒720之底表面，用以將晶粒72〇及 第一基板704黏著於第一基板700之上。本發明之一實施 21 201208004 例中，黏著材料722可使用乾膜式。黏著層722之厚度約 為10至30 μιη。在一實施例中，黏著材料722可為透明， .以作為發光應用。導電穿孔759形成於從導線電路7〇2至 導線電路705之間，藉由貫穿第一基板7〇〇及第二基板7〇4 所形成，且所述導電穿孔759係填滿導電材料，用以連接 第二基板704之導線電路705、706及第一基板7〇〇之導線 電路 701、702。 一具有複數個孔洞區域760之第一介電層723係設置 於第二基板704及晶粒720之上表面，且設置於晶粒72〇 側壁及晶粒容納開口側壁之間。本發明之一實施例中，第 一介電層723之材料可為乾膜式或液態介電材料。一重佈 層761係設置於孔洞區域76〇内及第一介電層上，用 以耦合連接墊721與導線電路705，更進一步通過導線電 路7〇5耦合至導電穿孔759。一第二介電層762係設置於 第一介電層723及重佈層761上。在一實施例中，第一介 電層723及第二介電層762可為透明，以作為發光應用。 一上標記，例如一商標或部分號碼，可利用雷射或印刷方 法’形成於第二介電層762，且柵袼陣列式（LGA type)封裝 或球狀矩陣排列式（BGA type)封裝的終端墊可形成於導線 電路702上。請參考圖二十八，於本發明擴散式球狀矩陣 排列封裝之一實施例中，數個開口設置於第二介電層 2用以配置金屬凸塊底座於其中，以及複數個焊球7⑽ 可設置於所述金屬凸塊底座上。一標記，例如一商標或部 分數字，可使用導線電路7〇2形成於第一基板7〇〇之底表 22 201208004 面。 …請參考圖二十-至圖二十七，係描述本發明之一種形 成半導體元件封裝方法的另一實施例。首先，準備—第一 基板700及-第二基板7G4。所述第—基板具有一導 線電路701及一具有對準標記之晶粒金屬墊位於其上 表面，且具有一導線電路7〇2位於其底表面。而所述第二 基板704具有一導線電路7〇5位於其上表面，且具有一導 線電路位於其底表面，如圖二十一所示。 其次，利用雷射或沖壓方法於所述第二基板7〇4上彤 成=晶粒容納開口 707，如圖二十二所示。接著，準備二 黏著材料722，如圖二十三所示。利用上述黏著材料722， 將所述第-基板7〇〇黏著於所述第二基板彻於真空狀 如圖一十四所示。接著，使用晶粒金屬墊701a之對準 標，，將晶粒720對準，並利用黏著材料722之附著力， 將j粒720黏著於該晶粒金屬墊7〇la，如圖二十五所示。 接著’將黏著材料722硬化。 接著，形成第一介電層723於第二基板7〇4及晶粒72〇 之上表面，且將所述第一介電層723推壓入晶粒720側壁 ^晶粒容納開口 707侧壁間之間隙，如圖二十六所示，其 :真滿第一基板704之粗糖度，且可控制第一介電層之最 後$面平整度。不需填滿晶粒側壁及不具有導電穿孔之晶 ^谷4開π側壁間的間隙’因為所述導電穿孔可為真空狀 態，其將不會影響溫度循環的問題。接著，使用光學處理 或雷射开）成第一介電層723之孔洞區域，如圖二十七所 23 201208004 示。接著，將第一介電層723硬化。其他形成重佈層、導 電穿孔、第二介電層等之程序係類似於上述實施例之敘 ' 述’故在此省略。 '•月參考圖一十九，本發明一實施例中，可於形成介電 層之前，形成一發光材料791，例如磷（ph〇sph〇r)，於晶粒 720之上，作為發光應用，以及形成一反射層，例如銀 (Ag)、金（Au)或鋁（A1)，於晶粒容納開口 7〇7側壁及晶粒 金屬墊701a之上，作為發光應用，以加強光反射因子。在 一實施例中，發光材料791可覆蓋於晶粒72〇上。在一實 施例中，可將反射層電錄於晶粒容納開口 7 〇 7側壁及晶粒 金屬墊701a上。 本發明内容的優點為： 上述製程可以輕易的形成面板型結構，並且輕易的控 制面板的粗糙（平整）度。上述基板之厚度可以被輕易的= 制，而且在製程中也可以排除晶粒位移之問題。可以省^ 射出成型工具；也不須導入化學機械研磨製程；本製程也 不會產生麵曲。藉由面板型態封裝製程，上述面板型基板 可以輕易地被完成。上述增層底下材料(主機板和基板土)埶 膨脹係數的匹配可以使具有較佳可靠度，並且在基板之 Χ/Υ方向也不會產生熱應力，彈性介電材料的使用；以吸 收ζ方向之應力。單元材料在分離（切割）的過程中會被切 割。 上述基板被預置為具有預先形成之晶粒容納開口 部連線穿孔(如果這是需要的)以及終端接觸金屬(對有機 24 201208004 基板而言）；上述晶粒容納開口之尺寸為每邊比晶粒之大小 增加約1 OOum〜20〇um，藉由填充彈性核心膠體，上述開口 •可以作為應力緩衝釋放區域，吸收由矽晶粒與基板（耐高溫 玻璃纖維板/雙馬來醯亞胺三氮雜苯樹脂）之間熱膨脹係數 不匹配，所造成之熱應力。此外，也可以在晶粒與基板側 壁間隙之間填充彈性介電材料，以吸收由熱膨脹係數不匹 配所造成之機械彎曲及/或熱應力。由於同時在上表面與底 表面施加上述簡單增層，故可增加封裴生產率（減少製造週 期）。上述終端墊形成於晶粒主動表面之對邊。 上述晶粒之放置製程係使用挑選與放置製程。在本發 明中，彈性核心膠體（樹脂、環氧樹脂化合物、石夕橡膠等等） 被回填於晶粒邊緣與穿孔側壁間之間隙，之後與第一基板 連接以成為熱應力之釋放緩衝，最後再執行真空熱固化。 面板形成之過程克服熱膨脹係數不匹配問題。上述晶粒與 基板之間的深度差約為25um，而介電層與重佈層皆形成於 面板之上與底表面。只有石夕橡膠介電材料（以石夕氧烧材料為 佳）被塗佈於主動表面與基板表面（以玻璃纖維板/耐高溫 玻璃纖維板/雙馬來醯亞胺三氮雜苯樹脂為佳）。由於介電 層為一感光層，接觸金屬墊可藉由光罩製程而被打開。上 述晶粒與基板（包括第一與第二基板）連接在-起。上述封 裝與主機板（母板）級封裝之可靠度也比以前更好。特別對 主機板級封裝溫度循環測試而言，由於基板與印刷電路板 (母板）之熱膨脹係n故不會有任何施加於焊接凸塊/ 球之熱機械應力；對主機板級封裝機械,彎曲測試而言，支 25 201208004 樓機械強度之機板底側可以吸收基板上側之晶粒區域斑邊 界區域之應力；具有保護功能之封裝結構，其厚度相當薄， 其不會超過20〇um〜3〇〇um。其成本低廉而製程簡單。該製 程也能夠輕易地形成複數晶粒封裝（可以一個接著一個地 將晶粒埋入面板基板以形成複數晶粒封裝）。 雖然本發明之參考實施例已被加以描述，然而對該領 域具有通常知識者應能理解本發明内容不被上述之實施例 所限制。再者，在本發明之精神與概念範疇内，可以提出 各種變化與修正。本發明由下述專利申請範圍所定義。 【圖示簡單說明】 圖一根據本發明之實施例’圖示一未加工基板其結構 之截面圖。 圖二根據本發明之實施例，圖示一具有晶粒容納開口 的基板之戴面圖。 圖三根據本發明之實施例’圖示一晶粒重新分配工具 之截面圖，工具之上表面有對準圖案與暫時膠。 圖四根據本發明之實施例，圖示一具有晶粒容納開口 的第二基板，其與工具相連結的截面圖。 圖五根據本發明之實施例，圖示一具有晶粒容納開口 並且與工具相連結之第二基板與一晶粒的截面圖。 圖六根據本發明之實施例，圖示黏著性材料填充入面 板型基板的截面圖。 圖七根據本發明之實施例，圖示第一基板與黏著性材 料真空連接的截面圖。 26 201208004 圖七A根據本發明之實施例，圖示面板型基板與工具 分開的截面圖。 圖八根據本發明之實施例，圖示一晶粒埋入式之面板 型基板。 圖九根據本發明之實施例，圖示位於導線型封裝上的 未加工晶圓之俯視圖。 圖十根據本發明之實施例，圖示一晶粒埋入式側邊增 層基板之俯視圖。 圖十一根據本發明之實施例，圖示被切成子面板型基 板以進行焊接與最終測試的面板型基板之俯視圖。 圖十二根據本發明之實施例，圖示系統級封裝結構之 截面圖。 圖十三根據本發明之實施例’圖示金屬覆蓋物附著於 系統級封襞表面之截面圖。 圖十四根據本發明之實施例，圖示一基板結構之截面 圖。 圖十五圖示一先前技術之截面圖。 圖十六圖示一先前技術之截面圖。 圖十七根據本發明之實施例，圖示一晶粒埋入式基板 之截面圖，其雙面增層以球狀矩陣排列的形式位於上表面 與底表面。 圖十八根據本發明之實施例，圖示一球狀矩陣排列形 式的系統級封裝之橫截面圖。 圖十九根據本發明之實施例，圖示一堆疊式結構之多 27 201208004 晶封裝之截面圖。 圖二十根據本發明之另一實施例，圖示一半導體元件 封裝之橫截面圖。 ,圖—十一至圖二十七根據本發明之另一實施例，圖示 形成一半導體元件封裝之方法的流程圖。 —圖二十八根據本發明之擴散型球狀矩陣排列式之一 貫施例：圖示一半導體元件封裝之橫截面圖。 ㈣圖I十九根據本發明之—實施例，圖示—半導體元件 封裝之橫戴面圖。 【主要元件符號說明】 介電層 基板材料 黏著材料 介電層 金屬 重佈層 第一基板 導線圖案 101a晶粒金屬塾 102 導線圖案 103導電穿孔 104第二基板 105 導線圖案 106 導線圖案 18 20 22 30 32 100 101 107 110 111 112 120 121 122 粒容納開口 工具 對準標記 暫時圖案膠 晶粒/晶片 在呂塾 黏著材料/應力緩衝料 曰曰 料 130 厚度 140薄型機械刀片 150 框架 151 晶粒 152 藍膠膜 153晝線槽 28 201208004 159 導電穿孔 600 晶粒 160 孔洞/種晶金屬層 601 黏著材料/應力 - 161 第一介電層 603 鋁質接線墊 162 重佈層金屬線 604 孔洞 163 第二介電層 605 重佈層 164 種晶金屬層/金屬凸塊 606 介電材料 底座 607 介電層 165 焊接金屬墊 620 核心膠體 170 面板 700 第一基板 171 子面板 701導線電路 180 焊接點 701a 晶粒金屬塾 181 晶粒 702導線電路 182 電容 703連接導電穿孔 183 電阻 704第二基板 184 金屬覆蓋物 705導線電路 202 第二基板 706導線電路 203 第一基板 707 E ?曰粒容納開口 204 黏著材料/應力緩衝層 720晶粒 400 介電層 721連接墊 401 孔洞 722黏著材料 402 重佈層 723第一介電層 403 介電層 759導電穿孔 404 孔洞/金屬凸塊底座 760孔洞區域 405 焊接球 761重佈層 緩衝層 29 201208004 790反射層 762第二介電層 * 780焊球 30Under bump metallurgy) l64. Solder paste or solder joints (conductive bumps) 18 are formed on the metal pads & Multiple wafer size packages, wafer level wafer size packages, spherical matrix arrangements, flip chip and 12 201208004 passive components 181, 182, 183 are soldered to metal pads by solder balls (4) such as ^1(1)(10); The metal bump base for the circuit side of the layer (the opposite side of the terminal metal pad). "Electrical materials 161 and 163 and adhesive material 122 act as stress buffer regions to absorb thermal mechanical stress between the die 120 and the second substrate 104 or the first substrate 1; During the temperature cycling process, or caused by the bending caused by the elastic properties of the dielectric material. The system-in-package described above constructs a land grid array package (LGA) package. The material of the first substrate 100 and the second substrate 104 is preferably an organic substrate such as epoxy resin (high temperature resistant glass fiber board (FR5), bismaleimide triazole resin (BT)), and a printed circuit board. The thermal expansion coefficients of the first substrate 1 and the second substrate 104 are preferably the same as those of the motherboard (printed circuit board). The above organic substrate is preferably an epoxy resin (high temperature resistant glass fiber board, bismaleimide triazabenzene resin) having a high glass transition temperature (Tg), and the above materials can easily form circuit patterns and internal wiring perforations. in. The metallic copper has a thermal expansion coefficient of about 16, and can also be applied to the first and second substrate materials. Glass, ceramics and tantalum can also be used as substrates. The above adhesive material 122 is preferably a ruthenium rubber-based elastic material. The thermal expansion coefficient of the organic substrate of the above epoxy resin (for high-temperature glass fiber board or bismaleimide triazole resin) is about 14 to 17 in the X/Y direction and about 30 to 60 in the Z direction, so A grain redistribution tool having a thermal expansion coefficient close to that of the above substrate is selected; this can reduce the grain displacement problem of the adhesive material during temperature curing. If the temperature cycle of the high temperature 13 201208004 stage is close to the glass transition temperature, the above-mentioned high temperature resistant fiberglass board/double-male yttrium triazine resin does not seem to return to its original position after the temperature cycle. In the process of panel type packaging, several high temperature processes are required, such as temperature curing process of dielectric material and adhesive material, etc. If the thermal expansion coefficient of the material is not matched, the grain displacement in the panel form is caused. The first and second substrates may be circular, such as in the form of a wafer, and may have a diameter of 200 mm, 30 mm or more. The first and second substrates described above may also be in the form of a rectangle such as a panel. The size is preferably the size of the substrate/flexible printed circuit process, because the above substrate/flexible circuit board manufacturing machine can be used completely, and the unit cost can be reduced. In an embodiment of the invention, the first and second dielectric layers (161 and 163) are preferably made of an elastic dielectric material, the elastic dielectric material is a oxy-fired polymer, a dow corning wl5000 series, and combinations thereof. Then rubber-based dielectric materials. In another embodiment, the first and second dielectric layers (161 and 163) are composed of polyimides or lycopene-based resins (10). The first and second dielectric layers (10) # 163) are preferably formed by a simple process. In an embodiment of the invention, the elastic dielectric layer is a material having a coefficient of thermal expansion greater than 10 〇〇 (ppm/QC) and an elongation of about 40% (20 to 5% in a hundred knives) Ten is better), and the hardness of the above materials is bounded by plastic and rubber fa1. The thickness of the above-mentioned elastic dielectric layer depends on the stress accumulated in the redistribution layer/dielectric layer interface during the temperature cycle test. In the embodiment of the present invention, the redistribution layer material comprises a gold alloy or a titanium/copper/nickel/gold alloy, and the thickness of the redistribution layer is in the range of 2 um to 15 um (if necessary) , can increase the thickness to 25um). The Ti/Cu alloy is formed by a sputtering technique and can be used as a seed metal layer; and the Cu/Au alloy or the Cu/Ni/Au alloy is formed by electroplating. The use of an electroplating process to form the redistribution layer provides sufficient thickness and better mechanical properties to resist thermal expansion coefficient mismatch in temperature cycling and mechanical bending. The above metal mat may be metal aluminum or metal copper or a combination thereof. The process of forming a buried die structure in the present invention comprises: preparing a first substrate 100 and a second substrate 1 (4) (glass fiber plate (FR4) / time high temperature glass fiber board (FR5) / double horse The raw material of the yttrium triazine resin (BT) is preferably used; and the contact metal pattern formed on the first substrate 1 与 and the bottom surface is respectively formed on the first substrate 1 〇 1, 1 〇 2; and used as the material line circuit, divided into the third substrate iQ4 contact with the bottom surface of the metal * 1G5, 1 () 6, as shown. The contact metal lands 101 102 105, 106 and the grain metal pad i J a of the substrate can be formed by a method of electroforming copper/nickel/gold structure. The connecting conductive vias (8) may be formed to penetrate the first substrate i (9) to connect the die metal pads (8) & and the contact metal pads 1G2 to facilitate grounding and heat sinks (which may be pre-fabricated in the process of fabricating the substrate). The grain receiving opening 1〇7 is made by laser cutting or mechanical punching (multi-grain punching) as slightly larger than the grain size on each side plus about 100um to 200um, as shown in Fig. 2. The depth of the opening is similar to the grain thickness (or about 25 um thick). Steps to improve, tool 11 〇, in order to position the die/substrate with 15 201208004 alignment 'S has an alignment key ln (above a single die) and a temporary pattern glue (temp〇rary pattern (4) Chuan 2 is formed on the upper surface of the tool 110, as shown in Fig. 3. The alignment mark lu of the above tool 11 includes the single-grain alignment mark and the alignment of the second substrate. It is better to cover the metal holes of the mat and the substrate, but it needs to be balanced to maintain the grain at a flat level. The temporary pattern glue ΐ2 is printed (or dispensed) on the workpiece 11以 to adhere the die and the first The surface of the two substrates. The temporary pattern glue has a pattern to adhere the aluminum pad 12! and the hole metal pad 5 of the second substrate 104. Thereafter, the process of the present invention comprises the second substrate 1〇4 and The alignment and adhesion of the temporary pattern glue 112 of the tool 11 is, for example, the contact metal pad 1〇5 can be attached to the temporary pattern glue 112 by alignment, as shown in FIG. 4. Next, the die is followed by Step preparation, including crystal back grinding to the desired thickness Degrees, for example, 127 or 200 microns; the wafer is attached to a frame 15 through a blue film 152, and the die 151 on the frame 15 is cut along the cutting line 153, and finally imaged. (9) The method of "(2)" distinguishes the wafers, as shown in Fig. 9. The die 12 with the die pad 121 is aligned (by the alignment mark 111) and attached to its face down tool 11 Temporarily patterned over the glue 112; wherein the dies are aligned and placed onto the tool by using a pick and place micro-alignment system; the above-described pick and micro-alignment system has a flip chip function to enable the die to be desired The pitch is redistributed to the tool, as shown in Fig. 5. The temporary pattern glue U2 adheres to the second substrate 1 〇4 grain accommodating opening in the die 120 (on the active surface side) above the tool 。. , printing a sticky material (filling material) 122, such as elastic core colloidal material 201208004 (elashc core paste materia 〇 to the back side of the die 12 与 and the bottom side of the second substrate. The above filling material 122 is filled in the crystal grain l2 The space between the ( (gap) 'covers the crystal 12〇 The back side of the grain and the bottom side of the second substrate are as shown in Fig. 6. The adhesive material 122 preferably covers the surface of the contact metal pad 105. Next, the first substrate 1 is vacuum-attached to the adhesive material 122, as shown in the figure. 7. The curing process uses ultraviolet or thermal curing to cure the adhesive material 122 to connect the first substrate 1 . Panel soldering (B〇ndin is used to solder the first substrate 100 to the second substrate 1) 〇4 and the back side of the die 12〇 to form a part. The thickness 13〇 of the above components can be controlled. After the vacuum welding is completed, the temporary pattern glue 112 is removed, and the tool 1〇〇 is separated from the above parts. To form a panel substrate (having a buried die 120, a first substrate 100, a second substrate, and an adhesive material 122), as shown in FIG. The method for separating the panel substrate comprises placing the object on a heating plate or an oven. When the temperature of the oven is about 1 〇〇〇c, the temporary pattern adhesive 112 becomes soft and loses adhesion, and then an external force is applied. At the edge of the above-mentioned panel substrate, a thin mechanical blade 14 is simultaneously used to bond the temporary pattern of the same edge of the panel substrate to the top; therefore, the panel substrate is separated from the tool 110, as shown in FIG. In addition, a solvent can be used to remove the panel substrate to remove temporary pattern glue residue. In one embodiment, the material of the temporary patterning gel comprises a polydimethy-siloxane gum and a resin dispersion. After the panel substrate is separated from the tool 110, a cleaning potential is performed; The surface of the wafer is cleaned by applying a wet and/or dry (plasma) cleaning. After the above-mentioned panel substrate is formed, the next process is to form a build-up structure on the upper surface of the die-substrate 104, as shown in FIG. Also, another alternative is to form a build-up structure on the bottom side of the first substrate i (10); the upper and lower layer structures can be formed while using the substrate/flexible circuit board process. The first step in forming the build-up structure is to use a spin/spray method: a film or a first dielectric layer on the circuit side. The first dielectric layer is then formed over the die 120 and the second substrate 1〇4, and the first gastro-electric layer 16 has a hole 160 formed therein, which can be exposed by a lithography process of exposure, development, and curing steps. The connection port 121 (die input/output port) and the contact pad 105 (substrate input/output pad) are provided, and in some examples, an etching process is required. A plasma cleaning step is then performed to clean the surface of the hole and the aluminum pad. Next, computer numerical control (c〇mputer numedeai coiitrob CNC) drilling or laser drilling is performed, and the metal pad 105 is contacted on the second substrate 1〇4 to contact the metal pad 1〇6 under the first substrate 100. Perforations are formed therebetween; a conductive material, such as copper (Cu), is then applied to the perforations to form conductive vias 159. The conductive vias 159 are formed to connect the upper and lower via circuits of the second substrate 104 and the upper and lower conductive circuits of the first substrate 1 . Next, titanium/copper is sputtered as a seed metal layer 16 over the first dielectric layer 161, the holes and the perforations. Thereafter, a photoresist is applied over the first dielectric layer i6l and the seed metal layer 160 (a dry film layer may be used), and then the photoresist is exposed and developed to form a pattern of the redistributed metal layer. The electroplating process is then performed to form a copper/gold or copper/nickel/gold re-layered metal. Finally, a redistribution metal line 162 is formed on the seed metal layer 160 by stripping the photoresist and wet etching. In general, the above process can simultaneously construct the above-mentioned conductive vias 159 and redistribution layers 18 201208004. Next, a second (upper) dielectric layer is coated, printed, or laminated onto the first dielectric layer 161 and the redistribution metal line 162. The second dielectric layer 163 is thus formed on the first dielectric layer ι61 and the redistribution metal line ι62, and has a metal bump base hole therein. The redistribution metal line 162 can be exposed using a lithography process of exposure, development, and curing steps, which in some instances requires an etch process. Next, titanium/copper (〇 5/〇 3 um) is sputtered as a seed metal layer 164 over the second dielectric layer i63 and the metal bump base holes. Next, a photoresist (dry film laminate) is applied to the second dielectric layer 163 and the seed metal layer 164. Then, the photoresist is exposed and developed to form a pattern of a solder metal pad. Then, an electroplating process is performed to form a copper/nickel/gold (3/3/0.2 um) solder metal pad 165 on the seed metal layer (seed metal layer) 164. Finally, the above photoresist is stripped again, and the solder metal pad 165 is cleaned by metal wet etching. The seed layer, the photoresist, and the plating or stripping process can be repeated to form a multi-layer redistribution layer and a dielectric layer on one side and/or both sides of the panel substrate. The panel type substrate can then be cut into sub-panel type substrates for final testing. For example, a twenty-inch panel 丨7〇 is cut into four 10-inch-sized sub-panels 171, as shown in FIG. Next, the solder ball implant or solder joint 18 〇 is printed on the solder metal pad 165. After the printing of the ball or the solder paste, a heat refl〇 process is performed on the solder ball side (for the spherical matrix type package). Then, using the conventional soldering process, the passive element 19 201208004 for wafer level wafer package, wafer size package, spherical matrix arrangement, flip chip, etc., such as capacitor 182, resistor 183 and other die 181 attached to the crystal The solder joint 18 之上 above the circuit of the granule 120 (above the redistribution layer) is shown in Fig. 12. The sub-panel 171 described above can be further cut into a plurality of units. Next, execute the test. The modular final test can be performed by contacting the terminal metal pad 102 using a vertical or epoxy probe card. In one embodiment, metal cover 184 may be overlying capacitor 182, resistor 183, and other crystal grains 181 for electromagnetic immunity (EMI) purposes, as shown in FIG. Referring to FIG. 14 , the unit substrate structure of the panel substrate 200 may include a die 201 , a first substrate 203 having a wire circuit on an upper side and a bottom side thereof, and a first substrate 202 having a die receiving opening and an upper side. The wire circuit on the bottom side, and the adhesive material (stress buffer layer) 2〇4. After the test is completed, the above packages are individually selected and placed on a tray (Tray & Reel). Another embodiment of the present invention is the final terminal form of a spherical matrix array package, as shown in Figures 17 and 18. The package structures in Figures 17 and 18 contain both the upper side and the bottom side layer. The details of the formation of the upper side and the bottom side layers described above with respect to Figs. 10 and 13 are omitted herein. The bottom side buildup layer includes a dielectric layer 4, a hole tree, a redistribution layer 4, a dielectric layer 403, a hole (metal bump base) 404, and a solder ball 405. The solder ball 405 is formed on the hole/same (metal bump base) 404 by printing. Another embodiment of the present invention stacks at least two substrates having buried dies (which may be multi-grain) having conductive vias to interconnect the telecommunications numbers as shown in FIG. The package structure of FIG. 19 includes a die 12 〇, 20 201208004 曰曰 granule 600 has a | g solder pad 6 〇 3, an upper side buildup layer, a middle buildup layer, and a bottom side buildup layer, the upper side buildup layer, the middle increase The formation of the layer and the underside enhancement layer is similar to that of FIG. 10 and FIG. 10, the details of which are omitted here. The upper side enhancement layer comprises a dielectric layer 606, a hole 604, a redistribution layer 6〇5 and a dielectric layer. 6〇7S. The back side of the above die/wafer 600 has an adhesive material (stress buffer layer) 601 and is attached to the die pad of the second substrate 丨〇4. An upper core colloid 62〇 can be selectively formed on the dielectric layer 607. The conductive via 159 can be formed by computer numerically controlled drilling or laser drilling. Referring to Figure 20, another embodiment of the present invention is shown. The semiconductor device package includes a first substrate 700 having a wire circuit 071 and a die metal pad 7 〇丨a having an alignment mark on an upper surface thereof, and a further The wire circuit 7〇2 is located on its bottom surface. A connection conductive via 703 is disposed on the first substrate 700 to connect the die metal pad 701a and the wire circuit 702 for grounding and heat dissipation. Further, the semiconductor device package includes a second substrate 7?4. The second substrate 7〇4 has a wire circuit 705 on its upper surface, and a wire circuit 7〇6 on its bottom surface, and has a die receiving opening for accommodating the die 720. A connection pad 721 is disposed on the upper surface of the die 720. The material of the connection pad 721 can be made of aluminum. In one embodiment of the invention, the thickness of the die 720 can be substantially equal to the thickness of the second substrate 704. An adhesive material 722 is disposed on the upper surface of the first substrate 700 and the bottom surfaces of the first substrate 704 and the die 720 for adhering the die 72 and the first substrate 704 to the first substrate 700. One embodiment of the present invention 21 201208004 In the example, the adhesive material 722 can be a dry film type. The thickness of the adhesive layer 722 is about 10 to 30 μm. In an embodiment, the adhesive material 722 can be transparent, for use as a lighting application. The conductive via 759 is formed between the wire circuit 7〇2 and the wire circuit 705, and is formed through the first substrate 7〇〇 and the second substrate 7〇4, and the conductive via 759 is filled with a conductive material. The wire circuits 705, 706 of the second substrate 704 and the wire circuits 701, 702 of the first substrate 7 are connected. A first dielectric layer 723 having a plurality of holes 760 is disposed on the second substrate 704 and the upper surface of the die 720, and disposed between the sidewalls of the die 72 and the sidewall of the die receiving opening. In one embodiment of the invention, the material of the first dielectric layer 723 can be a dry film or liquid dielectric material. A layer 761 is disposed in the hole region 76 and on the first dielectric layer for coupling the connection pad 721 and the wire circuit 705, and further coupled to the conductive via 759 by the wire circuit 7〇5. A second dielectric layer 762 is disposed on the first dielectric layer 723 and the redistribution layer 761. In an embodiment, the first dielectric layer 723 and the second dielectric layer 762 can be transparent for use as a lighting application. An upper mark, such as a trademark or part number, may be formed by laser or printing method on the second dielectric layer 762, and in a gated array (LGA type) package or a ball matrix array type (BGA type) package. A termination pad can be formed on the wire circuit 702. Referring to FIG. 28, in one embodiment of the diffused spherical matrix array package of the present invention, a plurality of openings are disposed in the second dielectric layer 2 for arranging the metal bump base therein, and a plurality of solder balls 7 (10) It can be disposed on the metal bump base. A mark, such as a trademark or a portion of the number, can be formed on the bottom surface of the first substrate 7 by using a wire circuit 7〇2. Referring to Figures 20 to 27, another embodiment of the method of forming a semiconductor device of the present invention will be described. First, the first substrate 700 and the second substrate 7G4 are prepared. The first substrate has a wire circuit 701 and a die metal pad having an alignment mark on an upper surface thereof, and has a wire circuit 7〇2 on a bottom surface thereof. The second substrate 704 has a wire circuit 7〇5 on its upper surface and a wire circuit on its bottom surface, as shown in FIG. Next, a grain receiving opening 707 is formed on the second substrate 7?4 by a laser or a stamping method, as shown in Fig. 22. Next, a second adhesive material 722 is prepared, as shown in Fig. 23. The first substrate 7 is adhered to the second substrate by vacuum as shown in FIG. Next, using the alignment mark of the grain metal pad 701a, the die 720 is aligned, and the j-particle 720 is adhered to the die metal pad 7〇la by the adhesion of the adhesive material 722, as shown in FIG. Shown. Next, the adhesive material 722 is hardened. Next, a first dielectric layer 723 is formed on the upper surface of the second substrate 7〇4 and the die 72〇, and the first dielectric layer 723 is pushed into the sidewall of the die 720 and the sidewall of the die receiving opening 707. The gap between the two, as shown in Fig. 26, is: the full sugar content of the first substrate 704, and can control the final surface flatness of the first dielectric layer. There is no need to fill the grain sidewalls and the gaps between the π sidewalls of the crystals without conductive vias. Because the conductive vias can be in a vacuum state, they will not affect the temperature cycling problem. Next, optical processing or laser opening is used to form the hole region of the first dielectric layer 723, as shown in Fig. 27, 201208004. Next, the first dielectric layer 723 is hardened. Other procedures for forming the redistribution layer, the conductive via, the second dielectric layer, and the like are similar to those of the above embodiment and are omitted herein. Referring to FIG. 19, in an embodiment of the present invention, a luminescent material 791, such as phosphorus (ph〇sph〇r), may be formed on the die 720 as a light-emitting application before forming the dielectric layer. And forming a reflective layer, such as silver (Ag), gold (Au) or aluminum (A1), on the sidewalls of the die receiving opening 7〇7 and the grain metal pad 701a, as a light-emitting application to enhance the light reflection factor . In one embodiment, luminescent material 791 can be overlying die 72. In one embodiment, the reflective layer can be electrically recorded on the sidewalls of the die receiving opening 7 〇 7 and the die pad 701a. The advantages of the present invention are as follows: The above process can easily form a panel type structure and easily control the roughness (flatness) of the panel. The thickness of the above substrate can be easily determined, and the problem of grain displacement can be eliminated in the process. It is possible to dispense with the molding tool; it is not necessary to introduce a chemical mechanical polishing process; the process does not produce a surface curvature. The above-mentioned panel type substrate can be easily completed by the panel type packaging process. The matching of the expansion coefficient of the underlying material (main board and substrate soil) can provide better reliability and no thermal stress in the Χ/Υ direction of the substrate, and the use of elastic dielectric material; The stress of the direction. The unit material is cut during the separation (cutting) process. The substrate is preset to have a pre-formed die-receiving opening portion of the via (if this is required) and the terminal contact metal (for the organic 24 201208004 substrate); the die-receiving opening has a size per side ratio The size of the crystal grains is increased by about 1 00 um to 20 〇 um. By filling the elastic core colloid, the above opening can be used as a stress buffer release region, which is absorbed by the ruthenium crystal grains and the substrate (high temperature resistant glass fiber slab / bismaleimide III) The thermal expansion coefficient between the azabenzene resins does not match, resulting in thermal stress. Alternatively, an elastic dielectric material may be filled between the die and the substrate side wall gap to absorb mechanical bending and/or thermal stress caused by a mismatch in thermal expansion coefficients. Since the above simple build-up is applied to both the upper surface and the bottom surface, the sealing productivity can be increased (the manufacturing cycle is reduced). The terminal pads are formed on opposite sides of the active surface of the die. The above-described die placement process uses a pick and place process. In the present invention, the elastic core colloid (resin, epoxy resin compound, Shishi rubber, etc.) is backfilled in the gap between the edge of the die and the sidewall of the perforation, and then connected to the first substrate to become a release buffer for thermal stress, and finally Vacuum heat curing is then performed. The process of panel formation overcomes the problem of thermal expansion coefficient mismatch. The difference in depth between the die and the substrate is about 25 um, and both the dielectric layer and the redistribution layer are formed on the upper and lower surfaces of the panel. Only Shixi rubber dielectric material (preferably as the Xixi oxy-combustion material) is applied to the active surface and the substrate surface (glass fiberboard/high temperature resistant glass fiberboard/double-maleimide triazabenzene resin is preferred) . Since the dielectric layer is a photosensitive layer, the contact metal pad can be opened by the photomask process. The die is connected to the substrate (including the first and second substrates). The reliability of the above package and motherboard (motherboard) package is also better than before. Especially for the motherboard-level package temperature cycle test, there is no thermal mechanical stress applied to the solder bump/ball due to the thermal expansion of the substrate and the printed circuit board (motherboard); In terms of bending test, the bottom side of the mechanical strength of the board 25 201208004 can absorb the stress in the boundary area of the grain area on the upper side of the substrate; the package structure with protection function is quite thin, and it will not exceed 20 〇 um~ 3〇〇um. Its cost is low and the process is simple. The process can also easily form a plurality of die packages (the die can be buried one after the other into the panel substrate to form a plurality of die packages). While the present invention has been described, it should be understood by those of ordinary skill in the art that the present invention is not limited by the embodiments described above. Further, various changes and modifications can be made within the spirit and concept of the invention. The invention is defined by the scope of the following patent application. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional view showing the structure of an unprocessed substrate according to an embodiment of the present invention. Figure 2 is a perspective view of a substrate having a die receiving opening, in accordance with an embodiment of the present invention. Figure 3 illustrates a cross-sectional view of a die re-distribution tool having an alignment pattern and temporary glue on the upper surface of the tool in accordance with an embodiment of the present invention. Figure 4 illustrates a cross-sectional view of a second substrate having a die receiving opening coupled to a tool, in accordance with an embodiment of the present invention. Figure 5 is a cross-sectional view of a second substrate and a die having a die receiving opening and coupled to a tool, in accordance with an embodiment of the present invention. Figure 6 is a cross-sectional view showing the filling of an adhesive material into a panel type substrate in accordance with an embodiment of the present invention. Figure 7 is a cross-sectional view showing the vacuum connection of the first substrate to the adhesive material in accordance with an embodiment of the present invention. 26 201208004 Figure 7A is a cross-sectional view showing the panel type substrate separated from the tool according to an embodiment of the present invention. Figure 8 illustrates a die-embedded panel-type substrate in accordance with an embodiment of the present invention. Figure 9 is a top plan view of a raw wafer on a wire type package, in accordance with an embodiment of the present invention. Figure 10 is a top plan view of a die embedded side edge buildup substrate in accordance with an embodiment of the present invention. Figure 11 is a plan view of a panel-type substrate cut into a sub-panel type substrate for soldering and final testing, in accordance with an embodiment of the present invention. Figure 12 is a cross-sectional view showing a system-in-package structure in accordance with an embodiment of the present invention. Figure 13 is a cross-sectional view showing the attachment of a metal covering to a system-level sealing surface in accordance with an embodiment of the present invention. Figure 14 is a cross-sectional view showing a substrate structure in accordance with an embodiment of the present invention. Figure 15 illustrates a cross-sectional view of a prior art. Figure 16 illustrates a cross-sectional view of a prior art. Figure 17 is a cross-sectional view showing a die-embedded substrate in which double-sided buildup layers are arranged in a spherical matrix arrangement on the upper surface and the bottom surface, in accordance with an embodiment of the present invention. Figure 18 is a cross-sectional view showing a system-in-package of a spherical matrix arrangement in accordance with an embodiment of the present invention. Figure 19 is a cross-sectional view of a 201200004 crystal package in accordance with an embodiment of the present invention. Figure 20 is a cross-sectional view showing a semiconductor device package in accordance with another embodiment of the present invention. Figure 11 - Figure 27 is a flow chart illustrating a method of forming a semiconductor device package in accordance with another embodiment of the present invention. - Figure 28 is a cross-sectional view of a semiconductor device package according to the present invention. (d) FIG. 19 is a cross-sectional view of a semiconductor component package in accordance with an embodiment of the present invention. [Main component symbol description] Dielectric layer substrate material Adhesive material Dielectric layer Metal redistribution layer First substrate conductor pattern 101a Grain metal 塾102 Conductor pattern 103 Conductive via 104 Second substrate 105 Conductor pattern 106 Conductor pattern 18 20 22 30 32 100 101 107 110 111 112 120 121 122 Grain accommodating opening tool Alignment mark Temporary pattern glue granule / wafer in 塾 塾 adhesive material / stress buffer material 130 130 thickness 140 thin mechanical blade 150 frame 151 grain 152 blue glue Membrane 153 昼 槽 28 201208004 159 Conductive perforation 600 Grain 160 hole / seed metal layer 601 Adhesive material / stress - 161 First dielectric layer 603 Aluminum wiring pad 162 Re-layer metal wire 604 Hole 163 Second dielectric Layer 605 redistribution layer 164 seed metal layer / metal bump 606 dielectric material base 607 dielectric layer 165 solder metal pad 620 core colloid 170 panel 700 first substrate 171 sub-panel 701 wire circuit 180 solder joint 701a grain metal 塾181 die 702 wire circuit 182 capacitor 703 is connected to the conductive via 183 resistor 704 second substrate 184 metal cover 705 wire circuit 202 second substrate 706 wire circuit 203 first substrate 707 E 曰 grain receiving opening 204 adhesive material / stress buffer layer 720 die 400 dielectric layer 721 connection pad 401 hole 722 adhesive material 402 redistribution layer 723 first Dielectric layer 403 dielectric layer 759 conductive perforation 404 hole / metal bump base 760 hole area 405 solder ball 761 rediscus buffer layer 29 201208004 790 reflective layer 762 second dielectric layer * 780 solder ball 30