A7 B7 五、發明説明（l ) 發明所屬的技術分野 本發明乃關於一種非揮發性半導體元件及其製造方 法，詳細是指透過電晶體的構造變更，得到非揮發性記 憶單元（memory cell)之高集積化的非揮發性半導體元件 及其製造方法。 習知之技術 非揮發性半導體元件，在電氣上可以作資料的消除 與儲存，具有即使沒有電源的供給，也可以作資料的保 存之特長，所以，最近，在多種分野上，擴大其應用範 圍。 此種非揮發性半導體元件，依記憶體單元列陣之不 同’大致區分為NAND型及NOR型，各有高集中化與高速 性的優缺點，在多種地方其使用都不斷的增加。 經濟部中央標準局員工消費合作社印製 其中，與本發明有直接相關的NOR型非揮發性半導 艘元件’其特徵在於：在一條位元線上，並聯連接多.數 個艘單元電晶嫌’而在連接於位元線的汲極與源極 線之間，只連接一個單元電晶體，可增大記憶體單元的 電流’且可以作高速動作；相反的，因為在位元線上， 並聯連接記憶艘單元電晶體’所以，在閱讀所選擇的單 元時’相鄰共通位元線的單元會被消去甚多，而記憶嫌 單元電晶體的Vth比外加到非選擇單元的第2閘電極的電 壓（例如Ον)還低，這時候會產生，不管選擇單元是 還是OFF，電流會流通，而全部的單元，會被讀成〇1^單 元的錯誤動作（read-disturbance)。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X29?公釐） A7 B7 五、發明説明（2 ) 為了在構造上解決最近的錯誤動作產生，在製造非 揮發性半導體元件的記憶體單元時，在汲極與源極線之 間’追加一個電晶體，成為由2個電晶體構成一個記憶體 單元。 第9至16圖，為習知NOR型非揮發性半導體元件的製 造方法之步驟順序圖’以下就詳細來說明該製造方法β 如第9圖所示，在半導體基板10上的所定部分形成場 (field)氧化膜12，區分為非活性領域及活性領域。 如第10圖所示，在半導體基板10上的活性領域，形 成閘絕緣膜14,在其上形成感光膜式樣（pattern ) w， 以露出所定部分的前述閘絕緣膜14的表面之後，在表面 露出的閘絕緣膜14上，打入離子雜質，在基板1〇内，形 成第 1接合領域（junction area) 18a。 經濟部中央棣隼局負工消費合作杜印製 (請先W讀f·面之ii-意事項再填寫本頁) 如第11圖所示，除去感光膜式樣（pattern ) 16，露 出所定部分的第1接合領域18a上的基板1〇表面，將附絕 緣膜14選擇蝕刻之後，在該蝕刻部分，形成比閘極絕緣 膜14薄的通道（tunnel)絕緣膜20。結果，形成於中央部 的通道絕緣膜20,會形成由在其周圍所形成的閘絕緣膜14 包圍的構造之式樣（pattern )。 如第12圖所示，在包含場氧化膜12與通道絕緣膜20 的閘絕緣膜14上，形成多晶矽材質的第1導電性膜22。 如第13圖所示，在第1導電性膜22全面形成層間絕緣 膜24,為了讓單元與單元之間的浮置閘（floating gate)分 開’露出場氧化膜12表面的所定部分，選擇蝕刻未圖示 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） A7 B7 經濟部中央標率局員工消費合作社印製 五、發明説明（ 的縱向（在圖面上將紙面穿透的方向）層間絕緣联24及 第1導電性膜22。在參照符號A_，為了助於了解，是層 間絕緣膜24及第1導電性膜22所定部分蚀刻處理的狀態， 以第13圖的假想線所棵§己的部分，由上所見的平面圓。 如第14圖所示’在包含場氡化膜12表面露出部的層 間絕緣膜24上’形成多晶石夕材質的第2導電性膜26» 如第15圈所示，以氧化膜作為蝕罩，將第2導電性膜 26、層間絕緣膜24及第1導電性膜22作選擇蝕刻以露出所 定部分的閘絕緣膜14表面。結果，在形成通道絕緣膜2〇 與第1接合領域的部分之基板10上，會經由層間絕緣膜24 ’形成疊層第1導電性膜材質的浮置閘22a與第2導電性膜 材質的控制閘（controller gate) 26a構造的感知電晶體（ sense transistor)，在其一側的半導體基板1〇上，經由層 間絕緣膜24’形成疊層第1導電性膜材質的浮置閘22&與 第2導電性膜材質的控制閘26a構造的選擇電晶體（sel.ect transistor)。 如第16圖所示，在閘極絕緣膜14的表面露出部，打 入離子雜質，在與第丨接合領域18a相鄰部分的基板1〇内 部，有一部分會與選擇電晶嫌重疊（over lap )，形成第 1接合領域18b，而在感知電晶體一側的基板〗〇内部，形 成源極領域28，在選擇電晶體側的基板1〇内部，形成汲 極領域3 0，並結束步称。 其結果’就完成了以下構造之非揮發性半導體元件 :在具備場氧化膜12的半導體基板10上的活性領域，形 ^1. - - - I si I 1 8 — 衣 I I - ^—a 1 (請先閲讀t面之注_$項再填寫本頁)A7 B7 V. Description of the invention (l) Technical field to which the invention belongs The present invention relates to a non-volatile semiconductor element and a method for manufacturing the same. In detail, the structure of a transistor is changed to obtain a non-volatile memory cell. Highly integrated non-volatile semiconductor device and manufacturing method thereof. Known technology Non-volatile semiconductor devices can be used to delete and store data electrically. They have the advantage of saving data even without power supply. Therefore, recently, the scope of application has been expanded in various fields. Such non-volatile semiconductor elements are roughly divided into NAND type and NOR type according to the difference of the memory cell array, each having the advantages and disadvantages of high concentration and high speed, and its use is increasing in various places. Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs, the NOR-type non-volatile semi-conductive ship element 'which is directly related to the present invention is characterized in that it is connected in parallel on a bit line. 'And between the drain and source lines connected to the bit line, only one unit transistor is connected, which can increase the current of the memory cell' and can operate at high speed; on the contrary, because on the bit line, in parallel Connect the memory cell transistor '. Therefore, when reading the selected cell, the cells of the adjacent common bit line will be eliminated a lot, and the Vth of the memory cell transistor is added to the second gate electrode of the non-selected cell. The voltage (such as Ον) is still low. At this time, no matter whether the selected unit is OFF or not, current will flow, and all the units will be read as read-disturbance of 〇1 ^ unit. This paper size applies the Chinese National Standard (CNS) A4 specification (210X29? Mm) A7 B7 V. Description of the invention (2) In order to solve the recent erroneous actions in construction, when manufacturing non-volatile semiconductor memory cells Add a transistor between the drain and source lines to form a memory cell with two transistors. FIGS. 9 to 16 are sequence diagrams of a conventional method for manufacturing a NOR-type nonvolatile semiconductor device. The manufacturing method is described in detail below. As shown in FIG. 9, a field is formed on a predetermined portion of the semiconductor substrate 10. The (field) oxide film 12 is divided into an inactive area and an active area. As shown in FIG. 10, a gate insulating film 14 is formed in an active area on the semiconductor substrate 10, and a photosensitive film pattern w is formed thereon to expose a predetermined portion of the surface of the gate insulating film 14 on the surface. Ion impurities are implanted on the exposed gate insulating film 14 to form a first junction area 18 a in the substrate 10. Du printed by the Central Government Bureau of the Ministry of Economic Affairs and consumer cooperation (please read the f. Face ii-intentions before filling out this page) As shown in Figure 11, remove the photosensitive film pattern 16 and expose the specified part After the surface of the substrate 10 on the first bonding region 18a is selectively etched, a tunnel insulating film 20 thinner than the gate insulating film 14 is formed in the etched portion. As a result, the channel insulating film 20 formed in the center portion forms a pattern of a structure surrounded by the gate insulating film 14 formed around the channel insulating film 20. As shown in FIG. 12, a first conductive film 22 made of polycrystalline silicon is formed on the gate insulating film 14 including the field oxide film 12 and the channel insulating film 20. As shown in FIG. 13, an interlayer insulating film 24 is formed on the first conductive film 22 in its entirety. In order to separate the floating gates between the cells, a predetermined portion of the surface of the field oxide film 12 is exposed, and etching is selected. Not shown This paper size applies to Chinese National Standards (CNS) A4 specifications (210X297 mm) A7 B7 Printed by the Staff Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention ( Orientation) The interlayer insulation 24 and the first conductive film 22. The reference symbol A_, for the purpose of understanding, is the state of the etching treatment of the predetermined portions of the interlayer insulation film 24 and the first conductive film 22, with the imaginary line in FIG. 13 The second part is circled from the plane seen above. As shown in FIG. 14, a second conductive film made of polycrystalline silicon is formed on the interlayer insulating film 24 including the exposed portion of the surface of the field polarization film 12. 26 »As shown in the 15th circle, the second conductive film 26, the interlayer insulating film 24, and the first conductive film 22 are selectively etched with the oxide film as an etching cover to expose a predetermined portion of the surface of the gate insulating film 14. Result In the formation of the channel insulation film 20 and the first 1 On the substrate 10 in the part of the bonding area, a floating gate 22a of a first conductive film material and a controller gate 26a of a second conductive film material are formed via an interlayer insulating film 24 '. A sense transistor is formed on one side of the semiconductor substrate 10 through the interlayer insulating film 24 'to form a floating gate 22 & and a control gate 26a made of a second conductive film. Sel.ect transistor. As shown in FIG. 16, an ion impurity is implanted in the exposed portion of the surface of the gate insulating film 14, and inside the substrate 10 adjacent to the junction area 18a, Some of them will overlap with the selected transistor to form the first junction region 18b. Inside the substrate on the sensing transistor side, a source region 28 is formed, and inside the substrate on the selected transistor side 10. , Forming the drain region 30, and ending the step scale. As a result, a non-volatile semiconductor device having the following structure is completed: an active region on a semiconductor substrate 10 having a field oxide film 12 is shaped as ^ 1.--- I si I 1 8 — 衣 II- ^ —A 1 (please read the note _ $ item on t side before filling in this page)
經濟部中央標準局貝工消費合作社印掣 A7 B7 五、發明説明（4 ) 成閘極絕緣媒14’使基板1〇表面會露出一定的部分，在 該閘極絕緣膜14間表面露出部分的基板1〇上，會形成比 前述閘極絕緣膜14薄的通道絕緣膜2〇,在通道絕緣膜2〇 與其周圍的閘極絕緣膜14上所定部分，會經由層間絕緣 膜24，形成由浮置閘22a與控制閘26a積疊所構成的感知 電晶體，而感知電晶體一側的前述閘極絕緣膜14上所定 部分，會形成和感知電晶體一樣的積疊構造之選擇電晶 雜，在通道絕緣膜20下方的基板1〇内部，會形成第1接合 領域18a’在該第1接合領域iga的一側，形成與選擇電晶 體一部分重疊（over lap)的第2接合領域18b，在場氧化 膜12與感知電晶體間的空間領域之基板1〇内部，會形成 源極領域28，在場氧化膜12與選擇電晶體間的空間領域 之基板10内部，會形成連結位元線的汲極領域3〇β 因此’前述構造的非揮發性半導體元件，會依下述 方法進行與資料的儲存、消除及判讀作業相關的一逄串 動作。此時’與資料的储存相關的去除（erase )及與資 料的消除相關的程式（program)就會依FN通道（f0wler_ nordheim tunnel)方式進行。以下就此詳細說明。 首先’說明去除的情形β將高電壓（例如丨6 V )外加 到感知電晶體的控制閘，在將連結汲極領域的位元線接 地之狀態下，將高電壓（例如16V)外加到擔任選擇性導 通電晶體的選擇電晶體之控制閘，在感知電晶體的控制 閘與位元線之間’供給強勁的電場，這時，通道絕緣膜 的障壁會變薄，透過形成於源極領域與汲極領域間的通 本紙張尺度適用中國國家標準（CNS ) A4規格（21〇><297公楚） C—— (請先閲讀t'·面之注_意事項再填寫本頁) 訂 經濟部中央標準局貞工消費合作社印裝 A7 B7 五、發明説明（5 ) '~~ 道，從位元線來的電子會透過通道絕緣膜，依FN通道方 式注入感知電晶艘的浮置_。結果，進行去除工作外 ，並將資料記錄於被程式化的單元。如此，電子一充填 於浮置閘時’該電子就會使記憶料元的門檻電壓（以 下稱Vth)上升，冑源電壓會供給至與字元線連結的控制 閘，一讀到單元，因為高的門檻電壓，不會形成通道、 電流不會流動’所以，會記憶一個狀態。 其次，說明為儲存新資訊而作的程式。讓感知電晶 體的控制閘接地，在將高電壓（例如16v)外加到與汲極 領域連結的位元線之狀態下，將高電壓（例如16V)外加 到擔任選擇性導通電晶體的選擇電晶體之控制閘，在感 知電晶魏的浮置閘與基板間的通道絕緣膜兩端，供給強 勁的電場，這時’通道絕緣膜的障壁會變薄，依FN通道 方式’儲存於浮置閘内的電荷，會透過變薄的絕緣膜障 壁，經由第1、第2接合領域18a、18b，從基板1〇内部的 汲極領域側拔出。結果，就進行了資料的程式。如此一 來，浮置閘内會沒有電荷，單元的Vth變低，所以，電源 電壓會供給至與字元線連結的控制閘，一讀到單元，因 低Vth會形成通道、使電流流動，可以記憶與初期不同的 狀態。 亦即，資料的判讀（read)，將適當的電壓外加到選 擇單元的字元線與控制閘，可以判讀記愧體單元電晶艘 有無電流，而確認。 發明欲解決的課題 本纸張尺度適用中國國家榇準（CNS ) A4規格（210X297公釐） (請先閲讀t·面之>i_意事項再填寫本頁)Printed by the Central Standards Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperatives, A7 B7 V. Description of the invention (4) The gate insulation medium 14 'is formed so that a certain part of the surface of the substrate 10 is exposed, and the exposed part of the surface between the gate insulation films 14 On the substrate 10, a channel insulating film 20 thinner than the foregoing gate insulating film 14 is formed. A predetermined portion of the channel insulating film 20 and the surrounding gate insulating film 14 passes through the interlayer insulating film 24 to form a floating electrode. The sensing transistor formed by stacking the gate 22a and the control gate 26a, and a predetermined portion of the gate insulating film 14 on the sensing transistor side will form a selective transistor with the same stacked structure as the sensing transistor. Inside the substrate 10 below the channel insulating film 20, a first bonding region 18a 'is formed on one side of the first bonding region iga, and a second bonding region 18b that partially overlaps with a selected transistor is formed. Inside the substrate 10 in the space area between the field oxide film 12 and the sensing transistor, a source region 28 will be formed. Inside the substrate 10 in the space area between the field oxide film 12 and the selection transistor, a bit line will be formed. Drain collar Domain 30β Therefore, the non-volatile semiconductor device with the aforementioned structure performs a series of operations related to data storage, erasure, and interpretation operations according to the following method. At this time, the erase related to the storage of the data and the program related to the deletion of the data will be performed in accordance with the f0wler_nordheim tunnel method. This is explained in detail below. First of all, explain the removal of the condition β. A high voltage (for example, 6 V) is applied to the control gate of the sense transistor, and a high voltage (for example, 16 V) is applied to the sensor while the bit line connected to the drain region is grounded. The selective gate of the selective conduction transistor is supplied with a strong electric field between the control gate of the sensing transistor and the bit line. At this time, the barrier of the channel insulation film will become thin, and it will be formed through the source field and The paper size between the drain electrodes is applicable to the Chinese National Standard (CNS) A4 specification (21〇 > < 297 Gongchu) C—— (Please read t '· Front Note_Notices before filling out this page) Order A7 B7 printed by Zhengong Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (5) '~~ Road, the electrons from the bit line will pass through the channel insulation film, and will be injected into the sensing transistor ship according to the FN channel. _. As a result, the removal work is performed and the data is recorded in the stylized unit. In this way, as soon as the electron is filled in the floating gate, the electron will increase the threshold voltage (hereinafter referred to as Vth) of the memory element, and the source voltage will be supplied to the control gate connected to the word line. A high threshold voltage will not form a channel and current will not flow ', so a state will be memorized. Next, the program for storing new information will be explained. Ground the control gate of the sensing transistor and apply high voltage (such as 16V) to the bit line connected to the drain field. The control gate of the crystal supplies a strong electric field at both ends of the channel insulation film between the floating gate of the sensor and the substrate. At this time, the barrier of the channel insulation film will be thinned and stored in the floating gate according to the FN channel method. The internal charges pass through the thin insulating film barrier and are pulled out from the drain region side inside the substrate 10 through the first and second bonding regions 18a and 18b. As a result, the data program was performed. In this way, there will be no charge in the floating gate and the Vth of the cell will be low. Therefore, the power supply voltage will be supplied to the control gate connected to the word line. Once the cell is read, the low Vth will form a channel and allow current to flow. It is possible to remember a different state from the initial stage. That is, the data is read, and an appropriate voltage is applied to the character lines and control gates of the selection unit to determine whether there is a current in the transistor cell of the shame unit and confirm it. Problems to be solved by the invention The paper size is applicable to China National Standards (CNS) A4 specification (210X297 mm) (please read the t &n; i_intentions before filling out this page)
Λ7 B7 五、發明説明（6 ) 製造具有如前述構造之元件時，為了在一個記憶體 單兀形成2個電晶體，以構成非揮發性元件，要比現有元 件的單位單元面積大，且内藏於smart card Ic，量產製品 的晶片尺寸縮小有其界限，因此無法達到半導體元件的 高集積化，此為問題所在。 此種問題，雖然，普通N〇RB的非揮發性半導饉元 件具有可以増大電流作高速動作的特長，但是，隨著位 疋線接觸與源極線所佔面積增大，記憶體很難高集積化 ’這又使問題更上一層，所以，改善對策變為當務之急 〇 本發明的目的，在於提供一種透過具備感知電晶體 及選擇電晶體的記憶體單元之構造變形，使非揮發性元 件的單位單元面積最小化，可實現記憶體單元的高集中 化之非揮發性半導體元件。 本發明的另一個目的，在於提供一種可以有效製.造 前述非揮發性半導體元件的半導體元件製造方法。 解決課題的手段 經濟部中央標準局員工消費合作社印製 n n n m n .^1 n n T (請先聞讀1!?'面之>£..^^項再填寫本頁} 本發明為達到前述之目的，提供一種由下構成的非 揮發性半導體元件： 形成於半導體基板上所定部分的通道絕緣膜；與該 通道絕緣膜相接，形成於周圍的前述基板上所定部分的 第1導電性膜；形成於前述通道絕緣膜與第1閘極絕緣膜 上’透過層間絕緣膜，疊層浮置閘與控制閘構造的感知 電晶體；形成於前述控制閘上的任意膜；形成於包括前 本紙張尺度適财關家鱗（CNS)从見格（21GX297公楚）----- -10 五、發明説明（ A7 B7 經濟部中央橾準局員工消費合作社印裝 述任意膜的前述感知電晶禮側壁之間隔材（spacer);形成 於該間隔材附近基板上的第2閘極絕緣膜；在含蓋包括前 述任韋膜上一側端部（edge)與間隔材（spacer)的前述第2 閑極絕緣膜上所定部分所形成的選擇閘；與該選擇閘所 定部分重疊（over lap )，形成於前述通道絕緣膜下方基 板内部的接合領域；及，形成於作為前述感知電晶體及 選擇電晶體的前述選擇閘兩端的基板内部之源極/汲極領 域0 又，本發明為達到另一個目的，提供一種由以下製 程所構成的非揮發性半導體元件之製造方法： 在具有場氧化膜的半導體基板上之活性領域，形成 第1絕緣膜的步驟；在前述第1閘絕緣膜下端的前述基板 内所定部分’形成接合領域的步驟；為使前述接合領域 所形成的部分之前述基板表面露出一定部分，將第1閘絕 緣膜作選擇性蝕刻，且在該表面露出部形成通道絕緣膜 之步称；在包含前述通道絕緣膜之前述第1閘極絕緣膜上 ’依序形成第1導電性膜與層間絕緣膜之步驟；為使前述 場氧化膜表面露出一定部分，而將前述層間絕緣膜與第1 導電性膜的一定部分作選擇性蝕刻之步驟；在包含前述 場氧化膜表面露出部的前述層間絕緣膜上，形成第2導電 性膜之步驟；在前述第2導電性膜之一定部分，形成任意 膜之步驟；以前述任意膜作為光軍（mask)，依序蚀刻 前述第2導電性膜、層間絕緣膜、第1導電性膜、及第1閘 絕緣膜，透過層間絕緣膜，疊層該上下部的控制閘與浮 請 先 間 面 之 注-Λ7 B7 V. Description of the invention (6) When manufacturing a component with the structure described above, in order to form two transistors in one memory unit to form a non-volatile component, the unit cell area of the existing component is larger than Hidden in smart card ICs, there is a limit to shrinking the wafer size of mass-produced products, so it is not possible to achieve high integration of semiconductor devices. This is the problem. This kind of problem, although ordinary NORB non-volatile semiconductor devices have the feature of high currents for high-speed operation, but as the area line contact and source line area increases, the memory is difficult 'High integration' raises the issue to the next level, so improving countermeasures becomes a top priority. The object of the present invention is to provide a non-volatile element by deforming the structure of a memory cell having a sensing transistor and a selective transistor. The unit cell area is minimized, and a non-volatile semiconductor device with high concentration of memory cells can be realized. Another object of the present invention is to provide a semiconductor device manufacturing method capable of efficiently manufacturing and manufacturing the aforementioned non-volatile semiconductor device. Means of solving the problem Printed by nnnmn. ^ 1 nn T of the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs (please read 1 !? 'face of > £ .. ^^ before filling out this page} The present invention achieves the foregoing The object is to provide a non-volatile semiconductor device composed of: a channel insulating film formed on a predetermined portion of a semiconductor substrate; a first conductive film connected to the channel insulating film and formed on a predetermined portion of the foregoing substrate; Formed on the aforementioned channel insulating film and the first gate insulating film through the interlayer insulating film, a sensing transistor with a floating gate and a control gate structure laminated; any film formed on the aforementioned control gate; formed on a paper including the former The scale suitable for wealth and wealth (CNS) from the grid (21GX297 Gongchu) ---- -10 V. Description of the invention (A7 B7 The Consumer Cooperatives of the Central Government Bureau of the Ministry of Economic Affairs printed the aforementioned sensor transistor with any film A spacer on the side wall of the ceremony; a second gate insulating film formed on the substrate near the spacer; the cover including the edge portion on one side of the Renwei film and the spacer on the spacer 2 Fixed part of the insulation electrode The formed selection gate; an overlap with a predetermined portion of the selection gate to form a bonding area inside the substrate under the aforementioned channel insulating film; and formed at both ends of the aforementioned selection gate as the sensing transistor and the selection transistor Source / drain field inside the substrate 0 In addition, in order to achieve another object, the present invention provides a method for manufacturing a non-volatile semiconductor device composed of the following process: an active field on a semiconductor substrate having a field oxide film, A step of forming a first insulating film; a step of forming a bonding region on a predetermined portion of the substrate at the lower end of the first gate insulating film; in order to expose a certain portion of the substrate surface of the portion formed in the bonding region, the first gate is exposed The step of selectively etching the insulating film and forming a channel insulating film on the exposed portion of the surface; the step of sequentially forming the first conductive film and the interlayer insulating film on the first gate insulating film including the channel insulating film. Step; in order to expose a certain portion of the surface of the field oxide film, a certain distance between the interlayer insulating film and the first conductive film is fixed; A step of selective etching; a step of forming a second conductive film on the interlayer insulating film including the exposed portion of the field oxide film surface; a step of forming an arbitrary film on a certain portion of the second conductive film; Using the aforementioned arbitrary film as a mask, the second conductive film, the interlayer insulating film, the first conductive film, and the first gate insulating film are sequentially etched, and the upper and lower controls are laminated through the interlayer insulating film. Gate and floating please note in advance-
I 訂 本紙張尺度適用中國國家標準（CNS ) Α4規格（2丨0 X 297公楚） 11 Λ7 ___B7 五、發明説明（8 ) 置閘之構造的感知電晶艘形成步称；在包含前述任意膜 之前述感知電晶逋的兩側壁，形成間隔材之步驟；在前 述間隔材周圍的前述基板上，形成第2閘絕緣膜之步称； 含蓋在包括前述任意膜之一側端緣部與間隔材的第2閘絕 緣膜上的一定部分，形成第3導電性膜材質的選擇閘之步 驟；及，作為前述感知電晶體及選擇電晶體之作用，在 前述選擇閘兩端的基板内部，形成源極領域及汲極領域 之步驟。 如前所述製造非揮發性半導體元件，因為是以絕緣 膜（例如任意膜及間隔材）作為媒介體，在感知電晶體 上端及側面，直接形成選擇電晶體的構造之記憶體單元 電晶體，所以，可使非揮發性元件的單位單元面積最小 化0 發明的實施形態 以下，說明本發明的實施形態。 * 經濟部中央標率局員工消費合作社印裝 本發明是透過具備有感知電晶體與選擇電晶體的非 揮發性記愫體單元的構造變更，將非揮發性元件的單位 單元面積最小化的技術，請參照第1至8圖所示的工程順 序圖，詳細說明。 如第1圖所示，在半導體基板100上的所定部分，形 成場氡化旗102，以區分為非活性領域與活性領域。 如第2圖所示，在基板1〇〇上的活性領域，形成 250〜350A厚的第1閘極絕緣膜1〇4，在該閘極絕緣膜104表 面形成感光膜樣式1〇6,以露出所定部分後，在表面露出 12 本紙張尺度適用中國國家樣隼（CNS ) A4規格（210X297公釐） 經濟部中央橾準局員工消費合作社印製 A7 B7 五、發明説明（9 ) 的閘極絕緣膜104上，打入離子雜質，而於基板1〇〇内， 形成接合領域108。 如第3圖所示，去除感光膜樣式106，在接合領域1〇8 上的基板100表面露出所定部分，於前述絕緣膜104上形 成感光膜樣式（無圖示）後，以其作為光罩，濕蝕刻第1閘 極絕緣膜104,然後去除感光膜式樣❶其次，在第1閘極 絕緣膜104被蝕刻的部分之基板1〇〇表面上，形成7〇~1〇〇人 厚的通道絕緣膜110。結果，就形成了中央部所形成的通 道絕緣膜110被周圍所形成的第1閘極絕緣膜104包圍的構 造式樣。 如第4圖所示，在包含場氧化膜和通道絕緣膜11〇的 第1閘極絕緣膜104上，依序形成多晶矽材質的第1導電性 膜112和層間絕緣膜Π4後，為使單元與單元間的浮置閘 分離，將未圖式的縱方向（在圊面上穿透紙面的方向）之層 間絕緣膜114與第1導電性膜112做所定部分的選擇蝕刻·， 以露出場氧化膜102表面之所定部分。在參照符號A中， 為了幫助理解，在層間絕緣膜114與第1導電性膜112已做 所定部分的選擇蝕刻之狀態下，將第4圖的假想線所標記 的部分，上視平面圖做圖示。此時，氧化膜的單層構造 及氧化膜/氮化膜/氧化膜的多層構造，都可適用作層間絕 緣膜114。 如第5圖所示，在包含場氧化膜表面露出部的層間絕 緣膜114上，依序形成多晶矽材質的第2導電性膜116和氧 化膜材質的任意膜118,並在其上形成用以限定感知電晶 本紙張尺度適用中國國家標準（CNS ) A4規格（2l0x297公釐）I The paper size of the edition is applicable to the Chinese National Standard (CNS) A4 specification (2 丨 0 X 297 Gongchu) 11 Λ7 ___B7 V. Description of the invention (8) The step of forming the sensing transistor with the gate structure formed; A step of forming a spacer on the two sidewalls of the aforementioned sensing electrode of the film; a step of forming a second gate insulating film on the substrate surrounding the spacer; and covering the edge of the side including one of the foregoing films Forming a selection gate of the third conductive film material with a certain portion of the second gate insulating film of the spacer; and, as a function of the sensing transistor and the selection transistor, inside the substrate at both ends of the selection gate, Steps to form source and drain domains. The non-volatile semiconductor element is manufactured as described above, because an insulating film (such as an arbitrary film and a spacer) is used as a medium, and a memory cell transistor that directly selects the structure of the transistor is formed on the upper and side of the sensing transistor. Therefore, the unit cell area of the non-volatile element can be minimized. Embodiments of the invention Embodiments of the invention will be described below. * Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs The present invention is a technology for minimizing the unit unit area of non-volatile components through the structural change of a non-volatile recording unit with a sensing transistor and a selective transistor. Please refer to the engineering sequence diagrams shown in Figures 1 to 8 for details. As shown in Fig. 1, a field flag 102 is formed on a predetermined portion of the semiconductor substrate 100 to distinguish between an inactive area and an active area. As shown in FIG. 2, a first gate insulating film 104 having a thickness of 250 to 350 A is formed in an active area on the substrate 100, and a photosensitive film pattern 106 is formed on the surface of the gate insulating film 104. After the predetermined part is exposed, 12 paper sizes are exposed on the surface. Applicable to the Chinese National Standard (CNS) A4 size (210X297 mm). Printed on the A7 B7 by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs. 5. Gates of the invention description (9). Ion impurities are implanted on the insulating film 104, and a bonding region 108 is formed within the substrate 100. As shown in FIG. 3, the photosensitive film pattern 106 is removed, a predetermined portion is exposed on the surface of the substrate 100 on the bonding area 108, a photosensitive film pattern (not shown) is formed on the insulating film 104, and then it is used as a photomask. First, the first gate insulating film 104 is wet-etched, and then the pattern of the photosensitive film is removed. Second, on the surface of the substrate 100 where the first gate insulating film 104 is etched, a channel having a thickness of 70 to 100 people is formed. Insulation film 110. As a result, a structure pattern in which the channel insulating film 110 formed in the center portion is surrounded by the first gate insulating film 104 formed in the periphery is formed. As shown in FIG. 4, on the first gate insulating film 104 including the field oxide film and the channel insulating film 110, a first conductive film 112 made of polycrystalline silicon and an interlayer insulating film Π4 are sequentially formed. Separate from the floating gates between the cells, and selectively etch the interlayer insulating film 114 and the first conductive film 112 in the vertical direction (the direction penetrating the paper surface) (not shown) to select a part to expose the field A predetermined portion of the surface of the oxide film 102. In reference symbol A, in order to help understanding, in a state where the interlayer insulating film 114 and the first conductive film 112 have been selectively etched, the portion marked by the imaginary line in FIG. 4 is plotted on the top plan Show. In this case, both the single-layer structure of the oxide film and the multilayer structure of the oxide film / nitride film / oxide film can be applied as the interlayer insulating film 114. As shown in FIG. 5, a second conductive film 116 made of polycrystalline silicon and an arbitrary film 118 made of an oxide film are sequentially formed on the interlayer insulating film 114 including the exposed portion of the field oxide film surface, and formed thereon The paper size of the sensing sensor is limited to the Chinese National Standard (CNS) A4 (2l0x297 mm)
In m i^i ^ϋ·> MR1^1 m —^n y I k'^i (請先閲讀1^-面之>±.意事項再填寫本頁) 13 五、發明説明（10 ) Λ7 B7 體形成部的感光膜樣式106後，以其作為光罩，蝕刻任意 膜118。其次，以前述感光膜樣式1〇6與任意膜Mg作為蝕 刻光單，依序蚀刻第2導電性膜、層間絕緣膜114、第1導 電性膜112及第1閘極絕緣膜1〇4。結果，在通道絕緣膜110 和第1閘極絕緣膜104上，會透過層間絕緣膜114，形成層 疊第1導電性膜材質的浮置閘112a與第2導電性膜材質的 控制閘116a構造的感知電晶體，其左右側的基板1〇〇表面 會露出。如此一來，以氧化膜材質的任意膜Π8作為光罩 ，形成感知電晶體，可達到其蚀刻工程的正確性。此時 ’多晶矽單層構造以外的“多晶矽/鎢金屬矽化物，，之多 層構造亦可適用作為前述第2導電性膜。 如第6圖所示’去除感光膜樣式1〇6,在包含任意膜Π8 與感知電晶體的基板100全面上，形成氧化膜或氮化膜材 質的絕緣膜後，加以回蚀（Etch Back)。華果，在任意膜118 經濟部中央標準局員工消費合作社印製 與感知電晶體的側壁，會形成絕緣膜材 如第7圖所示，利用氧化工程，在 露出部，形成第2閘極絕緣膜122,在^全面形成多晶石夕 材質的第3導電性膜124後，在第3導電性膜124上，形成 用以限定選擇電晶體形成部的感光膜樣式（未圖示），以其 作為光罩，蝕刻第3導電性膜124。結果，在包含任意膜lli 上一側邊緣部與間隔材120的第2閘極絕緣膜122上之所定 部分’形成第3導電性膜材質的選擇電晶體。此時，除多 晶矽單層構造以外的“多晶矽/鎢金屬矽化物，，之多層賴 造’亦可適用作為第3導電性膜。 質的間隔材120·。 基板100上的表面 本紙張尺度適用中國國家樣準（CNS ) A4規格（210X297公釐） (請先閲讀r面之.$項再填寫本頁)In mi ^ i ^ ϋ · > MR1 ^ 1 m — ^ ny I k '^ i (please read 1 ^ -face of > ±. Matters before filling out this page) 13 V. Description of the invention (10) Λ7 After the photosensitive film pattern 106 of the B7 body forming portion, the arbitrary film 118 is etched using the photosensitive film pattern 106 as a photomask. Next, the second conductive film, the interlayer insulating film 114, the first conductive film 112, and the first gate insulating film 104 are sequentially etched by using the aforementioned photosensitive film pattern 106 and arbitrary film Mg as an etching light sheet. As a result, the channel insulating film 110 and the first gate insulating film 104 pass through the interlayer insulating film 114 to form a structure in which the floating gate 112a of the first conductive film material and the control gate 116a of the second conductive film material are laminated. On the sensing transistor, the surface of the substrate 100 on the left and right sides is exposed. In this way, by using an arbitrary film Π8 made of an oxide film as a photomask to form a sensing transistor, the accuracy of its etching process can be achieved. In this case, “a polycrystalline silicon / tungsten metal silicide, other than a polycrystalline silicon single-layer structure, may have a multilayer structure suitable for the aforementioned second conductive film. As shown in FIG. 6”, the pattern of the photosensitive film 10 is removed. The film Π8 and the substrate 100 of the sensing transistor are all formed with an insulating film made of an oxide film or a nitride film, and then etched back (Etch Back). Huaguo, printed on any film 118 by the Consumer Standards Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs As shown in FIG. 7, an insulating film is formed on the side wall of the sensing transistor. As shown in FIG. 7, a second gate insulating film 122 is formed on the exposed portion by an oxidation process, and the third conductivity of the polycrystalline silicon material is formed on the entire surface. After the film 124, a photosensitive film pattern (not shown) for defining a selective transistor formation portion is formed on the third conductive film 124, and the third conductive film 124 is etched using this as a photomask. As a result, An optional edge of the upper side of the arbitrary film 11i and a predetermined portion of the second gate insulating film 122 of the spacer 120 form a selected transistor of a third conductive film material. At this time, the "polycrystalline silicon / Tungsten metal silicide, The multilayer Lai made 'can also be applied as the third conductive film. Quality spacer 120 ·. Surface on the substrate 100 This paper size is applicable to China National Standard (CNS) A4 specification (210X297 mm) (Please read the. $ Item on the r side before filling in this page)
14 11 材質的還擇 成與選擇閘 為感知電晶 經濟部中央標準局貝工消費合作社印製 Λ7 B7 五、發明説明（ 如第8圖所示，在第2閘極絕緣膜112表面露出部，打 入離子雜質，而在感知電晶艏與選擇電晶體兩端的基板 100内部’形成源極領域126與汲極領域128，完成本工程 〇 結果，在具備場氧化膜120的半導艘基板1〇〇上的活 性領域之所定部分，會形成通道絕緣膜110,且在其周圍 的活性領域之所定部分，會形成與通道絕緣膜11〇相接的 第1閘極絕緣膜104，在通道絕緣膜110與第1閘極絕緣膜 104上’透過層間絕緣膜114,形成依序層疊第1導電性膜 材質的浮置閘與第2導電性膜材質的控制閘構造的感知電 晶艘，且在控制閘上，形成任意膜118，在任意膜丨】8與 感知電晶體的側壁，形成絕緣膜材質的間隔材12〇，在 間隔材120附近的活性領域，形成第2閘極絕緣膜122， 在包含任意膜118上端一側邊緣部與間隔材的第2閘極 絕緣膜122上之所定部分，形成第3導電性 閘’在通道絕緣膜110下側基板100内部，形 所定部分重疊（over lap)的接合領域1〇8，在子 體與選擇電晶艎作用的選擇閘兩端的基板100内部，形成 源極領域126與汲極領域128，完成本非揮發性半導艘元 件。 在製造具有前述構造的非揮發性記憶體單元時，因 為感知電晶體與選擇電晶艏有資料合成（merge)的形態， 所以，可以比習知更減少單位單元的面積。 發明之效果 本紙張尺度"國家揉準（CNS ) A4規格（21〇><297公楚） {請先閲讀^面之注，意事項再填寫本頁)14 11 Material selection and selection gates are printed by the Central Standards Bureau of the Ministry of Economics and Electronics. Printed with Λ7 B7 by the Shellfish Consumer Cooperative. V. Description of the invention (as shown in Figure 8), the exposed part of the surface of the second gate insulating film 112 Injecting ionic impurities, and forming the source region 126 and the drain region 128 within the substrate 100 at both ends of the sensing transistor and the selective transistor, and completing the project. As a result, the semiconductor substrate with the field oxide film 120 is formed. A channel insulating film 110 is formed in a predetermined portion of the active area on 100, and a first gate insulating film 104 connected to the channel insulating film 11 is formed in a predetermined portion of the surrounding active area. The insulating film 110 and the first gate insulating film 104 penetrate the interlayer insulating film 114 to form a sensing transistor with a floating gate made of a first conductive film material and a control gate structure made of a second conductive film material in this order. An arbitrary film 118 is formed on the control gate, and a spacer 120 made of an insulating film is formed on the arbitrary film and the sidewall of the sensing transistor. A second gate insulating film is formed in the active area near the spacer 120. 122, Including any The upper edge of the Italian film 118 and a predetermined portion on the second gate insulating film 122 of the spacer form a third conductive gate. The predetermined portion overlaps inside the substrate 100 below the channel insulating film 110 (over lap). In the bonding area 108, a source region 126 and a drain region 128 are formed inside the substrate 100 at both ends of the daughter and the selection gate that acts as a transistor. The non-volatile semiconductor device is completed. When constructing a non-volatile memory cell, since the sensing transistor and the selective transistor have the form of a data merge, the area of the unit cell can be reduced more than conventionally. Effect of the invention Paper scale " Country Standard (CNS) A4 (21〇 > < 297 Gongchu) {Please read the note on ^ first, please fill in this page if you want to know)
15 經濟部中央樣準局員工消費合作社印製 Λ 7 ____Β7________ 五、發明説明（12 ) 如上說明，本發明是以任意膜與間隔材為媒介，在 包含感知電晶體上端邊緣側與側面的第2閘極絕緣膜122 上之所定部分，形成選擇電晶體，以製造非揮發性記憶 體單元，比起習知只以相互所定間隔來隔離、形成感知 電晶體與選擇電晶體之方法，可以減少基板上電晶體所 佔的面積，所以，可以將單位單元面積最小化，而得到 將非揮發性半導體元件高集積化的效果。 圖式的簡單說明 第1至8圖，為本發明非揮發性半導體元件的製造方 法之步驟順序圖。 第9至16圖’為習知非揮發性半導體元件的製造方法 之步驟順序圖。 本紙張尺度適用βϊ"家揉準（CNS ) A4規格（2Γ〇χ297^17 (請先閲讀'背面之仏^^項再填寫本頁)15 Printed by the Consumer Cooperative of the Central Sample Bureau of the Ministry of Economic Affairs Λ 7 ____ Β7 ________ V. Description of the Invention (12) As explained above, the present invention uses any film and spacer as the medium, and includes the second and third sides of the upper and lower sides of the sensing transistor. The selected portion of the gate insulating film 122 forms a selective transistor to manufacture a non-volatile memory cell. Compared with the conventional method of isolating and forming a sensing transistor and selecting a transistor at a predetermined interval from each other, the substrate can be reduced. The area occupied by the power-on crystal can minimize the unit cell area and obtain the effect of highly integrating non-volatile semiconductor elements. Brief Description of the Drawings Figures 1 to 8 are sequence diagrams showing the steps of a method for manufacturing a nonvolatile semiconductor device according to the present invention. Figures 9 to 16 are sequence diagrams showing the steps of a conventional method for manufacturing a nonvolatile semiconductor device. This paper size is applicable to βϊ " CNS A4 specification (2Γ〇χ297 ^ 17 (please read the '^^ on the back side before filling in this page)