TW586219B - Self-aligned split-gate flash cell structure and its contactless flash memory arrays - Google Patents

A self-aligned split-gate flash cell structure of the present invention comprises a ridge-shaped floating-gate layer being formed on a first gate dielectric layer with a first intergate dielectric layer being formed on its top portion and a second intergate dielectric layer being formed on its inner sidewall; a control/select-gate conductive layer being at least formed over a second gate dielectric layer and the first/second intergate dielectric layers; and a common-source diffusion region and a common-drain diffusion region being implanted by aligning to the control/select-gate conductive layer. The self-aligned split-gate flash cell structure is configured into two contactless array architectures: a contactless NOR-type flash memory array and a contactless parallel common-source/drain conductive bit-lines flash memory array.

586219 五、發明說明（1) (1 )發明所屬之技術領域 本發明與一種分閘式（split-gate)快閃記憶細胞元及 其快閃記憶陣列有關，特別是與具有一種楔形（r丨dge 一 shaped)漂浮閘層之一種自動對準（self - aHgned)分閘式 快閃記憶細胞元結構及其無接點快閃記憶陣列的製造方法 有關。 (2 )先前技術 一個分閘式快閃記憶細胞元結構通常具有一個選擇閘 (select-gate)區及一個漂浮閘（fi〇ating-gate)區係能提 供比一個疊堆閘（s t a c k - g a t e )細胞元結構較為大的細胞元 尺寸且經常被組成一種非或型（NOR-type )快閃記憶陣列。 圖一顯示一種傳統分閘式快閃記憶元件具有由一種局 部氧化矽（LOCOS)技術所形成的一個漂浮閘層21 1，其中漂 浮閘長由於鳥嘴（bird，s beak)形成的關係通常被定義成 比所使用技術之一個最小線寬（F )大；一個控制閘層2 1 5係 形成於一個局部氧化矽層2 1 2及一個較厚選擇閘氧化層2 1 4 之上；一個複晶矽氧化層2 1 3係形成於該漂浮閘層2 1 1的一 個側邊牆之上；一個源擴散區2 1 6及一個汲擴散區2 1 7係以❿ 自動對準方式形成於一個半導體基板2 0 0之内；以及一個 薄閘氧化層2 1 0係形成於該漂浮閘層2 11之下。圖一所示之 分閘式快閃細胞元結構係利用中間通道（m i d - c h a η n e 1)熱 電子注入法來寫入，比傳統疊堆閘細胞元結構所使用之通586219 V. Description of the invention (1) (1) The technical field to which the invention belongs The present invention relates to a split-gate flash memory cell and a flash memory array, and particularly to a wedge-shaped (r 丨A self-aHgned split-gate flash memory cell structure and a method of manufacturing a contactless flash memory array. (2) In the prior art, a split-type flash memory cell structure usually has a select-gate area and a floating-gate area, which can provide more than a stack-gate ) The cell structure is relatively large and is often composed of a NOR-type flash memory array. Figure 1 shows a conventional split-type flash memory device with a floating gate layer 21 1 formed by a local silicon oxide (LOCOS) technology, in which the floating gate length is usually determined by the relationship formed by a bird's beak. Defined to be larger than a minimum line width (F) of the technology used; a control gate layer 2 1 5 is formed on a local silicon oxide layer 2 1 2 and a thicker selective gate oxide layer 2 1 4; a complex A crystalline silicon oxide layer 2 1 3 is formed on a side wall of the floating gate layer 2 1 1; a source diffusion region 2 1 6 and a drain diffusion region 2 1 7 are formed in a Within the semiconductor substrate 200; and a thin gate oxide layer 2 10 is formed under the floating gate layer 2 11. The split flash cell structure shown in Figure 1 is written using the middle channel (m i d-c h a η n e 1) hot electron injection method, which is more general than the traditional stack cell structure.

586219 五、發明說明（2) 道熱電子注入（CHEI )法具有 功率。另外，由於分閘式快 一個高的臨界電壓，超擦洗 因而擦洗及驗証的控制邏輯 示之分閘式快閃記憶元件仍 準控制閘結構，一個細胞元 21 5相對於該漂浮閘層211間 制閘長不容易加予微縮化； ’擦洗所需的外加控制閘電 罩幕能力較差，該漂浮閘層 emission tip)較不易控制 形成一個較厚的局部氧化碎 尖角。 因此，本發明的一個主 溫製程來形成一種自動對準 一個較南的場發射效率之一 結構。 本發明的另一個目的係 閃細胞元結構具有一個可微 可以等於或小於4F 2。 本發明的一個進一步目 快閃細胞元結構具有一個較 本發明的一個額外目的 分閘式快閃記憶陣列架構。 較高的寫入效率及較低的寫入 閃細胞元結構之選擇閘區具有 (over-erase)問題可以避免， 電路可以簡化。然而，圖一所 具有一些缺點：由於非自動對 的尺寸較大；由於該控制閘層 的誤對準（misalignment)，控 耦合比（coupling ratio)較低 壓較高；由於該鳥嘴氧化層的 211的場發射尖端（field- · ;以及需要一個高溫的製程來 層2 1 2以獲得一個較為明顯的 要目的係能提供一個簡單的低 分閘式快閃細胞元結構並具有 種楔形（ridge-shaped)漂浮閘 能提供一種自動對準分閘式快 縮化（seal able)細胞元尺寸且 ❶ 的係能提供該自動對準分閘式 高的耗合比。 係能提供兩種無接點自動對準586219 5. Description of the invention (2) The hot electron injection (CHEI) method has power. In addition, because the switching gate is fast with a high critical voltage, the control logic shown in the control logic of the scrubbing and verification by the scrubbing and flashing is still quasi-controlling the gate structure. A cell 21 5 is opposite to the floating gate layer 211. The gate length is not easy to be miniaturized; 'The external control gate capacity required for scrubbing is poor, and the floating gate layer emission tip) is difficult to control to form a thicker localized oxidized broken corner. Therefore, a main temperature process of the present invention is used to form a structure that automatically aligns with a field emission efficiency that is relatively south. Another object of the present invention is that the amphocyte structure has a differentiable and can be equal to or less than 4F 2. A further object of the present invention is that the flash cell structure has an open-type flash memory array architecture that is an additional object of the present invention. Higher write efficiency and lower write Over-erase of the flash cell structure can be avoided, and the circuit can be simplified. However, Figure 1 has some disadvantages: due to the large size of the non-automatic pair; because of the misalignment of the control gate layer, the coupling ratio is lower and the pressure is higher; because of the bird's beak oxide layer The field emission tip of 211 (field- ·; and a high-temperature process is needed to layer 2 1 2 to obtain a more obvious purpose is to provide a simple low-breaking flash cell structure and have a wedge shape ( A ridge-shaped floating gate can provide an auto-aligned split-type seal able cell element size and a rugged system can provide this auto-aligned split-type high cost-effective ratio. The system can provide two kinds of Automatic contact alignment

第7頁 586219 五、發明說明（3) 本發明的其他目的及優點將於後續的揭示中來加予顯 現。 發明内容： 本發明之一種自動對準分閘式快閃細胞元結構係形成 於具有一個主動區由兩個平行淺凹槽隔離（STI)區所隔離 的一種第一導電型的一個半導體基板之上。一個細胞元區 可以分成三個區域：一個共源區、一個自動對準分閘區、 以及一個共汲區，其中上述之自動對準分閘區係介於該共 源區及該共汲區之間。上述之共源區至少包含一個第一側 邊踏介電墊層形成於該自動對準分閘區的一個第一側邊牆 之上及置於由位於該主動區之一種第二導電型的一個共源 擴散區和位於該兩個平行淺凹槽隔離區之兩個第三突出場 氧化物層所組成的一個第一平坦床之一部份表面之上。上 述之共浪區至少包含一個第二側邊牆介電墊層形成於該自 動對準分閘區的一個第二側邊牆之上及置於由位於該主動 區之該第二導電型的一個共汲擴散區和位於該兩個平行淺 凹槽隔離區之兩個第五突出場氧化物層所組成的一個第二 平坦床之一部份表面之上。上述之自動對準分閘區至少包 含一種楔形漂浮閘結構置於一個第一閘介電層之上且有一 個第一閘間介電層置於其頂部及一個第二閘間介電層形成 於其内側邊牆及尖端部份之上；以及一個平面化控制/選 擇閘導電層至少形成於該主動區之一個第二閘介電層及該 第一 /第二閘間介電層之上和置於位於該兩個平行淺凹槽Page 7 586219 V. Description of the invention (3) Other objects and advantages of the present invention will be revealed in subsequent disclosures. SUMMARY OF THE INVENTION An auto-aligned split-type flash cell structure of the present invention is formed on a semiconductor substrate of a first conductivity type having an active region separated by two parallel shallow groove isolation (STI) regions. on. A cell area can be divided into three areas: a common source area, an auto-alignment trip area, and a common draw area, where the above-mentioned auto-alignment trip area is between the common source area and the common draw area between. The above common source region includes at least a first side stepping dielectric pad layer formed on a first side wall of the auto-alignment opening region and disposed on a second conductive type in the active region. A common source diffusion region and a portion of the surface of a first flat bed composed of two third protruding field oxide layers in the two parallel shallow groove isolation regions. The above-mentioned common wave area includes at least a second side wall dielectric cushion layer formed on a second side wall of the auto-alignment opening area and placed on the second conductive type of the active area. A common-drain diffusion region and a portion of the surface of a second flat bed composed of two fifth protruding field oxide layers in the two parallel shallow groove isolation regions. The above-mentioned self-aligned gate opening area includes at least a wedge-shaped floating gate structure placed on a first gate dielectric layer and a first inter-gate dielectric layer on top of it and a second inter-gate dielectric layer formed. On the inner side wall and the tip portion; and a planarization control / selection gate conductive layer is formed at least on a second gate dielectric layer of the active area and the first / second inter-gate dielectric layer Up and placed on the two parallel shallow grooves

第8頁 586219 五、發明說明（4) 隔離區之第一突出/平面化場氧化物層的一部份表面之上 。上述之楔形漂浮閘結構係利用非等向乾式蝕刻法來形成 一個單邊斜角漂浮閘結構，而其楔形角部份係藉由一個側 邊牆介電墊層來定義。 本發明之自動對準分閘式快閃細胞元結構係用來組成 兩種無接點陣列架構：一種非或型快閃記憶陣列及一種平 行共源/汲導電位元線快閃記憶陣列。上述之無接點非或 型快閃記憶陣列至少包含複數共源導電管線交變地形成於 該共源區之内且與複數主動區及複數平行淺凹槽隔離區互 為垂直；複數共汲導電島至少形成於沿著該共汲區之每一 個的該複數主動區之上且位於該複數共源導電管線之間； 複數自動對準分閘式快閃細胞元結構形成於該複數共源導 電管線的每一條及其相鄰共汲導電島之間且具有一個延伸 平面化控制/選擇閘導電層作為一條字線；以及複數金屬 位元線與該複數共汲導電島積體化連結且同時經由複數硬 質罩幕介電層對準於該複數主動區來成形及蝕刻。 本發明之無接點平行共源/汲導電位元線快閃記憶陣 列至少包含複數共源導電位元線及複數共汲導電位元線交 變地形成且與複數主動區及複數平行淺凹槽隔離區互為垂 直；複數自動對準分閘式快閃細胞元結構形成於該複數共 源導電位元線之每一個及該複數共汲導電位元線之每一個 之間；以及複數金屬字線與複數平面化控制/選擇閘導電 島積體化連結且同時經由複數硬質罩幕介電層對準於該複 數主動區來成形及蝕刻。Page 8 586219 V. Description of the invention (4) The first protruding / planarized field oxide layer of the isolation region is on a part of the surface. The aforementioned wedge-shaped floating gate structure is formed by a non-isotropic dry etching method to form a single-sided oblique-angle floating gate structure, and its wedge-shaped corner portion is defined by a side wall dielectric cushion. The self-aligned split-type flash cell structure of the present invention is used to form two contactless array architectures: a non-or flash memory array and a parallel common source / drain conductive bit line flash memory array. The above non-contact non-or-type flash memory array includes at least a plurality of common source conductive pipelines alternately formed in the common source region and perpendicular to the plurality of active regions and the plurality of parallel shallow groove isolation regions. Conductive islands are formed at least on the plurality of active regions along each of the common drain regions and between the plurality of common source conductive lines; a plurality of automatically aligned split-type flash cell structures are formed on the plurality of common sources Each of the conductive pipelines and its adjacent common drain islands have an extended planarization control / selection gate conductive layer as a word line; and a plurality of metal bit lines are integrally connected with the plurality of common drain islands and At the same time, a plurality of hard mask dielectric layers are aligned to the plurality of active regions for forming and etching. The non-contact parallel common source / drain conductive bit line flash memory array of the present invention includes at least a plurality of common source conductive bit lines and a plurality of common drain conductive bit lines alternately formed and parallel to a plurality of active regions and a plurality of shallow recesses. The trench isolation regions are vertical to each other; a plurality of automatically aligned switching flash cell structures are formed between each of the plurality of common source conductive bit lines and each of the plurality of common drain conductive bit lines; and a plurality of metals The word lines are integrated with the plurality of planarization control / selection gate conductive islands and are simultaneously formed and etched by aligning the plurality of active mask regions with the plurality of hard mask dielectric layers.

586219 五、發明說明（5) 發明實施方式： 現請參見圖二A至圖二C，其中揭示製造本發明之一種 自動對準为閘式快閃細胞元結構及其無接點快閃記憶陣列 之一種淺凹槽隔離（ST I )結構的製程步驟及其剖面圖。 圖二A顯示一個第一閘介電層3〇丨形成於一種第一導電 型的一個半導體基板30 0之上；一個第一導電層3〇 2形成於 該第一閘介電層301之上；以及複數罩幕光阻pR1形成於該 第一導電層30 2之上來定義複數主動區（八八，3)(?以之下）及 複數平行淺凹槽隔離區（STI lines)(PRl之間）。上述之第 一閘介電層係一個熱氧化（thermal oxide)層或一個氮化 (ni trided)熱氧化層，其厚度係介於6〇埃和ι2〇埃之間。 上述之第一導電層30 2係由摻雜（doped)複晶矽或摻雜非晶 矽所組成且利用低壓化學氣相堆積法（LPCVD)來堆積，其 厚度係介於1 0 0 0埃和5 0 0 0埃之間。這裡值得一提的是，上 述之複數罩幕光阻PR 1的寬度及間距可以利用所使用技術 的一個最小線寬（F )來定義，如圖二A所標。 圖二B顯示位於該複數罩幕光阻pr 1之間的該第一導電 層3 0 2及該第一閘介電層3 0 1係藉由非等向乾式蝕刻法循序 地加予去除，然後非等向性地蝕刻該半導體基板3 〇 〇以形 成淺凹槽，接著去除該複數罩幕光阻 PR1。上述之淺凹槽 於該半導體基板30 0内的深度係介於3000埃和8000埃之間 圖 C顯示一個平面化場氧化物層3 0 3 a係填平圖二B所586219 V. Description of the invention (5) Embodiments of the invention: Please refer to FIG. 2A to FIG. 2C, which discloses the fabrication of an auto-aligned gated flash cell structure and a contactless flash memory array of the present invention. The process steps of a shallow groove isolation (ST I) structure and its sectional view. FIG. 2A shows that a first gate dielectric layer 30 is formed on a semiconductor substrate 300 of a first conductivity type; a first conductive layer 30 is formed on the first gate dielectric layer 301. ; And a plurality of mask photoresist pR1 is formed on the first conductive layer 302 to define a plurality of active regions (88,3) (below?) And a plurality of parallel shallow groove isolation regions (STI lines) (PR1 of between). The first gate dielectric layer is a thermal oxide layer or a ni trided thermal oxide layer, and its thickness is between 60 angstroms and 20 angstroms. The first conductive layer 302 is composed of doped polycrystalline silicon or doped amorphous silicon and is deposited by low pressure chemical vapor deposition (LPCVD). The thickness is between 100 angstroms and 100 angstroms. And 5 0 0 0 Angstroms. It is worth mentioning here that the width and pitch of the aforementioned multiple mask photoresist PR 1 can be defined using a minimum line width (F) of the technology used, as shown in Figure 2A. FIG. 2B shows that the first conductive layer 3 02 and the first gate dielectric layer 3 0 1 between the plurality of photoresistors pr 1 are sequentially added and removed by anisotropic dry etching. Then the semiconductor substrate 300 is anisotropically etched to form a shallow groove, and then the plurality of mask photoresist PR1 is removed. The depth of the shallow groove in the semiconductor substrate 300 is between 3000 angstroms and 8000 angstroms. Figure C shows a planarized field oxide layer 3 0 3 a.

第10頁 586219 五、發明說明（6) 示的每一個空隙。上述之平面化場氧化物層3 〇 3&係由二氧 化矽、磷玻璃（P-glass)、或硼磷玻璃（BP-giass)所組成 且利用LPCVD、高密度電漿（HDP)CVD、或電漿增強（PE)CVD 法來堆積，係先堆積一個厚二氧化矽膜3 0 3以填滿每一個 空隙，然後利用化學-機械磨平法（CMP)將所堆積之厚二氧 化矽膜3 0 3加予平面化並以該成形第一導電層3〇2a作為一 個磨平停止層（polishing stop)。圖二C又顯示一個第一 罩幕介電層3 0 4形成於由該平面化場氧化物層3〇3a及該成 形第一導電層302 a所交變地組成的一個平坦表面之上。上 述之第一罩幕介電層3 0 4係由氮化石夕所組成且利用l p c V D法 f 來堆積，其厚度係介於4 0 0 0埃和1 2 0 0 〇埃之間。圖二c所標 示之沿著一個主動區（A A)的一條C-C’線的剖面圖係顯示於 圖三A。 現請參見圖三A至圖三L，其中揭示製造本發明之一種 自動對準分閘式快閃細胞元結構及其無接點非或型快閃記 憶陣列的製程步驟及其剖面圖。Page 10 586219 V. Every gap shown in the description of the invention (6). The planarized field oxide layer 3 above is composed of silicon dioxide, phosphorus glass (P-glass), or borophosphoglass (BP-giass), and uses LPCVD, high-density plasma (HDP) CVD, Or plasma enhanced (PE) CVD method, first deposit a thick silicon dioxide film 3 0 3 to fill each gap, and then use chemical-mechanical smoothing (CMP) method to deposit the thick silicon dioxide The film 303 is planarized and the shaped first conductive layer 302a is used as a polishing stop. FIG. 2C shows that a first mask dielectric layer 304 is formed on a flat surface composed of the planarized field oxide layer 303a and the formed first conductive layer 302a alternately. The above-mentioned first mask dielectric layer 3 04 is composed of nitride nitride and is stacked using the l p c V D method f, and its thickness is between 4 Angstroms and 12 Angstroms. A cross-sectional view of a C-C 'line along an active area (A A) shown in FIG. 2c is shown in FIG. 3A. Referring now to FIGS. 3A to 3L, the process steps and cross-sectional views of manufacturing an auto-aligned split-type flash cell structure and a contactless non-or type flash memory array according to the present invention are disclosed.

圖三A僅揭示一個記憶陣列的一小部份，其中複數罩 幕光阻PR2係形成於該第一罩幕介電層3〇4之上以定義複數 第一虛擬閘區VG1 (介於PR2之間）及複數第二虛擬閘區VG2 (PR2之下）。上述之複數第一虛擬閘區（VG1)的每一個包含 一個共汲區及一對漂浮閘區。上述之複數第二虛擬閘區（ VG2)的每一個包含一個共源區及一對選擇閘區。這裡值得 一長：的疋，该第一虛擬閘區（VG1 )及該第二虛擬閘區（ν〇2) 係可以微縮化（s c a 1 a b 1 e )。FIG. 3A only reveals a small part of a memory array, in which a plurality of mask photoresistors PR2 are formed on the first mask dielectric layer 30 to define a plurality of first virtual gate regions VG1 (between PR2 Between) and plural second virtual gates VG2 (below PR2). Each of the plurality of first virtual gate areas (VG1) includes a common draw area and a pair of floating gate areas. Each of the plurality of second virtual gate regions (VG2) includes a common source region and a pair of selected gate regions. Here it is worth a long: 疋, the first virtual gate area (VG1) and the second virtual gate area (ν〇2) can be miniaturized (s c a 1 a b 1 e).

第11頁 586219 五、發明說明（7) 圖三B顯示位於該複數罩幕光阻PR2之間的該第一罩幕 介電層3 0 4係選擇性地加予去除，然後回蝕位於該複數平 订淺凹槽隔離區（sti unes)的該平面化場氧化物層3〇3a 以形成第一突出場氧化物層3 〇 3b，接著利用非等向乾式蝕 刻法蝕刻位於該第一虛擬閘區（VG丨）之該成形第一導電層 3 〇2a使其具有一個斜角θ ，然後去除該複數罩幕光阻pR2 。上述之平面化％氧化物層3〇3a及該成形第一導電層3〇2& 的蝕刻深度係一樣且約等於5 〇 〇埃和丨5 〇 〇埃之間，而該斜 角0係介於1 0度至3 0度之間。Page 11 586219 V. Description of the invention (7) FIG. 3B shows that the first mask dielectric layer 3 0 4 is selectively removed between the plurality of mask photoresist PR2, and then etched back to the The planarized field oxide layer 303a of the shallow trench isolation area is flattened to form a first protruding field oxide layer 303b, and then the non-isotropic dry etching method is used to etch the first dummy field oxide layer 303b. The shaped first conductive layer 302a of the gate region (VG 丨) has an oblique angle θ, and then the complex mask photoresist pR2 is removed. The etched depth of the planarized% oxide layer 303a and the formed first conductive layer 302 & is the same and is approximately equal to between 500 angstroms and 500 angstroms, and the oblique angle 0 is between Between 10 degrees and 30 degrees.

圖二c顯不一個第一閘間（intergate)介電層3〇5a係形 成於圖三B所示之該成形第一導電層3〇2b之上。這裡值得 強凋的疋，上述之第一閘間介電層3〇5a係一個熱複晶矽氧 化（poly-oxide)層或一個氮化熱複晶矽氧化層且其厚度係 介於150埃和3 0 0埃之間。圖三c又顯示一個平面化第二導 電層3 0 6a(未圖示）係形成於該第一閘間介電層3〇5&之上， 然後被回蝕以形成一個回蝕第二導電層3〇6b。上述之 化第二導電層3 0 6_由摻雜複晶矽或摻雜非晶矽 LP^ 3〇β^λFigure 2c shows that a first intergate dielectric layer 305a is formed on the shaped first conductive layer 30b shown in Figure 3B. Here it is worthy of strong decay. The first inter-gate dielectric layer 305a is a thermal polycrystalline silicon oxide layer or a nitrided thermal polycrystalline silicon oxide layer with a thickness of 150 angstroms. And 300 Angstroms. Figure 3c shows that a planarized second conductive layer 3 06a (not shown) is formed on the first inter-gate dielectric layer 3005 & and then etched back to form an etched back second conductive layer. Layer 306b. The above-mentioned modified second conductive layer 3 0 6_ is composed of doped polycrystalline silicon or doped amorphous silicon LP ^ 3〇β ^ λ

/ >母個工隙，然後利用CMP法將所堆積之厚第二導雷层 :〇上加予平面化、並以該成形第一罩幕介電層3〇6作：一個磨 平彳T止層。攻裡值得一提的是，一個金屬矽化物層 不）可以藉由上述之回蝕第二導電層3〇6b的一個 置於該回姓第二導電層3。61)之…該金屬石夕化物：：j 個矽化鎢（WS 1 2 )或鎢（w)層。圖三c又顯示一個平面化覆蓋/ > a gap, and then use the CMP method to add a thick second layer of lightning guide: 0 to planarize, and use the formed first mask dielectric layer 306 as a flattened 彳T stop layer. It is worth mentioning that a metal silicide layer cannot be used to etch back one of the second conductive layers 306b to the second conductive layer 3.61) of the metal stone eve. Compounds: j tungsten silicide (WS 1 2) or tungsten (w) layers. Figure 3c shows another flat coverage

第12頁 586219 五、發明說明（8) 乳化層3 0 7 a係填平琴笛 ^ . 〆*认社 十口亥第一虛擬閘區（VG1)的每一個 係先堆積一個厚-g /μ〜0 手一虱化石夕膜3 0 7以填滿每一個空隙 用CMP法將所堆積之厘一 &A a具/雨母1固工丨永 ^ ^ # a 厗一虱化矽層3 0 7加予平面化並 y 一 電層3 0 4 a作為一個磨平停止層。 泌@ ^ ΐ ^顯不位於該第二虛擬閘區（VG2)的每一個 : ;1電層3 04樣利用高溫磷酸或非等向乾 法2予去除，然後一個緩衝側邊牆介電墊層308a係 = Ϊ擬閘區（VG2)的每一個之所去除的該成形 幕7丨電層3 04a的每一個側邊牆之上。上述之緩衝側 電墊層308a係由氮化矽所組成且利用LpcVD法來堆 墊層寬度主要係形成一個緩衝區以供後續該成形第 層3 0 2 c (圖二e )之侧邊牆氧化之用。這裡可以清楚 、’上述之緩衝側邊牆介電墊層3 0 8a提供兩種功能： 避，，模形尖端受到非等向乾式蝕刻時所產生的破 一是提供一個側邊牆氧化的一個緩衝區，以避免尖 被純化。 ，圖三E顯示位於該第二虛擬閘區（VG2)的每一個 於"亥對緩衝側邊牆介電墊層3 0 8 a之間的該成形第一 $3 0 2 b係利用非等向乾式敍刻法來加予去除，然後以 準的方式進行離子佈植並於該複數主動區（AA)的每 内的該半導體基板300之表面形成一種第一導電型 離T佈植區309a，其中上述之離子佈植區309 a至少 個&離子佈植區如一個虛線所標示以作為臨界電壓 及一個深離子佈植區如打X X χ號所標示以形成一 空隙， ’再利 以該成 之該成 式蝕刻 形成於 第一罩 邊牆介 積，其 一導電 地看到 其一是 壞；另 端電極 之内位 導電層 自動對 一個之 的一個 包含一 的調整 個抵穿Page 12 586219 V. Description of the invention (8) Emulsified layer 3 0 7 a fills the piano flute ^. 〆 * Each of the first virtual gate area (VG1) of Shishehai is stacked one thick -g / μ ~ 0 Fossil membrane of hand lice 3 0 7 To fill each gap, use CMP method to collect the stacked centimeters & A a tool / rain mother 1 solid work 丨 Yong ^ ^ # a 虱 lice silicon layer 3 0 7 is planarized and an electric layer 3 0 4 a is used as a flattening stop layer. Bi @ ^ ΐ ^ is not located in each of the second virtual gate area (VG2): 1 electric layer 3 04 sample is removed using high temperature phosphoric acid or anisotropic dry method 2 and then a buffer side wall dielectric pad Layer 308a = above each of the side walls of the forming curtain 7 丨 electrical layer 3 04a removed from each of the pseudo gate areas (VG2). The above-mentioned buffer-side electrical cushion layer 308a is composed of silicon nitride and the width of the cushion layer is formed by using the LpcVD method to form a buffer zone for the subsequent forming of the side wall of the second layer 3 2 c (Figure 2e). Used for oxidation. It can be clearly stated here that the above-mentioned buffer side wall dielectric cushion layer 3 0 8a provides two functions: avoiding, and breaking the mold tip when subjected to anisotropic dry etching. One is to provide a side wall oxidation. Buffer to avoid the tips from being purified. FIG. 3E shows that the first $ 3 0 2 b formed between each of the second virtual gate area (VG2) between " Hai pair buffer side wall dielectric cushion layer 3 0 8 a is a non-equal It is removed by dry engraving, and then ion implantation is performed in a quasi manner and a first conductive type T-implanted region 309a is formed on the surface of the semiconductor substrate 300 in each of the plurality of active regions (AA) Among them, the above-mentioned ion implantation area 309 a has at least one & ion implantation area as indicated by a dashed line as a critical voltage and a deep ion implantation area as indicated by XX χ to form a gap. The formation of the formation is formed in the side wall of the first cover, and one of them is conductively seen and the other is bad; the inner conductive layer of the other electrode automatically adjusts the resistance of one of them including one.

586219 五、發明說明（9) 禁止區(punch-through stop)° 圖三F顯示進行一個熱氧化製程以形成一個第二閘介 電層3lla於該主動區的每一個之該半導體基板300的表面 之上及形成一個第二閘間介電層3 1 0a於該成形第一導電層 3 0 2 c的每一個側邊牆之上，然後該對緩衝侧邊牆介電墊層 3 0 8 a係利用高熱磷酸加予去除。這裡可以清楚看到，該第 二閘間介電層3 1 〇 a係交錯地形成於該尖端電極之上，本發 明之該尖端電極具有一個高場發射效率是可以預期的。另 外，在未去除該對緩衝側邊牆介電墊層308a之前，可以藉 由一個笑氣（N 2〇)或氨氣的環境進行一個熱氮化製程以氮化⑩ 該第二閘間介電層3 1 0 a及該第二閘介電層3 1 1 a，以增強該 尖端電極之該第二閘間介電層31〇a的耐用性（endurance) 圖三F又顯示一個平面化第三導電層3 12a (未圖示）係 形成於該第二虛擬閘區（VG 2)的每一個空隙且回蝕等於該 平面化覆蓋氧化層307 a的厚度，以形成一個回钱第三導電 層312b。上述之回触第二導電層312 b係由摻雜複晶石夕或捧 雜非晶矽所組成且利用LPCVD法來堆積。相似地，該回^ 第三導電層31 2b可以是一個複合導電層，諸如一個^ (WSh )或鎢（W)層形成於一個摻雜複晶矽或摻雜… 上，如同該回蝕第二導電層306b的形成方法。圖二卩^ 示一個第三側邊牆介電墊層3 1 3a係形成於該平面化一 $ = 化層3 0 7a的每〆個側邊牆之上且置於該第二虛擬閘區畚 一個之内的該回蝕第三導電層312 b的一部份表而* :、 仏田〈上，以586219 5. Description of the invention (9) Punch-through stop ° Figure 3F shows that a thermal oxidation process is performed to form a second gate dielectric layer 3111 on the surface of the semiconductor substrate 300 in each of the active regions. And a second inter-gate dielectric layer 3 1 0a is formed on each side wall of the first conductive layer 3 0 2 c, and then the pair of buffer side wall dielectric pads 3 0 8 a It is removed by addition of high-temperature phosphoric acid. It can be clearly seen here that the second inter-gate dielectric layers 3 1 0a are staggeredly formed on the tip electrode, and it is expected that the tip electrode has a high field emission efficiency. In addition, before removing the pair of buffer side wall dielectric pads 308a, a thermal nitridation process may be performed in a N2O or ammonia environment to nitride the second interlayer dielectric. Electrical layer 3 1 0 a and the second gate dielectric layer 3 1 1 a to enhance the endurance of the second inter-gate dielectric layer 31〇a of the tip electrode FIG. 3F shows a planarization The third conductive layer 3 12a (not shown) is formed in each gap of the second virtual gate area (VG 2) and etched back is equal to the thickness of the planarized cover oxide layer 307 a to form a third money back The conductive layer 312b. The above-mentioned second conductive layer 312 b is composed of doped polycrystalline silicon or doped amorphous silicon and is deposited by the LPCVD method. Similarly, the third conductive layer 31 2b may be a composite conductive layer, such as a (WSh) or tungsten (W) layer formed on a doped polycrystalline silicon or doped ... A method for forming the two conductive layers 306b. Figure 2 卩 ^ shows a third side wall dielectric cushion layer 3 1 3a is formed on each side wall of the planarization layer = 0 7a and is placed in the second virtual gate area A part of the etched back third conductive layer 312 b within one is shown as follows: *, Putian

586219 五、發明說明（ίο) 定義該選擇閘區。586219 5. Description of the invention (ίο) Define the selection gate area.

圖三G顯示複數罩幕光阻PR3形成於該平面化覆蓋氧化 層307 a之上及鄰近第三側邊牆介電墊層313a的一部份表面 之上’然後該回#第三導電層先回蝕至該平面化場氧化層 30 3a的一個頂部水平，再以自動對準的方式非等向性地回 蝕該複數平行淺凹槽隔離區（STi lines)的每一個之該平 面化場氧化物層3 0 3 a至該第二閘介電層3丨丨a的一個頂部水 平以形成第一突場氧化物層3 0 3 c (未圖示），接著非等向性 地去除殘留的回#第二導電層312 b以形成由該第二閘介電 層3 1 1 a及該第一突出場氧化物層303 c所交變地組成的一個 第一平坦表面於該共源區的每一個之内，然後以自動對準 的方式跨過該第二閘介電層311 a佈植摻雜質於該複數主動 區的每一個之該半導體基板300的表面以形成一種第二導 電型的共源擴散區3 1 4 a。上述之共源擴散區3 1 4 a可以是淡 摻雜、中度摻雜、或高摻雜。FIG. 3G shows that a plurality of mask photoresists PR3 are formed on the planarized cover oxide layer 307a and a portion of the surface adjacent to the third side wall dielectric pad layer 313a. First etch back to a top level of the planarized field oxide layer 30 3a, and then anisotropically etch back the planarization of each of the plurality of parallel shallow groove isolation regions (STi lines) in an automatic alignment manner. The field oxide layer 3 0 3 a to a top level of the second gate dielectric layer 3 丨 丨 a forms a first burst field oxide layer 3 0 3 c (not shown), and is then removed anisotropically. The remaining second conductive layer 312 b forms a first flat surface composed of the second gate dielectric layer 3 1 1 a and the first protruding field oxide layer 303 c alternately on the common source. Within each of the regions, a dopant is then implanted across the second gate dielectric layer 311 a in an automatic alignment manner on the surface of the semiconductor substrate 300 in each of the plurality of active regions to form a second The conductivity type common source diffusion region 3 1 4 a. The above-mentioned common source diffusion region 3 1 4 a may be lightly doped, moderately doped, or highly doped.

圖三Η顯示一對第一側邊牆介電墊層3 1 5 a係形成於該 共源區的每一個側邊牆之上且置於該第一平坦表面的一部 份表面之上，然後以自動對準的方式跨過該第二閘介電層 3 1 1 a佈植一個高劑量的摻雜質於該複數主動區的每一個之 該半導體基板300的表面以形成該第二導電型的一個高摻 雜共源擴散區3 1 4b於該共源擴散區3 1 4a的每一個之内，接 著利用稀釋氫氟酸溶液的泡浸法或非等向乾式蝕刻法去除 位於該對第一側邊牆介電墊層3 1 5a之間的該第二閘介電層 3 1 1 a並同時蝕刻該第二突出場氧化物層3 0 3 c以組成一個第FIG. 3A shows that a pair of first side wall dielectric pads 3 1 5 a are formed on each side wall of the common source region and are placed on a part of the first flat surface. A high-dose dopant is then implanted across the second gate dielectric layer 3 1 1 a on the surface of the semiconductor substrate 300 in each of the plurality of active regions in an automatic alignment manner to form the second conductive layer. A highly doped common source diffusion region 3 1 4b of each type is located in each of the common source diffusion regions 3 1 4a, and then a dilute hydrofluoric acid solution or a non-isotropic dry etching method is used to remove the The second gate dielectric layer 3 1 1 a between the first side wall dielectric pads 3 1 5 a and simultaneously etches the second protruding field oxide layer 3 0 3 c to form a first

第15頁 586219 五、發明說明（11) 一平坦床於該共源區的每一個之内。上述之第一平坦床係 交變地由該高摻雜共源擴散區3 1 4b及一個第三突出場氧化 物層3 0 4d所組成。圖三Η又顯示一個共源導電管線3 1 7b / 3 1 6b係形成於該共源區的每一個之該對第一側邊牆介電墊 層3 1 5a之間的該第一平坦床之上，然後一個第一平面化厚 二氧化矽層3 1 8 a係形成於該共源區的每一個之該共源導電 管線3 1 7b/ 3 1 6b及該對第一側邊牆介電墊層3 1 5a之上。上 述之第一側邊牆介電墊層3 1 5 a係由氮化矽或二氧化石夕所組 成且利用LPCVD法來堆積。上述之共源導電層31 6b係由摻 雜複晶石夕所組成且利用L P C V D法來堆積，係先堆積一個厚 第四導電層3 1 6來填滿該對第一側邊牆介電墊層3丨5a之間 的每一個空隙，然後利用CMP法將所堆積的厚第四導電層 3 1 6加予平面化並以該對第三側邊牆介電層3丨3a作為磨平 停止層，接著回蝕該平面化第四導電層3丨6a。上述之共源 覆蓋導電層3 1 7b可以是矽化鎢或鎢層，其中上述之矽化鎢 或鎢層可以利用類似該共源導電層316b的形成方法成 。這裡值得一提的是，該摻雜 植一個高劑量的摻雜質以作為 高摻雜共源擴散區3 1 4b於該共 。上述之第一平面化厚二氧化 玻璃（P-glass)、或硼磷玻璃 LPCVD、HDPCVD、或 PECVD法來 化厚二氧化矽層3 1 8a係先堆積 個結構表面之上，再利用CMP 複晶石夕層3 1 6 b可以進一步佈 形成該第二導電型的一個淺 源擴散區3 1 4 a的每一個之内 石夕層3 1 8 a係由二氧化矽、磷 (BP-glass)所組成且係利用 堆積。相似地，該第一平面 一個厚二氧化矽層318於整 法將所堆積之厚二氧化矽層 586219 五、發明說明（12) 气二平面化並以該對第三側邊牆介電塾層3 1 3a作為磨 二：二圖三Η又顯示複數罩幕光阻PR“a)係形成於該 ^、’’、品、母個之上及鄰近第三側邊牆介電墊層3 1 3a之一 部份表面之上。 圖一 1 員示該平面化覆蓋氧化層3 0 7 a係利用緩衝氫氟 =液，非等向乾式钱刻法加予去除，然後去除；= 阻=R4(a)，接著一個第四側邊牆介電墊層以以形成於 =第二虛擬閉區（VG1)的每一個側邊牆之上且置於該回餘 第一導電層3 0 6b的一部份表面之上來定義該漂浮閘區。 圖三J顯示複數罩幕光阻pR4(a)再次形成於先前複數 ί ί ^阻PR4(a)之相同的位置，然後位於該對第四側邊牆 二電墊層31 9a之間的該回蝕第二導電層3〇6b及該第一閘間 =電層30 5a係循序地被去除，接著該第一突出場氧化物層 30jb係被回蝕至等於該第一閘介電層3〇lb之頂部水平，然 ，該成形第一導電層3 0 2c以自動對準的方式利用非等向& 二=刻法加予去除以形成由該第一閘介電層3 〇 1 b及一個第 二大出％氧化物層3 0 3 e所組成的一個第二平坦表面，再接 著以自動對準的方式進行離子佈植以形成該第二導電型的 共汲擴散區32 0a於該共汲區的每一個之該複數主動區的該 半導體基板30 0的表面。上述之共汲擴散區32〇a可以是淡 摻雜、中度摻雜、或高摻雜。 圖三K顯示上述之複數罩幕光阻PR4(b)被去除，接著 一個第二側邊牆介電墊層3 2 1 a形成於該共汲區的每一個内 側邊牆之上及置於該第二平坦表面的一部份表面之上，然Page 15 586219 V. Description of the invention (11) A flat bed is within each of the common source areas. The above-mentioned first flat bed is alternately composed of the highly doped common source diffusion region 3 1 4b and a third protruding field oxide layer 3 0 4d. Fig. 3 shows another common source conductive pipeline 3 1 7b / 3 1 6b formed in the first flat bed between the pair of first side wall dielectric pads 3 1 5a in each of the common source regions. On top, then a first planarized thick silicon dioxide layer 3 1 8 a is formed on the common source conductive pipeline 3 1 7b / 3 1 6b and the pair of first side walls of each of the common source regions. Electrical pad 3 1 5a. The above-mentioned first side wall dielectric pad 3 1 5 a is composed of silicon nitride or dioxide and is deposited by the LPCVD method. The above-mentioned common source conductive layer 31 6b is composed of doped polycrystalline stone and is stacked by LPCVD method. A thick fourth conductive layer 3 1 6 is first stacked to fill the pair of first side wall dielectric pads. Each gap between the layers 3, 5a, and then planarized the thick fourth conductive layer 3 1 6 stacked with the CMP method and smoothed the pair of third side wall dielectric layers 3 3a as a smooth stop Layer, and then etch back the planarized fourth conductive layer 316a. The above-mentioned common source covering conductive layer 3 1 7b may be a tungsten silicide or tungsten layer, wherein the above-mentioned tungsten silicide or tungsten layer may be formed by a method similar to the common source conductive layer 316b. It is worth mentioning here that the doping implants a high dose of dopants to serve as the highly doped common source diffusion region 3 1 4b in the common. The first planarized thick silicon dioxide (P-glass), or borophosphoglass LPCVD, HDPCVD, or PECVD method to thicken the silicon dioxide layer 3 1 8a is first deposited on the surface of the structure, and then CMP is used. The spar layer 3 1 6 b can be further formed to form a shallow source diffusion region 3 1 4 a of the second conductivity type. The slate layer 3 1 8 a is made of silicon dioxide and phosphorus (BP-glass). ) And is made up of piles. Similarly, a thick silicon dioxide layer 318 on the first plane will stack the thick silicon dioxide layer 586219 during the whole process. 5. Description of the invention (12) The gas two is planarized and the pair of third side walls are dielectric. The layer 3 1 3a is used as the grinding second: the second figure and the third figure again show that a plurality of mask photoresistors PR "a" are formed on the ^, '', the product, the mother and the dielectric pad layer 3 adjacent to the third side wall 1 3a on a part of the surface. Figure 1 shows the planarized covering oxide layer 3 0 7 a is using buffered hydrogen fluoride = liquid, non-isotropic dry money engraving method to remove and then remove; = resistance = R4 (a), followed by a fourth side wall dielectric pad to be formed on each side wall of the = second virtual closed area (VG1) and placed on the remaining first conductive layer 3 0 6b Part of the surface to define the floating gate area. Figure IIIJ shows that the multiple mask photoresistor pR4 (a) is formed again in the same position as the previous plural PR4 (a), and is then located in the fourth pair. The etched back second conductive layer 306b and the first gate = electrical layer 30a between the two side wall electrical pads 31-9a are sequentially removed, and then the first protruding field oxide layer 30jb is etched back to a level equal to the top of the first gate dielectric layer 30 lb. However, the formed first conductive layer 3 2c utilizes non-isotropic & two = engraved addition in an automatic alignment manner. Removing to form a second flat surface composed of the first gate dielectric layer 3 0b and a second large-out% oxide layer 3 0 3e, and then performing ion implantation in an automatic alignment manner To form the second-conduction-type diffusion region 32 0a on the surface of the semiconductor substrate 300 of the plurality of active regions of each of the common-drain regions. The above-mentioned diffusion region 32 0a may be lightly doped. , Moderately doped, or highly doped. Figure 3K shows that the above-mentioned multiple mask photoresist PR4 (b) is removed, and then a second side wall dielectric pad layer 3 2 1 a is formed in the common drain region. Above each inner side wall and on a portion of the surface of the second flat surface, then

第17頁 586219 五、發明說明（13) 後以自動對準的方式跨過 劑量的摻雜質於該複數主 以形成該第二導電型的一 洩擴散區3 2 0 a的每一個之 3 2 1 a係由氮化矽或二氧化 。圖三K又顯示位於該對 該第一閘介電層3 0 1 b係利 乾式#刻法加予去除，而 突出場氧化物層3 0 3e亦同 ;然後，一 一個之該對 之上。上述 物層3 0 3 f及 化第五導電 第五導電層 一個高劑量 雜共汲擴散 擴散源，然 ，然後利用 提的是，在 (barrier -層可以形成 圖三 L 示的表面之 個平面化第五 第二側邊牆介 之第二平坦床 該高摻雜共沒 層3 2 2 a係一個 3 22a亦可以先 的摻雜質以作 區3 2 0 b於該共 後堆積一個厚 CMP法或傳統 未堆積該厚矽 •π e t a 1 )層諸如 於該薄摻雜複 顯不一個第'一 上且與該平面 該第一閘介電層3 0 1 b佈植一個高 動區的該半導體基板300的表面 個高摻雜共汲擴散區32Ob於該共 内。上述之第二側邊牆介電墊層 矽所組成且利用LPCVD法來堆積 第二側邊牆介電墊層3 2 1 a之間的 用稀釋氫氟酸的泡浸法或非等向 位於該共、/¾區的每一個之該第四 時被蝕刻以形成一個第二平坦床 導電層3 2 2 a係形成該共沒區的每 電墊層3 2 1 a之間的該第二平坦床 係交變地由一個第五突出場氧化 擴散區3 2 0 b所組成。上述之平面 平面化摻雜複晶矽層。該平面化 堆積一個薄複晶矽層，接著佈植 為形成該第二導電型之該淺高摻 汲擴散區320 a之内的一個摻雜質 矽化鎢或鎢膜以填滿每一個空隙 回钱法加予平面化。這裡值得一 化鎢或鎢膜之前，一個障礙金屬 一個氮化鈦（TiN)或氮化鈕（TaN) 晶碎層之上。 連線金屬層3 2 3係形成於圖三K所 化第五導電層3 22a同時經由複數Page 17 586219 V. Description of the invention (13) After the amount of dopants that cross the dose in an auto-aligned manner is formed in the plurality of mains to form a second diffusion type of each of the drain leakage regions 3 2 0 a 2 1 a is made of silicon nitride or dioxide. FIG. 3K also shows that the first gate dielectric layer 3 0 1 b is a dry-type # etch method, and the protruding field oxide layer 3 0 3e is the same; then, one by one on. The above-mentioned object layer 3 0 3 f and the fifth conductive fifth conductive layer are a high-dose heterodyne diffusive diffusion source, and then, by using the barrier-layer, a plane as shown in FIG. 3L can be formed. The second flat bed of the fifth and second side wall, the highly doped common layer 3 2 2 a is a 3 22 a, and a dopant may be used as the region 3 2 0 b after the total thickness is deposited. The CMP method or the traditional unstacked thick silicon π eta 1) layer, such as a thin active doped layer on top of the first gate dielectric layer and a first gate dielectric layer 3 0 1 b, implants a hyperactive region. A high-doped common-drain diffusion region 32Ob on the surface of the semiconductor substrate 300 is within the common. The above-mentioned second side wall dielectric cushion layer is composed of silicon and the LPCVD method is used to stack the second side wall dielectric cushion layer 3 2 1 a by a dipping hydrofluoric acid dipping method or an anisotropic method. Each of the common and / ¾ areas is etched at the fourth time to form a second flat bed conductive layer 3 2 2 a which forms the second between each of the electric pad layers 3 2 1 a of the common area. The flat bed alternately consists of a fifth protruding field oxidation diffusion region 3 2 0 b. The above-mentioned plane planarizes the doped polycrystalline silicon layer. The planarization stacks a thin polycrystalline silicon layer, and is then implanted to form a doped tungsten silicide or tungsten film within 320 a of the shallow high doped diffusion region of the second conductivity type to fill each void. Add flatness. It is worthwhile here to place a barrier metal on top of a titanium nitride (TiN) or nitride button (TaN) crystal chip before a tungsten or tungsten film. The wiring metal layer 3 2 3 is formed on the fifth conductive layer 3 22a as shown in FIG.

第18頁 586219 五、發明說明（14) 硬貝罩幕層（未圖不）來成形及蝕刻以形成複數金屬位元線 3 2 3a與複數平面化共汲導電島322b積體化連結，其中上述 之複數硬質罩幕層的每一個至少包含一個第二罩幕介電層 3 2 4a對準於該複數主動區的每一個之上及一個側邊牆介電 墊層325a(見圖四）形成於該第二罩幕介電層32乜的每一個 側邊牆之上。圖三L的各種剖面圖將分別顯示於圖四b至圖 四E中。Page 18 586219 V. Description of the invention (14) The hard shell cover layer (not shown) is formed and etched to form a plurality of metal bit lines 3 2 3a and a plurality of planarizations and a conductive island 322b integrated connection, in which Each of the plurality of hard mask layers described above includes at least one second mask dielectric layer 3 2 4a aligned on each of the plurality of active regions and a side wall dielectric cushion layer 325a (see FIG. 4). It is formed on each side wall of the second mask dielectric layer 32 '. Various cross-sectional views of FIG. 3L are shown in FIGS. 4b to 4E, respectively.

圖四A顯示本發明之一種無接點非或型快閃記憶陣列 的一個簡要頂視圖，其中沿著一條A_A，線的剖面圖係揭示 於圖三L·中。如圖四A所示，該複數主動區（aa，s)及該複數 平行淺凹槽隔離區（STI 1 ines)係交變地形成於該第一導 電型的該半導體基板3 0 0之上；複數共源導電管線317b/ 316b(CSBL)係交變地形成且與該複數平行淺凹槽隔離區（ STI lines)互為垂直，其中上述之複數共源導電管線317b / 3 1 6b的每一個係形成於該對第一側邊牆介電墊層3 1 5a之 間的該第一平坦床之上而該第一平坦床係交變地由該第三 突出場氧化物層3 0 3d及位於該共源擴散區3 1 4a之間的該淺 高摻雜共源擴散區3 1 4b所組成；該複數平面化共汲導電島 3 2 2b係交變地形成於該複數共源導電管線3 1 7b/ 3 1 6b之間 且分別置於該對第二側邊牆介電墊層3 2 1 a之間的該第二平 坦床之上，其中上述之第二平坦床係由該第五突出場氧化 物層3 0 4 f及形成於該共汲擴散區3 2 0 b的每一個之内的該淺 高摻雜共汲擴散區320 b所組成；複數自動對準分閘快閃記 憶細胞元係置於該複數共源導電管線3 1 7 b/ 3 1 6 ^^的每一個Fig. 4A shows a schematic top view of a non-contact non-or-type flash memory array of the present invention, in which a cross-sectional view taken along a line A_A is disclosed in Fig. 3 L ·. As shown in FIG. 4A, the plurality of active regions (aa, s) and the plurality of parallel shallow groove isolation regions (STI 1 ines) are alternately formed on the semiconductor substrate 300 of the first conductivity type. ; The plurality of common source conductive lines 317b / 316b (CSBL) are formed alternately and perpendicular to the plurality of parallel shallow groove isolation regions (STI lines), wherein each of the plurality of common source conductive lines 317b / 3 1 6b A system is formed on the first flat bed between the pair of first side wall dielectric pads 3 1 5a and the first flat bed is alternately formed by the third protruding field oxide layer 3 0 3d And the shallow highly doped common source diffusion region 3 1 4b located between the common source diffusion region 3 1 4a; the complex planarized common drain conductive islands 3 2 2b are alternately formed on the complex common source conduction The pipelines 3 1 7b / 3 1 6b are respectively placed on the second flat beds between the pair of second side wall dielectric pads 3 2 1 a, wherein the second flat beds are formed by the A fifth protruding field oxide layer 3 0 4 f and the shallow highly doped common-drain diffusion region 320 b formed in each of the common-drain diffusion regions 3 2 0 b; a plurality of Moving the alignment flash memorized cell opening disposed in the ternary complex were each source 3 1 7 b / 3 1 6 ^^ conductive line

第19頁 586219 五、發明說明（15) 及該複數平面化共汲導電島32 2b的每一個之間，·複數金屬 位元線323a與該複數共汲導電島322b積體化連結係同時經 由該複數硬質罩幕層來成形及蝕刻並與該複數共源導電管 線317 b/ 316 b互為垂直，其中上述之複數硬質罩幕層至少 包含該第二罩幕介電層324a對準於該主動區（AA)及該側邊 牆介電墊層3 2 5 a形成於該第二罩幕介電層3 2 4 a的每一個側 邊牆之上。圖四A所示之各種剖面圖如一條B-B，線、一條 C-C’線、一條D-D’線、及一條E-E，線所標示係分別揭示於 圖四B至圖四E中。P.19 586219 V. Description of the invention (15) and each of the plurality of planarized common conductive islands 32 2b, the complex metal bit line 323a and the complex common conductive island 322b integrated connection system are simultaneously passed The plurality of hard mask layers are formed and etched and are perpendicular to the plurality of common source conductive lines 317 b / 316 b, wherein the plurality of hard mask layers include at least the second mask dielectric layer 324a aligned with the An active area (AA) and the side wall dielectric pad 3 2 5 a are formed on each side wall of the second mask dielectric layer 3 2 4 a. Various cross-sectional views shown in FIG. 4A are a B-B, a line, a C-C 'line, a D-D' line, and an E-E. The lines are respectively shown in FIGS. 4B to 4E.

現請參見圖四B至圖四E，其中揭示圖四a所標示的各 種不同剖面圖。圖四B顯示圖四A所示之沿著該共源區如 一條B - B ’線所標示的一個剖面圖，其中上述之共源導電管 線317b/ 31 6b係形成於由該第三突出場氧化物層3 0 3d及位 於該共源擴散區3 1 4 a之内的該淺高摻雜共源擴散區3 1 4 b所 組成；一個第一平面化厚二氧化矽層3 1 8 a係形成於該共源 導電管線317b/ 3 16b之上；以及複數金屬位元線323a藉由 上述之複數硬質罩幕層來成形及餘刻係形成於該第一平面 化厚二氧化矽層31 8a之上。Please refer to FIG. 4B to FIG. 4E, which disclose various cross-sectional views indicated in FIG. 4a. FIG. 4B shows a cross-sectional view shown in FIG. 4A along the common source area as indicated by a B-B 'line, wherein the aforementioned common source conductive pipeline 317b / 31 6b is formed by the third protruding field An oxide layer 3 0 3d and the shallow highly doped common source diffusion region 3 1 4 b within the common source diffusion region 3 1 4 a; a first planarized thick silicon dioxide layer 3 1 8 a Is formed on the common source conductive pipeline 317b / 3 16b; and a plurality of metal bit lines 323a are formed and formed on the first planarized thick silicon dioxide layer 31 by the plurality of hard mask layers described above 8a or more.

圖四C顯示圖四A所示之沿著該選擇閘區如一條C - C，線 所標示的一個剖面圖，其中上述之平面化控制/選擇閘導 電層3 1 2 c係交變地形成於該平面化場氧化物層3 0 3 a及該第 二閘介電層3 11 b之上；該第三側邊牆介電墊層3 1 3a係置於 該平面化控制/選擇閘導電層3 1 2 c之上；以及該複數金屬 位元線3 2 3 a係形成於該第三側邊牆介電墊層3 1 3 a之上係藉FIG. 4C shows a cross-section view along the selection gate area such as a C-C line shown in FIG. 4A, in which the above-mentioned planarization control / selection gate conductive layer 3 1 2 c is formed alternately. Above the planarized field oxide layer 3 0 3 a and the second gate dielectric layer 3 11 b; the third side wall dielectric cushion layer 3 1 3a is placed on the planarization control / selection gate conductive Layer 3 1 2 c; and the plurality of metal bit lines 3 2 3 a are formed on the third side wall dielectric pad layer 3 1 3 a

586219 五、發明說明（16) 由上述之複數硬質罩幕層來成形及蝕刻。該第一導電型的 該離子佈植區3 0 9 b形成於該第二閘介電層3 1 1 b之下至少包 含一個淺離子佈植區如虛線所標示以作為臨界電壓的調整 及一個深離子佈植區如打X X X號所標示以形成一個抵穿 禁止區。 圖四D顯示圖四A所示之沿著該漂浮閘區如一條D""D’線 所標示之一個剖面圖，其中該第一閘間介電層3 0 5 b係形成 於該漂浮閘層3 0 2 d之上；一個平面化控制/選擇閘導電層 30 6c係交變地形成於該第一突出場氧化物層3 0 31)及該第一 閘間介電層3 0 5 b之上；一個第四側邊牆介電墊層3 1 9 a係形 成於該平面化控制/選擇閘導電層30 6c之上；以及該複數 金屬位元線323 a藉由所述之複數硬質罩幕層324 a〆325 3來 成形及蝕刻。 圖四E顯示圖四A所示之沿著該共汲區如一條E — E ’線所 標示之一個剖面圖，其中上述之複數金屬位元線3 2 3 a與該 複數平面化共汲導電島322 b係同時藉由上述之複數硬質罩 幕層324a/ 32 5a來成形及蝕刻。上述之複數平面化共汲導 電島3 2 2 b的每一個係至少形成於該第二平坦床之該淺高摻 雜共汲擴散區320 b之上。上述之第二平坦床係交變地由該 第五突出場氧化物層3 0 3 f及該淺高摻雜共汲擴散區3 2 0 b形 成於該共汲擴散區3 2 0 a之内所組成。上述之複數硬質罩幕 層3 2 4 a/ 3 2 5 a的每一個至少包含該第二罩幕介電層324 a對 準於該主動區之上及該側邊牆介電墊層3 24a形成於該第二 罩幕介電層324a的每一個側邊牆之上以消除誤對準，以形586219 V. Description of the invention (16) Formed and etched by the above-mentioned plural hard cover curtain layers. The ion implantation region 3 0 9 b of the first conductivity type is formed under the second gate dielectric layer 3 1 1 b and includes at least one shallow ion implantation region as indicated by a dashed line as a threshold voltage adjustment and a The deep ion implantation area is marked as XXX to form a penetration prohibited area. FIG. 4D shows a cross-sectional view along the floating gate area as indicated by a D " D 'line shown in FIG. 4A, in which the first inter-gate dielectric layer 3 0 5 b is formed on the floating gate. Above the gate layer 3 0 2 d; a planarization control / selection gate conductive layer 30 6c is alternately formed on the first protruding field oxide layer 3 0 31) and the first inter-gate dielectric layer 3 0 5 b; a fourth side wall dielectric cushion layer 3 1 9 a is formed on the planarization control / selection gate conductive layer 30 6c; and the plurality of metal bit lines 323 a by the plurality The hard mask layer 324 a〆325 3 is formed and etched. FIG. 4E shows a cross-sectional view indicated by an E—E ′ line along the common drain region shown in FIG. 4A, in which the above-mentioned plurality of metal bit lines 3 2 3 a and the plurality of planarization planes are collectively conductive. The island 322 b is simultaneously formed and etched by the above-mentioned plural hard cover curtain layers 324 a / 32 5 a. Each of the above-mentioned plurality of planarized common-drain conductive islands 3 2 2 b is formed at least on the shallow high-doped common-drain diffusion region 320 b of the second flat bed. The above-mentioned second flat bed is alternately formed within the common-drain diffusion region 3 2 0 a by the fifth protruding field oxide layer 3 0 3 f and the shallow highly doped common-drain diffusion region 3 2 0 b. Composed of. Each of the plurality of hard mask layers 3 2 4 a / 3 2 5 a includes at least the second mask dielectric layer 324 a aligned on the active area and the side wall dielectric cushion layer 3 24 a It is formed on each side wall of the second mask dielectric layer 324a to eliminate misalignment.

第21頁 586219Page 586219

五、發明說明（17) 成無接點的接觸結構。 現請參見圖五A至圖五C’其中揭示接續圖三K之後的 製程步驟及其剖面圖以製造本發明之一種自動對準分閘式 快閃細胞元結構及其無接點平行共源/沒導電位元線快^ 記憶陣列。5. Description of the invention (17) A contactless contact structure. Please refer to FIG. 5A to FIG. 5C ′. The process steps and cross-sectional views following FIG. / No conductive bit line fast ^ memory array.

圖五纖示圖三K所示之位於該共汲區的每一個之内的 該平面化第五導電層322a係經回蝕以形成一個共汲導電展 3 2 2c，然後一個共汲覆蓋導電層32 6b係形成於該共歧導^ 層3 2 2c之上，接著一個第二平面化厚二氧化矽層32 7^4 成於該共汲覆蓋導電層326 b之上。相似地，上述之共& 蓋導電層32 6b可以利用製造該共源覆蓋導電層31 7b的相覆 製程來形成。上述之第二平面化厚二氧化矽層327a係由， 氧化矽、磷玻璃（P-glass)、或硼磷玻璃（BP-glass)所了 成且利用LPCVD、HDPCVD、或PECVD法來堆積。 說 圖五B顯示該第一 /第二平面化厚二氧化矽層3l8a/Figure 5 shows the planarized fifth conductive layer 322a located within each of the common drain regions shown in Figure 3K. Etching back to form a common drain spreading 3 2 2c, and then a common drain covering conductive A layer 32 6b is formed on the common divergent conductive layer 3 2 2c, and a second planarized thick silicon dioxide layer 32 7 ^ 4 is formed on the common drain conductive layer 326 b. Similarly, the above-mentioned common & cap conductive layer 32 6b can be formed by a lamination process for manufacturing the common source cap conductive layer 3 17b. The above-mentioned second planarized thick silicon dioxide layer 327a is made of silicon oxide, phosphorous glass (P-glass), or borophosphate glass (BP-glass), and is deposited by LPCVD, HDPCVD, or PECVD. Say Figure 5B shows the first / second planarized thick silicon dioxide layer 318a /

3 2 7a及該第一 /第二側邊牆介電墊層3丨5a// 3 2丨a的彎曲 份係利用非等向ϋ刻法或緩衝氫氟酸溶液先加予回蝕，然 後該第三/第四側邊牆介電墊層3丨3a/ 3丨9祕利用高溫磷 酸或非等向乾式蝕刻法加予去除，接著一個平面化覆蓋閘 導電層3 28a係形成於該回蝕第二/第三導電層312c//3〇6c 之上。上述之平面化覆蓋閘導電層32 8 a係由矽化鎢（WSi 2 ) 或鎢（W )所組成。 _圖五C顯不—個第一連線金屬層3 2 9係形成於圖五B所 不的平坦表面之上且與該平面化覆蓋閘導電層32 8a、該回3 2 7a and the first / second side wall dielectric cushion layer 3 丨 5a // 3 2 丨 a The bending parts are firstly etched back by anisotropic etching or buffered hydrofluoric acid solution, and then The third / fourth side wall dielectric cushion layer 3 丨 3a / 3 丨 9 is removed by using high-temperature phosphoric acid or anisotropic dry etching, and then a planarized conductive gate conductive layer 3 28a is formed on the back. Etching on the second / third conductive layer 312c // 306c. The above-mentioned planarized conductive gate conductive layer 32 8 a is composed of tungsten silicide (WSi 2) or tungsten (W). Fig. 5C shows that a first connecting metal layer 3 2 9 is formed on the flat surface not shown in Fig. 5B and covers the gate conductive layer 32 8a and the planarization layer.

第22頁 586219 五、發明說明（18) '^ 蝕第二導電層306c、及該回蝕第三導電層312 c同時利用上 述之複數硬質罩幕層（見圖示）來同時成形及蝕刻以形成複 數金屬字線329a與複數平面化控制/選擇閘導電島328b、 31 2d、3 0 6d積體化連結，其中上述之複數硬質罩幕層的每 一個係包含一個第二罩幕介電層324a對準於該主動區之上 及一個側邊牆介電墊層3 2 5a形成於該第二罩幕介電層324a 的每一個側邊牆之上。圖五C的各種剖面圖將分別顯示於 圖六B至圖六E中。 圖六A揭示本發明之一種無接點平行共源/汲導電位 元線快閃記憶陣列的一個頂視佈建圖，其中該複數主動區 jp (AA’ s)及該複數平行淺凹槽隔離區（STI 1 ines)係交變地 形成於該第一導電型的該半導體基板300之上；該複數共 源導電管線317b/ 316b (CSBL)及複數共汲導電管線3 2 6b/ 322c (CDBL)係交變地形成且與該複數平行淺凹槽隔離區（ STI 1 ines)互為垂直；複數自動對準分閘式快閃記憶細胞 元係形成於該複數共源導電管線3 1 7b/ 3 1 6b的每一個及其 鄰近共汲導電管線3 2 6 b/ 3 2 2 c之間；以及該複數金屬字線 (WL)與該複數控制/選擇閘導電島328b、312d、3 0 6d積體 化連結係同時藉由該複數硬質罩幕層來成形及蝕刻並與該 複數共源導電管線317b/ 31 6b互為垂直，其中上述之複數 硬質罩幕層至少包含該第二罩幕介電層324a對準於該主動 區及該側邊牆介電墊層3 2 5a形成於該第二罩幕介電層324a 的每一個側邊牆之上。相似地，上述之複數共源導電管線 3 1 7b/ 3 1 6b係形成於該對第一側邊牆介電墊層3 1 5b之間的Page 22 586219 V. Description of the invention (18) '^ The second conductive layer 306c is etched, and the etched back third conductive layer 312c is simultaneously formed and etched by using the plurality of hard cover curtain layers (see the figure). A plurality of metal word lines 329a are formed to be integrated with the plurality of planarization control / selection gate conductive islands 328b, 31 2d, and 3 06d, wherein each of the plurality of hard mask layers described above includes a second mask dielectric layer 324a is aligned on the active area and a side wall dielectric pad 3 2 5a is formed on each side wall of the second mask dielectric layer 324 a. Various cross-sectional views of Fig. 5C are shown in Figs. 6B to 6E, respectively. FIG. 6A discloses a top-view layout diagram of a contactless parallel common source / drain bit line flash memory array according to the present invention, wherein the complex active area jp (AA's) and the complex parallel shallow grooves An isolation region (STI 1 ines) is alternately formed on the semiconductor substrate 300 of the first conductivity type; the plurality of common source conductive lines 317b / 316b (CSBL) and the plurality of common drain conductive lines 3 2 6b / 322c ( CDBL) are formed alternately and are perpendicular to the parallel parallel shallow groove isolation area (STI 1 ines); the plural auto-aligned split-type flash memory cell line is formed on the plural common source conductive pipeline 3 1 7b / 3 1 6b and each of its adjacent common-drain conductive lines 3 2 6 b / 3 2 2 c; and the plurality of metal word lines (WL) and the plurality of control / selection gate conductive islands 328b, 312d, 3 0 The 6d integrated connection is simultaneously formed and etched by the plurality of hard mask layers and is perpendicular to the plurality of common source conductive lines 317b / 31 6b, wherein the plurality of hard mask layers include at least the second mask. A dielectric layer 324a is aligned on the active area and the side wall dielectric pad layer 3 2 5a is formed on the second cover. The curtain dielectric layer 324a is on each side wall. Similarly, the plurality of common source conductive lines 3 1 7b / 3 1 6b are formed between the pair of first side wall dielectric pads 3 1 5b.

第23頁 586219 五、發明說明（19) ό亥第一平坦床之上’而該第_平坦床係 出场氧化物層3 0 3 d及形成於該共源擴^ 高摻雜共源擴散區3 1 4b所組成；上^之 3 2 6 b/ 3 2 2 c係形成於該對第二側邊牆介 該第二平坦床之上，而該第二平坦床係 出場氧化物層3 0 3 f及置於該共汲擴散@ 摻雜共汲擴散區3 2 0a所組成。圖六A戶斤 如一個B - B ’線 個C-C’線 個 D-D， 係分別顯示於圖六B至圖六E中。 現請參見圖六B至圖六E，其中揭示 種不同剖面圖。圖六B係顯示圖六八所示 一個B - B ’線所標示的一個剖面圖，其中 線3 1 7b/ 3 1 6b係形成於該對第一側邊牆 的該第一平坦床之上；該第一平面化厚 形成於該共源導電管線3 1 7b/ 3 1 6b之上 字線3 2 9a形成於該第一平面化厚二氧化 交變地由該第三突 區3 1 4 a之内的該淺 複數共沒導電管線 電墊層3 2 1 b之間的 交變地由該第五突 3 2 0b之内的該淺高 標示之各種剖面圖 線、及一個E-E’線 圖六 A所標示的各 之沿著該共源區如 該複數共源導電管 介電墊層3 1 5 b之間 二氧化矽層31 8b係 ;以及該複數金屬 矽層31 8b之上係藉Page 23, 586219 V. Description of the invention (19) The first flat bed is above the first flat bed and the field oxide layer 3 0 3 d is formed on the common source diffusion ^ highly doped common source diffusion region Composed of 3 1 4b; the upper 3 2 6 b / 3 2 2 c is formed on the pair of second side walls through the second flat bed, and the second flat bed is out of the oxide layer 3 0 3 f and the common-drain diffusion doped common-drain diffusion region 3 2 0a. Fig. 6 A households, such as one B-B 'line, C-C' line, D-D, are shown in Fig. 6B to Fig. 6E, respectively. Please refer to Fig. 6B to Fig. 6E, which show different sectional views. FIG. 6B shows a cross-sectional view indicated by a B-B 'line shown in FIG. 68, where line 3 1 7b / 3 1 6b is formed on the first flat bed of the pair of first side walls. ; The first planarized thickness is formed on the common source conductive pipeline 3 1 7b / 3 1 6b, the word line 3 2 9a is formed on the first planarized thickness, and the second protruding area is alternately formed by the third protruding area 3 1 4 The alternation between the shallow complex common conductive line electric cushion layer 3 2 1 b within a is indicated by the various cross-sectional lines marked by the shallow height within the fifth protrusion 3 2 0b, and an E-E Each of the lines indicated by line A of FIG. 6 is a silicon dioxide layer 31 8b along the common source region such as the plurality of common source conductive tube dielectric pads 3 1 5 b; and the plurality of metal silicon layers 31 8b Borrow

由該複數硬質罩幕層來成形及蝕刻。上述之第一平坦床係 交變地由該第三突出場氧化物層3 0 3 d及該淺高摻雜共源擴 散區3 1 4b形成於該共源擴散區3 1 4a之内所組成。 圖六C顯不圖六A所不之沿者選擇問區如^一個C-C’線所 標示之一個剖面圖，其中該複數金屬字線3 2 9 a與該複數平 面化控制/選擇閘導電島3 28b/ 31 2d積體化連結係藉由該 複數硬質罩幕層來成形及蝕刻；以及該平面化控制/選擇 閘導電島328b/ 31 2d係形成於該第二閘介電層31 lb之上及The plurality of hard mask layers are formed and etched. The first flat bed described above is composed of the third protruding field oxide layer 3 0 3 d and the shallow highly doped common source diffusion region 3 1 4b formed in the common source diffusion region 3 1 4a. . Fig. 6C shows a cross-sectional view of the area selected by the followers of Fig. 6A, as indicated by a C-C 'line, where the plurality of metal word lines 3 2 9 a and the plurality of planarization control / selection gates The conductive island 3 28b / 31 2d integrated connection is formed and etched by the plurality of hard cover curtain layers; and the planarization control / selection gate conductive island 328b / 31 2d is formed on the second gate dielectric layer 31 above lb and

第24頁 586219 五、發明說明（20) ^-- 鄰近平面化場氧化物層303 a的一部份表面之上。該第—導 電型的該離子佈植區3 0 9b係形成於該鄰近平面化場氧化物 層303a之間的該第二閘介電層3nb之下，其中包含一個淺 離子佈植區如虛線所標示以作為臨界電壓的調整及一個深 離子佈植區如打X X X號所標示以形成一個抵穿禁止區。 圖六D顯示圖六姆示之沿著該漂浮閘區如一個D〜D，線 所標示之一個剖面圖，其中該複數金屬字線32 9a與該複數 平面化控制/選擇閘導電島328b/ 3〇6d積體化連結藉由該 複數硬質罩幕層來同時成形及蝕刻係形成於該第一閘間介 電層3 0 5 d之上及鄰近第一突出場氧化物層303 b之一部份表 面之上；該第一閘間介電層3 0 5b係形成於該漂浮閘層3 〇 2d 之上；以及該漂浮閘層3 0 2 d係形成於該第一閘介電層3 〇 1 c 之上。 圖六E顯示圖六A所示之沿著該共汲區如一個E — E，線所 標示之一個剖面圖，其中該複數共源導電管線32 6b/ 3 22c 的每一個係形成於該對第二側邊牆介電墊層3 2丨間的該 第二平坦床之上；該第二平面化厚二氧化矽層327b係形成 於該共汲導電管線326b/ 322c之上；以及該複數金屬字線 3 2 9 a形成於該第二平面化厚二氧化矽層3 2 7 b之上係經由該 複數硬質罩幕層來成形及姓刻。上述之第二平坦床係交變 地由該第五突出場氧化物層3 0 3 f及該淺高摻雜共汲擴散區 3 2 0 b形成於該共沒擴散區3 2 0 a之内所組成。 根據圖四A及圖六A，該複數平行淺凹槽隔離區（STI 1 i nes)的每一個之寬度及間距可以利用所使用技術的一個Page 24 586219 V. Description of the invention (20) ^-It is adjacent to a part of the surface of the planarized field oxide layer 303a. The ion-conducting region 3 0 9b of the first conductivity type is formed under the second gate dielectric layer 3nb between the adjacent planarized field oxide layers 303a, and includes a shallow ion-implanting region such as a dotted line. The mark is used as the adjustment of the threshold voltage and a deep ion implantation area is marked as XXX to form a breakdown prohibited area. FIG. 6D shows a cross-sectional view shown in FIG. 6M along the floating gate area as a line D ~ D, in which the plurality of metal word lines 32 9a and the plurality of planarization control / selection gate conductive islands 328b / The 306d integrated connection is simultaneously formed and etched by the plurality of hard mask layers on the first inter-gate dielectric layer 3 0 5 d and adjacent to one of the first protruding field oxide layer 303 b. Over a part of the surface; the first inter-gate dielectric layer 3 05b is formed on the floating gate layer 3002d; and the floating gate layer 3 0 2d is formed on the first gate dielectric layer 3 〇1 c. FIG. 6E shows a cross-sectional view shown in FIG. 6A along the common drain region as an E-E, line, where each of the plurality of common source conductive lines 32 6b / 3 22c is formed in the pair On the second flat bed between the second side wall dielectric pads 3 2 and 2; the second planarized thick silicon dioxide layer 327b is formed on the common-drain conductive line 326b / 322c; and the plurality The metal word line 3 2 9 a is formed on the second planarized thick silicon dioxide layer 3 2 7 b and is formed and engraved through the plurality of hard mask layers. The second flat bed described above is alternately formed within the common diffusion region 3 2 0 a by the fifth protruding field oxide layer 3 0 3 f and the shallow highly doped common-drain diffusion region 3 2 0 b. Composed of. According to FIG. 4A and FIG. 6A, the width and pitch of each of the plurality of parallel shallow groove isolation regions (STI 1 ines) can be made using one of the technologies used.

第25頁 586219 五、發明說明（21) i 最小線寬（F )來定義；該複數共源區的每一個及該複數共 浪區的每一個可以分別定義為X丨F及X 3 F ;以及一個自動對 準分閘式快閃記憶細胞元的一個控制/選擇閘區可以定義 為X 2 F。這裡可以清楚看到’ X r X及χ 3係可微縮化係數且 玎以定義等於1，則圖四Α及圖六a的一個細胞元尺寸如一 個虚線方形所標示係等於4 F 2。因此，本發明的一個細胞元 尺寸可以藉由控制該可微縮化係數Χι、Χ2及χ3來製造成比 4 F Η、。這裡值得強調的是，本發明之自動對準分閘式快閃 記憶細胞元藉由一個較高場發射效率之該楔形漂浮閘結構 的該尖端電極及一個較高耦合比之自動對準結構來擦洗。 基於此，本發明之主要優點及特色可以總結如下： (a)本發明的自動對準分閘式細胞元結構係可微縮化且一 個細胞元尺寸可以製成小於4F 2。 較 個 1 由 藉 以。 可洗 構擦 結來 元構 胞結 細閘 式浮 閘漂 分形 準換 對種 訪一 I 自的 的率 明效 發射 本發 }場 b (C)本發明之兩種無接點快閃 共源管線於該共源擴散區之上 有較低的管線電阻及相對於該 容0 記憶陣列能提供一個高導電 比先前技術之埋層擴散線具 半導體基板之較小的管線電 d本發明之一 g #接點#或型决閃記隐陣列㉟提供一個 金屬位元線與共 >及導雷& 、 、^ ^ 电島積體化連結以組成一種無接點陣Page 25 586219 V. Description of the invention (21) i minimum line width (F) to define; each of the complex common source area and each of the complex common wave area can be defined as X 丨 F and X 3 F, respectively; And a control / selection gate of an auto-aligned switching flash memory cell can be defined as X 2 F. It can be clearly seen here that ′ X r X and χ 3 are differentiable coefficients and are equal to 1 by definition, then the size of a cell in Figure 4A and Figure 6a as indicated by a dashed square is equal to 4 F 2. Therefore, a cell size of the present invention can be made into a ratio of 4 F Η, by controlling the micronizable coefficients X 1, X 2 and χ 3. It is worth emphasizing here that the self-aligned split-type flash memory cell of the present invention uses the tip electrode of the wedge-shaped floating gate structure with a higher field emission efficiency and an auto-alignment structure with a higher coupling ratio. scrub. Based on this, the main advantages and features of the present invention can be summarized as follows: (a) The self-aligning and switching cell structure of the present invention can be miniaturized and the size of a cell can be made smaller than 4F 2. Compare 1 by. Washable structure, structure-cell structure, fine-gate floating gate drift, fractal quasi-replacement, effective rate, effective launch rate, field b), field b (C), two kinds of non-contact flash flashes of the present invention The source pipeline has a lower pipeline resistance above the common source diffusion region and can provide a pipeline with a higher conductivity than a buried pipeline with a semiconductor substrate of a buried diffusion line of the prior art. A g # 接点 # or a type of flash memory array provides a metal bit line and a total > and a lead &, ^ ^ electric island integrated connection to form a contactless dot matrix

第26頁 586219 五、發明說明（22) 列結構且具有較低的位元線電阻。 (e )本發明之一種平行共源/汲導電位元線快閃記憶陣 能提供共源導電管線及共汲導電管線擁有一個高導^層且 具有較低的管線電阻及相對半導體基板之較小的技二^ 。 g綠電容 (f )本發明 提供一個金 結以組成一 之一種平行 屬字線與平 種無接點陣 共源/汲導 面化控制/ 列結構且具 電位元線快 選擇閘導電 有較低的字 閃記憶陣列 島積體化連 線電阻。Page 26 586219 V. Description of the invention (22) Column structure and low bit line resistance. (e) A parallel common source / drain bit line flash memory array of the present invention can provide a common source conductive pipeline and a common drain pipeline having a high conductivity layer and a lower pipeline resistance and a relatively low semiconductor substrate. Little skill two ^. g Green capacitor (f) The present invention provides a gold junction to form a parallel metal word line and a flat contactless dot matrix common source / drain surface control / column structure with a potential element line fast selection gate conductive. Low word flash memory array island integrated wiring resistance.

本發明雖特別以參考所 ’但僅是代表陳述而非限制 之細節，對於熟知此種技術 f細節的更動在不脫離本發 造’但亦屬本發明的範嘴。 附的例子或内涵來圖示及描述 。再者’本發明不偈限於所列 的人亦可瞭解，各種不同形狀 明的真實精神和範疇下均可製Although the present invention is specifically based on reference, but is only a representative statement rather than a limiting detail, changes to the details of the well-known technology f do not depart from the present invention, but also belong to the scope of the present invention. Attached examples or connotations to illustrate and describe. Furthermore, the present invention is not limited to those listed, and it can be understood that the real spirit and scope of various shapes can be made.

第27頁 586219 圖式簡單說明 圖六A至圖六E顯示本發明之一種自動對準分閘式快閃 細胞元結構及其無接點平行共源/汲導電位元線快閃記憶 陣列的一個頂視佈建圖及其各種不同的剖面圖，其中圖六 A顯示一個頂視佈建圖；圖六B顯示圖六A所示之沿著一個 B - B ’線的一個剖面圖；圖六 C顯示圖六 A所示之沿著一個 C-C’線的一個剖面圖；圖六D顯示圖六 A所示之沿著一個 D - D ’線的一個剖面圖；以及圖六E顯示圖六A所示之沿著一 個E-E’線的一個剖面圖。 代表圖號說明： 300 半導體基板 3 0 2 第一導電層 3 0 3 a平面化場氧化物層 303c第二突出場氧化物層 3 0 3 e第四突出場氧化物層 3 0 4 第一罩幕介電層 3 0 6 c控制閘導電層 3 0 7a平面化覆蓋氧化層 3 0 9 b離子佈植區 3 1 1 b第二閘介電層 312d選擇閘導電島 314a共源擴散區 315a第一側邊牆介電墊層 317b共源覆蓋導電層 3 0 1 c第一閘介電層 3 0 2 d楔形漂浮閘層 3 0 3b第一突出場氧化物層 3 0 3d第三突出場氧化物層 3 0 3 f第五突出場氧化物層 3 0 5b第一閘間介電層 3 0 6d控制閘導電島 3 0 8 a緩衝側邊牆介電墊層 3 1 0 a第二閘間介電層 3 1 2 c選擇閘導電層 313a第三側邊牆介電墊層 314b淺高摻雜共源擴散區 316b共源導電層Page 586219 Brief Description of Drawings Figures 6A to 6E show an auto-aligned split-type flash cell structure of the present invention and its contactless parallel common source / drain conductive bit line flash memory array. A top-view layout diagram and its various cross-sectional views, of which FIG. 6A shows a top-view layout diagram; FIG. 6B shows a cross-sectional view along a B-B 'line shown in FIG. 6A; Sixth C shows a cross-sectional view along a CC line shown in FIG. 6A; FIG. 6D shows a cross-sectional view along a D-D 'line shown in FIG. 6A; and FIG. 6E shows FIG. 6A is a cross-sectional view taken along an EE ′ line. Representative drawing number description: 300 semiconductor substrate 3 0 2 first conductive layer 3 0 3 a planarized field oxide layer 303c second protruding field oxide layer 3 0 3 e fourth protruding field oxide layer 3 0 4 first cover Screen dielectric layer 3 0 6 c Control gate conductive layer 3 0 7a Planar cover oxide layer 3 0 9 b Ion implanted area 3 1 1 b Second gate dielectric layer 312d Select gate conductive island 314a Common source diffusion region 315a First One side wall dielectric pad layer 317b common source covering conductive layer 3 0 1 c first gate dielectric layer 3 0 2 d wedge-shaped floating gate layer 3 0 3b first protruding field oxide layer 3 0 3d third protruding field oxidation Physical layer 3 0 3 f Fifth protruding field oxide layer 3 0 5b First gate dielectric layer 3 6 6d Control gate conductive island 3 0 8 a Buffer side wall dielectric cushion layer 3 1 0 a Second gate Dielectric layer 3 1 2 c Selective gate conductive layer 313 a Third side wall dielectric pad layer 314 b Shallow highly doped common source diffusion region 316 b Common source conductive layer

第29頁 586219 圖式簡單說明 318a第一平面化厚二氧化矽層 319a第四側邊牆介電墊層 320a共汲 3 2 0b淺高摻雜共汲擴散區 321a第二 3 2 2b共汲導電島 322c共汲導電層 323a金屬 3 24a第二罩幕介電層 3 2 5a側邊 3 2 6b共汲覆蓋導電層 3 2 7b第二平面化厚二氧化矽層 328b平面化覆蓋導電島 329a金屬 擴散區 側邊牆介電塾層 位元線 牆介電墊層 字線Page 586219 Simple illustration of 318a first planarized thick silicon dioxide layer 319a fourth side wall dielectric pad layer 320a shared 3 2 0b shallow highly doped common drain diffusion region 321a second 3 2 2b shared drain The conductive island 322c collectively draws the conductive layer 323a, the metal 3 24a, the second mask dielectric layer 3 2 5a, the side 3 2 6b, and the collectively covered conductive layer 3 2 7b. The second planarized thick silicon dioxide layer 328b planarizes and covers the conductive island 329a. Metal diffusion zone side wall dielectric 塾 layer bit line wall dielectric pad word line