TWI282621B - CMOS image sensors having pixel arrays with uniform light sensitivity - Google Patents

Solid state CMOS active pixel sensor devices having unit pixels that are structured to provide improved uniformity of pixel-to-pixel sensitivity across a pixel array without the need for an additional light shielding layer. For example, unit pixels with symmetrical layout patterns are formed whereby one or more lower-level BEOL metallization layers are designed operate as light shielding layers which are symmetrically patterned and arranged to balance the amount of incident light reaching the photosensitive regions.

I282621?if 九、發明說明： 【發明所屬之技術領域】 本發明實質上是關於具有改良之回應均勻性 ( response unif0rmity)的cM〇s主動晝素感測器裝置，且 詳言之，是關於用於製造具有晝素結構之CM〇s主動晝素 感測器裝置的方法，前述晝素結構在整個一晝素陣列上提 供晝素間感度之增強之均勻性。 【先前技術】 • 6開發tB各麵^之目態成縣置，其終包括電荷 • 耦合裝置（CCD)以及互補金氧半導體（CM〇s)影像感 • 測裝置，以及基於CCD影像感測設計與CMOS影像感測 6又a十之組合的併合影像感測器（hybrid image sensor )。通 常，CCD、CMOS固態成像感測器以及CCD影像感測器 基於當矽暴露於光時發生之“光電效應，，而運作。詳言 之’ CCD以及CMOS影像感測器包括晝素陣列，在前述 晝素陣列中每一單位晝素包括一光接收區域（light % receiving region)，前述光接收區域包括形成於前述晝素 之一主動石夕區域（active silicon region)中之一或多個光貞 測器（photo detector)元件（諸如光電二極體）。當前述 光接收區域曝露於光時，可見光以及近IR (紅外）光光譜 中之光子具有充足之能量以擊穿石夕中的共價鍵（covalent bond)，藉此將電子自價帶（vaience band)釋放至導帶 (conduction band)中。產生之電子之數量與光強度成比 例。光子產生之電荷藉由光偵測器元件積聚於晝素陣列 6 1282621 18824pif 中，且接著經偵測並處理以產生一數位影像。 圖1是說明一具有一 4電晶體（4-T)主動晝素感測器 構架之習知CMOS影像感測裝莧之一單位畫素的示意電 路圖。通常，例示性單位畫素（10)包括一 PD (光偵測器） 元件（或光接收元件）、一轉移電晶體（transfer transistor) TX、一 FD (浮動擴散（floating diffusion))區域（或感 測節點）、一重置電晶體（reset transistor ) RX、一放大器 DX (或源極隨|馬放大器（ source follower amplifier))以 及一選擇電晶體（select transistor) SX。前述PD元件可為 一例如形成於前述晝素（10)之一光接收區域（或感光區 域）中之光電二極體或固定光電二極體（pinned photodiode)。藉由前述轉移電晶體τχ之運作來將pd元 件耦合至前述FD區域/自FD區域去耦合。前述重置電晶 體RX具有一連接至一 RS控制訊號線之閘電極。前述轉 移電晶體TX具有一連接至一丁G控制訊號線之閘電極。 前述選擇電晶體sx具有一連接至一 SEL控制訊號線之閘 電極以及-連接至一輸出（行）、線〇u丁之源電極。運作 月述電晶體RX、TX、DX以及sx以執行諸如重置晝素， 將所積聚之電荷自！>D元件轉移至FD區域，以及將FD區 域中之前述所積聚之電荷轉換成-經放大並轉移至前述輪 出線OUT之可量測的電壓。 更特疋口之，别述例示性單位晝素（10)運作如下。 =素或電荷收集期)期間，用入射光來照 一/、 4PD 兀件之—電位阱（potential well)(或 I282621pif 域）中積聚光產生之電荷。在前述整合期完成 一施加至前述RS控制訊號線之重置控制訊號 置電日日體RX，以自FD區域排出電荷並將FD區 考電位（例如’對FD區域進行充電至近似 =詈2VDD減去重置電晶㈣之臨限電壓）。在前 f之後，藉由一施加至前述TG控制訊號線之控 敫活轉移電晶體τχ以將前述所積聚之光產生之 ΙΤπ π广件轉移至™區域。前述放大器電晶體敗放 # sx 前述經放大之電壓經由前述選擇電晶 r衝兔合至行輸出線（26) ’前述選擇電晶體 、SX猎由-知加至前述SEL控制訊號線的列選擇訊號而得 Μ激活。 Α歷史上，歸因於CCD影像感測器所提 (derange) Μ, PPN ( 〇fL以及對光之高感度，故類比CCD影像感測器已 統治固態成像助之市場。然而，在CM叫支術^進已 導致改良之CMOS影像感測器料的發展 ^ CMOS固態影像感測器在各種固態成像應用曰中取代 。固態、CM0S影像感測器提供各種優點包括，例如低 製造成本、使用-單個電壓電源之低功率消耗、系統單晶 片整合（system-on-chip integration)、高迷運作（例如，曰 以高圖框率（frame rate)捕獲連續之影像） > ~cT 弟欠 ”列、晶片上影像處理系統、對單位畫素：二取 荨。相反地，CCD影像感測裝置之製造是昂責的，通常要 8 1282621 18824pif 求以不同時鐘速率（clock speed)之具有顯著較高之功率 消耗之2個、3個或3個以上的供應電壓，且不允許對單 位晝素之隨機存取。 然而與固態CCD相比，習知CMOS主動晝素感測器 具有更低之填充因數（fill factor) ” ，其導致降級之效I282621? if the invention belongs to the technical field of the invention: The present invention relates substantially to a cM〇s active halogen sensor device with improved response uniformity (relevant unif0rmity), and in particular, A method for fabricating a CM〇s active halogen sensor device having a halogen structure, the aforementioned halogen structure providing enhanced uniformity of sensitivity between the elements of the monoterpene array. [Prior Art] • 6 Developed the appearance of each side of tB into a county, which ultimately includes a charge-coupled device (CCD) and a complementary MOS device (CM〇s) image sensing device, and based on CCD image sensing. A hybrid image sensor designed to combine CMOS image sensing with a combination of ten and ten. In general, CCD, CMOS solid-state imaging sensors, and CCD image sensors operate based on the "photoelectric effect" that occurs when exposed to light. In detail, CCD and CMOS image sensors include halogen arrays, Each unit of the halogen element in the foregoing pixel array includes a light receiving region, and the light receiving region includes one or more apertures formed in an active silicon region of one of the aforementioned pixels. Photodetector element (such as a photodiode). When the aforementioned light-receiving area is exposed to light, the photons in the visible and near-IR (infrared) light spectrum have sufficient energy to break through the covalentity of the stone A covalent bond whereby the electron's vaience band is released into the conduction band. The amount of electrons produced is proportional to the intensity of the light. The charge generated by the photon is accumulated by the photodetector element. In the pixel array 6 1282621 18824pif, and then detected and processed to produce a digital image. Figure 1 is a diagram illustrating a structure with a 4-transistor (4-T) active pixel sensor A schematic circuit diagram of a unit pixel of a CMOS image sensing device. Typically, the exemplary unit pixel (10) includes a PD (photodetector) element (or light receiving element), a transfer transistor (transfer transistor) TX, an FD (floating diffusion) region (or sensing node), a reset transistor RX, an amplifier DX (or source follower amplifier), and a Selecting a transistor SX. The PD element may be, for example, a photodiode or a pinned photodiode formed in a light receiving region (or a photosensitive region) of one of the aforementioned halogens (10). The pd device is coupled to the FD region/decoupled from the FD region by the operation of the transfer transistor τ. The reset transistor RX has a gate electrode connected to an RS control signal line. The transfer transistor TX Having a gate electrode connected to a G control signal line. The selection transistor sx has a gate electrode connected to a SEL control signal line and - connected to an output (row), line The source electrode of the U. The operating transistors RX, TX, DX, and sx are operated to perform, for example, resetting the halogen, transferring the accumulated charge from the !D component to the FD region, and the aforementioned in the FD region. The accumulated charge is converted into a measurable voltage that is amplified and transferred to the aforementioned wheel output OUT. More specifically, the exemplary unit (10) is operated as follows. During the charge period, the incident light is used to accumulate the charge generated by the light in the potential well (or I282621pif domain) of a /, 4PD element. During the integration period, a reset control signal power-on day RX applied to the RS control signal line is completed to discharge the charge from the FD region and charge the FD region (eg, 'charge the FD region to approximately = 詈 2 VDD Subtract the threshold voltage of the reset transistor (4). After the first f, the ΙΤππ wide piece generated by the accumulated light is transferred to the TM area by a control transfer transistor τχ applied to the TG control signal line. The amplifier circuit is defeated # sx, and the amplified voltage is coupled to the line output line (26) via the selected electro-optic crystal r. The selection transistor is selected from the above-mentioned SEL control signal line. The signal is activated. Α Historically, due to the CCD image sensor's derangement, PPN (〇fL and high sensitivity to light, analog CCD image sensors have dominated the market for solid-state imaging. However, in CM The advancement of CMOS image sensor materials has led to the development of improved CMOS image sensor materials. CMOS solid-state image sensors have been replaced by various solid-state imaging applications. Solid-state, CMOS image sensors offer various advantages including, for example, low manufacturing cost and use. - Low power consumption of a single voltage supply, system-on-chip integration, and high-level operation (for example, capturing continuous images at a high frame rate) > ~cT owe Column, on-chip image processing system, on the unit pixel: two 荨. Conversely, the manufacture of CCD image sensing device is very responsible, usually 8 1282621 18824pif to find a significant difference in clock speed High power consumption of 2, 3 or more supply voltages, and random access to unit pixels is not allowed. However, compared with solid-state CCD, conventional CMOS active pixel sensors have lower Fill factor (Fill factor) ", which results in degraded effect

能（例如，對入射光之低感度、低量子效率、不良之訊雜 比（signal_to-noiseratio)以及有限之動態範圍）。通常， 前述晝素“填充因數”（或孔徑效率（apertureefflciency)) 指代晝素之光接收區域（或感光區域）之面積與晝素之總 面積的比率。歸因於在環繞設計成之感光區域之單位晝素 中之主動電路與關聯之互連的合併，所以CMOS主動晝素 感測器具有低“填充因數”。參看圖2進一步解釋一 COMS主動晝素感測器之“填充因數，，，圖2示意說明一 單位畫素（20)之一例示性佈局圖案。 如圖2中所描繪，前述單位晝素（2〇)之總表面面積 包括一經界定之感光區域（21)以及一環繞前述感光區域 (21)之電晶體區域（22)。前述感光區域（21)是經設 計以捕獲穿透晝素（20)之入射光之晝素的區域。在感光 區域（21)之主動矽中形成一光接收元件（例如，光電二 極體PD)。前述電晶體區域（22)是其中形成有主動組件 (例如，放大器、重置以及列選擇電晶體）以及後段製程 (Back_End-Of_Line，BE0L)互連結構的晝素區域。$為 區域（22)中之前述主動電路元件以及互連吸收或反射了 電晶體區域（22)上之大多數入射光，所以在很大程度上， 1282621 18824pif 前述電晶體區域（22 )實質上是一 “光滅（optically知以），， 區域。因此，晝素（20)之能夠吸收光子以產生電荷的感 光區域（21)為電晶體區域（22)所需之晝素區域所限制， 從而導致一低填充因數。各種晝素設計包括L形光電二極 體，矩形形狀光電二極體以及正方形光電二極體，其提供 不同之“填充因數”。 ’、Can (for example, low sensitivity to incident light, low quantum efficiency, poor signal-to-noiser ratio, and limited dynamic range). Generally, the aforementioned "filling factor" (or aperture efficiency) refers to the ratio of the area of the light receiving region (or photosensitive region) of the halogen to the total area of the halogen. The CMOS active pixel sensor has a low "fill factor" due to the combination of active circuitry and associated interconnects in a unit of pixel surrounding the designed photosensitive region. Referring to Figure 2, the "fill factor" of a COMS active pixel sensor is further explained. Figure 2 schematically illustrates an exemplary layout pattern of a unit pixel (20). As depicted in Figure 2, the aforementioned unit pixel ( The total surface area of the surface includes a defined photosensitive region (21) and a transistor region (22) surrounding the photosensitive region (21). The photosensitive region (21) is designed to capture penetrating alizarin (20). a region of the element of the incident light. A light receiving element (for example, a photodiode PD) is formed in the active turn of the photosensitive region (21). The aforementioned transistor region (22) is formed with an active component (for example) , amplifier, reset, and column select transistor) and the back-end process (Back_End-Of_Line, BE0L) interconnect structure of the pixel region. $ is the region (22) of the aforementioned active circuit components and interconnections absorb or reflect the transistor Most of the incident light on the region (22), so to a large extent, 1282621 18824pif The aforementioned transistor region (22) is essentially a "light-off" region. Therefore, the photosensitive region (21) of the halogen (20) capable of absorbing photons to generate charges is limited by the pixel region required for the transistor region (22), resulting in a low fill factor. Various halogen designs include L-shaped photodiodes, rectangular shaped photodiodes, and square photodiodes that provide different "fill factor." ’,

儘管前述電晶體區域（22)很大程度上是晝素（2〇) 之一“光滅”區域，但是電晶體區域（22)之下方之基板 可吸收某些入射之光而導致光產生之電荷的產生。可爿^前 述光產生之電荷收集於PD元件之電位阱中。在此方面， 因為晝素之電晶體區域（22)亦可作用於pd元件收集之 電荷，所以主動晝素之“設計成的，，填充因數（其基=感 光區域（21)之實際曝露面積（孔徑））與“有效，Γ填充 因數不同。此外，可藉由接面（例如，FD區域）或電晶體 區域（22)中之主動組件之電位阱來捕獲電晶體區域（22) 中之某些光產生之電荷，或前述電荷可擴散至鄰近畫素之 PD元件並被收集於其中。因此，電晶體區域（22)中之光 電荷的產生可導致雜訊且促使整個前述晝素陣列上之非均 勻的晝素回應。 在某些習知主動畫素設計中，藉由使用一形成於晝素 陣列之上之一分離之金屬光屏蔽層來降低晝素回應的非均 勻性，其中前述光屏蔽層運作以屏蔽入射光免於進入晝素 電晶體區域，但是包括與感光區域對準之孔徑以允許入射 光抵達畫素之感光區域。實質上，前述光屏蔽層運作以將 1282621 I8824pif S述、、二界疋之感光區域之晝素回應與前述電晶體區域之晝 去回應分離，且，此在整個晝素陣列上實現一更均勻之晝 ^卜回應。然而，對額外光屏蔽之使用導致晝素填充因數減 夕以及較低之量子效率（QE)效能（且因此，降級之效能）， f為建構主動晝素感測器造成位置設計限制，如將參看圖 3而作解釋。 ，3是一具有分離之光屏蔽層之習知CMOS主動晝素 籲 -單位晝素的示意側視圖。詳言之，目3說明一 ^成於一由一隔離層（31)所界定之半導體基板（30)之 一^動區域中之一單位晝素的一部分。在前述晝素之主動 矽區域中形成一光電二極體元件PD以及擴散區域（32) j及（33)。在前述基板（30)之上形成一堆疊結構（34)。 月?!返堆疊層（34)包括多個閘電極（例如，轉移電晶體Τχ 以及重置電晶體Rx)以及形成前述BE〇l金屬化互連之透 明η電層以及非透明金屬層的交替層（alternating layer)。 形成一上部金屬層以運作作為一具有一經界定之寬度為w 響之開口（孔徑）（34b)的光屏蔽（34a)，其與基板（3〇) 中之PD元件對準。前述金屬屏蔽（34a)反射/阻斷晝素表 面上之某些入射光，且某些入射光進入穿過前述孔徑（34b) 並穿過堆疊層（34)之隧道區域（tunnel region) (34c) (其缺乏B0EL結構之金屬線）且被PD元件吸收。 儘管前述光屏蔽（34a)可增加畫素間回應之均勻性， 但是對分離之光屏蔽層（34a)之使用降低晝素感度。當然， 對前述額外光屏蔽層（34a)之使用導致堆疊層（34)之高 1282621 18824pif 度/2增大’且因此增大隧道高度與孔徑寬度之縱橫比（意 即，比率。當前述縱橫比增大時，導致在有限入射 角中可穿過孔徑（34b)至？〇元件之入射光的數量減少， 其導致較低之晝素感度以及較低之qE。隨著CM〇s技術 按比例縮小為更小之特徵尺寸（feature size)，可形成更 小尺寸之晝素以及光屏蔽孔徑以增加積體密度（integrati〇n density)。然而在實務水準上，儘管存在更小之可用設計 # 標準，但是歸因於有效運作所需之要求的晝素感度水準所 以主動晝素感測為之尺寸將受限制。當然，因為使用更小 之5又计私準來建構具有分離之光屏蔽之晝素，所以隧道高 度△與孔徑覓度w的縱橫比增大，其導致降低之晝素感 度。因此，為了致能前述更小之設計標準，當使用有效光 屏蔽以最小化整個晝素陣列上之晝素間感度的變化時，需 要限制基板（30)上之堆疊層（34)的高度乃。 【發明内容】 大體而言，本發明之例示性實施例包括具有改良之回 • 應均勻性的固態CMOS主動晝素感測器裝置。更特定言 之，本發明之例示性實施例包括用於製造具有晝素陣列之 ， COMS主動晝素感測器的方法，前述晝素陣列之單位書素 經設計以在整個晝素陣列上提供增加之晝素間感度之均勻 性而無需額外光屏蔽層。在本發明之一例示性實施例中， COMS主動晝素感測器包括單位晝素構架，在前述單位書 素構架中設計有一或多個低程度金屬化層以提供BE〇L互 連以及I/O以及控制線並且運作作為增加晝素間感度之均 12 1282621 18824pif 句性的光屏蔽層。詳言之，<稱地圖案化並圍繞光接收元 件而排列-或多個低程度金屬化層以平衡抵達感光區域之 入射光的數量。 在本發明之-例示性實施例中，一影像感測裝置包括 一包括多個形成於一半導體基板中之單位晝素的晝素陣 列。每-單位晝素包括多個讀出元件（read〇ut dement )以 及至少一光接收7L件。在前述晝素陣列之上形成一第一佈 • 線層（wiring layer)，前述第一佈線層包括一第一佈線圖 pattern of wiring line )。前述第一佈線圖案包括介於 單位晝素中之讀出元件之間的電互連，其中前述第一佈線 層是一光學阻斷層，其阻斷每一單位晝素中之入射光以為 晝素陣列中之每一光接收元件保持實質上相同之感度。 μ在另一例示性實施例中，在前述第一佈線層之上形成 一第一佈線層。前述第二佈線層包括一第二佈線圖案，其 中础述第二佈線圖案包括電壓供應線。第二佈線層是第二 光學阻斷層，前述第二光學阻斷層進一步阻斷每一單位晝 素中之入射光以為晝素陣列之每一光接收元件保持實質上 相同之感度。 在本發明之其它例示性實施例中，前述第一佈線圖案 包括具有虛没突起元件（pr〇truciing element)之晝素控制 線’且雨述第二佈線圖案包括具有虛設突起元件之畫素1/〇 線。電壓供應線可包括虛設突起元件。 在另一例示性實施例中，前述第一佈線圖案是由一在 前述晝素陣列中之每一單位晝素中重複的第一單位圖案所 13 1282621 18824pif 形成’且前述第二佈線圖案是由一在前述晝素陣列中之卞 -單位晝素中重複之第二單位圖案所形成。前述用於每丄 單位晝素之第一以及第一單位圖案經排列以在每一單位查 素中界定一相似尺寸以及形狀之孔徑以便曝露每一單位$ 素之-光接收區域。前述每-單位晝素之光接收區域包^ 一包括前述單位晝素之光接收元件的主動區域。每一查素 之光接收區域可更包括一與前述包括光接收元件之主動區 域相鄰之非主動區域的至少一部分。 °° 在本發明之又一例示性實施例中，每一單位書素是一 包括-第-子晝素單位以及-第二子晝素單位之S用J位 晝素。前述第一佈線圖案包括一在前述晝素陣列中之每一 單位晝素中重複的第一單位圖案，且前述第一單位圖案包 括一在前述畫素陣列中之每一單位晝素之每一子晝素單位 中重複的子單位圖案。前述子單位圖案包括一襯墊元件 (pad element)，其中前述襯墊元件是一用於前述第一子 晝素單位之隔離虛設襯墊元件，且其中前述襯墊元件是一 用於前述第二子畫素單位之電接觸襯墊，前述電接觸襯墊 ，接至第二子晝素單位之一讀出元件。在另一實施例中， 第一以及第二子晝素單位之子單位圖案形成一鏡像 (mirror image )圖案。 ▲為讓本發明之上述和其他目的、特徵和優點能更明顯 易酸，下文特舉較佳實施例，並配合所附圖式，作詳細說 明如下。 、。 【實施方式】 14 1282621 18824pif 現將參看附圖進一步洋細論述具有改良之回應均勻性 之固態CMOS主動畫素感測器裝置的例示性實施例。應瞭 解，圖式僅為示意描繪，其中各種組件、層以及區域之厚 度以及尺寸並非按比例繪製，而是為達成明確之目的而作 誇示。應進一步瞭解，當本文中描述一層處於另一層或基 板之“上”或“上方”肖’此層可直接處於其他層或基板 上，或亦可存在介入層。應進一步瞭解，在所有圖示中所 使用之相同參考數字表示同#或類似或具有同樣或類似功 能的元件。 實質上而言，如本文中所描述之本發明的例示性實施 ::用素陣列之c〇Ms主動晝素感測器 二列中設計晝素結構在整個晝素陣列 圖/二f-ΐΐί㈣之均勻性而無需額外光屏蔽層。 二丁旦’、、纟°構可用以解釋本發明之通用發明概 心。如上文中所說明，圖2描繪一具 以及電晶體區域（22)之③紅或（21) 目的晝素（20)。為了本發明之 目的假汉則述感先區域（21) p 動石夕區域之面積，根據）表不主 形成於前述主動魏域中u真充因數-光電二極體 區域剛示電晶體L或：1域⑻之周邊 中光產生之電荷最有可卩刀’在前述部分 散至*素的ι它區诚广兀件所收集，但是亦可擴 非均;性。為達二;明上之晝素感度的 周邊區域⑵)之組4;的右=pd區域⑻與 為有效感光區域（或“EPS區 15 1282621 18824pif 域’’）。應瞭解，由於主動晝素感測器之EpS區域將基於 諸如PD元件之實際尺寸以及結構、晝素中之pD元件與 相鄰組件之空間以及電子的關係等各種因素而變化，故圖 2中所說明之前述EPS區域僅例示而言。 在本發明之一例示性實施例中，C0MS主動晝素感測 為包括卓位晝素構架，在前述單位晝素構架中設計有一或 多個低程度金屬化層以提供BE0L互連，且運作作為增加 • 晝素間感度之均勻性的光屏蔽層。詳言之，g稱地圖案化 並圍繞母一晝素之PD區域（21)而排列一或多個低程度 金屬化層以運作作為平衡抵達感光區域之入射光之數量的 光屏蔽（阻斷）層。圖案化前述金屬化層以在每一晝素中 有效地界定對稱之孔徑，前述孔徑為陣列中之每一晝素曝 露相同數量以及/或相同部分的EPS區域。前述曝露之Eps 區域可包括全部（或實質上）整個前述感光區域（21)以 及W述周邊區域（23)之至少一部分。以此方式，金屬化 • 圖案提供實質上相同之光屏蔽面積，因此提供入射光接收 $率之均勻分佈。對額外光屏蔽層之去除允許降低bE0L 至屬化，因此導致增加之填充因數以及感度。 可實施關於晝素結構以及如上文中參考圖2所描述之 A屬化圖案的通用發明概念，來用於各種類型之CMOS主 動晝素影像感測器，包括3-T、4-T、5-ΊΓ主動畫素感測器 =及共用以及非共用CM0S主動晝素感測器架構。為達成 "兒明之目的，將在下文中參看諸如圖4至圖10中所描繪之 用單位晝素構架來詳細論述本發明之例示性實施例。詳 16 1282621 18824pif 三之，圖4是一具有一可將本發明應用於其之共用晝素構 杀之晝素陣列的示意電路圖。圖5至圖1〇說明一用於基於 圖4之晝素陣列電路結構來建構一半導體CM〇s主動晝素 衫像感測裝置的方法，前述半導體CM〇s主動晝素影像感 =置具有對稱結構之單位畫素以提供均勻感度。然而應 ::解本务明並不限於共用晝素結構，且一般熟習此項技 術者可谷易地想像實施基於本文之教示之各種晝素構架之 發明概念。 〃 參看圖4，展示一包括多個單位晝素（41)之晝素陣 歹】（4〇)母單位畫素（41)包括兩個光電二極體（42a) /门（b)以及共同連接至一 170區域（感測節點）之兩 =移電晶體（43a)以及（43b)。每一單位畫素（41) -體(44)，一放大器電晶體(45)以及 k擇電日日體（46)。電源VDD連接至前述重 電晶體(46)。前述共用畫素結:為 於上文中I看^寸提供更高之密度設計。晝素（41)類似 在- i: 之4-τ主動晝素感測器而運作。 i產生(41) ^找域上〜射光導致 尤座生之電何，珂述電荷由光電二極體（42 ，電位麵收集接面)所收集。在一電 精由激活個別轉移閘極（transfergate) (43a)又^間， 來將所收集之電荷自光電二極體（42a) =b) 至FD區域。： 轉移 17 1282621 18824pifAlthough the aforementioned transistor region (22) is largely a "light-off" region of the halogen (2〇), the substrate below the transistor region (22) can absorb some incident light and cause light to be generated. The generation of electric charge. The charge generated by the light can be collected in the potential well of the PD element. In this respect, since the transistor region (22) of the halogen can also act on the charge collected by the pd element, the active element is "designed, the fill factor (its base = the actual exposed area of the photosensitive region (21) (Aperture)) is different from "effective, Γ fill factor. In addition, the charge generated by some of the light in the transistor region (22) may be captured by a potential well of the active component in the junction (eg, FD region) or transistor region (22), or the aforementioned charge may diffuse to A PD element adjacent to the pixel is collected therein. Thus, the generation of photocharges in the transistor region (22) can cause noise and contribute to a non-uniform enthalpy response across the aforementioned pixel array. In some conventional primary animin design, the non-uniformity of the quinonic response is reduced by using a metal light shielding layer formed on one of the pixel arrays, wherein the light shielding layer operates to shield the incident light. It is exempt from entering the alizarin transistor region, but includes an aperture aligned with the photosensitive region to allow incident light to reach the photosensitive region of the pixel. In essence, the light shielding layer operates to separate the pixel response of the photosensitive region of the 1282621 I8824pif S and the boundary of the boundary with the aforementioned transistor region, and this achieves a more uniformity over the entire pixel array. After that, ^bu responded. However, the use of additional light shielding results in a reduced factor of the fill factor and a lower quantum efficiency (QE) performance (and, therefore, the performance of the degradation), f is a positional design limitation for constructing an active pixel sensor, such as See Figure 3 for an explanation. , 3 is a schematic side view of a conventional CMOS active element with a separate light shielding layer. In detail, item 3 illustrates a portion of a unit of a pixel in a region of the semiconductor substrate (30) defined by an isolation layer (31). A photodiode element PD and diffusion regions (32) j and (33) are formed in the active germanium region of the aforementioned halogen. A stacked structure (34) is formed over the aforementioned substrate (30). The return stack layer (34) includes a plurality of gate electrodes (eg, transfer transistor Τχ and reset transistor Rx) and a transparent η electrical layer forming the aforementioned BE〇1 metallization interconnect and alternating non-transparent metal layers Alternating layer. An upper metal layer is formed to operate as a light shield (34a) having a defined width (aperture) (34b) of width w, which is aligned with the PD elements in the substrate (3〇). The aforementioned metal shield (34a) reflects/blocks some of the incident light on the surface of the halogen, and some of the incident light enters the tunnel region (34c) through the aforementioned aperture (34b) and through the stacked layer (34). (It lacks the metal wire of the B0EL structure) and is absorbed by the PD element. Although the aforementioned light shield (34a) increases the uniformity of response between pixels, the use of a separate light-shielding layer (34a) reduces the sensitivity of the element. Of course, the use of the aforementioned additional light shielding layer (34a) results in a height of 1282621 18824 pif degrees/2 of the stacked layer (34) and thus increases the aspect ratio of the tunnel height to the aperture width (ie, the ratio. When the ratio is increased, the number of incident light that can pass through the aperture (34b) to the 〇 element in a limited incident angle is reduced, which results in a lower lucifer sensitivity and a lower qE. The scale is reduced to a smaller feature size, which can form a smaller size of the pixel and the light shielding aperture to increase the integrati density. However, in practice, although there is a smaller available design #标准, but due to the required level of sensibility required for effective operation, active size sensing will be limited in size. Of course, because of the smaller 5 and the private standard to construct a separate light shield Therefore, the aspect ratio of the tunnel height Δ to the aperture twist w is increased, which results in a reduced luciferity sensitivity. Therefore, in order to enable the aforementioned smaller design criteria, effective light shielding is used to minimize When the sensitivity between the elements on the individual pixels is changed, it is necessary to limit the height of the stacked layer (34) on the substrate (30). [SUMMARY] In general, exemplary embodiments of the present invention include improvements. Back to the solid state CMOS active pixel sensor device that should be uniform. More specifically, an exemplary embodiment of the present invention includes a method for fabricating a COMS active pixel sensor having a pixel array, the foregoing The unit map of the prime array is designed to provide increased uniformity of sensitivity between the elements of the monolithic array without the need for an additional light shielding layer. In an exemplary embodiment of the invention, the COMS active pixel sensor Including the unit pixel framework, one or more low-level metallization layers are designed in the above-mentioned unit book structure to provide BE〇L interconnection and I/O and control lines and operate as an increase in the sensitivity between the elements 12 1282621 18824pif A sentence-like light-shielding layer. In particular, <stitched and arranged around the light-receiving element - or a plurality of low-level metallization layers to balance the amount of incident light reaching the photosensitive region. In an exemplary embodiment, an image sensing device includes a pixel array including a plurality of unit halogens formed in a semiconductor substrate. Each unit of the pixel includes a plurality of read elements (read〇ut dement) And at least one light receiving 7L. A first wiring layer is formed on the foregoing pixel array, and the first wiring layer includes a first wiring pattern pattern of wiring line. The foregoing first wiring pattern includes an electrical interconnection between the read elements in the unit pixel, wherein the first wiring layer is an optical blocking layer that blocks incident light in each unit of the pixel. Each of the light receiving elements in the prime array maintains substantially the same sensitivity. μ In another exemplary embodiment, a first wiring layer is formed over the aforementioned first wiring layer. The second wiring layer includes a second wiring pattern, wherein the second wiring pattern includes a voltage supply line. The second wiring layer is a second optical blocking layer, and the second optical blocking layer further blocks incident light in each unit of the pixel to maintain substantially the same sensitivity for each of the light receiving elements of the halogen array. In other exemplary embodiments of the present invention, the aforementioned first wiring pattern includes a pixel control line ' having a pr〇truciing element' and the second wiring pattern includes a pixel 1 having a dummy protruding element /〇 line. The voltage supply line may include dummy protrusion elements. In another exemplary embodiment, the first wiring pattern is formed by a first unit pattern 13 1282621 18824pif repeated in each unit pixel in the foregoing pixel array, and the foregoing second wiring pattern is A second unit pattern formed by repeating in the 卞-unit element in the aforementioned halogen matrix. The first and first unit patterns for each unit of the unit are arranged to define a similar size and shape aperture in each unit of the sample to expose the light receiving area of each unit. The aforementioned light receiving region per unit cell includes an active region of the light receiving element including the unit pixel. The light receiving region of each of the elements may further include at least a portion of the inactive region adjacent to the aforementioned active region including the light receiving element. °° In still another exemplary embodiment of the present invention, each unit of the morpheme is a s-based singular element including a -th-sub-halogen unit and a second sub-halogen unit. The first wiring pattern includes a first unit pattern repeated in each unit of the pixel array, and the first unit pattern includes a unit of each unit in the pixel array. A repeating subunit pattern in a subunit. The sub-unit pattern includes a pad element, wherein the pad element is an isolation dummy pad element for the first sub-cell unit, and wherein the pad element is used for the second An electrical contact pad of a sub-pixel unit, the electrical contact pad being connected to one of the second sub-cell units. In another embodiment, the sub-unit patterns of the first and second sub-cell units form a mirror image pattern. The above and other objects, features, and advantages of the present invention will become more apparent and the preferred embodiments of the invention. ,. [Embodiment] 14 1282621 18824pif An illustrative embodiment of a solid state CMOS primary anemone sensor device with improved response uniformity will now be further discussed with reference to the accompanying drawings. It is understood that the drawings are merely schematic representations, and the various components, layers, and regions are not to scale and the dimensions are not intended to be It will be further understood that when a layer is described as being "on" or "above" another layer or substrate, the layer may be directly on the other layer or substrate, or an intervening layer may be present. It should be further understood that the same reference numerals are used in the drawings and the same reference In essence, an exemplary implementation of the invention as described herein: designing a halogen structure in a two-column array of c〇Ms active halogen sensors using a prime array in the entire pixel array diagram / two f-ΐΐί (4) Uniformity without the need for an additional light shielding layer. The structure of the two general inventions can be used to explain the general inventive concept of the present invention. As illustrated above, Figure 2 depicts a red or (21) objective halogen (20) with a transistor region (22). For the purpose of the present invention, the area of the first region (21) is the area of the first region (21), and the surface of the region is formed according to the above-mentioned active Wei domain. The true charging factor-photodiode region is shown as a transistor L. Or: The charge generated by the light in the periphery of the 1 field (8) is the most sturdy. 'In the above part, it is scattered to the prime of the area, and it can be expanded. For the second area; the surrounding area of the sensitization of the sensitization (2)); the right = pd area (8) and the effective sensitized area (or "EPS area 15 1282621 18824pif domain ''). It should be understood that due to active sensation The EpS area of the detector will vary based on various factors such as the actual size and structure of the PD element, the space of the pD element in the element and the space of the adjacent component, and the relationship between the electrons, etc., so the aforementioned EPS area illustrated in FIG. 2 is merely exemplified. In an exemplary embodiment of the present invention, the C0MS active halogen sensing is configured to include a bitter pixel structure, and one or more low-level metallization layers are designed in the foregoing unit pixel structure to provide a BE0L interconnection. And operate as a light-shielding layer that increases the uniformity of the sensitivity between the elements. In other words, g is patterned and arranged around one or more low-level metallization layers around the PD-region (21) of the parental element. Operating as a light-shielding (blocking) layer that balances the amount of incident light reaching the photosensitive region. The aforementioned metallization layer is patterned to effectively define a symmetric aperture in each element, the aforementioned aperture being each of the arrays Exposure The same number and/or the same portion of the EPS region. The aforementioned exposed Eps region may include all (or substantially) the entire aforementioned photosensitive region (21) and at least a portion of the peripheral region (23). In this manner, metallization The pattern provides substantially the same light shielding area, thus providing a uniform distribution of the incident light receiving rate. The removal of the additional light shielding layer allows for a reduction in bE0L to the genus, thus resulting in an increased fill factor and sensitivity. And a general inventive concept of the A-generator pattern as described above with reference to FIG. 2 for use in various types of CMOS active pixel image sensors, including 3-T, 4-T, 5-ΊΓ main animin sensing And common and non-shared CMOS active-instrument sensor architectures. For purposes of achieving "children's purposes, an exemplary embodiment of the present invention will be discussed in detail below with reference to a unitary pixel architecture such as that depicted in Figures 4-10. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 16 1282621 18824pif III, Figure 4 is a schematic circuit diagram of a pixel array having a shared halogen composition to which the present invention can be applied. Figure 5 to Figure 1 Mingyi is used for constructing a semiconductor CM〇s active 昼 衫 像 像 基于 基于 基于 , , , , , , 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体In order to provide uniform sensitivity. However, it should be noted that: The solution to this book is not limited to the shared structure of the element, and those who are familiar with the technology can easily imagine the invention concept of various elementary frameworks based on the teachings of this article. 4, showing a unitary matrix comprising a plurality of unit halogens (41) (4) mother unit pixels (41) comprising two photodiodes (42a) / gates (b) and connected to one Two of the 170 regions (sensing nodes) = shifting transistors (43a) and (43b). Each unit of pixel (41) - body (44), an amplifier transistor (45) and k elective solar body (46). The power supply VDD is connected to the aforementioned re-crystal (46). The aforementioned common pixel combination: provides a higher density design for the above I. Alizarin (41) operates similarly to the 4-τ active quinone sensor at -i:. i generates (41) ^ finds the field ~ the light causes the heat of the seat, and the charge is collected by the photodiode (42, potential surface collecting junction). The charge is collected from the photodiode (42a) = b) to the FD region by activating the individual transfer gates (43a). : Transfer 17 1282621 18824pif

根據本發明之一例示性實施例，可將前述單位晝素 (41)建構成具有對稱結構，前述對稱結構在整個陣列（4〇 ) 上提供均勻的畫素間感度而無需一分離之、額外光阻斷 層圖5至圖10說明根據本發明之一例示性實施例一用於 ，造一具有一如圖4中所說明之共用晝素架構之影像感測 裝置的方法。詳言之，如下文中將參看圖5至1〇進一步詳 ^解釋，對稱地圖案化並圍繞晝素之光電二極體區域排列 前述單位畫素之金屬化層以作為界定在整個晝素陣列上之 每一單位晝素中之對稱地類似的光接受區域的光阻斷屏 蔽，前述單位晝素之金屬化層在主動組件與1/〇訊號線之 間為晝素提供互連。 ^ ^ 園〕八王_ 况明根艨本發明之一例示担 製造一影像感測裝置的初始步驟。詳言之，圖5八是二蚩 素陣列（50)之示意平面圖，其說明用於具有一共用主^ 畫素感測器構架之單位晝素（51)之主動區域的_初 局圖案。此外，圖5B是沿著圖5A之線5β至5β的^音 橫截面圖，且圖5C疋沿者圖5A之線5C至5C 66 :二w 截面圖 如圖5 A中所描繪，陣列（5 〇 )中之每一單位晝 畫素面精P面積，為；金杰切η口 > β ,, — I ’、 5 1 丨丨1甲之母一單位； 佔用相同晝素面積P面積，為達成說明之目的用P〜 PY來表示前述P㈣，如由圖5A中所描繪之虛線 其中Px表示-單位晝素⑻之寬度（在列方向二= ργ表示-早位晝素（51)之長度（在行方向内）。 在圖5Α之例示性實施例中，每一單位晝素（5 =外， 包才舌" 18 1282621 18824pif 對子晝素單位（51a)以及（51b)。在圖5A中，每一子 晝素單位（51a)佔用一中心線c上方之單位晝素（51) 的一上部部分，且每一子晝素單位（51b)佔用前述中心線 C下方之單位晝素（51)的一下部部分。認為前述子晝素 單位（51a)以及（51b)佔用中心線C上方以及下方之相 同之面積P子面積=KP面積0According to an exemplary embodiment of the present invention, the unit cell (41) may be constructed to have a symmetrical structure, and the symmetrical structure provides uniform inter-pixel sensitivity over the entire array (4〇) without a separate and additional Light Blocking Layer FIGS. 5-10 illustrate a method for fabricating an image sensing device having a shared pixel architecture as illustrated in FIG. 4, in accordance with an illustrative embodiment of the present invention. In detail, as will be further explained below with reference to FIGS. 5 to 1 , the metallization layer of the unit pixel is symmetrically patterned and arranged around the photodiode region of the pixel as defined on the entire pixel array. The light-blocking shield of the symmetrically similar light-receiving region of each unit of the pixel, the metallization layer of the unit of the pixel provides interconnection between the active component and the 1/〇 signal line. ^^园〕八王_ 况明根艨 One of the examples of the present invention is the initial step of manufacturing an image sensing device. In particular, Figure 5-8 is a schematic plan view of a dioxane array (50) illustrating an initial pattern for an active region of a unit cell (51) having a common main pixel sensor architecture. 5B is a cross-sectional view taken along line 5β to 5β of FIG. 5A, and FIG. 5C is taken along line 5C to 5C 66 of FIG. 5A: a cross-sectional view of the second w as depicted in FIG. 5A, an array ( 5 〇) 昼 素 素 素 素 素 素 , ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; For the purpose of illustration, P(P) is denoted by P~PY, as indicated by the dashed line depicted in Fig. 5A, where Px represents the width of the unit-element (8) (in the column direction two = ργ - early bit (51) Length (in the row direction). In the exemplary embodiment of Figure 5, each unit of morpheme (5 = outer, packet only tongue " 18 1282621 18824pif pair of subunits (51a) and (51b). In Fig. 5A, each sub-unit unit (51a) occupies an upper portion of a unit cell (51) above a center line c, and each sub-unit unit (51b) occupies a unit below the center line C. The lower part of the prime (51). It is considered that the aforementioned sub-unit units (51a) and (51b) occupy the same area above and below the center line C. P sub-area = KP 0 product

如圖5A至圖5C中所描、、、目’V-千/丨儿重iw )包括 多個主動區域Al、A2、A3以及A4，前述主動區域由一 幵>成於一半導體基板（1〇〇)之一蟲晶基板層（1〇2)中的 隔離區域（103)所界定。在本發明之一例示性實施例中， 月(J述基板層（102)是一使用習知方法而形成之p摻雜層 (p-doped layer)。可用磷摻雜劑來形成前述基板^ (1〇2)。應瞭解在其它例示性實施例中，摻雜層（丨⑽)θ 可為一 Ν摻雜層（N-doPed layer)。基板（ι〇〇)可為η i或Ρ型。刖述隔離區域（1〇3)可由諸如二氧化矽之 =====離(STI)切局部氧化 在前述例示性實施例中，每一單位晝素（5 =域先Ai。—，動區域A1為其，形成有光接收: 之主動區域體鳩光區域。每一單位晝素(51) 域。詳言之是麟晝錢㈣的主動區 ，電晶體以及FD區域界定主動區 ”、㈣重置電晶體以及放大器電晶體界定主動 19 1282621 18824pif 區域。如圖5A中所描繪，由子晝素單位（51a)中之主動 區域A1/A2所形成的形狀是一由子晝素單位（51b)之主 動區域A1/A2所形成的形狀關於前述單位畫素（51 )之中 〜線c的鏡像。一給定之單位晝素（51)之主動區域八3 以及A4分別整體地連接至單位晝素（51)上方以及下方 之鄰近之單位晝素的主動區域A4以及A3。更特定言之， 一單位晝素（51)之一子晝素單位（51b)的主動區域A4 参如主動區域A3而延伸至一鄰近單位晝素（51)之一子晝 素單位（51a)中。如圖5A之例示性實施例中所展示，前 述主動區域Al、A2、A3以及A4對稱地形成於整個陣列 (50)上之每一畫素（51)中。換言之，主動區域A1、 A2、A3以及A4為主動區域界定一單位圖案，前述圖案在 整個晝素陣列（50)上為每一單位畫素（51)而重複。在 此方面，主動區域A1/A2/A3在整個陣列（5〇)上為每一 子晝素單位（51a)界定一子單位圖案，且主動區域 A1/A2/A4在整個陣列（50)上為每一子晝素單位（51b) 界定一子單位圖案。 圖6A、圖6B以及圖6C說明在形成用於主動電晶體 以及光接收元件（例如，光電二極體）之閘電極之後的例 示性晝素感測器陣列（50)。詳言之，圖6A是說明單位 晝素（51)之閘電極之一佈局圖案的例示性俯視平面圖。 圖6B以及圖6C是分別沿著線6B至6β以及線6c至 之圖6A的示意橫截面圖，其說明形成於主動區域A1中之 光接收元件（ll〇a、110b)以及形成於主動區域A4之一 20 1282621 18824pif 部分中的1^擴散區域（111)。 如在圖6A中所描繪，每一單位晝素（51)包括形成 於沿著電晶體主動區域A2、A3以及A4之位置處的各種 閘電極，包括轉移電晶體TX之轉移閘電極（TGI、TG2) (或轉移閘極）、重置電晶體RX之重置閘電極（RG)(或 重置閘極）、一放大器電晶體DX之源極隨耦閘電極（SFG ) 以及選擇電晶體SX之選擇閘電極（RSG)。形成前述閘 電極以重疊前述電晶體主動區域之部分以及鄰近之隔離區 域（103 )之部分。 如圖6B以及圖6C中所描繪，在前述單位晝素（51) 之前述主動區域A1中形成一光接收元件（11〇)。前述光 接收元件（丨1〇)包括一 P+層（108)(或HAD (電洞積 聚一極體）（hole accumulation diode)層）以及一形成於 兩述P+層（108)下方之内埋式η阱層（buried n_well layer) (109)。如此項技術中已知，堆疊p+/n/p層（108)/(1 〇9) / (102)形成一固定光電二極體裝置。因為此等裝置所提 供之各種優點，所以通常在主動晝素感測器設計中實施固 定光電二極體。舉例而言/一固定光電二極體裝置允許自 PD區域至FD區域（16〇)之完整的電荷轉移。此外，前 述P+層（108)藉由將前述内埋式η阱層（1〇9)與矽表面 疋供減少之暗電流（darkcurrent)(如與習知光電 二極體相比）且促使PD區域中之光產生之電荷被積聚並 限制於内埋式n阱層（1〇9)中。如此，前述垆層（、^8) 有效地屏蔽η阱〇09)免遇主動矽表面處熱產生^電荷， 21 1282621 18824pif 從而導致暗電流以及相麟訊元素（nQise element)減少。 此外層（108)運作以藉由在p+層與n牌層之間之接 面中捕獲短波長可見光（藍光）來增加晝素之光譜回應， 而更深之p/n _面可觀更長波長的光（紅光以及紅外 光）。 儘官未特定描緣，但是執行額外處理步驟以為主動晝 素電晶體在主動區域A2、A3以及A4之相關部分中形& ^源極摻雜域。舉例而言，FD齡區域形成於鄰近 於則述轉移閘電極TG1以及TG2之前述主動區域八2中。 此外，如圖6C中所翁，N+摻雜區域形成於主動區域之 相關部A中，在前述相關部分中將通道連接 釀^on)(待隨後形成）接觸至前述主動區域。舉例而 吕，如圖6C中所展示，一摻雜區域（111)形成於鄰近於 源極__SFG之主動區域〜之—末端部分^= 摻雜區域（111)形成驅動畫素陣列（5G)之—輸 之放大器（緩衝器）電晶體之—源極/汲極區域， 當通道接觸點（如下文中將解釋）。 一 極。=:知二法來'成圖6A中·會之前述閘電 由連_地在基板之上連續地形成-絕 、，彖層以及¥電料來形賴述閘電極 料熱氧化而形成之氧化層（或氧切層）示 性貫把射，可使H如CVD (化學論轉（如論 厂dep了二）或ALD (原子層沉積（a deP_〇n))方法之已知方法藉由沉積諸如氮化石夕、二〇 22 1282621 18824pif 等絕緣材料來形成前述_層 而沉積之多晶石夕所形成。箭、十宁电禮J由使用CVD 它合適之閑電極材料之其二=由諸如鎢、銅或其 形成在本發明執之單=? 層。 々W為《閘電極界定閘極絕緣 11〇1^外夹二使用習知方法來形成光電二極體（110a、 舉例而言’在_例示性實施例中 二動=心開σ的光阻圖案（pte 彳J:第-植•用一第二 ir 執行 里來將n型雜質（例如，娜子或坤離子）植人主動巴朽 八1中以便形成前述内埋式續層（1(^)。植人主動&域 圖=、圖7B以及圖7C是說明根據本發明之一例示 第一程度金屬化圖案之形成之後的晝素感測 的例示性圖。詳言之，，7A是說明晝素感 、口口車列（50)之一例不性的第一程度金屬化圖案⑴） 23 I282^24lifAs shown in FIG. 5A to FIG. 5C, the target 'V-thousand-child weight> includes a plurality of active regions A1, A2, A3, and A4, and the active region is formed of a semiconductor substrate (for example). 1〇〇) is defined by an isolation region (103) in one of the insecticidal substrate layers (1〇2). In an exemplary embodiment of the present invention, the substrate layer (102) is a p-doped layer formed by using a conventional method. The phosphorous dopant may be used to form the substrate. (1〇2) It should be understood that in other exemplary embodiments, the doping layer (丨(10)) θ may be an N-doPed layer. The substrate (ι) may be η i or Ρ The isolation region (1〇3) can be locally oxidized by a ======(STI) such as cerium oxide. In the foregoing exemplary embodiment, each unit of halogen (5 = domain Ai. The moving area A1 is formed with light receiving: the active area body light-emitting area. Each unit of the halogen (51) domain. In detail, the active area of the Lin Qian Qian (4), the transistor and the FD area define the active area , (4) resetting the transistor and the amplifier transistor to define the active 19 1282621 18824pif region. As depicted in Figure 5A, the shape formed by the active region A1/A2 in the subunit unit (51a) is a subunit unit ( The shape formed by the active region A1/A2 of 51b) is a mirror image of the line c in the aforementioned unit pixel (51). A given unit of halogen ( 51) The active regions VIII and A4 are integrally connected to the active regions A4 and A3 of the unit cells above and below the unit halogen (51). More specifically, one of the units (51) The active region A4 of the subunit unit (51b) extends into the subunit unit (51a) of a neighboring unit cell (51), as shown in the exemplary embodiment of FIG. 5A, as shown in the exemplary embodiment of FIG. 5A. The active regions A1, A2, A3, and A4 are symmetrically formed in each pixel (51) on the entire array (50). In other words, the active regions A1, A2, A3, and A4 define a unit pattern for the active region, the foregoing The pattern is repeated for each unit of pixels (51) over the entire array of pixels (50). In this regard, the active area A1/A2/A3 is for each subunit unit (51a) over the entire array (5〇). Defining a subunit pattern, and the active area A1/A2/A4 defines a subunit pattern for each subunit unit (51b) over the entire array (50). Figures 6A, 6B, and 6C illustrate the formation After the active transistor and the gate electrode of the light receiving element (eg, photodiode) An exemplary pixel sensor array (50). In detail, Figure 6A is an exemplary top plan view illustrating one of the gate electrodes of the unit halogen (51). Figures 6B and 6C are along line 6B, respectively. A schematic cross-sectional view to 6β and line 6c to FIG. 6A, which illustrates a light-receiving element (11a, 110b) formed in the active area A1 and a 1^ formed in one of the active area A4 20 1282621 18824pif part Diffusion zone (111). As depicted in FIG. 6A, each unit of halogen (51) includes various gate electrodes formed at locations along the transistor active regions A2, A3, and A4, including transfer gate electrodes (TGI, transfer transistor TX) TG2) (or transfer gate), reset gate electrode (RG) of reset transistor RX (or reset gate), source-coupled gate electrode (SFG) of an amplifier transistor DX, and select transistor SX Select the gate electrode (RSG). The foregoing gate electrode is formed to overlap a portion of the aforementioned active region of the transistor and a portion of the adjacent isolation region (103). As depicted in FIG. 6B and FIG. 6C, a light receiving element (11A) is formed in the aforementioned active area A1 of the aforementioned unit halogen (51). The light receiving element (丨1〇) includes a P+ layer (108) (or a HAD (hole accumulation diode) layer) and a buried type formed under the two P+ layers (108) a buried n_well layer (109). As is known in the art, the stacked p+/n/p layers (108)/(1 〇9) / (102) form a fixed photodiode device. Because of the various advantages offered by such devices, fixed photodiodes are typically implemented in active pixel sensor designs. For example, a fixed photodiode device allows for complete charge transfer from the PD region to the FD region (16 Å). In addition, the P+ layer (108) promotes PD by using the buried n-well layer (1〇9) and the surface of the germanium to reduce the dark current (as compared with the conventional photodiode). The charge generated by the light in the region is accumulated and confined in the buried n-well layer (1〇9). Thus, the foregoing germanium layer (, 8) effectively shields the n-well 〇 09) from the heat generated at the surface of the active germanium, 21 1282621 18824pif, thereby causing a decrease in dark current and nQise element. The further layer (108) operates to increase the spectral response of the halogen by capturing short-wavelength visible light (blue light) in the junction between the p+ layer and the n-plate layer, while the deeper p/n _ surface is longer wavelength Light (red light and infrared light). The process is not specifically described, but additional processing steps are performed to form the & source-doped domains in the active portions of active regions A2, A3, and A4 for the active germanium transistors. For example, the FD age region is formed in the aforementioned active region 八 2 adjacent to the transfer gate electrodes TG1 and TG2. Further, as shown in Fig. 6C, the N+ doped region is formed in the associated portion A of the active region, and the channel is connected to the active region in the aforementioned related portion. For example, as shown in FIG. 6C, a doped region (111) is formed adjacent to the active region of the source __SFG - the end portion ^ = the doped region (111) forms a driving pixel array (5G) - the source/drain region of the amplifier (buffer) transistor, when the channel contacts (as explained below). One pole. =: knowing the second method to form the picture of the above-mentioned gates in Figure 6A. The gates are formed continuously on the substrate by the _ ground, and the ruthenium layer and the electric material are formed by thermal oxidation of the gate electrode material. The oxide layer (or oxygen-cut layer) can be used to illuminate H, such as CVD (known as chemical depolarization) or ALD (a deP_〇n) methods. It is formed by depositing an insulating material such as nitriding cerium, lanthanum 22 1282621 18824pif, etc. to form the aforementioned _ layer and depositing the polycrystalline stone. The arrow and the tening electrons are made of CVD. = by a layer such as tungsten, copper or the like formed in the present invention. 々W is "the gate electrode defines the gate insulation 11 〇 1 ^ outer clip two using conventional methods to form a photodiode (110a, for example For example, in the exemplary embodiment, the second action = the opening of the sigma photoresist pattern (pte 彳 J: the first plant • use a second ir to perform the n-type impurity (for example, Nazi or Kun ion)植人 initiative 八八中 in order to form the aforementioned buried continuation layer (1 (^). implanted active & domain map =, Figure 7B and Figure 7C is illustrative according to the present invention An exemplary diagram of the halogen sensing after the formation of the first degree metallization pattern is exemplified. In detail, 7A is a first degree metallization pattern indicating that the elemental sensation and the mouthpiece train (50) are inconsistent. (1)) 23 I282^24lif

之示意俯視平面圖，而圖7B以及圖7C是分別沿著線7B 至7B以及線7C至7C之圖7A之畫素影像感測器陣列（5〇) 的示意橫截面圖。 ，根據本發明之一例示性實施例，設計前述第一程度金 屬化圖案（L1)以用於各種目的。舉例而言，前述第一程 度金屬化圖案（L1)包括導線以及互連以在晝素組件以及 支撐晝素I/O之間提供電連接。另外，v前述第一程度金屬 化圖案（L1)運作作為一在整個陣列（)上每一書素（51 ) • 中具有—重複、對稱圖案的光阻斷層，前述結斷層經設 計以平均化每一單位晝素（51)中之光電二極體（11〇&以 及110b)的感度以及整個陣列（50)之上之單位晝素（51) 之光電一^虽體的感度。形成前述第一程度金屬化圖宰（li) 以在每一畫素中有效地組態或相反界定對稱的光接收區 域。如上文中參看圖5A所論述，前述陣列（％)中之每 一單位晝素（51)佔用相同之晝素面積Ρ _ = ΡχχΡγ。此 外，在圖7Α之例示性實施例中，為達成說明之目的，每 φ 一晝素（51)之一 EPS(有效感光）區域佔用一由xPy 所界定的面積，其中表示列方向内之EPS區域的寬度（其 小於Px)且其中PY表示行方向内之EPS區域的長度（其 與行方向内之晝素單位（51)的長度相同）。詳言之，如 圖7A中所描繪，每一單位晝素（51)之一例示性eps區 域包括由光電二極體（U〇a以及ii〇b)所佔用之晝素區域 以及一環繞前述光電二極體（110a以及110b)之周邊區域。 參看圖7A，前述第一程度金屬化圖案（L1)包括各 24 i282m. 種控制線，前述控制複白 Xr ryn r ^ vjy nu、(重置閑極）控制線 ()〇 (轉移閘極）控制線（141)以及（142)， (列選擇閘極）控制線（M4)。前述奶控 制線—(143)猎由通道連接（133)而連接至陣列（⑹之 ^列_之全部單位晝素（51)的RG電極。前述RSG &制線Π44)藉由通道連接（134)而連接至陣列（5〇) 之-給定之列中之全部單位晝素（51)的SG電極。前述 TG控制線（141)以及（142)分別藉由通道連接（⑶） 以及（132)而連接至_ (5G)之—給定之财之全部單 位畫素（51)的TGa以及TGb (轉移開極）電極。 另外’前述第-程度金屬化圖案（L1)包括金屬襯墊 (145a)、（145b)以及⑽），以及互連線（14⑷以 及（146b)。前述襯墊（145b)藉由一通道連接（即而 連接至摻縣域（1U)。前述婦（149) &鄰近之單位 ^素（在行方向内）所共用，且藉由—通道連接（139)而 連接至前述列選擇電晶體以及緩衝放大器電晶體之一共用 摻雜區域（源極級極區域）。前述互連線（M6a)在前述 重置電晶體以及前述上部FD區域之間提供一電 ^之，前述互連線⑽a)之-末端藉由通道插塞（yia㈣） 136)而連接至重置電晶體之一源極區域，且藉由一通道 插塞（137a),而連接至一上部浮動擴散區域。前述互連線 (146b)在鈾述源極隨耦電晶體之閘電極（π。）盥前述 下部ro @域之間提供-電連接。詳言之，前述錢線 (146b)之一末端藉由插塞（138)而連接至源極隨耦電晶 25A schematic top plan view is shown, and FIGS. 7B and 7C are schematic cross-sectional views of the pixel image sensor array (5A) of FIG. 7A along lines 7B to 7B and lines 7C to 7C, respectively. According to an exemplary embodiment of the present invention, the aforementioned first degree of metallization pattern (L1) is designed for various purposes. For example, the aforementioned first degree metallization pattern (L1) includes wires and interconnects to provide an electrical connection between the pixel components and the supporting pixel I/O. In addition, v the first degree metallization pattern (L1) operates as a light blocking layer having a repeating, symmetrical pattern in each of the pixels (51) in the entire array (), the aforesaid junction layer being designed to average The sensitivity of the photodiodes (11〇 & and 110b) in each unit of halogen (51) and the sensitivity of the unit of the unit of halogen (51) over the entire array (50). The aforementioned first degree metallization pattern (li) is formed to effectively configure or otherwise define a symmetric light receiving region in each pixel. As discussed above with reference to Figure 5A, each unit of halogen (51) in the aforementioned array (%) occupies the same pixel area Ρ _ = ΡχχΡ γ. Further, in the exemplary embodiment of FIG. 7A, for the purpose of explanation, one of the EPS (effective photosensitive) regions per φ 昼 ( (51) occupies an area defined by xPy, which represents the EPS in the column direction. The width of the region (which is less than Px) and where PY represents the length of the EPS region in the row direction (which is the same length as the pixel unit (51) in the row direction). In detail, as depicted in FIG. 7A, one exemplary eps region of each unit of halogen (51) includes a pixel region occupied by photodiodes (U〇a and ii〇b) and a surrounding Peripheral regions of the photodiodes (110a and 110b). Referring to FIG. 7A, the first degree metallization pattern (L1) includes 24 i282m. control lines, the control resetting Xr ryn r ^ vjy nu, (reset idle) control line () 〇 (transfer gate) Control lines (141) and (142), (column selection gate) control lines (M4). The aforementioned milk control line - (143) is connected to the array (133) by the channel connection (133) to the array (the RG electrode of all units of the unit (51). The aforementioned RSG & line 44) is connected by a channel ( 134) and connected to the SG electrode of the array (5〇) - all of the unit halogens (51) in a given column. The aforementioned TG control lines (141) and (142) are connected to _ (5G) - TGa and TGb of all unit pixels (51) of a given wealth by channel connections ((3)) and (132), respectively. Electrode) electrode. Further, the aforementioned first-degree metallization pattern (L1) includes metal pads (145a), (145b) and (10), and interconnect lines (14(4) and (146b). The aforementioned pads (145b) are connected by a channel ( That is, it is connected to the doping area (1U). The neighboring unit (149) & adjacent unit is shared (in the row direction), and is connected to the column selection transistor and buffer by the channel connection (139). One of the amplifier transistors shares a doped region (source-level pole region). The aforementioned interconnect (M6a) provides an electrical connection between the reset transistor and the aforementioned upper FD region, and the aforementioned interconnect (10) a) The end is connected to one of the source regions of the reset transistor by a channel plug (yia) and is connected to an upper floating diffusion region by a channel plug (137a). The aforementioned interconnect (146b) provides an electrical connection between the uranium source and the gate electrode (π.) of the coupled transistor and the aforementioned lower ro@ domain. In detail, one end of the aforementioned money line (146b) is connected to the source follower transistor 25 by a plug (138).

1282621 18824pif 體=:、車i前述互連線(146b)之另一末端藉由插塞1282621 18824pif body =:, car i the other end of the interconnect (146b) by plug

Uj/b)而連接至下部fd區域。 屬化==，示性實施例中所崎，前述第-程度金 屬化圖木（L1)運作作為一光阻斷層，其中第—程度金屬 化圖案（L1)由一在整個陣列（5〇)上每一畫素（^)中 ^複的單位圖案所形成。詳言之，前述第度金屬化圖 水（L1)經形成以具有一在整個前述陣列上每一單位晝素 (=)中重複的對稱單位圖案（稱為單位L1圖案）了設 。十士述單位LI ®案作為—光阻斷層，前述光阻斷層在每 了單位晝素（51)中界定對稱地類似的光接收區域且運作 以均勻地並對稱地屏蔽入射光免於進入環繞每一單位晝素 (51)中之光電二極體之感光區域，以藉此均勻化每一單 位晝素（51)中之光電二極體（11此以及u〇b)的感度以 及整個陣列（5G)之上之單位晝素之全部光電二極體的感 度。别述單位L1圖案經對稱地圖案化並排列以均勻覆蓋 環繞前述光電二極體（110a以及110b)之周邊區域。 在另一例示性實施例中，一用於每一晝素單位（51) 之單位L1是由一用於每一子晝素單位（5la)以及（51b) 之子單位圖案（或子單位L1圖案）所纽成，其中前述子 旦素單位（51a)以及（51b)之前述子單位li圖案形成 一關於單位晝素（51)之中心線c的鏡像圖案。 詳言之，前述轉移閘極線（141)以及（142)在書素 (51)之光電二極體（110a)以及（11%)之間之一感光 區域中於列方向内延伸。對稱地圖案化並排列前述轉移閘 26 1282621 18824pif 極線（141)以及（142)以提供相等之光阻斷面積，且將 前述轉移閘極線（141)以及（142)分別地安置並排列於 環繞光電二極體（ll〇a)以及（11〇b)之感光區域之上， 以便和:供相等的光阻斷面積且均勻化二極體之感度。此 外，轉移閘極線（141)以及（142)具有對稱突起部分D3 以及D4。前述突起部分D3以及D4是虛設元件，其經形 成以覆蓋EPS區域中之感光區域並進一步界定晝素之光接 收面積，且因此均勻化二極體之感度。在圖7A之例示性 • 實施例中，轉移閘極線（141)以及（142)是關於前述子 畫素單位（51a)與（51b)之間之中心線C的鏡像圖案。 類似地，前述RG控制線（143 )以及RSG控制線（144 ) 在行方向内之鄰近之畫素（51)的光電二級體（11〇a)以 及（110b)之間之一感光區域中於列方向内延伸。在每一 単位旦素（51)中對稱地圖案化並排列前述控制線（μ)) 以及（144)以提供光電二極體（ll〇a)以及（ii〇b)之間 之感光區域之相等的光阻斷面積，以便分別提供相等的光 • 阻斷面積並均勻化二極體之感度。在圖7A之例示性實施 例中，别述RG控制線（143 )以及RSG控制線（144 )是 關於前述子晝素單位（5la)與（51b)之間之中心線C的 鏡像圖案。 母一子畫素單位（51b)中之襯墊元件（145b)經形成 以為通道插塞（135)提供一電連接，並具有一延伸區域以 提供對鄰近於光電二極體（11〇b)之感光區域的光屏蔽。 對稱地圖案化並排列每一子晝素單位（5ia)中之襯藝元件 27 I282621f (145a)以補償相應子晝素單位（51b)之襯墊元件（μ%)。 換言之，前述襯墊元件〇45a)是一虛設元件D1，前述虛 設元件D1不具有電功能而是僅運作以屏蔽入射光並均勻 化二極體（110a)以及（UOb)之間的感度。在圖7A之 例示性實施例中，前述襯墊元件（145a)以及（145b)是 關於前述子晝素單位（51a)與（51b)之間之中心線c的 鏡像圖案。 對稱地圖案化並排列前述互連線（146a)以及（146b) • 以致能光屏蔽並均勻化光電二極體之感度。前述互連 (146a)經形成為具有延伸/突起部分D2，前述延伸/突起 部分D2運作以補償前述下部互連（146b)之插塞（138) 接觸部分，且因此均句化二極體（11〇a、11〇b)之面積以 及感度。另外，一給定之單位晝素之互連（146a、146b) 包括經伸長之部分，前述經伸長之部分經安置以覆蓋鄰近 之單位晝素（51)中之光電二極體的感光區域。在圖7A 之例示性實施例中，前述互連（146a)以及（146b)是關 • 於前述子晝素單位（51a)與（51b)之間之中心線c的鏡 像圖案。 圖7B以及圖7C疋分別沿著線7B至7B以及線7C至 7C之圖7A之示意橫截面圖。使用習知方法在基板之上形 成一介電層（120)。舉例而言，前述介電層（12〇)可由 使用CVD製程而沉積之二氧化矽所形成。使用習知方法 來形成諸如前述通道連接（135)(以及上文中圖7A中所 描述之其它通道連接）之通道連接（或插塞）。舉例而言， 28 1282621 l8824pif 可藉由蝕刻介電層（120)以形成通道孔，使用習知方法來 沉積諸如銅或鎢之導電材料以用前述導電材料填充前述通 道孔來形成通道連接（例如，插塞135)，且接著執行一 蝕刻製程或CMP製程以移除介電層（120)之表面上的導 $材料並平面赠述表面。接著可#由，#由缝來沉積 一諸如銅或鋁之導電材料並接著使用一習知光微影製程來 圖案化前述導電層，來形成前述第一程度金屬化層（li)。 圖8A、圖8B以及圖8C是說明根據本發明之一例示 性實施例在一第二程度金屬化圖案（L2)之形成之後的晝 素感測為陣列（50)的例示性圖。詳言之，圖8A是說明 晝素感測器陣列（50)之一第二程度金屬化圖案（L2)之 例示性佈局的示意俯視平面圖，而圖8B以及圖8c是分別 =著線8B至8B以及、線8C至8C之圖8A之晝素影像感測 為陣列（50)的示意橫截面圖。 根據本發明之一例示性實施例，將前述第二程度金屬 化圖案（L2)對稱地圖案化並排列成環繞每一單位書素 ^51)中之PD元件（11〇a以及n〇B)以作為一光阻斷層， 韵述光阻斷層進一步界定/組態每一單位晝素（Μ )之光接 收區域以便進一步均勻化每一子畫素單位（51)中之光電 —極體（110a以及ll〇b)的感度以及整個晝素陣列（5〇) 上之光電二極體的感度。 詳言之，在如圖8A中所描繪之本發明的一例示性實 =例中，妯述第二程度金屬化圖案（L2)經形成以在整個 釗述陣列上具有一在每一單位晝素（51)中重複的單位金 29 1282621 18824pif 屬化圖案（稱為單值U_)。將前述麵的單位L2gJ 案設計作為一光阻斷層，前述光阻斷層與前述重複的單位 L1圖案結合而進-步界定每—單位晝素（51)中之對稱地 類似的光減區域並運作以均勻地並對稱地屏蔽入射光免 於進入環繞每-單位畫素（51)中之光電二極體之感光區 域以便提供進一步晝素感度均勻化。此外，在圖8a之例 示性實施例中，前述用於每一晝素單位（51)之單位L2 ，案包括一用於每一子晝素單位（5la)以及（51b)的子 f位金屬化圖案（或子單位L2圖案），其中前述子畫素 單，（51a)以及（5lb)之前述子單位L2圖案是關於前 述單位晝素（51)之中心線c的鏡像圖案。 參看圖8A至圖8C，前述第二金屬化層（L2)經圖案 化以包括行輸出線（175)、電源（VDD)線（179)以及 互連線（176)。前述行輸出線（175)藉由通道連接（165) =連接至前述第一金屬化層（L1)之襯墊元件（145b)。 則述行輸出線（175)沿著光電二級體區域（110a、u〇b) 之邊緣在行方向内延伸並屏蔽鄰近於光電二極體（ll〇a、 11〇b)相鄰之感光區域之未被第一金屬化圖案（L1)覆蓋 的彼等部分。前述行輸出線（175)包括為接觸（165)區 域補侦突起之虛設元件（D5)以藉均勻化感度。在圖8A 之例不性實施例中，前迷行輸出線（175)是關於前述子晝 素單位（51a)與（51b)之間之中心線C的鏡像圖案。 為進行進一步均勻化，參見圖8B，通道插塞（未圖示） 可視需要而形成於輸出線（175)之突起虛設元件（D5) 30 1282621 18824pif ，第-金屬化圖案（L1)之虛設襯墊元件（m)之間以補 償接觸插塞（165)。 互連（176)在單位晝素（51)之第一與第二叩區域 之間提供電連接。詳言之，形成一接觸插塞（)以將 互連線（167)之一末端連接至對準於接觸插塞（137的（圖 =)之第一金屬化層（L1)之互連線（146a)的一末端部 刀。另外，形成一接觸插塞（167b)以將互連線（167)之 φ 另一末端連接至對準於接觸插塞（137b)之第一金屬層 (^1)之互連線（146b)的一末端部分。在圖8A之例示 性實施例中，前述互連（176)是關於前述子晝素單位（51a) 與（51b)之間之中心線c的鏡像圖案。 前述電源線（179)沿著光電二級體（110a、110b)之 邊緣在行方向内延伸並屏蔽鄰近於前述光電二極體 (UOa、ll〇b)之感光區域之未被第一金屬化圖案（L1) 覆蓋的彼等部分。前述電源線（179)具有突起部分，前述 突起部分具有連接至第一金屬層（L1)之接觸襯墊（149) • 的接觸插塞（169)。電源線（179)具有在光電二級體（110a 以及110b)之間之感光區域之上延伸的突起虛設元件（D6) 以提供對未被第一金屬化圖案（L1)之控制線（141-144) 覆蓋之感光區域的進一步屏蔽，且進一步界定光接收區 域。在圖8A之例示性實施例中，前述電源線（179)具有 關於前述子畫素單位（5la)與（51b)之間之中心線C的 鏡像圖案。 參看圖8B以及圖8C，使用習知方法在具有第一金屬 31 I28262l l8824pif 化，案（LI)之基板上形成一層間介電層（15〇)。舉例 ，言，前述介電層（150)可由使用CVD製程而沉積之二 孔化矽所形成。前述插塞（135)(以及如上文中在圖8A 中所4田述之其它插塞）是例如使用諸如上文中所描述之習 法由銅或鎢所形成的。接著可藉由，藉由濺鍍來沉積 "者如銅或|呂之導電材料並接著使用一習知光微影製程來 圖案化前述導電層，來形成前述第二金屬化層（L2)。 春#圖9是說明前述閘電極與前述第一金屬化層L1以及 第二金屬化層L2之組合佈局圖案的示意俯視平面圖。如 所展不，在每一晝素（51)中，將第一以及第二金屬化層 L1以及L2對稱地圖案化並排列成圍繞光電二級體區域 (ll〇a以及ll〇b)，從而使得前述第一以及第二層在EPS 區域中有效地界定孔徑，前述孔徑曝露每一晝素中之光接 收區域，其中前述光接收區域在尺寸以及面積上是對稱的。 在圖9中所描繪之例示性實施例中，前述光接收區域 包括主動區域A1之大部分以及環繞前述區域A1之感光區 • 域的一部分。藉由對稱地圖案化下部金屬化層中之一者或 多者來運作作為光屏蔽，可最大化光接收區域之被曝露之 面積以增加晝素感度，同時為一給定之晝素中之每一光電 二極體以及整個晝素陣列上之光電二極體保持均勻的晝素 感度。對於圖9之例示性共用晝素結構而言，藉由形成閘 極層L1以及金屬化層L2以具有每一單位畫素中之重複的 單位圖案以及每一單位晝素中之用於子畫素單位之重複的 子晝素圖案，來獲得一給定之單位晝素（51)中之光電二 32 1282621 18824pif 極體110a以及110b之間的均勻化的感度。此外，在另一 例示性實施例中，儘管每一單位晝素中之子晝素圖案是關 於單位晝素之中心線C之一鏡像圖案，但是應瞭解並不要 求使用一鏡像圖案。 圖10是說明一可形成於前述晝素感測器陣列（50)之 上之第三金屬化層（L3)之佈局圖案的示意俯視平面圖。 前述第三金屬化層（L3)經圖案化以形成隔離襯墊（190) (鋁或銅），前述隔離襯墊不具有電功能，但是其作用以 ^ 減少基板中之總體步驟的差異，前述差異是由形成於主動 晝素陣列（50)中的導電層與形成於包括諸如類比數位轉 換器、ISP (影像訊號處理器）等電路（之固態影像感測器 晶片之一周邊邏輯區域中的導電層的不同數量所導致。 在圖10之例示性實施例中，可在主動區域A2以及鄰 近於前述區域A2之A1之區域上以一方式對稱地圖案化並 排列第三導電圖案（190)，此方式提供對未被第一以及第 二金屬化層覆蓋之感光區域的進一步光屏蔽，但是避免限 9 制可捕獲之入射光的角度。 應進一步瞭解，可將根據本發明之例示性實施例具有 經架構有畫素之晝素陣列的CM〇s影像感測裝置實施於 =種類型之基於處理器的系統。舉例而言，圖u是根據本 务月之例示性貫施例之一具有一影像感測裝置之系統 ^2〇〇)的咼階方塊圖。舉例而言，前述系統（2〇〇)可實 鉍於例如電腦系統、攝影機系統、掃描器、機器視覺系統、 車輛導航系統、視訊電話、監視系統、自動聚焦系統、星 33 1282621 18824pif 體追蹤儀系統、運動偵測系統、影像穩定系統、移動電話 以及其它基於處理器之系統中。 實質上而言，前述系統（200)包括一 CMOS影像器 裝置（210)，一或多個CPU (中央處理單元）或微處理 器（220)、一或多個I/O裝置（230)、一軟性磁碟驅動 器（240 )(或其它§己’丨思卡插槽）、ram ( 250 )以及一 CD ROM驅動器（260)，前述之全部經由一系統匯流排 (270)而被有效地耦合。所實施之系統組件的類型將視系 統之類型而變化。舉例而言，通常將諸如軟性磁碟驅動器 (240)以及CD R0M驅動器（26〇)之周邊裝置與例如; 人電腦或膝上型電腦一起而加以使用。 、CMOS影像器裝置（210)包括一可使用本文中所描 ^之任一例示性晝素架構而建構的晝素陣列。前述cM〇s 〜像裝置（210)產生來自供應自前述晝素陣列之訊號的一 輪出影像。CMOS影像器裝置（210)在匯流排（27〇)之 上或其它通訊鏈路上與系統組件通訊。在另一例示性實施 響7中，處理器（220)、CMOS影像器裝置（21G)以及記 憶體（250)可整體地形成於一單個IC晶片上。 ΰ 〜雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 $範圍内，當可作些許之更動與潤飾，因此本發明之保護 乾圍當視後附之申請專利範圍所界定者為準。 ϋ 【圖式簡單說明】 圖1是說明一具有一 4電晶體（4_τ)主動晝素感測器 34 1282621 18824pif 構架之習知CMOS影像感測裝置之一單位畫素的示意電 路圖。 圖2說明_例示性單位晝素佈局以說明書素瑱充因數 之概念。 〆 圖3是一具有一光屏蔽層之習知單位書素的示意側視 圖。 圖4是一具有一共用晝素構架之主動晝素感測器陣列 φ 的不意電路圖，可將本發明應用於前述共用畫素構架。 圖5至圖10說明一用於基於圖4之晝素陣列電路結構 來建構一半導體CMOS主動晝素影像感測裝置的方法，前 ，半導體CMOS主動畫素影像感測裝置具有對稱結構之 單位晝素以提供均勻感度。 圖11是根據本發明之一例示性實施例之一具有一影 像感測裝置之系統的高階方塊圖。 【主要元件符號說明】 10 :晝素 參 20 :單位晝素 21 ·感光區域 22 :電晶體區域/PD區域 23 ·周邊區域 3〇 :基板 31 :隔離層 32 ·擴散區域 3 3 ·擴散區域 35 1282621 18824pif 34 :堆疊結構/堆疊層 34a :光屏蔽 34b :孔徑 34c :隧道區域 40 :晝素陣列 41 :單位晝素 42a :光電二極體 42b :光電二極體Uj/b) is connected to the lower fd area. Generic ==, in the exemplary embodiment, the first degree metallization pattern (L1) operates as a light blocking layer, wherein the first degree metallization pattern (L1) consists of one in the entire array (5〇) A unit pattern is formed in each pixel (^). In detail, the aforementioned third metallization pattern water (L1) is formed to have a symmetrical unit pattern (referred to as a unit L1 pattern) repeated in each unit of halogen (=) over the entire array. As a light blocking layer, the aforementioned light blocking layer defines a symmetrically similar light receiving region in each unit of halogen (51) and operates to uniformly and symmetrically shield the incident light from the incident light. Entering a photosensitive region surrounding the photodiode in each unit of halogen (51) to thereby homogenize the sensitivity of the photodiode (11 and u〇b) in each unit of halogen (51) and The sensitivity of all photodiodes of a unit of halogen above the entire array (5G). The unit L1 patterns are symmetrically patterned and arranged to uniformly cover the peripheral regions surrounding the aforementioned photodiodes (110a and 110b). In another exemplary embodiment, a unit L1 for each pixel unit (51) is a sub-unit pattern (or sub-unit L1 pattern for each sub-unit unit (5la) and (51b). The pattern of the aforementioned sub-units li of the aforementioned sub-denier units (51a) and (51b) forms a mirror image pattern about the center line c of the unit halogen (51). In detail, the transfer gate lines (141) and (142) extend in the column direction in one of the photosensitive regions between the photodiodes (110a) and (11%) of the pixel (51). The transfer gates 26 1282621 18824pif pole lines (141) and (142) are symmetrically patterned and arranged to provide equal light blocking areas, and the aforementioned transfer gate lines (141) and (142) are respectively disposed and arranged Surrounding the photosensitive regions of the photodiode (11〇a) and (11〇b) to provide the same light blocking area and uniformize the sensitivity of the diode. Further, the transfer gate lines (141) and (142) have symmetric protruding portions D3 and D4. The aforementioned protruding portions D3 and D4 are dummy elements which are formed to cover the photosensitive regions in the EPS region and further define the light receiving area of the halogen, and thus homogenize the sensitivity of the diode. In the exemplary embodiment of Fig. 7A, the transfer gate lines (141) and (142) are mirror images of the center line C between the aforementioned sub-pixel units (51a) and (51b). Similarly, the aforementioned RG control line (143) and the RSG control line (144) are in a photosensitive region between the photodiodes (11〇a) and (110b) of the adjacent pixels (51) in the row direction. Extend in the column direction. The control lines (μ) and (144) are symmetrically patterned and arranged in each of the germanium (51) to provide a photosensitive region between the photodiodes (11a) and (ii) Equal light blocking areas to provide equal light respectively • Block the area and homogenize the sensitivity of the diode. In the exemplary embodiment of Fig. 7A, the RG control line (143) and the RSG control line (144) are mirror images of the center line C between the aforementioned sub-cell units (5la) and (51b). A spacer element (145b) in the mother-sub-pixel unit (51b) is formed to provide an electrical connection for the channel plug (135) and has an extended region to provide proximity to the photodiode (11〇b) Light shielding of the photosensitive area. The lining elements 27 I282621f (145a) in each subunit unit (5ia) are symmetrically patterned and arranged to compensate for the spacer elements (μ%) of the corresponding sub-unit units (51b). In other words, the aforementioned spacer element 〇45a) is a dummy element D1 which does not have an electrical function but operates only to shield incident light and to homogenize the sensitivity between the diodes (110a) and (UOb). In the exemplary embodiment of Fig. 7A, the aforementioned spacer members (145a) and (145b) are mirror images of the center line c between the aforementioned sub-cell units (51a) and (51b). The aforementioned interconnect lines (146a) and (146b) are symmetrically patterned and arranged to enable light shielding and uniformization of the sensitivity of the photodiode. The aforementioned interconnect (146a) is formed to have an extension/protrusion portion D2 that operates to compensate for the plug (138) contact portion of the aforementioned lower interconnection (146b), and thus the homogenized diode ( The area and sensitivity of 11〇a, 11〇b). Additionally, a given unit of halogen interconnect (146a, 146b) includes an elongated portion that is disposed to cover the photosensitive region of the photodiode in the adjacent unit halogen (51). In the exemplary embodiment of Fig. 7A, the aforementioned interconnections (146a) and (146b) are mirror images of the center line c between the aforementioned sub-cell units (51a) and (51b). Fig. 7B and Fig. 7C are schematic cross-sectional views of Fig. 7A along lines 7B to 7B and lines 7C to 7C, respectively. A dielectric layer (120) is formed over the substrate using conventional methods. For example, the dielectric layer (12 Å) may be formed of cerium oxide deposited using a CVD process. Conventional methods are used to form channel connections (or plugs) such as the aforementioned channel connections (135) (and other channel connections described above in Figure 7A). For example, 28 1282621 l8824pif can form a via connection by etching a dielectric layer (120) to form a via hole, using a conventional method to deposit a conductive material such as copper or tungsten to fill the via hole with the aforementioned conductive material (eg, Plug 135), and then an etch process or CMP process is performed to remove the conductive material on the surface of the dielectric layer (120) and to planarize the surface. Then, a conductive material such as copper or aluminum is deposited by the slit and then patterned using a conventional photolithography process to form the first degree metallization layer (li). 8A, 8B, and 8C are illustrative diagrams illustrating the sensing of a matrix (50) after formation of a second degree metallization pattern (L2), in accordance with an exemplary embodiment of the present invention. In particular, Figure 8A is a schematic top plan view illustrating an exemplary layout of a second degree metallization pattern (L2) of one of the halogen sensor arrays (50), while Figures 8B and 8c are respectively = line 8B to The pixel image of FIG. 8A of 8B and line 8C to 8C is sensed as a schematic cross-sectional view of the array (50). According to an exemplary embodiment of the present invention, the second degree metallization pattern (L2) is symmetrically patterned and arranged to surround the PD elements (11〇a and n〇B) in each unit of the pixel. As a light blocking layer, the rhyme blocking layer further defines/configures the light receiving region of each unit of halogen (Μ) to further homogenize the photo-polar body in each sub-pixel unit (51). The sensitivity of (110a and ll〇b) and the sensitivity of the photodiode on the entire halogen array (5〇). In particular, in an exemplary embodiment of the invention as depicted in FIG. 8A, the second degree metallization pattern (L2) is formed to have one in each unit on the entire array. Repeated unit gold 29 1282621 18824pif genitive pattern (called single value U_) in element (51). The unit of the aforementioned surface L2gJ is designed as a light blocking layer, and the light blocking layer is combined with the above-mentioned repeated unit L1 pattern to further define a symmetrically similar light-reducing area in each unit element (51). It also operates to uniformly and symmetrically shield the incident light from entering the photosensitive region surrounding the photodiode in each unit pixel (51) to provide further uniformization of the pixel sensitivity. Further, in the exemplary embodiment of FIG. 8a, the foregoing unit L2 for each unit of the prime unit (51) includes a sub-f-position metal for each sub-unit unit (5la) and (51b). The pattern (or sub-unit L2 pattern), wherein the aforementioned sub-picture sheets, the sub-unit L2 patterns of (51a) and (5lb) are mirror images of the center line c of the unit cell (51). Referring to Figures 8A through 8C, the aforementioned second metallization layer (L2) is patterned to include a row output line (175), a power (VDD) line (179), and an interconnect (176). The row output line (175) is connected to the pad element (145b) of the first metallization layer (L1) by a via connection (165). The row output line (175) extends in the row direction along the edge of the photodiode region (110a, u〇b) and shields the adjacent photosensitive photodiode (11a, 11〇b) The portions of the region that are not covered by the first metallization pattern (L1). The aforementioned row output line (175) includes a dummy element (D5) that complements the protrusion of the contact (165) region to uniformize the sensitivity. In the exemplary embodiment of Fig. 8A, the front output line (175) is a mirror image of the center line C between the aforementioned sub-unit units (51a) and (51b). For further homogenization, referring to FIG. 8B, a channel plug (not shown) may be formed on the output line (175) as needed by the protruding dummy element (D5) 30 1282621 18824pif , the dummy lining of the first metallization pattern (L1) Between the pad elements (m) to compensate for the contact plugs (165). The interconnect (176) provides an electrical connection between the first and second turns of the unit cell (51). In detail, a contact plug () is formed to connect one end of the interconnect (167) to the interconnect line of the first metallization layer (L1) aligned with the contact plug (137). An end knives of (146a). Further, a contact plug (167b) is formed to connect the other end of φ of the interconnect (167) to the first metal layer aligned with the contact plug (137b) (^ 1) an end portion of the interconnect (146b). In the exemplary embodiment of Figure 8A, the aforementioned interconnect (176) is about a centerline c between the aforementioned sub-cell units (51a) and (51b) The image pattern (179) extends in the row direction along the edge of the photodiode (110a, 110b) and shields the photosensitive region adjacent to the photodiode (UOa, llb) The first metallization pattern (L1) covers the same portion. The aforementioned power supply line (179) has a protruding portion having a contact plug connected to the contact pad (149) of the first metal layer (L1) ( 169) The power supply line (179) has a protruding dummy element (D6) extending over the photosensitive area between the photodiodes (110a and 110b) Providing further shielding of the photosensitive region that is not covered by the control lines (141-144) of the first metallization pattern (L1), and further defining a light receiving region. In the exemplary embodiment of FIG. 8A, the aforementioned power supply line ( 179) having a mirror image pattern of the center line C between the aforementioned sub-pixel units (5la) and (51b). Referring to FIG. 8B and FIG. 8C, using the conventional method, there is a first metal 31 I28262l l8824pif, case (LI An intermediate dielectric layer (15 Å) is formed on the substrate. For example, the dielectric layer (150) may be formed of a two-hole yttrium deposited using a CVD process. The plug (135) (as above) Other plugs as described in Fig. 8A are formed of copper or tungsten, for example, using a method such as that described above. Then, by sputtering, etc., such as copper or | Lu's conductive material is then patterned using a conventional photolithography process to form the second metallization layer (L2). Spring # Figure 9 illustrates the gate electrode and the first metallization layer L1 and Description of the combined layout pattern of the two metallization layers L2 A top plan view. As shown, in each element (51), the first and second metallization layers L1 and L2 are symmetrically patterned and arranged to surround the photodiode region (ll〇a and ll〇). b) such that the aforementioned first and second layers effectively define an aperture in the EPS region, the aforementioned aperture exposing the light receiving region in each element, wherein the aforementioned light receiving region is symmetrical in size and area. In the exemplary embodiment depicted in 9, the aforementioned light receiving region includes a majority of the active region A1 and a portion of the photosensitive region• region surrounding the aforementioned region A1. By operating one or more of the lower metallization layers symmetrically to function as a light shield, the exposed area of the light receiving region can be maximized to increase the sensibility of the sputum while at the same time being a given element A photodiode and the photodiode on the entire halogen array maintain a uniform halogen sensitivity. For the exemplary shared pixel structure of FIG. 9, by forming the gate layer L1 and the metallization layer L2 to have a repeating unit pattern in each unit pixel and a sub-picture for each unit of the pixel The repeating sub-purine pattern of the prime unit is used to obtain the uniformity of sensitivity between the photodiodes 32 1282621 18824pif polar bodies 110a and 110b in a given unit of halogen (51). Further, in another exemplary embodiment, although the sub-tenk pattern in each unit of the pixel is a mirror image pattern of the center line C of the unit pixel, it is understood that it is not necessary to use a mirror pattern. Figure 10 is a schematic top plan view showing a layout pattern of a third metallization layer (L3) which may be formed over the aforementioned pixel sensor array (50). The foregoing third metallization layer (L3) is patterned to form a spacer liner (190) (aluminum or copper), the spacer liner having no electrical function, but acting to reduce the difference in overall steps in the substrate, The difference is formed by a conductive layer formed in the active pixel array (50) and in a peripheral logic region formed by one of the solid-state image sensor wafers including an analog digital converter, an ISP (image signal processor), and the like. A different number of conductive layers is caused. In the exemplary embodiment of FIG. 10, the third conductive pattern (190) may be symmetrically patterned and arranged in a manner on the active area A2 and the area adjacent to the A1 of the foregoing area A2. This approach provides for further light shielding of the photosensitive regions not covered by the first and second metallization layers, but avoids limiting the angle of incident light that can be captured. It is further understood that exemplary implementations in accordance with the present invention may be implemented For example, a CM〇s image sensing device having a pixel array with a pixel structure is implemented in a processor type based system of the type. For example, the figure u is an exemplary according to the current month. One embodiment having an image system for sensing apparatus of 2〇〇 ^) of a block order 咼 FIG. For example, the foregoing system (2〇〇) can be implemented in, for example, a computer system, a camera system, a scanner, a machine vision system, a vehicle navigation system, a videophone, a surveillance system, an autofocus system, and a star 33 1282621 18824pif body tracker. Systems, motion detection systems, image stabilization systems, mobile phones, and other processor-based systems. In essence, the aforementioned system (200) includes a CMOS imager device (210), one or more CPUs (Central Processing Unit) or microprocessor (220), one or more I/O devices (230), A flexible disk drive (240) (or other §'s card slot), ram (250), and a CD ROM drive (260), all of which are effectively coupled via a system bus (270) . The type of system components implemented will vary depending on the type of system. For example, peripheral devices such as a flexible disk drive (240) and a CD ROM drive (26) are typically used with, for example, a personal computer or a laptop. The CMOS imager device (210) includes a pixel array that can be constructed using any of the exemplary pixel structures described herein. The aforementioned cM〇s~image device (210) produces a round of image from the signal supplied from the aforementioned pixel array. The CMOS imager device (210) communicates with system components over a busbar (27A) or other communication link. In another exemplary embodiment 7, the processor (220), the CMOS imager device (21G), and the memory (250) may be integrally formed on a single IC wafer. Although the present invention has been described above by way of a preferred embodiment, it is not intended to limit the invention, and those skilled in the art can make some modifications and refinements without departing from the spirit of the invention. The protection of the present invention is defined by the scope of the patent application. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic circuit diagram showing a unit pixel of a conventional CMOS image sensing device having a 4-transistor (4_τ) active pixel sensor 34 1282621 18824pif frame. Figure 2 illustrates the concept of an exemplary unit pixel layout with a description of the prime factor. Figure 3 is a schematic side elevational view of a conventional unit cell having a light shielding layer. 4 is an unintentional circuit diagram of an active pixel sensor array φ having a shared pixel frame, to which the present invention can be applied. 5 to FIG. 10 illustrate a method for constructing a semiconductor CMOS active pixel image sensing device based on the pixel array circuit structure of FIG. 4. Before, the semiconductor CMOS main anime image sensing device has a unit of symmetric structure. It is used to provide uniform sensitivity. Figure 11 is a high level block diagram of a system having an image sensing device in accordance with an exemplary embodiment of the present invention. [Description of main component symbols] 10: Alizarin 20: unit halogen 21 · Photosensitive region 22: transistor region / PD region 23 · Peripheral region 3: substrate 31: isolation layer 32 · diffusion region 3 3 · diffusion region 35 1282621 18824pif 34: stacked structure/stacked layer 34a: light shield 34b: aperture 34c: tunnel area 40: halogen array 41: unit pixel 42a: photodiode 42b: photodiode

43a :轉移電晶體/轉移閘極 43b :轉移電晶體/轉移閘極 44 :重置電晶體 45 :放大器電晶體 46 :選擇電晶體 50 :晝素陣列 51 :單位晝素 51a ··子晝素單位 51b :子晝素單位 100 :半導體基板 102 :磊晶基板層/摻雜層 103 :隔離區域 108 : p+層 109 : η阱層 110 :光電二極體/光接收元件 110a:光電二級體/光電二極體區域/光接收元件 36 1282621 18824pif 110b :光電二級體/光電二極體區域/光接收元件 111 :摻雜區域/n+擴散區域 120 :介電層 131 :通道連接 132 :通道連接 133 :通道連接 134 :通道連接43a: transfer transistor / transfer gate 43b: transfer transistor / transfer gate 44: reset transistor 45: amplifier transistor 46: select transistor 50: halogen array 51: unit halogen 51a · · 昼素Unit 51b: subunit unit 100: semiconductor substrate 102: epitaxial substrate layer/doped layer 103: isolation region 108: p+ layer 109: n well layer 110: photodiode/light receiving element 110a: photodiode / Photodiode region / light receiving element 36 1282621 18824pif 110b : Photodiode / photodiode region / light receiving element 111 : Doped region / n + diffusion region 120 : Dielectric layer 131 : Channel connection 132 : Channel Connection 133: Channel Connection 134: Channel Connection

135 :通道連接/通道插塞 136 :通道插塞 137a :通道插塞/接觸插塞 137b :通道插塞/接觸插塞 139 :通道連接 141 : TG控制線 142 : TG控制線 143 : RG控制線 144 : RSG控制線 145a:金屬襯墊/襯墊元件 145b :金屬襯墊/襯墊元件 146a :互連線 146b :互連線 149 :金屬襯墊/接觸襯墊 150 :層間介電層 165 :通道連接/接觸插塞 167b :接觸插塞 37 1282621 18824pif 169 :接觸插塞 175 :行輸出線 176 :互連 179 :電源線 190 ··隔離襯墊/第三導電圖案 200 :系統 210 : CMOS影像器裝置135: Channel connection/channel plug 136: Channel plug 137a: Channel plug/contact plug 137b: Channel plug/contact plug 139: Channel connection 141: TG control line 142: TG control line 143: RG control line 144: RSG control line 145a: metal pad/pad component 145b: metal pad/pad component 146a: interconnect 146b: interconnect 149: metal pad/contact pad 150: interlayer dielectric layer 165: Channel connection/contact plug 167b: contact plug 37 1282621 18824pif 169: contact plug 175: row output line 176: interconnect 179: power line 190 · spacer spacer / third conductive pattern 200: system 210: CMOS image Device

220 :微處理器 230 : I/O 裝置 240 :軟性磁碟驅動器 250 : RAM/記憶體 260 : CD ROM驅動器 270 :系統匯流排 5B :線 5C :線 6B :線 6C :線 7B :線 7C ··線 8B ··線 8C :線 A1 :主動區域 A2 :主動區域 A3 :主動區域 38 1282621 18824pif A4 :主動區域 C :中心線 D1 ·虛没元件 D2 :延伸/突起部分 D3 :突起部分 D4 :突起部分 D5 ··突起虛設元件220: microprocessor 230: I/O device 240: flexible disk drive 250: RAM/memory 260: CD ROM drive 270: system bus 5B: line 5C: line 6B: line 6C: line 7B: line 7C Line 8B · Line 8C: Line A1: Active area A2: Active area A3: Active area 38 1282621 18824pif A4: Active area C: Center line D1 • Virtual element D2: Extension/protrusion part D3: Protrusion part D4: Protrusion Part D5 ··Protrusion dummy component

D6 :突起虛設元件 ] DX :放大器/源極隨耦放大器 FD :浮動擴散 h :隧道高度 L1 :第一程度金屬化圖案 OUT :輸出（行）線 PD :光電二極體D6 : Projection dummy component ] DX : Amplifier / source follower amplifier FD : Floating diffusion h : Tunnel height L1 : First degree metallization pattern OUT : Output (row) line PD : Photodiode

Px ··單位晝素之寬度Px ··Unit width

Px1 ··列方向内EPS區域的寬度Px1 ··· the width of the EPS area in the column direction

Py :單位晝素之長度 RG :重置閘電極 RSG :列選擇閘極 RX :重置電晶體 SEL :控制訊號線 SFG :源極隨耦閘電極 STI :淺溝槽隔離 SX :選擇電晶體 39 1282621 18824pif TG :轉移閘電極 TGI :轉移閘電極 TG2 :轉移閘電極 TX :轉移電晶體 VDD :源極電壓 W:孔徑寬度Py: unit length of the element RG: reset gate electrode RSG: column selection gate RX: reset transistor SEL: control signal line SFG: source with coupling gate electrode STI: shallow trench isolation SX: select transistor 39 1282621 18824pif TG : Transfer gate electrode TGI : Transfer gate electrode TG2 : Transfer gate electrode TX : Transfer transistor VDD : Source voltage W: Aperture width