1287433 九、發明說明： 【發明所屬之技術領域】 本發明係有關於半導體元件封裝構造，其特別有關於被 屏蔽保護不受電磁干擾的半導體元件封裝構造。 【先前技術】 典型的半導體元件封裝是將電路設置在電路基板上，例 如印刷電路板或陶瓷基板上。其電路的效能可能會因電磁 干擾（EMI)而受到不利的影響。電磁干擾（EMI)是來自於 電子系統電路内，由於無意間電磁場能量放射而耦合產生 之不希望得到的信號或雜訊。 來自一主動信號線路的信號能量與另一信號線路之間 的耦合作用，稱為串擾（crosstalk)。相對於遠端信號源產 生的電磁干擾，串擾是系統内部的電磁干擾。串擾的大小 與電路的平行傳輸長度及特徵阻抗的大小成正比，而與二 個電路之間的間隔成反比。 現在電子系統變得越來越小，且系統内電子構件的密度 越來越大。因此，電子元件的尺寸越來越小，而有利於韓 射出越來越高的頻率信號。同時，這些電子系統的操作頻 率頻率也在增加，更有利於高頻電磁波干擾的發生。電磁 干擾可來自遠離一敏感接收電路的電子系統；或者雜訊源 可來自同一系統内的一個電路（串擾或是近端信號源的輻 射耦合）。所有這些雜訊來源的加乘效應就是使得敏感系統 的效能下降或是產生錯誤。 1287433 【發明内容】 因此’本發明之主要目的在於提供被屏蔽保護不受電磁 干擾的半導體元件封裝構造。 為達上述以及其他目的，具有本發日㈣徵的半導體 封裝構造大致上包含··-半導體元件電性連接並固定於一 基板，-封裝體封膠包覆該半導體元件於該基板之上 面，及:電磁干擾屏蔽層形成於該封裝體上且大致 住該半導體元件。較佳地，該電磁干擾屏蔽層連接至一接 地電位，例如，一延伸於該基板上表面之接地線路。 、根據本發明之一面向，該電磁干擾屏蔽層可為一導電熱 ^性或熱固性樹脂製成之殼體。該導電熱塑性或熱固性樹 脂可包含一熱塑性或熱固性母材及複數個導電填料混合而 成。該殼體可藉由一黏著層固定於該封裝體，或利用強制 插入的方式使該殼體緊配合且接觸該封裝體。 根據本發明之另一面向，該電磁干擾屏蔽層係為與該封 衣體相互接觸之一導電塗層或一無電電鐘金屬層。 +根據本發明之另一面向，該電磁干擾屏蔽層可為一金屬 罩藉由一黏著層固定於該封裝體。 本發明另提供一種製造上述半導體元件封裝構造的方 法。該方法包含：（a)黏接數個半導體元件至一包含有複 數個基板之一基板條，該每一基板包含延伸於該基板上表 面之至少一接地線路；（b)電性連接該半導體元件至該基 板條；（c)封膠包覆該半導體元件於該基板條之上表面以 形成數個封裝體，其中該每一接地線路位於任兩相鄰封裝 U87433 及⑷設置—電磁干擾屏蔽層於該每-封裝體上 文许該電磁干擾屏蔽層連接至接地線路。 勢=明進—步提供上述铸體元件封裝構造的另—種 板侔包含:(a)電性連接該半導體元件至該基 形二模=包覆?半導體元件於該基板條之上表面以 ^ 棋塑座物，（c ) 一切成置猫广· 步驟將兮磁朔洋& \ 早顆（Singulation step) %將该杈塑產物分割成複數個 毁置—帝谥+振p p 领立的杈塑早兀，及（d) 私域干擾屏敝層於該每一辑幾單元上。 【實施方式】 為了對於本發明之上述及苴 有更完整的了解，以下舉本“=、優點及其他方面’ 相關的圖示’作詳細朗如後。二較佳的實施例’配合 件封所不為根據本發明—實施例之半導體元 第1 A圖揭示四個掇 圖中）設於一基板條11〇 1〇〇(僅有一個標示於第Μ 112(僅有一個標示於第 孩基板條110包含複數個基板 個基板112，鈇@ 圖中）。雖然第1 Δ圖僅繪示四 且與其它製造;^目|板條可包含純數量之基板， 〜衣罝相各，例如 包含至少-個半導體元件12::該每一個模塑產物100 圖中），例如含銀之環氧4、 、错由一導電膠層（未示於 圖中)，貼覆於-基-非導電膠(未示於 銲線130連接於基板丨1 牛蛉體凡件120藉由複數條 2上’該些銲線130係作為電輸入 1287433 輸出而連結至:第-組接點（未示於圖中），例如設於基板 112上表面之導電線路或接墊。此外，該半導體元件 町藉由複數個錫球（S〇lder Ball)連接至基板112。該些 錫球可利用任何已知的凸塊（Bumping)製程形成在半導& 元件120之正面（active surface)上。該基板I。之上表 面ϋ包含有一第二組接點（未示於圖中）用以電性連接^ 複數個表面連接技術(SMT)元件14〇上。為了電性連接至一 印刷電路板外側，該基板之下表玛豫有—第三組 承於圖中），、且其係電性連接於該第—組接點與第^组接 點’亚且，通常有複數個錫球（未示於圖中）設在該基板 112之第三組接點。該基板條11Q可由—玻璃纖維強化型 BT (biSIMleimide-triazine)樹脂或卯_4玻璃纖維強化 裂環氧樹脂之蕊層所製成，藉此增加該基板條11〇之機械 強度。 如第1A圖所示，該每一半導體元件12〇係被封勝包覆 於该基板條110之上表面以形成前述模塑產物1卯。在封 膠包覆後’每一半導體元件12M皮包覆在一封裝體 (package body)150内。因此’經由—切成單顆步驟可將 第1A圖所示之組件分開成為個別之半成品（請參照第⑶圖 所示）。 ^ 接著’將-導電熱塑性或熱複合物（eQ_und)製成 之殼體160設於該封裝體150上以有效地減少電磁波韓射 穿透過去的量，藉此使得半導體元件12〇接收到的總電磁 干擾劑量低於其所能容忍的程度。特別的是，該導電熱塑 1287433 性或熱固性樹脂可包含一熱塑性或熱固性母材及複數個導 電填料混合而成。適於本發明所使用之填料包含有不銹鋼 纖維、金屬粉末/粒子、鍍鎳碳纖維（NCG Fiber)、金屬鍍 層基板（非纖維）如鎳-石墨粉、鎳-t母粉、銀-玻璃珠。該 熱塑性母材可為熱塑性樹脂如聚丙烯（PP)、聚乙烯（PE)、 聚苯乙烯（PS)、苯乙烯（ABS)、聚醋酸乙烯酯（EVA)及聚氯 乙烯（PVC)。其中，根據本發明之殼體ι6〇可由前述之導電 複合物依據該封裝體150之輪廓預製成形而製得。該殼= 160可藉由一黏著層（未示於圖中）一其較佳為一導電黏 著層（其可利用浸潰或配送方式形成）一固定於該封裝體 150 〇 ^ 此外，該殼體160亦可直接利用緊配插入的方式固定於 該封I體150 ’使該殼體16〇可緊密的定位於該封裝體“ο 上。在此實施例中，該殼體16〇與該封裝體15〇相互接觸， 且該二者間並未設有任何黏著層。較佳地，該殼體16〇係 連接至接地電位。詳細言之，該殼體16〇可經由上述之導 電黏著層連接至一延伸於該基板112之上表面之接地線路 邊接地線路170藉由該基板112所設的專用垂直端 點，例如導孔（via) 180連接至一獨立接地部（未示於圖 中j該接地部可以分佈在基板112中任何適當的位置，並 且電性連接至一外部印刷電路（pc)板（未示於圖中）之 接地端，以提供接地電位。 用於本發明之基板條11〇可具有一綠漆（s〇lder st)(未示於圖中），且該綠漆相對於前述接點及該接 1287433 地線路170設有開口，使該接點及該接地線路170可裸露 於綠漆。 第2A至2C圖所示為根據本發明另一實施例之半導體元 件封裝構造之製捏。 在該半導體元件120及該表面接著元件140分別安裝至 該基板212,及進行一例行打線製程連接該半導體元件120 與該基板212之後，該半導體元件120及該表面接著元件 140係皆被封膠包覆於該基板條2JJ之上表面，以形成一 模塑產物200 (請參照第2A圖）。在封膠包覆後，該半導 體元件120及該表面接著元件140係皆被封膠包覆於一封 裝體250内。一般係利用一成形模排列封裝（MAP，mold array package)模塑製程來完成封膠包覆。接著，進行模 塑後固化及切成單顆步驟而獲得如第2B圖所示之獨立模 塑單元。在此切成單顆步驟，一樹脂膠鑛片（resin-bond saw blade)沿預設之切割線（例如，第2A圖之虛線所示） 將第2A圖所示之模塑產物200切割成為獨立的模塑單元。 然後，將一導電熱塑性或熱固性複合物（compound)製成 之殼體260設於該封裝體250以屏蔽電磁干擾（EMI)。詳 細言之，該殼體260係利用前述之導電複合物依據第2B圖 所示之模塑單元之輪廓預製成形而製得。請參照第2C圖所 示，該殼體260包含有一主體260a及自該主體260a延伸 之一側牆260b，該側牆260b底部與該基板212之下表面 平齊。該殼體260可藉由一黏著層（未示於圖中），其較佳 為一導電黏著層，固定於第2B圖所示之模塑單元。 1287433 此外’該殼體260亦可直接利用強制插入的方式安裝於 第2β圖所示之模塑單元上，使該殼體26〇可緊配合第 圖所不之模塑單元用以將其固定在位置上。在此實施例 中w 亥〃又體2 6 0與該模塑單元相互择觸，且其二者間並未 設有任何黏著層。 幸乂佳地，該殼體260係連接至接地電位。此外，該殼體 了連接至該基板212之一獨立接地部（未示於圖中）。~ 肩接地部可以分佈在基板212中佳饵適當的位置，並電性 連接至外部印刷電路（PC )板（未示於圖中）之接地端， 以提供接地電位。此外，該殼體260之側牆260b底部可直 接連接至一外部印刷電路（PC)板（未示於圖中）之接地 端0 第3A至3B圖所示為根據本發明另一實施例之半導體元 件封I構造之製桎。請參照第3A圖所示，一導電塗層 如—導電墨印層，直接形成於該模塑產物1〇〇及基板條11〇 之—部分用以屏蔽電磁干擾（EMI)。該模塑產物1〇〇及基 板條11〇係與第1A圖所示者相同，以下將不再說明其細 希。該導電塗層310可以利用與常見塗料相同的方式塗 佈’例如利用一喷搶（或刷子）或經由一浸潰步驟達成。 :導電塗層310包含有導電填料，例如炭黑（carbon black) 或^壬何導電金屬（如習用之銅、鎳、銀等或其組合）混合 非導電載體。然而，該導電塗層310亦以一無電電鐘金 屬層取代。 然後，進行一切成單顆步驟使第3A圖之組合分開為個 1287433 裝構造(請參照第3β圖所示)。較佳地， 係利用與第1Α至1C圖所述大致相同的方 式運接至接地奮^ 實施例之半導^第4Α至4C圖㈣為根據本發明另一 切割線（例如，=域構沿預狀 弟4A圖之虛線所示）切割第4A圖所示之 產物成為第4β圖所示獨立的模塑單元之後，將一 導电塗層410形成於第4Β圖所示之模塑單元以屏蔽電磁干 ，（ΕΜΙ)、該拉塑產物200及基板薇210係與第2Α圖所示 相同’以下將不再說 。該導 前述相同的方式塗佈，此外，該導電塗層利用 體他及自該主體她延伸之一側牆侧=主 410b底部與該基板212之下表面平齊。 該側牆 導電塗層410亦可以一無電電鑛金屬層取代該 導電塗層410係利用嫩至2C心致=地，該 連接至接地電位。 71 ^ A致相同的方式 第5A至5B圖所示為根據本發明另一每 件封裝構造之製植。請參照第5A圖所示只導體元 藉由黏著層52Q Μ於該些封裝體15〇用^2罩51〇 _。該模塑產物100及基板條11〇 干擾 相同，以下將不再說明其細節。該金屬罩5ι =所示者 電金屬（如習用之銅、錄、銀或其組合）所擎成由往何導 意的是，該黏著層520可以一雙面膠帶（由=面_值得注 之樹脂薄膜組成）取代。 x有點膠 之後，進行一切成單顆步驟使第5A圖之組合分門為、 10 1287433 別之半導體元件封裝構造（請參照第5B圖所示）。較佳地， 該金屬罩510係以如第1A至1C圖所述大致相同的方式連 接至接地電位。此外，該金屬罩510可藉由一層銲接介面 (例如金-錫焊料）、一導電性黏著層、或電阻銲接的方式 固定於該基板112之接地線路170。 第6A至6C圖所示為根據本發明另一實施例之半導體元 件封裝構造之製捏。在一鋸片沿預設之切割線（例如，第 6A圖之虛線所示）將第6A圖所兩各模塑產物200切割成 為如第6B圖所示獨立的模塑單元之後，將數個金屬罩 610(請參照第6C圖）藉由黏著層620固定於封裝體250以 屏蔽電磁干擾（EMI)。該模塑產物200及基板條210係與 第2A圖所示者相同，以下將不再說明其細節。該金屬罩 610大致與該金屬罩510相同，此外，該金屬罩610包含 有一主體610a及自該主體610a延伸之一侧牆610b，且該 側牆610b底部與該基板212之下表面平齊。較佳地，該金 屬罩610係以如第2A至2C圖所述大致相同的方式連接至 接地電位。 雖然本發明已以前述較佳實施例揭示，然其並非用以限 定本發明，任何熟習此技藝者，在不脫離本發明之精神和 範圍内，當可作各種之更動與修改，因此本發明之保護範 圍當視後附之申請專利範圍所界定者為準。 11 1287433 【圖式簡單說明】 第1 A至1C圖：其係根據本發明一實施例之半導體元件封 裝構造主要製造步驟之剖視圖。 第2A至2C圖：其係根據本發明另一實施例之半導體元件 封裝構造主要製造步驟之剖視圖。 第3A至3B圖：其係根據本發明另一實施例之半導體元件 封裝構造主要製造步驟之剖視圖。 第4A至4C圖：其係根據本發明另一實施例之半導體元件 封裝構造主要製造步驟之剖視圖。 第5A至5B圖：其係根據本發明另一實施例之半導體元件 封裝構造主要製造步驟之剖視圖。 第6A至6C圖：其係根據本發明另一實施例之半導體元件 封裝構造主要製造步驟之剖視圖。 主要元件符號說明 100半導體元件封裝構造 110基板條 112基板 120半導體元件 130銲線 140表面接著元件 150封裝體 160殼體 170接地線路 180 導孔（via) 200模塑產物 210基板條 212基板 250封裝體 260殼體 260a主體 300封裝構造 310塗層 410塗層 410a主體 410b側牆 510金屬罩 520黏著層 610金屬罩 610a主體 610b側牆 620黏著層 260b側牆 12BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device package structure, and more particularly to a semiconductor device package structure that is shielded from electromagnetic interference. [Prior Art] A typical semiconductor component package is to place a circuit on a circuit substrate such as a printed circuit board or a ceramic substrate. The performance of its circuit may be adversely affected by electromagnetic interference (EMI). Electromagnetic interference (EMI) is an undesired signal or noise from an electronic system circuit that is coupled due to unintentional electromagnetic field energy emissions. The coupling between the signal energy from one active signal line and the other signal line is called crosstalk. Crosstalk is electromagnetic interference within the system relative to electromagnetic interference generated by remote sources. The size of the crosstalk is proportional to the parallel transmission length of the circuit and the magnitude of the characteristic impedance, and inversely proportional to the spacing between the two circuits. Electronic systems are now getting smaller and smaller, and the density of electronic components within the system is growing. Therefore, the size of the electronic component is getting smaller and smaller, which is advantageous for the Korean to emit an increasingly higher frequency signal. At the same time, the operating frequency of these electronic systems is also increasing, which is more conducive to the occurrence of high-frequency electromagnetic interference. Electromagnetic interference can come from an electronic system that is remote from a sensitive receiving circuit; or the noise source can come from a circuit within the same system (crosstalk or radiative coupling of a near-end source). The additive effect of all these sources of noise is to make the performance of sensitive systems degraded or cause errors. 1287433 SUMMARY OF THE INVENTION Accordingly, it is a primary object of the present invention to provide a semiconductor device package structure that is shielded from electromagnetic interference. In order to achieve the above and other objects, the semiconductor package structure having the present invention has a semiconductor device electrically connected and fixed to a substrate, and a package encapsulating the semiconductor device on the substrate. And: an electromagnetic interference shielding layer is formed on the package and substantially surrounds the semiconductor element. Preferably, the EMI shielding layer is connected to a ground potential, for example, a ground line extending over the upper surface of the substrate. According to one aspect of the invention, the electromagnetic interference shielding layer can be a housing made of a conductive thermosetting or thermosetting resin. The electrically conductive thermoplastic or thermosetting resin may comprise a thermoplastic or thermosetting matrix and a plurality of electrically conductive fillers. The housing may be fixed to the package by an adhesive layer, or the housing may be tightly fitted and contacted by forced insertion. According to another aspect of the invention, the electromagnetic interference shielding layer is in contact with the package body with a conductive coating or a metal-free metal layer. + According to another aspect of the invention, the EMI shielding layer can be a metal cover secured to the package by an adhesive layer. The present invention further provides a method of manufacturing the above-described semiconductor device package structure. The method comprises: (a) bonding a plurality of semiconductor components to a substrate strip comprising a plurality of substrates, each substrate comprising at least one grounding line extending from an upper surface of the substrate; (b) electrically connecting the semiconductor And (c) sealing the semiconductor component on the upper surface of the substrate strip to form a plurality of packages, wherein each of the ground lines is disposed in any two adjacent packages U87433 and (4) - electromagnetic interference shielding The layer is adjacent to the per-package and the electromagnetic interference shield is connected to the ground line. The other layer of the above-described cast component package structure comprises: (a) electrically connecting the semiconductor component to the base die = cladding; the semiconductor component is on the upper surface of the substrate strip ^ Chess and plastic objects, (c) Everything is set to cat wide. Steps will be 兮 朔 & & & S S S S S S S S S S S S S S S S S S S S S S S S S S S S S 分割 分割 分割 — — — — — — — — The plastics are early, and (d) the private domain interference screen is layered on each of the units. [Embodiment] In order to have a more complete understanding of the above and the above description of the present invention, the following "=, advantages and other aspects of the related diagrams" are described in detail below. Two preferred embodiments 'fitted parts 1A of the semiconductor element according to the present invention - an embodiment of the present invention is shown in FIG. 1A), which is disposed on a substrate strip 11〇1〇〇 (only one is indicated on the first page 112 (only one is indicated on the first child) The substrate strip 110 includes a plurality of substrate substrates 112, 鈇@图). Although the first Δ diagram is only shown in four and other fabrications; the slats may include a pure number of substrates, Including at least one semiconductor component 12:: each of the molded products 100 in the figure), for example, a silver-containing epoxy 4, a layer of a conductive paste (not shown), and a substrate-based Conductive adhesive (not shown in the bonding wire 130 connected to the substrate 丨1 蛉 蛉 凡 120 120 120 120 120 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 ( ( ( ( ( ( ( ( In the figure, for example, a conductive line or a pad provided on the upper surface of the substrate 112. Further, the semiconductor element is conditioned. The plurality of solder balls are connected to the substrate 112. The solder balls may be formed on the active surface of the semiconductor material 120 by any known bumping process. Substrate I. The upper surface ϋ includes a second set of contacts (not shown) for electrically connecting a plurality of surface mount technology (SMT) elements 14 。 for electrical connection to a printed circuit board The underside of the substrate has a third group (in the figure), and is electrically connected to the first set of contacts and the second set of contacts, and usually has a plurality of solder balls ( Not shown in the figure) is disposed on the third set of contacts of the substrate 112. The substrate strip 11Q may be made of glass fiber reinforced BT (biSIMleimide-triazine) resin or 卯_4 glass fiber reinforced epoxy resin core layer. Manufactured thereby, the mechanical strength of the substrate strip 11 is increased. As shown in FIG. 1A, each of the semiconductor elements 12 is wrapped over the upper surface of the substrate strip 110 to form the aforementioned molded product 1卯 After the encapsulation is coated, each semiconductor component 12M is covered in a package body. Within 150. Therefore, the components shown in Figure 1A can be separated into individual semi-finished products by a single step (see Figure (3)). ^ Next - Conductive thermoplastic or thermal composite (eQ_und) The fabricated housing 160 is disposed on the package body 150 to effectively reduce the amount of electromagnetic wave penetration through the past, whereby the total electromagnetic interference dose received by the semiconductor component 12 is less than it can tolerate. The conductive thermoplastic 1287433 or thermosetting resin may comprise a thermoplastic or thermosetting base material and a plurality of conductive fillers. Fillers suitable for use in the present invention comprise stainless steel fibers, metal powders/particles, nickel-plated carbon fibers (NCG Fiber), metal-coated substrates (non-fibers) such as nickel-graphite powder, nickel-t mother powder, silver-glass beads. The thermoplastic base material may be a thermoplastic resin such as polypropylene (PP), polyethylene (PE), polystyrene (PS), styrene (ABS), polyvinyl acetate (EVA), and polyvinyl chloride (PVC). Wherein, the casing ι6〇 according to the present invention can be produced by pre-forming the conductive composite according to the outline of the package 150. The shell = 160 may be fixed to the package body 150 by an adhesive layer (not shown), preferably a conductive adhesive layer (which may be formed by dipping or dispensing). The body 160 can also be directly fixed to the sealing body 150' by means of tight fitting insertion so that the housing 16 can be tightly positioned on the package "o. In this embodiment, the housing 16" The package body 15 is in contact with each other, and there is no adhesive layer between them. Preferably, the case 16 is connected to a ground potential. In detail, the case 16 can be electrically conductively adhered via the above. The layer is connected to a ground line side ground line 170 extending on the upper surface of the substrate 112. The dedicated vertical end point of the substrate 112, such as a via 180, is connected to a separate ground portion (not shown). The ground portion may be distributed at any suitable position in the substrate 112 and electrically connected to a ground end of an external printed circuit (PCB) board (not shown) to provide a ground potential. The substrate strip 11 can have a green lacquer (not shown) And the green paint is provided with an opening relative to the contact and the line 17073 of the connection 1287433, so that the contact and the ground line 170 can be exposed to the green paint. Figures 2A to 2C show another according to the present invention. In the semiconductor device package structure of the embodiment, the semiconductor device 120 and the surface contact device 140 are respectively mounted on the substrate 212, and after a row bonding process is performed to connect the semiconductor device 120 and the substrate 212, the semiconductor The component 120 and the surface subsequent component 140 are both encapsulated on the upper surface of the substrate strip 2JJ to form a molded product 200 (please refer to FIG. 2A). After the encapsulation is coated, the semiconductor component 120 And the surface adhesive element 140 is encapsulated in a package body 250. The molding process is generally performed by a molding process (MAP) molding process. Then, molding is performed. Post-cure and cut into individual steps to obtain a separate molding unit as shown in Figure 2B. Here, a single step is performed, a resin-bond saw blade along a predetermined cutting line (eg , the dotted line of Figure 2A The molded product 200 shown in Fig. 2A is cut into individual molding units. Then, a housing 260 made of a conductive thermoplastic or thermosetting compound is placed in the package 250 to shield the electromagnetic Interference (EMI). In detail, the housing 260 is formed by pre-forming the conductive composite according to the contour of the molding unit shown in Fig. 2B. Referring to Figure 2C, the housing 260 A body 260a and a side wall 260b extending from the body 260a are included, and the bottom of the side wall 260b is flush with the lower surface of the substrate 212. The housing 260 can be attached to the molding unit shown in Fig. 2B by an adhesive layer (not shown) which is preferably a conductive adhesive layer. 1287433 In addition, the housing 260 can also be directly mounted on the molding unit shown in FIG. 2 by means of forced insertion, so that the housing 26 can be tightly fitted to the molding unit of the figure to fix it. In position. In this embodiment, the molding unit is in contact with the molding unit, and there is no adhesive layer therebetween. Fortunately, the housing 260 is connected to a ground potential. Additionally, the housing is coupled to a separate ground portion of the substrate 212 (not shown). The shoulder ground portion may be distributed in a suitable position on the substrate 212 and electrically connected to the ground of an external printed circuit (PC) board (not shown) to provide a ground potential. In addition, the bottom of the side wall 260b of the housing 260 can be directly connected to the ground end of an external printed circuit (PC) board (not shown). FIGS. 3A to 3B are diagrams showing another embodiment of the present invention. The fabrication of the semiconductor device package I structure. Referring to Fig. 3A, a conductive coating such as a conductive ink stamp is formed directly on the molded product 1 and the substrate strip 11 to shield electromagnetic interference (EMI). The molded product 1〇〇 and the substrate strip 11 are the same as those shown in Fig. 1A, and the details thereof will not be described below. The conductive coating 310 can be applied in the same manner as conventional coatings, e.g., using a spray (or brush) or via an impregnation step. The conductive coating 310 comprises a conductive filler such as carbon black or a conductive metal such as conventional copper, nickel, silver or the like or a combination thereof. However, the conductive coating 310 is also replaced by a metal-free metal layer. Then, proceed to a single step to separate the combination of Figure 3A into a 1287433 assembly (see Figure 3β). Preferably, the fourth embodiment to the fourth embodiment of the present invention is carried out in substantially the same manner as described in FIGS. 1 to 1C. FIG. 4 is a fourth cutting line according to the present invention (for example, = domain structure). After cutting the product shown in FIG. 4A into a separate molding unit shown in FIG. 4A along the dashed line of the pre-form 4A, a conductive coating 410 is formed in the molding unit shown in FIG. In order to shield the electromagnetic dry, (ΕΜΙ), the drawn plastic product 200 and the substrate Wei 210 are the same as those shown in the second drawing, 'will not be described below. The coating is applied in the same manner as described above. Further, the conductive coating utilizes the body and one side wall side of the main body extending from the main body = the bottom of the main 410b is flush with the lower surface of the substrate 212. The sidewall conductive coating 410 can also be replaced by an electroless mineral metal layer. The conductive coating 410 is applied to the ground potential using a tender to 2C core. 71 ^ A is the same way. Figures 5A to 5B show the implantation of another package structure according to the present invention. Referring to FIG. 5A, only the conductor elements are attached to the package body 15 by the adhesive layer 52Q, and the cover 51 〇 _ is used. The molded product 100 and the substrate strip 11 are the same, and the details thereof will not be described below. The metal cover 5 i = the metal (such as conventional copper, recording, silver or a combination thereof) shown in the guide is that the adhesive layer 520 can be a double-sided tape (by = face _ worth noting Replacement of resin film composition). After a bit of glue, do everything in a single step to make the combination of Figure 5A separate, 10 1287433 other semiconductor component package structure (please refer to Figure 5B). Preferably, the metal cover 510 is connected to the ground potential in substantially the same manner as described in Figures 1A through 1C. In addition, the metal cover 510 can be secured to the ground line 170 of the substrate 112 by a solder interface (e.g., gold-tin solder), a conductive adhesive layer, or resistance soldering. 6A to 6C are views showing the pinching of a semiconductor element package structure according to another embodiment of the present invention. After the saw blade is cut along the predetermined cutting line (for example, as indicated by the dashed line in FIG. 6A), the two molded products 200 of FIG. 6A are cut into separate molding units as shown in FIG. 6B, and then several The metal cover 610 (please refer to FIG. 6C) is fixed to the package body 250 by an adhesive layer 620 to shield electromagnetic interference (EMI). The molded product 200 and the substrate strip 210 are the same as those shown in Fig. 2A, and the details thereof will not be described below. The metal cover 610 is substantially the same as the metal cover 510. Further, the metal cover 610 includes a main body 610a and a side wall 610b extending from the main body 610a, and the bottom of the side wall 610b is flush with the lower surface of the substrate 212. Preferably, the metal cover 610 is connected to the ground potential in substantially the same manner as described in Figures 2A through 2C. While the present invention has been disclosed in its preferred embodiments, the present invention is not intended to limit the invention, and the invention may be variously modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application. 11 1287433 BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A to 1C are cross-sectional views showing main manufacturing steps of a semiconductor element package structure according to an embodiment of the present invention. 2A to 2C are cross-sectional views showing main manufacturing steps of a semiconductor element package structure according to another embodiment of the present invention. 3A to 3B are cross-sectional views showing main manufacturing steps of a semiconductor element package structure according to another embodiment of the present invention. 4A to 4C are cross-sectional views showing main manufacturing steps of a semiconductor element package structure according to another embodiment of the present invention. 5A to 5B are cross-sectional views showing main manufacturing steps of a semiconductor element package structure according to another embodiment of the present invention. 6A to 6C are cross-sectional views showing main manufacturing steps of a semiconductor element package structure according to another embodiment of the present invention. Main component symbol description 100 semiconductor component package structure 110 substrate strip 112 substrate 120 semiconductor component 130 bonding wire 140 surface subsequent component 150 package 160 housing 170 grounding line 180 via 200 molding product 210 substrate strip 212 substrate 250 package Body 260 housing 260a body 300 package construction 310 coating 410 coating 410a body 410b side wall 510 metal cover 520 adhesive layer 610 metal cover 610a body 610b side wall 620 adhesive layer 260b side wall 12