TWI313867B - Soft programming non-volatile memory utilizing individual verification and additional soft programming of subsets of memory cells - Google Patents

A set of non-volatile storage elements is divided into subsets for soft programming in order to more fully soft-program slower soft programming elements. The entire set of elements is soft-programmed until verified as soft programmed (or until a first subset of elements is verified as soft programmed while excluding a second subset from verification). After the set is verified as soft programmed, a first subset of elements is inhibited from further soft programming while additional soft programming is carried out on a second subset of elements. The second subset can include slower soft programming elements. The second subset can then undergo soft programming verification while excluding the first subset from verification. Soft programming and verifying for the second subset can continue until it is verified as soft programmed. Different step sizes can be used for increasing the size of the soft programming signal, depending on which subset is being soft programmed and verified.

13111552號專利申請案 , 中文說明書替換頁(98年4月） 九、發明說明： 優先權主張Patent Application No. 13111552, Replacement Page of Chinese Manual (April 1998) IX. Invention Description: Priority Claim

本專利申請案主張於2005年3月31日Hemink等人提出之 美國臨時專利申請案第60/667,043號標題為 「NON-VOLATILE MEMORY ERASE OPERATIONS WITH OVER-ERASE PROTECTION」之優先權，該申請案以引用 方式整份併入本文。 相關申請案交互參考 本專利申請與下列申請案參考交互參照，並且均以引用 方式整份併入本文：The present application claims priority to U.S. Provisional Patent Application Serial No. 60/667,043, entitled "NON-VOLATILE MEMORY ERASE OPERATIONS WITH OVER-ERASE PROTECTION", filed on March 31, 2005, which is incorporated herein by reference. The citations are incorporated herein in their entirety. CROSS-REFERENCE TO RELATED APPLICATIONS This application is hereby incorporated by reference in its entirety in its entirety in the the the the the the the the the the the

Hemink等人同時提出之美國專利申請案第11/296,05 5號 (現為美國專利第7,403,424號）（代理人檔案號碼第 SAND-01066US0 號）標題為「ERASING NON-VOLATILE MEMORY USING INDIVIDUAL VERIFICATION AND ADDITIONAL ERASING OF SUBSETS OF MEMORY CELLS」；U.S. Patent Application Serial No. 11/296,05, issued to Hemink et al. (now U.S. Patent No. 7,403,424) (Attorney Docket No. SAND-01066US0) entitled "ERASING NON-VOLATILE MEMORY USING INDIVIDUAL VERIFICATION AND ADDITIONAL ERASING OF SUBSETS OF MEMORY CELLS";

Hemink等人同時提出之美國專利申請案第11/296,028號 (現為美國專利第7,400,537號）（代理人檔案號碼第 SAND-01066US1 號）標題為「SYSTEMS FOR ERASING NON-VOLATILE MEMORY USING INDIVIDUAL VERIFICATION AND ADDITIONAL ERASING OF SUBSETS OF MEMORY CELLS」；U.S. Patent Application Serial No. 11/296,028 (now U.S. Patent No. 7,400,537) (Attorney Docket No. SAND-01066US1) entitled "SYSTEMS FOR ERASING NON-VOLATILE MEMORY USING INDIVIDUAL VERIFICATION AND ADDITIONAL" ERASING OF SUBSETS OF MEMORY CELLS";

Hemink等人同時提出之美國專利申請案第11/296,071號 (現為美國專利第7,408,804號專利）（代理人檔案號碼第 SAND-01066US3 號）標題為「SYSTEMS FOR SOFT 109918-980409.doc 货年4月）日修正替換買 •131 1552號專利申請案 , 中文說明書替換頁(98年4月）US Patent Application No. 11/296,071 (now U.S. Patent No. 7,408,804) (Attorney Docket No. SAND-01066US3) entitled "SYSTEMS FOR SOFT 109918-980409.doc" Month) Correction of the replacement of the patent application No. 131 1552, Chinese manual replacement page (April 1998)

PROGRAMMING NON-VOLATILE MEMORY UTILIZING INDIVIDUAL VERIFICATION AND ADDITIONAL SOFT PROGRAMMING OF SUBSETS OF MEMORY CELLS」；PROGRAMMING NON-VOLATILE MEMORY UTILIZING INDIVIDUAL VERIFICATION AND ADDITIONAL SOFT PROGRAMMING OF SUBSETS OF MEMORY CELLS";

Masaaki Higashitani同時提出之美國專利申請案第 1 1/295,755號（現為美國專利第7,430，138號）（代理人檔案號 碼第 SAND-01054US0 號）標題為「 ERASING NON-VOLATILE MEMORY UTILIZING CHANGING WORD LINE CONDITIONS TO COMPENSATE FOR SLOWER ERASING MEMORY CELLS」；以及US Patent Application No. 1 1/295,755 (now U.S. Patent No. 7,430,138) (Attorney Docket No. SAND-01054US0) titled "ERASING NON-VOLATILE MEMORY UTILIZING CHANGING WORD LINE CONDITIONS" by Masaaki Higashitani TO COMPENSATE FOR SLOWER ERASING MEMORY CELLS"; and

Masaaki Higashitani同時提出之美國專利申請案第 11/296,03 2號（現為美國專利第7,403,428號）（代理人檔案號 碼第 SAND-01054US2 號）標題為「SYSTEMS FOR ERASING NON-VOLATILE MEMORY UTILIZING CHANGING WORD LINE CONDITIONS TO COMPENSATE FOR SLOWER ERASING MEMORY CELLS」。 【發明所屬之技術領域】 本發明係關於用於擦除非揮發性記憶體裝置之半導體技 術。 【先前技術】 半導體記憶體裝置已變成愈來愈普遍運用在各種電子裝 置中。舉例而言，行動電話、數位攝影機、個人數位助理、 行動運算裝置、非行動運算裝置及其他裝置中皆使用非揮 發性半導體記憶體。電氣可擦除式可程式規劃唯讀記憶體 (Electrical Erasable Programmable Read Only Memory ； EEPROM)(包括快閃EEPROM)及電氣可程式規劃唯讀記憶 體（Electronically Programmable Read Only Memory ； 109918-980409.doc 1313867 EPROM)係最普遍的非揮發性半導體記憶體。 )夬閃圮憶體系統之一項實例使用NAND結構，其包括夾 在兩個選擇閘極之間串聯排列的多個電晶體，的該等 電晶體與該等選擇閑極被稱為一NAND串。圖〗繪示一 NAND串的俯視圖。圖2繪示其同等電路。圖所示之該 NAND串包括夾在一第一選擇閘極12〇與一第二選擇開極 122之間串聯的四個電晶體1〇〇、1〇2、1〇4和1〇6。選擇閘極 φ n〇連接該NAND串至位元線126。選擇閘極122連接該 NAND串至源極線128。藉由將適當電壓經由選擇線sgd施 加至控制閘極120CG來控制選擇閘極12〇。藉由將適當電壓 經由選擇線SGS施加至控制閘極122CG來控制選擇閘極 122。電晶體1〇〇、102、104和1〇6各包括一控制閘極及一浮 動閘極，形成一記憶體單元的閘極元件。舉例而言，電晶 體100具有控制閘極100CG及浮動閘極100FG。電晶體1〇2 包括控制閘極102CG及浮動閘極102FG。電晶體1〇4包括控 φ 制閘極1〇4CG及浮動閘極W4FG。電晶體106包括控制閘極 106CG及浮動閘極106FG。控制閘極100CG係連接至字線 WL3，控制閘極丨02CG係連接至字線WL2，控制閘極丨〇4C(} 係連接至字線WL1及，控制閘極106CG係連接至字線WL〇。 请注思’雖然圖1及2緣示出在該NAND串中有四個記憶體 單元，但是使用四個記憶體單元僅係作為一項實例予以提 供。一 NAND串可具有少於四個記憶體單元或多於四個記憶 體單元。舉例而言，一些NAND串將包括8個記憶體單元、 1 6個記憶體單元、32個記憶體單元等等。本文中之論述未 109918.doc 1313867 限定一 NAND串中的任何特定記憶體單元數量。 一種使用NAND結構之快閃記憶體系統的典型架構將包 括數個NAND串。舉例而言，圖3繪示一具有更多NAND串 之記憶體陣列的三個NAND串202、204和206。圖3所示之該 等NAND串中的每一NAND串包括兩個選擇電晶體（或選擇 閘極）及四個記憶體單元。舉例而言，NAND串202包括選擇 電晶體220和230及記憶體單元222、224、226和228。NAND 串204包括選擇電晶體240和250及記憶體單元242、244、246 和248。每串係藉由一個選擇閘極（例如，選擇閘極230和選 擇閘極250)而連接至源極線。一選擇線SGS係用於控制源極 側選擇閘極。各種NAND串係藉由選擇閘極220、240 (受控 於選擇線SGD)等等而連接至各自位元線。在其他具體實施 例中，該等選擇線未必需要成為共有線。字線WL3被連接 至記憶體單元222及記憶體單元242的控制閘極。字線WL2 被連接至記憶體單元224及記憶體單元244的控制閘極。字 線WL1被連接至記憶體單元226及記憶體單元246的控制閘 極。字線WL0被連接至記憶體單元228及記憶體單元248的 控制閘極。如所示，一位元線及各自NAND串構成記憶單元 陣列之一行。該等字線（WL1、WL2、WL3和WL4)構成陣列 之列。每一字線連接該列中每一記憶體單元的控制閘極。 舉例而言，字線WL2被連接至記憶體單元224、244及252的 控制閘極。 每一記憶體單元可儲存資料（類比或數位）。當儲存一位 元之數位資料時，記憶體單元之可能的臨限電壓範圍被劃 109918.doc 1313867 刀成經指派為邏輯資US Patent Application No. 11/296,03 2 (now U.S. Patent No. 7,403,428) (Attorney Docket No. SAND-01054US2) titled "SYSTEMS FOR ERASING NON-VOLATILE MEMORY UTILIZING CHANGING WORD" by Masaaki Higashitani LINE CONDITIONS TO COMPENSATE FOR SLOWER ERASING MEMORY CELLS". TECHNICAL FIELD OF THE INVENTION The present invention relates to semiconductor technology for erasing non-volatile memory devices. [Prior Art] Semiconductor memory devices have become more and more widely used in various electronic devices. For example, non-volatile semiconductor memory is used in mobile phones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices, and other devices. Electrical Erasable Programmable Read Only Memory (EEPROM) (including flash EEPROM) and Electrically Programmable Read Only Memory (109918-980409.doc 1313867) EPROM) is the most common non-volatile semiconductor memory. An example of a flash memory system uses a NAND structure including a plurality of transistors sandwiched between two select gates, the transistors and the selected idle electrodes being referred to as a NAND string. Figure 〖 shows a top view of a NAND string. Figure 2 shows its equivalent circuit. The NAND string shown in the figure includes four transistors 1 〇〇, 1 〇 2, 1 〇 4, and 1 〇 6 sandwiched between a first selection gate 12 〇 and a second selection opening 122. The gate φ n〇 is selected to connect the NAND string to the bit line 126. Select gate 122 connects the NAND string to source line 128. The selection gate 12 is controlled by applying an appropriate voltage to the control gate 120CG via the selection line sgd. The selection gate 122 is controlled by applying an appropriate voltage to the control gate 122CG via the selection line SGS. The transistors 1 〇〇, 102, 104, and 〇6 each include a control gate and a floating gate to form a gate element of a memory cell. For example, the transistor 100 has a control gate 100CG and a floating gate 100FG. The transistor 1〇2 includes a control gate 102CG and a floating gate 102FG. The transistor 1〇4 includes a gate φ1CG4CG and a floating gate W4FG. The transistor 106 includes a control gate 106CG and a floating gate 106FG. The control gate 100CG is connected to the word line WL3, the control gate 丨02CG is connected to the word line WL2, the control gate 丨〇4C(} is connected to the word line WL1 and the control gate 106CG is connected to the word line WL〇. Please note that although Figures 1 and 2 show four memory cells in the NAND string, the use of four memory cells is provided as an example only. A NAND string can have less than four Memory cells or more than four memory cells. For example, some NAND strings will include 8 memory cells, 16 memory cells, 32 memory cells, etc. The discussion in this article is not 109918.doc 1313867 defines the number of any particular memory cell in a NAND string. A typical architecture for a flash memory system using a NAND structure will include several NAND strings. For example, Figure 3 depicts a memory with more NAND strings. Three NAND strings 202, 204, and 206 of the body array. Each of the NAND strings shown in Figure 3 includes two select transistors (or select gates) and four memory cells. NAND string 202 includes select transistors 220 and 230 and memory Body units 222, 224, 226, and 228. NAND string 204 includes select transistors 240 and 250 and memory cells 242, 244, 246, and 248. Each string is connected by a select gate (eg, select gate 230 and select The gate 250) is connected to the source line. A select line SGS is used to control the source side select gate. The various NAND strings are connected by selecting the gates 220, 240 (controlled by the select line SGD) and the like. To other bit lines, in other embodiments, the select lines do not necessarily need to be shared lines. Word line WL3 is connected to memory cell 222 and control gate of memory unit 242. Word line WL2 is connected to memory The control unit of the body unit 224 and the memory unit 244. The word line WL1 is connected to the control unit of the memory unit 226 and the memory unit 246. The control of the word line WL0 is connected to the memory unit 228 and the memory unit 248. Gate. As shown, one bit line and its respective NAND string form one row of memory cell arrays. The word lines (WL1, WL2, WL3, and WL4) form a column of arrays. Each word line connects each of the columns. Control gate of the memory unit. For example, word line WL2 Connected to the control gates of memory cells 224, 244, and 252. Each memory cell can store data (analog or digital). When storing digital data for one bit, the possible threshold voltage range of the memory cell Was assigned 109918.doc 1313867

“ ㈣閃記憶體之-項l二兩段範圍。在NAND ^ p艮電壓為負且被定義：：：體早凡被擦除之後的臨 為正且祐〜萬 、1」。程式化操作之後的臨限電壓 '' 疋義為「〇」0當臨限電壓為負且嘗1施力〇袂$批 制閉極來進行讀取時’負且“施加0伏至控 A « ^ η 、 體早7將開通以指示出正在儲 「 氐未開啟，其指示出儲存邏輯 ·/_」5己憶體單元亦可以儲存多級位資訊，舉例而言，多 資料。假使儲存多級位諸，則按資料級位之數 :來^可能的臨限„範圍。舉例而言’如果儲存四級 「之貝：’則有四個臨限電魔範圍被指派為資料值Γ11」、 10」、01」及「00」。在]^^^型記憶體之一項實例中， 擦除操作之後的臨限電塵為負且被定義為「η」。三個不同 正臨限電塵係用於狀態「1〇」、「〇1」及「〇〇」。 以下美國專利案/專利中請案中提供NAND型快閃記憶體 籲及其運作的相關實例，所有該等案均以引用方式併入本文 中.吳國專利案第5,570,3 15號；美國專利案第5,774,397號； 吴國專利案第6,〇46,935號；美國專利案第M56,528號及美 國專利申請案第09/893,277 (公告第仍20〇3/〇〇〇2348號）。 當程式化-快閃記憶體單元時，一程式化電麼被:加至 控制閘極（經由一所選字線）且位元線被接地。來自p井的電 子被注入至浮動閘極。當電子累積於浮動閘極中時，浮動 閘極變成荷載負電荷狀態，並且該記憶體單元的電壓上 升。該記憶體單元的浮動閘極電荷及臨限電壓可指示出一 W99lS.doc -10- 1313867 相對應於所儲存之資料的特定狀態。 為了擦除NAND型快閃記憶體的記憶體單元，使電子從每 一圮憶體單元的浮動閘極轉移至井區及基板。典型地，一 或多個高電壓（例如，約16伏至20伏）擦除脈衝被施加至井 區，:使電子離開每一記憶體單元的浮動閑極而吸引至井 區。每-記憶體單元的字線被接地或被供應⑽，以產生一 跨随穿氧化物區的高電位，以吸引電子。如果在施加__擦 除電I脈衝後未擦除_ NAND串的每—記憶體單元，則可增 大脈衝大小且重新施加至該NAND#，直到擦除每—記揀體 單元。介於脈衝之間所增大的擦除電壓增量典型稱為擦除 電壓步進大小（step size)。 ，用先前技術的典型擦除操作可導致—财肋串中記憶 體早兀之間的捧险@、玄 ^ 速羊不同。一些記憶體單元到達已擦除 ^態之㈣臨限電壓位準的速率可快於或慢於其他記憶體 早、可導致過擦除較快速擦除之記憶體單元，肩因夺 彼等較快速捧除之吁掊挪U货' ” °己隐體早兀繼續承受到為了充分捧除令 NAND串的較緩慢記 _ 刀^牙…哀 心體早TL所施加的擦除電壓。 同的擦除速率可導致縮短一 — 。己隐體單7〇或NAND串的猫搭 壽命。典型的擦除接作介^ ^ 申的循％ ’…、亦可導致一 NAND串中記憶體單元 間的臨限電壓相里。^ 早兀之 後，NAND串的—:，在施加-或多個擦除電壓脈衝之 、2多個記憶體單元之臨限電壓可不同於 NAND串或裝置的其 — 门於忒 °己隐組早兀之臨限電壓。為了克朋屮 效應，已使用一種通當 見服此 除後調整—或多 议彳7用以在擦 隐體早元的臨限電壓。軟性程式化包 I09918.doc 1313867 括施加一相對低程式化電壓（低於實際程式化所使用的電 壓）至一或多個記憶體單元。軟性程式化典型包括以一連串 脈衝來施加-程式化電壓，其中在每一施加程式化電壓脈 衝之間，以一步進大小為單位來增大該等脈衝。軟性程式 化使記憶體單元的臨限電壓上升，以使所擦除之記憶體單 元群（population)的臨限電壓分佈變窄及/或上升◊但是，軟 性程式化可增加程式化時間及擦除時間。 此外’傳統軟性程式化可遭受到不同記憶體單元之間屬 性相異的-些相同效應。該等記憶體單元可能擦除缓慢， 亦可能軟性程式化緩慢。在軟性程式化結束時’彼等較缓 軟性程式化之記_體置；& 4 厲體早兀的擦除臨限電壓可低於該 NAND串之記憶體單元的檫除臨限電壓。 【發明内容】 本文描述之技術係關於用於以提供更一致擦除臨限電壓 之方式來擦除及/或軟性程式 不八化非揮發性記憶體裝置之技 術。根據一具體實施例，提供— „ ^ 奴仏種系統，其考量在擦除及 軟性程式化操作期間，一或多 w °己隐體早兀的個別特性、 “除運作模式及軟性程式化運作模式。 —非揮發性儲存元件隼人 芒+ ;隹 件木口（例如’—NAND串）可被劃分成 右干子集，以進行槔除 、w ^ ^ 免過擦除較快速擦除的儲 存几件。整個該非揮發性儲存 > ☆ 件集合破擦除，直到續非 揮發性儲存元件集合之—第 亥非 噔為已隸^ 非揮兔性儲存元件子集被驗 口且马已被擦除。該第一非姑π t, 弟非揮叙性儲存元件子隼 速擦除之非揮發性儲存开杜a 卞市了包括較快 則儲細牛。驗證該第一非揮發性儲存元 1099l8.doc 1313867 件子集包括排除驗證_第_ 一 弟一非揮發性儲存元件子集。該第 一非揮發性儲存元件双 集被驗近為已被擦除後，禁止擦除 6亥第一非揮發性儲存 趣心奸七 集’同時進一步擦除該第二非 揮發性儲存元件子集。告 ’、w 0"第—非揮發性儲存元件子集被 驗。^為已被擦除時，續非播八ω 丄 X D亥非揮备性儲存元件集合被驗證為已 扭·“人 禪“生儲存兀件集合是否已被擦除可包 括.排除驗證該第一非揮發性 ^ ^ 卜料_存凡件子集，或-起驗證 =—_發_存元件子集及該第二非揮發性儲存元件 子集。依據正被擦除及驗證的非揮發性館存元件子集，可 使用不同步進大小，以 八 館存元件集合。 心丈率且精確地擦除該非揮發性 :非揮發性儲存元件集合可被劃分成若干子集，以進行 式化，以便更徹底軟性程式化較緩慢軟性程式化之 ^生健存兀件。整個該非揮發性儲存元件集合被軟性 直到驗證為已被軟性程式化（或直到—第 性儲存元件子隼祐驗执 早x 木被驗5且為已被軟性程式化，同時排除驗證 人弟—非揮發性儲存元件子集）。在該非揮發性儲存元件集 :被驗證為已被軟性程式化之後，禁止進一步軟性程式化 :第:非揮發性儲存元件子集，同時對一第二非揮發性儲 ==子集執行額外軟性程式化。該第二非揮發性健存元 “集了包括較緩慢軟性程式化之非揮發性儲存元件。接 著，該第二非揮發性儲存 ^ 兀仟于集可歷經軟性程式化驗 科排除驗證該第一非揮發性儲存元件子集。可繼續 人’生程式化及驗證該第二非揮發性儲存元件子集，直到該 '099l8.doc 1313867 第二非揮發性料元件子集被驗證為已被軟性程式化。依 據正被軟性程式化及驗證的非揮發性儲存元件子集，可使 ^不同步進大小來遞增軟性程式化訊號之大小。在一具體 只施例中，根據本文描述之技術的軟性程式化係繼根據本 文描述之技術的擦除後予以執行。"(4) The range of the flash memory - item l two and two paragraphs. The voltage in the NAND ^ p艮 is negative and is defined as follows: :: The body is immediately after the erase is positive and uke ~ 10,000, 1". The threshold voltage after the stylized operation '' 疋 为 为 当 当 当 当 当 当 当 当 当 当 当 当 当 当 当 临 临 临 临 临 临 临 临 临 临 临 临 临 临 临 临 临 临 临 临 临 临 临 临 临 临« ^ η, 体早7 will be opened to indicate that it is storing " 氐 is not open, it indicates storage logic · / _" 5 memory unit can also store multi-level information, for example, multiple data. If you store multiple levels, then by the number of data levels: to the possible threshold „ range. For example, if you store four levels of “Bei:: then four thresholds of electric magic are assigned as data. Values are 11", 10", 01" and "00". In an example of the ^^^ type memory, the threshold dust after the erase operation is negative and is defined as "η". Three different positive-threshold electric dusts are used for the status "1", "〇1" and "〇〇". The following U.S. Patent/Patents provide examples of NAND-type flash memory calls and their operation, all of which are incorporated herein by reference. Wu Guo Patent No. 5,570,3 15; Patent No. 5,774,397; Wu Guo Patent No. 6, No. 46,935; U.S. Patent No. M56,528, and U.S. Patent Application Serial No. 09/893,277, the entire disclosure of which is hereby incorporated by reference. When stylized-flash memory cells, a stylized power is applied to the control gate (via a selected word line) and the bit line is grounded. Electrons from the p-well are injected into the floating gate. When electrons accumulate in the floating gate, the floating gate becomes a load negative state, and the voltage of the memory cell rises. The floating gate charge and threshold voltage of the memory cell can indicate that a W99lS.doc -10- 1313867 corresponds to a particular state of the stored data. In order to erase the memory cells of the NAND type flash memory, electrons are transferred from the floating gate of each memory cell to the well region and the substrate. Typically, one or more high voltage (e. g., about 16 volts to 20 volts) erase pulses are applied to the well region: electrons are drawn away from the floating idle of each memory cell to the well region. The word line of each memory cell is grounded or supplied (10) to create a high potential across the oxide region to attract electrons. If each memory cell of the _ NAND string is not erased after the __ erased I pulse is applied, the pulse size can be increased and reapplied to the NAND# until the per-sort body unit is erased. The increase in erase voltage between pulses is typically referred to as the erase voltage step size. The typical erasing operation using the prior art can result in the difference between the memory of the early and the early memory of the ribs, and the mysterious sheep. Some memory cells reach the (4) threshold voltage level of the erased state. The rate of the threshold voltage level may be faster or slower than other memory cells, which may cause over-erasing and faster erasure of memory cells. The fast-moving 之 掊 掊 U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U The erasure rate can result in shortening the lifetime of a cat with a single 7 〇 or NAND string. A typical eraser can be used to refer to % '... In the threshold voltage phase. ^ After the early ,, the threshold voltage of the NAND string -:, when applying - or multiple erase voltage pulses, the threshold voltage of more than 2 memory cells can be different from the NAND string or device - The gate is in the 己 ° 隐 隐 隐 隐 隐 隐 隐 隐 隐 隐 隐 隐 隐 隐 隐 隐 隐 隐 隐 隐 隐 隐 隐 隐 隐 隐 隐 隐 隐 隐 隐 隐 隐 隐 隐 隐 隐 隐 隐 隐 隐 隐 隐 隐 隐The soft stylized package I09918.doc 1313867 includes the application of a relatively low stylized voltage (less than the actual stylization used) Voltage) to one or more memory cells. Soft stylization typically involves applying a stylized voltage in a series of pulses, wherein the pulses are incremented by a step size between each applied stylized voltage pulse. Soft stylization increases the threshold voltage of the memory cell to narrow and/or increase the threshold voltage distribution of the erased memory cell population. However, soft stylization can increase the programming time and Erase time. In addition, 'traditional soft stylization can suffer from the same effect of different properties between different memory cells. These memory cells may be erased slowly, or may be softly stylized slowly. At the end of soft stylization At the time of 'the slower and softer stylization _ body; & 4 the early erase threshold voltage can be lower than the threshold voltage of the memory unit of the NAND string. The techniques described are directed to techniques for erasing and/or soft-programming non-volatile memory devices in a manner that provides a more consistent erase threshold voltage. Provided — „ ^ slave system, which considers the individual characteristics of one or more w° invisible early during erasure and soft stylization operations, “except for operational modes and soft stylized modes of operation. — non-volatile The storage element is 隼 芒 隹 隹 隹 隹 隹 隹 隹 隹 隹 隹 隹 隹 隹 隹 隹 隹 隹 隹 隹 隹 隹 隹 隹 隹 隹 隹 隹 隹 隹 隹 隹 隹 隹 隹 隹 隹 隹 隹 隹 隹 隹 隹 隹 隹 隹 隹 隹Sexual Storage> ☆ The set is broken and erased until the non-volatile storage component collection is continued—the first is a subset of the non-waving rabbit storage component and the horse has been erased. Non-guest π t, the non-volatile storage element of the non-volatile storage of the idling erase non-volatile storage opened a 卞 city, including the faster storage of fine cattle. Verify that the first non-volatile storage element 1099l8.doc 1313867 subset includes a subset of non-volatile storage elements. After the double set of the first non-volatile storage element is inspected as being erased, it is forbidden to erase the first non-volatile storage of the six sets of 'six while collecting the second non-volatile storage element. set. The ', w 0" first-non-volatile storage component subset was tested. ^ When it has been erased, the non-broadcast eight ω 丄 XD hai non-storage storage component set is verified as twisted · "Human Zen" raw storage 集合 collection has been erased can be included. Exclude verification of the first A non-volatile ^ ^ _ _ a subset of parts, or - verification = - _ _ storage element subset and the second non-volatile storage element subset. Depending on the subset of non-volatile library components being erased and verified, different step sizes can be used to aggregate the components. The non-volatile storage of the non-volatile storage element set can be divided into several subsets for further liberalization to more slowly soften the slower, softer stylized components. The entire set of non-volatile storage elements is soft until it is verified to have been softly stylized (or until - the first storage element is tested and the other is verified by the soft and stylized, and the verification is performed. A subset of non-volatile storage elements). After the non-volatile storage element set: verified to have been soft-programmed, further soft stylization is prohibited: a non-volatile storage element subset, while performing additional softness on a second non-volatile storage == subset Stylized. The second non-volatile memory element "collects a non-volatile storage element that includes a slower, softer stylization. Then, the second non-volatile storage can be verified by the soft program testing. A subset of non-volatile storage elements. The second non-volatile storage element subset can continue to be programmed and verified until the '099l8.doc 1313867 second non-volatile material element subset is verified to have been softened Stylized. Depending on the subset of non-volatile storage elements being soft-programmed and verified, the size of the soft stylized signal can be increased by different step sizes. In a specific example, according to the techniques described herein The soft stylization is performed following erasure according to the techniques described herein.

'在-具體實施例中’提供一種擦除非揮發性記憶體之方 法，其包括啟用擦除一非揮發性儲存元件集合。該非揮發 性儲存元件集合的一第一非揮發性儲存元件子集及一第二 非揮發性健存元件子集被啟用以進行擦除。當該第一非揮 發性儲存元件子集及該第二非揮發性储存元件子集被啟用 以進行擦料，接著—或多個擦除電隸衝被 ::;儲:元件集合。施加該等脈衝，直到該第-編 ==子集被驗證為已被擦除。該第一非揮發性儲存 兀件子集被驗證為已被擦除後，禁止進—步擦除 揮發性儲存元件子隼，π 4 ^ … 件子集同時该第二非揮發性儲存元件子集 tr啟用以進行騎°當㈣—轉發性儲存元件子隼 破不止且㈣二非揮發性儲存元件子集被啟料，接著〃 或多個額外擦除電壓脈衝被施加至 合。施加該等額外脈衝，直到 单U生储存凡件集 集被驗證為已被擦除。 —I性儲存元件子 在一具體實施例中，提供一種 向乜.一非4 /、種非揮發性記憶體系統，其 括· 非揮發性儲存· r U π汞σ ，以及管理電 非揮發性儲存元件隼合 路其與该 十果。通讯。，亥非揮發性儲存元人 括一第一非揮發性儲在 本5已 干知I王储存兀件子集及一 乐一非揮發性儲存元 1099J8.doc -14- 1313867 元件二 電路使用一項技術來擦除該非揮發性儲存 ^牛“，該技術包括.·當該非揮發性儲存元件集合中之 非揮發性儲存元件被啟用以進行擦除時，施加—捧除 電望至该非揮發性健存元件集合；驗證 存元件早隹s木.y入 弟非揮發性儲 存元：：！ 時排除驗證-第二非揮發性儲 件子集，以及重複該施加及驗證，直到該第 性儲存元件子集被驗證為已被 亓杜工5亥弟一非揮發性儲存 ==驗證為已被擦除後’該管理電路禁止擦除該第 儲元件子集，並且啟用擦除該第二非揮發性 件子集。當啟用該第二非揮發性儲存元件子集以進 丁=並且禁止擦除該第一非揮發性儲存元件子集時，接 人1理電路施加一擦除電壓至該非揮發性儲存元件集 厂f由驗證該第二非揮發性儲存元件子集是否已被捧 除’來驗證該非揮發性儲存㈣集合是否已被擦除。 體體實施例中’提供一種軟性程式化非揮發性記憶 肢…包括·施加-或多個軟性程式化脈衝至一非揮 元件集合，直到該非揮發性儲存元件集合被:： ρ程式化。在該非揮發性儲存元件集合被驗證為 ^軟性程式化後，禁止軟性程式化該非揮發性儲存元件 :之帛#揮發性儲存元件子冑；以及施加一或多個 頜外軟性程式化脈衝至該非揮發性儲存元件集人之—第二 非揮發性儲存元件子集，同時禁止軟性程式㈣第-_ 2儲存元件子集。在一具體實施例中，軟性程式化係繼 掭除後予以執行，如上文所述。 WSM8.doc 15 1313867 根據本發明另一具ff眚姑加 tg Ju 〇騣只細例，提供一種非揮發性 系統’其包括··-非揮發性儲存元件集合；以及管心 ^該非揮發性料元件集合通訊。該非揮發㈣存元件 集5包括一第一非揮發性健存元件子集及-第二非揮發性 储存儿件子集。、該管理電路㈣程式化該非揮發性儲存元 件其权f生私式化方式為··施加一軟性程式化電麼至 揮發性儲存元件集合巾的每—非揮發性料元件；以及驗 證該非揮發性儲存元件集合是否已被軟性程式化。該管理 電路重複該施加及驗證，直到該非揮發性儲存元件集合被 驗證為已被軟性程式化。驗證該非揮發性儲存元件集合已 被軟性程式化之後，該管理電路施加該軟性程式化電壓至 該第-非揮發性儲存元件子集中的每—非揮發性儲存元 ,:以及驗證該第—非揮發性儲存元件子集是否已被軟性 程式化，同時排除驗證該第二非揮發性儲存元件子集。 從說明書、附圖及申請專利範圍將可明白本發明的其他 特徵、態樣及目的。 【實施方式】 圖4繪示可用於實施本發明之一或多項具體實施例的快 閃記憶體系統之一具體實施例的方塊圖。可使用其他系統 及實施方案。記憶體單元陣列302受控於行控制電路3〇4、 列控制電路306、共同源極線控制電路3丨〇及p井控制電路 308。行控制電路304被連接至記憶體單元陣列％〕的位元 線，用於：讀取記憶體單元中儲存的資料；在一程式化操 109918.doc -16- !313867 作期間判定記憶體單元之狀態；以及控制位元線之電位位 準以促進或不止程式化及擦除。列控制電路306被連 字線，用以：選擇其中一個字線；施加讀取電壓；結合受 控於行控制電路304的位a線電位位準來施加程式化電 壓，以及施加擦降雪阿 ’、電屋。共同源極線控制電路31〇控制—連 接至°己憶體單70的共同源極線（圖4中標示為「共同源極 線」）。p井控制電路3 〇 8控制p井電壓。 隐體單A中错存的資料係由行控_電路_予以讀出 且係經由資料輪入/輪出缓衝器312而輸出至外部"Ο線。擬 餘存於記憶體單元中的資料係經由該等外部ι/〇線而輪入 至该資料輸入/輸出緩衝器312，並且傳送至該行控制電路 6亥4 線被連接至控制器3 1 g。 用於控制器快閃記憶體裝置的命令資料被輸人至控制器 318。該命令資料將所要求的操作告知快閃記憶體。輸入的 命令被傳送至屬於控制電路315之部件的狀態機316。狀態 機316控制行控制電路3〇4、列控制電路遍、共同源極線控 制電路310、p井控制電路3〇8及資料輸入/輸出緩種了器扣。 狀態機316亦可輸出快閃記憶體的狀態資料，諸如「就緒/ 忙綠」（reADY/busy)或「通過/失敗」（pass/fa叫。、 控制器318被連接至或可連接於一主機系統，諸如個人電 腦、數位攝影機或個人數位助自料。控制器與起始命令 的主機通訊’諸如儲存資料至記憶^車列3〇2或從記憶體陣 列：2讀取資料’以及提供或接收此等資料。控制器3㈣ 此寻命令轉換成命令電路3丨4 (其屬於控制電路3^之部件） 1099I8.doc -】7- 1313867In a particular embodiment, a method of erasing non-volatile memory is provided that includes enabling erasure of a set of non-volatile storage elements. A subset of the first non-volatile storage element and a second non-volatile storage element subset of the non-volatile storage element set are enabled for erasing. When the first non-volatile storage element subset and the second non-volatile storage element subset are enabled for rubbing, then - or more of the erased electrical bursts are :: stored: a set of components. These pulses are applied until the epoch == subset is verified as having been erased. After the first non-volatile storage element subset is verified as having been erased, the step of erasing the volatile storage element sub-injection, the π 4 ^ ... subset and the second non-volatile storage element are prohibited The set tr is enabled for riding. (4) - the forwarding storage element is smashed and the (iv) two non-volatile storage element subsets are activated, and then 〃 or a plurality of additional erase voltage pulses are applied. These additional pulses are applied until the single U-storage collection is verified to have been erased. An I-storage element, in one embodiment, provides a non-volatile, non-volatile memory system including non-volatile storage, r U π mercury σ, and management of electrical non-volatile The sexual storage element combines the same with the ten fruit. communication. , Hai non-volatile storage yuan including a first non-volatile storage in this 5 has been known I Wang storage pieces subset and a music one non-volatile storage element 1099J8.doc -14- 1313867 component two circuit use one Technique for erasing the non-volatile storage ", the technique includes: when the non-volatile storage element in the non-volatile storage element set is enabled for erasing, applying - removing the electricity to the non-volatile a set of storage components; verifying the storage component early 隹swood.y entering the non-volatile storage element::! Excluding the verification-second non-volatile storage subset, and repeating the application and verification until the sexual storage The subset of components is verified to have been erased by the non-volatile storage == verified as having been erased. 'The management circuit prohibits erasing the subset of the storage elements and enables erasing the second non- a subset of volatile components. When the second subset of non-volatile storage elements is enabled to enable and erase the subset of the first non-volatile storage elements, the receiving circuit applies an erase voltage to the non-volatile The volatile storage component set f is verified by the second Whether the subset of volatile storage elements has been removed to verify that the non-volatile storage (four) set has been erased. In a body embodiment, 'providing a soft stylized non-volatile memory limb... including · applying - or multiple Softly stylizing the pulse to a non-volatile component set until the non-volatile storage component set is: ρ stylized. After the non-volatile storage component set is verified as being soft-programmed, soft programming of the non-volatile storage component is prohibited : 帛# volatile storage element sub-胄; and applying one or more externally soft stylized pulses to the non-volatile storage element set - the second non-volatile storage element subset, while prohibiting the soft program (four) - _ 2 stores a subset of components. In a specific embodiment, the soft stylization system is executed after being removed, as described above. WSM8.doc 15 1313867 According to the present invention, another ff眚加加tg Ju 〇騣In a detailed example, a non-volatile system is provided which includes a collection of non-volatile storage elements, and a collection of non-volatile material elements. The non-volatile (four) storage element set 5 The first non-volatile storage component subset and the second non-volatile storage component subset are included. The management circuit (4) stylizes the non-volatile storage component. Softly stabilizing each non-volatile material component of the volatile storage component collection towel; and verifying whether the non-volatile storage component collection has been softly programmed. The management circuit repeats the application and verification until the non-volatile storage The set of components is verified to have been soft-programmed. After verifying that the set of non-volatile storage elements has been soft-programmed, the management circuit applies the soft stylized voltage to each non-volatile portion of the subset of the first-non-volatile storage elements. Sex storage element: and verify whether the subset of the first non-volatile storage element has been softly programmed while excluding the verification of the second non-volatile storage element subset. Other features, aspects, and objects of the present invention will become apparent from the description and drawings. [Embodiment] FIG. 4 is a block diagram showing one embodiment of a flash memory system that can be used to implement one or more embodiments of the present invention. Other systems and implementations can be used. The memory cell array 302 is controlled by a row control circuit 〇4, a column control circuit 306, a common source line control circuit 3A, and a p-well control circuit 308. The row control circuit 304 is connected to the bit line of the memory cell array %] for: reading the data stored in the memory unit; determining the memory unit during a stylized operation 109918.doc -16-!313867 The state of the bit line; and the potential level of the control bit line to facilitate or not to stylize and erase. Column control circuit 306 is connected to the word line for selecting one of the word lines; applying a read voltage; applying a stylized voltage in conjunction with a bit a line potential level controlled by row control circuit 304, and applying a wiper snow , electric house. The common source line control circuit 31 is controlled to connect to the common source line of the memory unit 70 (labeled "common source line" in Fig. 4). The p-well control circuit 3 〇 8 controls the p-well voltage. The data stored in the hidden unit A is read by the row control_circuit_ and output to the external "Ο line via the data wheel in/out buffer 312. The data to be left in the memory unit is clocked into the data input/output buffer 312 via the external ι/〇 line, and transmitted to the line control circuit 6 to be connected to the controller 3 1 g. Command data for the controller flash memory device is input to the controller 318. This command data informs the flash memory of the required operation. The entered command is passed to state machine 316 which is part of control circuit 315. The state machine 316 controls the row control circuit 3〇4, the column control circuit, the common source line control circuit 310, the p-well control circuit 3〇8, and the data input/output buffer. The state machine 316 can also output status data of the flash memory, such as "reADY/busy" or "pass/fa" (pass/fa call.) the controller 318 is connected to or can be connected to one. A host system, such as a personal computer, a digital camera, or a personal digital device. The controller communicates with the host that initiates the command 'such as storing data to memory ^car column 3〇2 or reading data from memory array: 2' and providing Or receive such information. Controller 3 (4) This seek command is converted into command circuit 3丨4 (which belongs to the control circuit 3^) 1099I8.doc -] 7- 1313867

的解譯及執行的命令邙祙 .A 0 J 。中々電路314係與狀態機3 16通 訊。控制器3 1 8典型台括螻灰 匕括、每衝器記憶體，用於寫入至或讀取 自記憶體陣列的使用者資料。 -項示範性記憶體系統包括一個積體電路(其包括控制 益3⑻及-或多個積體電路晶片（每—積體電路^包— 記憶體陣列及相關聯之捭岳丨 铋制、輸入/輸出及狀態機電路）。一 項趨勢係在一或多個積I#雷 尺夕1U槓體電路晶片上將一系統的記憶體陣Interpretation and execution of the command 邙祙 .A 0 J . The middle circuit 314 is in communication with the state machine 3 16 . The controller 3 1 8 is typically included in the flash memory, per-buffer memory for writing to or reading user data from the memory array. - The exemplary memory system includes an integrated circuit (which includes control benefits 3 (8) and - or a plurality of integrated circuit chips (each - integrated circuit package - memory array and associated 捭 丨铋 system, input /Output and State Machine Circuitry. A trend is to have a system of memory arrays on one or more I# Lei Yi Xi 1U bar circuit chips.

列及控制Θ電路整合在—起。記憶體系統可被嵌入為主機 糸統的部件’或可被包括於一可卸除式插入至主機系統中 、隐卡（或其他封裝）中。此—記憶卡可包括整個記憶體系 統(例如，包括控制器)’或僅包括記憶體陣列與相關聯之周 邊=路（連同嵌入於主機中的控制器或控制功能）。因此，控 制印可被敢入為主機中或被包括於可卸除式記憶體系統 内。 月 '閱圖5，圓中繪示記憶體單元陣列3 〇2之示範性結 #構。作為—項實例，描述一種被分割成1，〇24個區塊_AND I·夬門EEPRQM。可以同時擦除每—區塊中儲存的資料。在 :具體實施例中，⑽係被同時擦除之記憶體單元的最小 〇π 在此κ例中’母一區塊有8，512行。每一區塊典型被 劃分成若干頁（可能係一程式化單位）。其他程式化之資料單 位亦係可貫行且列入考量。在一具體實施例中，個別頁可 被劃分成若干區段，並且區段可包含作為一基本程式化操 作而一次寫入的最少數量之記憶體單元。一或多頁資料典 型被儲存於一列記憶體單元中。 109918.doc -18- 1313867 在圖5所示實例之每—區塊中有8,512行，其被劃分成偶 數行及奇數行^位元線被劃分成偶數位元線（BLe)及奇數位 元線（BLo)。在一種奇數/偶數位元線架構中，對沿—共同 字線且連接至奇數位元線的記憶體單元進行一次程式化，The column and control circuit are integrated. The memory system can be embedded as part of the host system' or can be included in a removable form into a host system, a hidden card (or other package). This - the memory card may include the entire memory system (e.g., including the controller)' or only the memory array and associated peripheral = way (along with controllers or control functions embedded in the host). Therefore, the control print can be dared to be included in the host or included in the removable memory system. Month's drawing Figure 5 shows an exemplary structure of the memory cell array 3 〇2. As an example, a description is made that one is divided into 1, 24 blocks _AND I·夬 EEPRQM. The data stored in each block can be erased at the same time. In the specific embodiment, (10) is the minimum 〇 π of the memory cells that are simultaneously erased. In this κ example, the parent block has 8,512 rows. Each block is typically divided into pages (possibly a stylized unit). Other stylized data units are also considered and considered. In one embodiment, individual pages can be divided into segments, and segments can contain a minimum number of memory cells that are written at a time as a basic stylized operation. One or more pages of data are typically stored in a list of memory cells. 109918.doc -18- 1313867 There are 8,512 rows in each block of the example shown in Figure 5, which are divided into even rows and odd rows. The bit lines are divided into even bit lines (BLe) and odd bits. Line (BLo). In an odd/even bit line architecture, the memory cells along the common word line and connected to the odd bit lines are programmed once,

並且對沿一共同字線且連接至偶數位元線的記憶體單元進 行另一次程式化。圖5繪示串聯連接以形成—nand串的四 個記憶體單元。雖然圖中繪示每一NAND串中包括四個記憶 體單元，但是可以㈣四個以上或以下記憶體單元（例如: Μ、32或其他數量）。NAND串的一終端係經由一第一選擇 電晶體或閘極（其連接至選擇閘極汲極線SGD)而連接至— 相對應之位元線，並且另一終端係經由一第二選擇電晶體 (其連接至選擇閘極源極線SGS)而連接至一共同源極線。 在其他具體實施例巾，該等位元線未㈣分成偶數及奇 數位元線。此類架構通常稱為「全位元線架構」。在一種全 位凡線架構中，於讀取及程式化操作期間，同時選擇—區 塊的所有位元線。沿一共同字線且連接至任何位元線的： 憶體單元被同時程式化。 叫、· r胡间，Μ呀選擇 4,256個記憶體單元。該等所選記憶體單元具有相同的字線 (例如，WL2-i)及同一種位元線（例如’偶數位元線）。因此、， 可以同時讀取或程式化532個位元組資料。該等同時讀取或 程式化的532個位元組資料形成一邏輯頁。因此，在此實例 中’-個區塊可儲存至少八頁。當每_記憶體單元儲存兩 個位元的資料時（例如，一種多級位記憶體單元），_個區塊 109918.doc -19- 1313867 *八’r〜四％及頁。 外，亦可使用除圖4及5以外的架構來實施具體實施例。 在讀取與驗證操作中，使一所選區塊的選擇間極 一或多《擇《，並且使該所職塊的相選 如，糊、和和脱3)上升至_讀取傳送電塵（例如、.A 伙），以使電晶體運作為傳送閘極。該所選區塊的所選 (例如，WL2)被連接至—參考電歷，對於每—讀取乾驗执操 作來指定該參考電麼的位準，以判定所涉及的記:元 ^否高於或低於該參考電㈣位準。舉例而 § ’在—位元記憶體單元的讀取操作中，該所選字線WL2 被接地，使得谓測其臨限 _ 體單元的_喿作中，==於。伏。在-位元記憶 伏，你… 所選子線WL2被連接至(例如)0·8 、传式化進行過程中僅測其臨限電屋是否已 0.8伏。於讀取盘驗 】達 …驗证期間，源極與P井為零伏。所選位亓 線（BLe)被預充電至（例如 讀取或驗證位準，則… 準。如果臨限電壓高於 元，所以涉及 ^相關聯之非傳導狀態記憶體單 方而 ^(BLe)的電位位準維持高位準。另一 士果限電壓低於讀取或驗證位準，則因A非值 狀態之記憶體單元，所以、牛… 丨則因為非傳導 小至低位準，心之位元線(BLe)的電位位準減 放大。:二小於°·5伏。藉由連接至位元線的❹] 放大斋來偵測記憔髀昱_ , At ^ J ^ 電壓。記憶體單：是 並且感測所得之位元線 負電荷是否、^ 否破程式化或擦除之間的差異取決於 、 3儲存於浮動閘極中。舉例而+ ,士 Iέ φ + 被儲存於浮動閑極 j而5如果負電荷 則臨限電壓變成較高且電晶體可能 109918.doc -20- 1313867 處於增強操作模式。 收^項實例中’當程式化一記憶體單元時，没極及p井接 一且^控制閣極接收量值遞增的—連串程式化脈衝。在 Z錢例中，該連串脈衝的脈衝量值在邮·伏範 不门2他具體實施例中’該連串脈衝的脈衝範圍可能 單而言，具有-高於12伏的開始位準。於記憶體And another stylization is performed on the memory cells along a common word line and connected to the even bit lines. Figure 5 illustrates four memory cells connected in series to form a -nand string. Although four DRAM cells are included in each NAND string, four or more memory cells (e.g., Μ, 32, or other numbers) may be used. A terminal of the NAND string is connected to the corresponding bit line via a first selection transistor or gate (which is connected to the selected gate drain line SGD), and the other terminal is via a second selection A crystal (which is connected to the select gate source line SGS) is connected to a common source line. In other embodiments, the bit lines are not (four) divided into even and odd bit lines. This type of architecture is often referred to as a "full bit line architecture." In a full-scale architecture, all bit lines of a block are selected simultaneously during read and program operations. Along a common word line and connected to any bit line: The memory cells are programmed simultaneously. Call, · r Hu, oh, choose 4,256 memory units. The selected memory cells have the same word line (e.g., WL2-i) and the same bit line (e.g., 'even bit line). Therefore, 532 bytes of data can be read or programmed simultaneously. The 532 bytes of data that are simultaneously read or programmed form a logical page. Therefore, in this example, the '-blocks can store at least eight pages. When each _memory unit stores two bits of data (for example, a multi-level memory unit), _ blocks 109918.doc -19- 1313867 * eight'r~four% and pages. In addition, specific embodiments may be implemented using architectures other than those of Figures 4 and 5. In the reading and verifying operation, one or more selections of a selected block are selected, and the selection of the selected block, such as paste, and and off, is raised to read the transmission dust. (eg, .A gang) to operate the transistor as a transfer gate. The selected block (eg, WL2) of the selected block is connected to the reference electrical calendar, and the level of the reference power is specified for each read dry operation to determine the number of records involved: At or below the reference power (four) level. For example, § 'in the read operation of the bit memory cell, the selected word line WL2 is grounded, so that the _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Volt. In the -bit memory, you... The selected sub-line WL2 is connected to (for example) 0·8. During the process of the pass-through, only the threshold house is 0.8 volts. During the reading test, the source and P wells are zero volts during verification. The selected bit line (BLe) is precharged (for example, reading or verifying the level, then... if the threshold voltage is higher than the element, the associated non-conducting state memory is unilaterally ^(BLe) The potential level is maintained at a high level. If the voltage of the lower limit is lower than the reading or verifying level, then the memory unit of the non-value state is, therefore, the cow... 丨 because the non-conducting is small to the low level, the heart The potential level of the bit line (BLe) is reduced by amplifying.: Two is less than °·5 volts. 电压, At ^ J ^ voltage is detected by ❹] amplification of the bit line connected to the bit line. Single: Yes and sense the difference between the negative charge of the resulting bit line, whether it is broken or stylized or erased, and 3 is stored in the floating gate. For example, +, I I φ φ + is stored in the floating The idle pole j and 5 if the negative charge, the threshold voltage becomes higher and the transistor may be 109918.doc -20- 1313867 in the enhanced operation mode. In the example of the item 'when staging a memory unit, there is no pole and p The well is connected to one and the other is a series of stylized pulses that are incremented in value. In the case of Z money, the company The pulse magnitude of the string pulse is in the specific embodiment of the invention. The pulse range of the series of pulses may, alone, have a starting level of - above 12 volts.

驗證操::::期在=程式化脈衝之間的週期中實行 ^ 在母一程式化脈衝之間讀取正被並行程式 準之體單元群組中之每一記憶體單元的程式化位 播\疋5己憶體單元是否已到達或超過其正被程式化時 —八的驗證位準。驗證程式化的-項手段係測試-特 ::較傳導。經驗證已被充分程式化之記憶體單元被 舉例而言’在N娜記憶體單元中，鎖定方式係對於 所有後續程式化脈衝’使位元線從〇上升至例如，2.5 伏）’以終止彼等記憶體單元的程式化過程。在—些情況 下:將限制脈衝數量（例如，2〇個脈衝），並且如果最後一個 脈衝2分程式化一既定記憶體單元，則假設一錯誤。在 —些實施方案中，在程式化之前先擦除記憶體單元(以區塊 為單位或其他單位）。 ^6、’曰不根據—具體實施例之程式化電屢訊號。此訊號具 有量值遞增的一脈衝集合。該等脈衝之量值係按一預先決 定步進大小隨每-脈衝予以遞增。在—項包含儲存多位元 貝料的i It體單兀的具體實施例中’—示範性步進大小為 0.2伏（或0.4伏）。介於每―程式化脈衝之間係驗證脈衝。圖 109918.doc -21 - 1313867 6之訊號假設一種四壯能a a ^ 狀心式记憶體早元’因此’該訊號包括 三個驗證脈衝。舉你丨而 U而吕’介於程式化脈衝33〇與332之間 係三個連續的驗證脈衝。 _ r衝所繪不之一弟一驗證脈衝334係處Verification operation:::: Period is executed in the period between = stylized pulses ^ Reads the stylized bits of each memory unit in the group of body units being parallelized by the parent-synchronized pulse Whether the broadcast unit has reached or exceeded the verification level when it is being programmed. Verify that the stylized - item means test - special :: more conductive. Memory cells that have been verified to be fully stylized are exemplified by 'in the N Na memory cell, the locking mode is for all subsequent stylized pulses 'to raise the bit line from 〇 to, for example, 2.5 volts' to terminate The stylization process of their memory cells. In some cases: the number of pulses will be limited (for example, 2 pulses), and if the last pulse is programmed to divide a given memory cell by 2, an error is assumed. In some embodiments, the memory cells (in blocks or other units) are erased prior to programming. ^6, 'Do not rely on the stylized electric relay signal of the specific embodiment. This signal has a set of pulses with increasing magnitude. The magnitude of the pulses is incremented with each pulse in a predetermined step size. In a particular embodiment where the term contains an i It body unit that stores a multi-element feedstock, the exemplary step size is 0.2 volts (or 0.4 volts). A verification pulse is generated between each "stylized pulse". The signal of Figure 109918.doc -21 - 1313867 6 assumes that a four-strong energy a a ^ heart-shaped memory early element 'so' the signal includes three verification pulses. For you, U and Lu' are between three stylized pulses between the stylized pulses 33〇 and 332. _ r rushed to draw one of the brothers a verification pulse 334 line

於零伏驗證電壓位進。拉+ & A ^ ^ 接在第一驗證脈衝後的第二驗證脈Verify the voltage at zero volts. Pull + & A ^ ^ to the second verification pulse after the first verification pulse

衝336係處於第—驗證電壓位準。接在第二驗證脈衝後的第 三驗證脈衝338係處於第三驗證㈣位準。-種能夠以八種 狀態來儲存資料的多狀態記憶體單元可能必須在七個比較 點處實行驗證操作。因&，在兩個連貫程式化脈衝之間依 序施加七個驗證脈衝’以在七個驗證位準實行驗證操作。 系統可依據七個驗證操作來決定記憶體單元的狀態。一項 減小驗證時間負荷的手段係使用更高效率的驗證程序，舉 例而言’如下列以下專利申請案所揭示：u.s. 2002年12 月5曰提出之專利申請案第1〇/314,〇55號標題為「如訂^The rushing 336 is at the first verification voltage level. The third verify pulse 338 following the second verify pulse is at the third verify (four) level. A multi-state memory unit capable of storing data in eight states may have to perform verification operations at seven comparison points. Because of &, seven verify pulses are applied sequentially between two consecutive stylized pulses to perform the verify operation at seven verify levels. The system can determine the state of the memory unit based on seven verification operations. A means of reducing the verification time load is to use a more efficient verification procedure, for example, as disclosed in the following patent applications: US Patent Application No. 1/314, filed December 5, 2002, 〇 Title 55 is "If you order ^

Verify for Mult 卜 State Memories」；200 5 年 10 月 27 日提出之 專利中請案第----------號[代理人檔案號碼第 SAND-1051US1 號]標題為「Method for Programming of MulU-State Non-Volatile Memory Using Smart Verify」；以 及2005年10月27日提出之專利申請案第__________號[代 理人槽案號碼第SAND-105 1US0號]標題為「Apparatus forVerify for Mult (State Memories); 200 Patent Proposal No.---------- [Agent File Number SAND-1051US1] titled "Method for Programming" Of MulU-State Non-Volatile Memory Using Smart Verify"; and Patent Application No. __________ [Agent No. SAND-105 1US0] filed on October 27, 2005, entitled "Apparatus for

Programming of Multi-State Non-Volatile Memory Using Smart Verify」’該等案均以引用方式整份併入本文。 如上文所述之讀取與驗證操作係根據此項技術中熟知的 技術予以實行。因此’熟悉此項技術者可改變許所解說的 細節。 109918.doc -22- 1313867 —圖7緣示用以解說程式化非揮發性記憶體方法之-具體 貫施:的流程圖。在步驟340，擦除擬程式化的記憶體單 凡。步驟340可包括捧除多於海 ^ 0,, 牙、夕於擬私式化之記憶體單元的記憶 體早·，以區塊為單位或其他單位)。在步驟⑷，執 =人性程式化，以使所擦除之記憶體單元的臨限電編 ”。由於擦除程序，一些記憶體單元可能處於深於所需 白、已擦除狀態。軟性程式化可施加小程式化脈衝，以使所 擦除之記憶體單元的臨限„較接近擦除驗證位準。在圖7 的步驟3 5 0，一「咨姓讲、 人 貝枓載入」D?令係由控制器3 j 8予以發出 且被輸入至命令電路314,以允許將資料輸人至資料輸入/ 輸出緩衝器312。輸入之資料被辨識為一命令，且經由一輸 入至命令電路314的命令鎖存訊號（圖中未緣示）而由狀態機 3 1 6予以鎖存。在步驟3 $ 9γ t二、 ^騍·352攸控制器或主機將指定頁位址 的位址資料輸入至列控制器或解碼器3〇6。輸入之資料被辨 識為頁位址’且經由狀態機3 1 6予以鎖存（受到輸入至命令 電路314的位址鎖存訊號所影響）。在步驟354,所定址之頁 的一頁程式化資料被輸入至資料輸入/輸出緩衝器312以進 =程式化。舉例而言’在—具體實施例中可輸人532位元組 貧料。該資料被鎖存在用於所選位元線的適當暫存器中。 在-些具體實施例中’該資料亦被鎖存在用於驗證操作使 用之所選位兀線的第二暫存器中。在步驟356，一「程式化」 命:係由控制器318予以發出且被輸入至資料輸入/輸出缓」 衝器312。經由輸入至命令電路314的命令鎖存訊號而由狀 態機316鎖存該命令。 109918.doc -23- 1313867Programming of Multi-State Non-Volatile Memory Using Smart Verify"' is hereby incorporated by reference in its entirety. The reading and verifying operations as described above are carried out in accordance with techniques well known in the art. Therefore, those who are familiar with the technology can change the details of the explanation. 109918.doc -22- 1313867 - Figure 7 shows a flow chart for explaining the stylized non-volatile memory method. At step 340, the stylized memory is erased. Step 340 may include removing more than the sea ^ 0, the teeth, the memory of the memory unit that is to be privateized, the block, or other units. In step (4), the execution is humanized, so that the memory unit of the erased memory unit is electronically edited. Due to the erase program, some memory units may be deeper than the desired white and erased state. A small stylized pulse can be applied to bring the threshold of the erased memory cell closer to the erase verify level. In step 305 of FIG. 7, a "speaking, squatting" D? command is issued by the controller 3j8 and input to the command circuit 314 to allow data to be input to the data input. / Output buffer 312. The input data is recognized as a command and is latched by state machine 316 via a command latch signal (not shown) that is input to command circuit 314. In step 3, $9γt2, ^骒·352攸 controller or host inputs the address data of the specified page address to the column controller or decoder 3〇6. The input data is identified as a page address' and is latched via state machine 316 (affected by the address latch signal input to command circuit 314). At step 354, a page of the stylized data of the addressed page is input to the data input/output buffer 312 for programming. For example, in a particular embodiment, 532 bytes of lean material can be input. This data is latched in the appropriate register for the selected bit line. In some embodiments, the data is also latched in a second register for verifying the selected bit line used for the operation. In step 356, a "stylized" life is issued by controller 318 and input to data input/output buffer 312. The command is latched by the state machine 316 via a command latch signal input to the command circuit 314. 109918.doc -23- 1313867

藉由「程式化」命令之觸發，使用圖6所示之施加至適當 字線的步進式脈衝’將在步驟354中鎖存的資料程式化至由 狀態機316所控制的所選記憶體單元中。在步驟358，施加 至所選字線的程式化脈衝電壓位準v p g m被初始化為開始 脈衝（例如，12伏）’並且狀態機3 16所維護的一程式計數器 PC被初始化為〇。在步驟36〇，第一 vpgm脈衝被施加至所選 字線。如果儲存在一特定資料鎖存器中邏輯「〇」指示出應 程式化相對應之記憶體單元，則相對應之位元線被接地。 另一方面，如果儲存在一特定鎖存器中的邏輯「丨」指示出 相對應之記憶體單元應維持其現有資料狀態、，則相對應之 位元線被連接至VDD以禁止程式化。 你乂郤以2’驗證所選記憶體單元之狀態。如果偵測到一 所選記憶體單元的目標臨限電壓已到達適當位準，則相對 應之資料鎖存器中儲存的資料被變更為邏輯「丨」。如果偵 測到目標臨限電壓未到達適當位準，則不變更相對、 料鎖存器中儲存的資料。在此方式中，在本身相對應之資 =鎖存器中已儲存邏輯「1」的位元線不需要Η程式化 :所有資料鎖存器皆正在儲存邏輯「!」時，狀態機知道已 ::二：：有所選記憶體單元。在步驟364 ’檢查是否所有資 —广正储存邏#「lj。若是’因為所有所選記憶體單 :二已Γ以程式化且經驗證其目標狀態，戶斤以程式化程序 成功。在步驟366報告「通過」（PASS)狀態。 「】在步：364 ’如果判定非所有資料鎖存器正儲存邏輯 程式化程序繼續奸。在步驟368,比對-程式化 i099l8.doc -24. 1313867 限制值來&查_程式計數器Pc。_項實例之程式化限制值 係20 ’但疋’在各種實施方案中可以使用其他值。如果該 程式計數器PC不小於2G，則在步驟369判定尚未成功程式化 的位元數量是否等於或小於預先決定數量。如果未成功程 式化的位元數量等於或小於預先決定數量，則用旗標將程 式切序標示為已通過’並且在步驟371報告一通過狀態。 在讀取程序期間’可使用錯誤修正來修正未成功程式化的 位元。但是’如果未成功程式化的位元數量大於預先決定 數罝’則用旗標將程式化程序標示為已失敗，並且在步驟 3 70報告一失敗狀態。如果該程式計數器pc小於2〇，則按該 步進大小來遞增Vpgm位準’並且在步驟372累加該程式： 數器PC。在步驟372，程序迴圈回到步驟36G，R施加下一 Vpgm脈衝。 圖7之冰％圖繪示單次行程（single_pass)程式化方法，其 可應用於二元儲存（binary stC)rage)。在—種可應詩多級位 儲存的兩次行程（two_pass)程式化方法中，舉例而言，可在 單次反覆流程中使用多項程式化或驗證步驟。對於程式化 操作的每一行程，可執行步驟358至372。在第一行程中， 可施加一或多個程式化脈衝並且驗證其結果，以判定—記 憶體單7G是否處於適當的中間狀態。在第二行程中，可施 加一或多個程式化脈衝並且驗證其結果，以判定一記憶體 單元是否處於適當的最終狀態。 在成功程式化程序結束時’記憶體單元的臨限電壓應在 經程式化之記憶體單元的一或多項臨限電壓分佈内或在經 I09918.doc -25- 1313867 擦除之記憶體單元的一臨限電壓分佈内。圖8繪示當每—記 憶體單7L儲存—位元資料時記憶體單元陣列的臨限電壓分 佈。圖8繪示經擦除之記憶體單元的第一臨限電壓分佈3肋 及經程式化之記憶體單元的第二臨限電壓分佈3 8 2。在—具 體實施例中’第―臨限電麗分佈38〇中的臨限電壓位準為負 且相對應於邏輯「丨」，而第二臨限電壓分佈382中的臨限電 壓位準為正且相對應於邏輯「0」。 圖9繪示當每一記憶體單元係以四項物理狀態來儲存兩 位元資料時記憶體單元陣列的示範性臨限電壓分佈。臨限 電壓分佈384表示處於已擦除狀態（儲存「〗丨」）之記憶體單 元的臨限電壓分佈’其具有負臨限電壓位準。臨限電壓分 佈386表示處於第一已程式化狀態（儲存「1〇」）之記憶體單 元的臨限電壓分佈。臨限電壓分佈388表示處於第二已程式 化狀態（儲存「00」）之記憶體單元的臨限電麼分佈。臨限電 壓^布390表示處於第三已程式化狀態（健存「〇1」之記憶 體單元的臨限電屡分佈。在此實例中，單一記憶體單元中 儲存之兩個位元的每一位元係來自一不同邏輯頁。即，每 一記憶體單元中儲存之兩個位元的每-位元承載一不同邏 輯頁位址。圖中方塊所示之位元對應於—下部頁。圖中圓 圈所不之位兀對應於—上部頁。在一具體實施例中，使用 :格雷碼（gray code)序列，將該等邏輯狀態指派給記憶體 :几的相、Μ物理狀k' ’使得如果一浮動閘極的臨限電壓錯 誤地偏移至其最鄰近的臨限電壓狀態範圍，則僅一個位元 將受到影響。為了提供改良之可靠度，較佳方式為，緊縮 109918.doc •26- 1313867 別l限電壓分佈（臨限電壓分 跫乍）原因係臨限電壓分 佈愈Us，讀取裕度（相鄰狀能 俞寬。 狀心、l限電壓分佈之間的距離） 當然，如果記憶體係以四種 揞鲈… 以上物理狀態運作，則在記 =…定義臨限電壓窗内的臨限電厂堅分佈數量等於狀 1。再者，雖然特定位元模式已被指派給每一分佈或 物理狀態，但是可指派不同的位元模式。The data latched in step 354 is programmed to the selected memory controlled by state machine 316 using a stepped pulse applied to the appropriate word line as shown in FIG. 6 by a "programming" command. In the unit. At step 358, the programmed pulse voltage level vpgm applied to the selected word line is initialized to a start pulse (e.g., 12 volts)' and a program counter PC maintained by state machine 316 is initialized to 〇. At step 36, a first vpgm pulse is applied to the selected word line. If a logical "〇" stored in a particular data latch indicates that the corresponding memory cell should be programmed, then the corresponding bit line is grounded. On the other hand, if the logic "丨" stored in a particular latch indicates that the corresponding memory cell should maintain its existing data state, then the corresponding bit line is tied to VDD to disable stylization. You will verify the status of the selected memory unit by 2'. If it is detected that the target threshold voltage of a selected memory cell has reached the appropriate level, the data stored in the corresponding data latch is changed to a logical "丨". If it is detected that the target threshold voltage has not reached the appropriate level, the data stored in the relative, material latch is not changed. In this mode, the bit line that has stored logic "1" in its corresponding corresponding = latch does not need to be stylized: when all data latches are storing logic "!", the state machine knows that ::2:: There is a selected memory unit. In step 364 'check if all the resources - Guangzheng storage logic # "lj. If 'all because the selected memory list: two has been programmed to verify the target state, the user succeeded in stylized procedures. In the steps 366 reports the status of "PASS". "] at step: 364 'If it is determined that not all data latches are storing logical stylized programs to continue treacherous. In step 368, compare-stylize i099l8.doc -24. 1313867 limit value to & check_program counter Pc The stylized limit value of the item instance is 20 'but 'other values can be used in various embodiments. If the program counter PC is not less than 2G, then in step 369 it is determined whether the number of bits that have not been successfully programmed is equal to or Less than a predetermined number. If the number of unsuccessfully stylized bits is equal to or less than a predetermined number, the flag is marked with the flag as passed "and a pass status is reported in step 371. During the reading process" Use error correction to fix unsuccessfully stylized bits. But 'If the number of unsuccessfully stylized bits is greater than the predetermined number 则', the stylized program is marked as failed by the flag, and a report is reported in step 3 70. Failed state. If the program counter pc is less than 2, the Vpgm level is incremented by the step size and the program is accumulated in step 372: the counter PC. In step 3 72, the program loops back to step 36G, R applies the next Vpgm pulse. The ice % graph of Figure 7 shows a single stroke (single_pass) stylization method, which can be applied to binary storage (binary stC). A two-pass stylized method that can be stored in multiple levels, for example, multiple stylization or verification steps can be used in a single iteration. For each stroke of a stylized operation, Steps 358 to 372 are performed. In the first pass, one or more stylized pulses may be applied and the result verified to determine if the memory bank 7G is in an appropriate intermediate state. In the second pass, one or Multiple stylized pulses and verify their results to determine if a memory cell is in the proper final state. At the end of the successful stylization program, the threshold voltage of the memory cell should be in the programmed memory cell. Within a threshold voltage distribution or within a threshold voltage distribution of a memory cell erased by I09918.doc -25-1313867. Figure 8 shows a memory bank when each memory is stored in a single 7L-bit data. The threshold voltage distribution of the element array. Figure 8 illustrates the first threshold voltage distribution of the erased memory cell 3 ribs and the second threshold voltage distribution of the programmed memory cell 3 8 2 . In the embodiment, the threshold voltage level in the first-th power limiting distribution 38〇 is negative and corresponds to a logic “丨”, and the threshold voltage level in the second threshold voltage distribution 382 is positive and phase. Corresponds to logic "0". Figure 9 illustrates an exemplary threshold voltage distribution of a memory cell array when each memory cell stores two bits of data in four physical states. The threshold voltage distribution 384 represents the threshold voltage distribution of the memory cell in the erased state (stored "丨"), which has a negative threshold voltage level. The threshold voltage distribution 386 represents the threshold voltage distribution of the memory unit in the first programmed state (storing "1"). The threshold voltage distribution 388 represents the threshold distribution of the memory cells in the second programmed state (stored "00"). The threshold voltage 390 indicates that the memory is in the third programmed state (the memory of the "〇1" is stored in the memory. In this example, each of the two bits stored in the single memory unit One element is from a different logical page. That is, each bit of two bits stored in each memory cell carries a different logical page address. The bit shown in the block in the figure corresponds to the lower page. The circle in the figure does not correspond to the upper page. In a specific embodiment, the gray code sequence is used to assign the logic states to the memory: a few phases, a physical state k ''Even if a threshold voltage of a floating gate is erroneously shifted to its nearest threshold voltage state range, only one bit will be affected. To provide improved reliability, the preferred method is to tighten 109918 .doc •26- 1313867 Don't limit the voltage distribution (preventive voltage bifurcation). The reason is that the threshold voltage distribution is more Us, the read margin (the adjacent shape can be Yu wide. The centroid, the limit voltage distribution between Distance) Of course, if the memory system is in four... When the above physical state operates, the number of fixed power plants in the threshold voltage window is equal to the value 1. In addition, although a specific bit pattern has been assigned to each distribution or physical state, it can be assigned. Different bit patterns.

通常’正被並行程式化的記憶體單元係沿一字線的交替 兄憶體單元。舉例而言’圖3繪示沿一字線WL2之更多數量 記憶體單it中的三個記憶體單元224、244和252 一交替之 記憶體單元集合（包括記憶體單元咖和252)儲存來自邏輯 %數頁」）的位兀’而另一交替之記憶體單元集 合（包括記憶體單元244)儲存來自邏輯頁2和3(「奇數 的位元。 ' 在一具體實施例中，擦除記憶體單元之方式為：使p井上 升至-擦除電壓(例如，20伏)’並且接地或施加。伏至所選 區塊的字線，同時源極線及位元線係處於浮動狀態。圖ι〇 繪不用於執行擦除操作之示範性偏壓條件。由於電容耦 合’導致非所選字線（例士σ，在非所選之非擬擦除區塊中的 子線）位元線、選擇線及共同源極線也上升至高正電位（例 如，20伏）。因此，施加強電場至所選區塊的記憶體單元之 隧穿氧化物層’並且由於浮動閘極的電子被發射至基板， 導致所選記憶體單元的資料被擦除。擦除意指藉由將電子 從記憶體單元的浮動閘極轉移出纟，而降低記憶體單元的 109918.doc -27- 1313867 臨限電壓。當足夠的電子從浮動閘極轉移至p井區時，所選 記憶體單元的臨限電壓變成負。—旦臨限電壓到達一預先 =定之充分低值’隨即將記憶體單元視為已被擦除且擦除 耘序視為已完成或成功。因此’擦除記憶體單元意指降低 記憶體單元的臨限電壓，並且未意謂著完成或成功擦除記 憶體早凡。可對整固記憶體陣列、記憶體陣列的—或多個 區塊或其他記憶體單元單位來執行擦除。擦除電壓訊號 U㈣以-連串擦除電壓脈衝進行施加，其中在每一 脈衝之間實行一擦除驗證操作。如果在施加一擦除電壓脈 衝後正被擦除的記憶體單元單位未被驗證為已擦除’則可 將另-擦除電壓脈衝施加至P井區。在一些具體實施例中， t於每一後續脈衝，遞增擦除電壓的峰值（例如，以丨伏為 單位’從16伏遞增至20伏）。 圖11的圖表係繪示對於一典型擦除操作（例如，在圖1〇之 偏壓條件下），在施加一單一擦除電壓脈衝期間，一ναν〇 串之各種部分處電壓。圖丨丨之實例繪示理想狀況，其忽略 了閘極間電容電荷_合’如下文所述。曲線41G繪示出接收 擦除電壓訊號Verase2p井區的電壓。擦除電壓脈衝促使p井 爬升（ramp up)至20伏且接著回到〇伏。曲線414和412繪示該 NAND串之記憶體單元的控制閘極電壓及浮動閘極電壓。在 施加挺除電壓脈衝之前，浮動閘極電壓取決於記憶體單元 的已程式化狀態且典型低於〇伏。在圖丨〗中，假設在第一擦 除電壓脈衝之前，浮動閘極電壓為值“伏。在整個擦除操 作期間，控制閘極電歷4]4维持在〇伏，而浮動閘極電壓 109918.doc -28- 1313867 以與P井電壓成比例方式上升。 電容栽彳于動間極係跨隨穿介電區而 电合耦δ至p井。在許>Nan i - 甲只把方案中，介於記憶體 早兀之沣動閘極與p井區 40 .〇〇/ ^ J 07电各耦合比率為約 0 〇據此，浮動閘極電慶412 #以豳+»· 电丛·412係以與P井電壓呈約0.5:1 率U耦合比率係50%時）上升 下方摞…β 才’上升至約9伙電壓。圖11的圖表 知i、所仔之擦除電位（介 井 ㈧於。己德體早几之浮動閑極與p , 、位）。擦除電位等於介於p井電壓（Verase = 2 伏）與浮動閘極電壓（v = ^ ^ ^ rase 伏）之間的差值。對於圖11所示 \，第一擦除電壓脈衝開始時，擦除電位等於約u 子意’在實際擦除電麼脈衝期間’擦除電位隨著電 ^于閘極轉移至P井而變化。結果，當在擦除電麼脈衝 =井：到。伏時’浮動間極電壓將不同於施加擦除電壓 門f之别的電壓。典型地，在第-擦除電壓脈衝之後浮動 問極電雕將· k X α 期 電壓。、_ ，目對應於記憶體單元的一負（已檫除）臨限 、NAND串内的實際電壓位準將不同於關於圖η之理想 2 述的電壓位準。因為介於鄰近浮動閑極之間與介 於、擇閘極盘鄭折.、变以 /、何丨近斤動閘極之間的電容電荷耦合， 施加相同捧i m ’、’、 條件下’一 NAND串的不同記憶體單元遭 、到不同的擦除電位。 圖2提供_種包括8個記憶體單元之仙串的剖面圖。 雖然相對於^1 1 Ώ 蝴一 、圖12及一種8記憶體單元型NAND結構來提呈具 體實施例，作早士机。。 —本务月不受此項限制，並且可按照包括8 個以下或以上$情邱s , 己匕、肢早Μ例如，4、12、16或以上）的許多 109918.doc -29- 1313867 種NAND結構來運用本發明。如圖12所示，n娜串的記憶 ” μ單兀係形成在p井區54〇中。每一記憶體單元⑽、、 • 506 508、510、512、5 14和5 16)包括-種堆疊式閘極結構， 該堆疊式閉極結構係由控制間極（5〇2c、5〇4c、5〇&、5〇以、 51〇〇、512。、514〇和516(：)與浮動閘極（5〇2卜5〇4卜5〇6卜 51〇f、512f、5l4f和516f)所組成。浮動閘極係形成在氧化 物膜或其他介電合成膜頂部上的p井表面i。控#問極係在 φ '于動閘極上方，而且氧化物層或其他隔離介電層使控制閘Usually, the memory cells being serialized in parallel are alternated in a word line. For example, FIG. 3 illustrates three memory cells 224, 244, and 252 in a larger number of memory cells along WL2, an alternate memory cell set (including memory cells and 252). The bits from the logical % page ") and another alternate set of memory cells (including memory unit 244) are stored from logical pages 2 and 3 ("odd bits." In a particular embodiment, wipe The memory cell is implemented by raising the p-well to an erase voltage (eg, 20 volts) and grounding or applying it to the word line of the selected block while the source and bit lines are floating. Figure ι〇 depicts an exemplary bias condition that is not used to perform an erase operation. The non-selected word line (eg, σ, the sub-line in a non-selected non-erased block) due to capacitive coupling' The source line, the select line, and the common source line also rise to a high positive potential (eg, 20 volts). Therefore, a strong electric field is applied to the tunneling oxide layer of the memory cell of the selected block' and the electrons due to the floating gate are Emitted to the substrate, causing the data of the selected memory unit to be Erase means that the threshold voltage of the memory cell is reduced by transferring electrons from the floating gate of the memory cell out of the memory cell. When sufficient electrons are transferred from the floating gate to the p In the well zone, the threshold voltage of the selected memory cell becomes negative. Once the threshold voltage reaches a predetermined low value, the memory cell is considered to have been erased and the erase sequence is considered completed. Or succeed. Therefore, 'erasing the memory unit means lowering the threshold voltage of the memory unit, and does not mean completing or successfully erasing the memory. It can be used to fix the memory array, the memory array - or more Erasing is performed by a block or other memory cell unit. The erase voltage signal U(4) is applied with a series of erase voltage pulses, wherein an erase verify operation is performed between each pulse. If an erase is applied The memory cell unit being erased after the voltage pulse is not verified as erased' then another erase voltage pulse can be applied to the P well region. In some embodiments, t is incremented for each subsequent pulse. Erasing voltage The value (eg, in increments of volts 'from 16 volts to 20 volts.) The graph of Figure 11 is shown for a typical erase operation (e.g., under the bias conditions of Figure 1), applying a single During the erase voltage pulse, the voltage at various parts of the ναν〇 string is shown. The example of the figure shows the ideal condition, which ignores the inter-gate capacitance charge _ _ as described below. Curve 41G shows the reception erase The voltage of the voltage signal Verase2p well. The erase voltage pulse causes the p-well to ramp up to 20 volts and then back to the sag. Curves 414 and 412 show the control gate voltage and float of the memory cell of the NAND string. Gate voltage. The floating gate voltage is dependent on the programmed state of the memory cell and is typically below the stagnation before applying the voltage step-down pulse. In the figure, it is assumed that the floating gate voltage is the value "volts" before the first erase voltage pulse. During the entire erase operation, the control gate motor 4]4 is maintained at the stagnation, and the floating gate voltage 109918.doc -28- 1313867 rises in proportion to the voltage of the P-well. The capacitor is planted in the inter-electrode pole and crosses the dielectric region to electrically couple the δ to p well. In Xu > Nan i - A In the scheme, the coupling ratio between the swaying gate and the p-well region of the memory well is about 0. According to this, the floating gate is 412#豳豳+»· Cong·412 is about 50% when the U-coupling ratio is about 0.5:1 with the P-well voltage.) It rises below 摞...β to rise to about 9 volts. The graph in Figure 11 shows that i, the erase potential (Jijing (8) Yu. The first few floating idle poles with p, ,). The erase potential is equal to the p-well voltage (Verase = 2 volts) and the floating gate voltage (v = ^ ^ ^ rase volts) The difference between the two. For the first erase voltage pulse shown in Figure 11, the erase potential is equal to about u, which means 'when the actual erase voltage is pulsed'. ^ changes when the gate is transferred to the P well. As a result, when the pulse is erased = well: to volts, the floating-pole voltage will be different from the voltage applied to the erase voltage gate f. Typically, After the first-erase voltage pulse, the floating voltage poles will have a k × α period voltage. , _ , which corresponds to a negative (destroyed) threshold of the memory unit, and the actual voltage level in the NAND string will be different. Regarding the voltage level described in Figure 2, ideally because of the capacitance-charge coupling between the adjacent floating idle poles and between the gates of the gates, the voltages of the gates, and the gates of the gates. Applying the same memory type 'im', ', under conditions, 'a NAND string of different memory cells are subjected to different erase potentials. Figure 2 provides a cross-sectional view of a string of 8 memory cells. ^1 1 Ώ 一 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 $情邱s, 匕, limbs early, for example, 4, 12, 16 or above) many 109918.doc -29- The invention is applied to a 1313867 NAND structure. As shown in Fig. 12, the memory of the n-series is formed in the p-well region 54A. Each of the memory cells (10), 506 508, 510, 512, 5 14 and 5 16) comprises a stacked gate structure consisting of a control pole (5〇2c, 5〇4c) , 5〇 &, 5〇, 51〇〇, 512., 514〇 and 516(:) with floating gates (5〇2 Bu 5〇4 Bu 5〇6 Bu 51〇f, 512f, 5l4f and 516f The floating gate is formed on the surface of the p-well on the top of the oxide film or other dielectric synthesis film. The control system is above the φ 'over the gate, and the oxide layer or other isolation dielectric Layer control gate

極與浮動閑極分隔。記憶體單元的控 極 字線 WL0、WL1、WL2、乳3、WL4、WL5、WL6/=7A 鄰近記憶體單元之間共用N+擴散區542，藉此使記憶體單元 互相串聯連接而形成一 NAND串。彼等N+擴散區形成該等 記憶體單元令之每一記憶體的源極及汲極。Ν+擴散區 連接至該NAND串的位元線，而Ν+擴散區528連接至多個 NAND串的共同源極線。選擇閘極52〇和522係由相同於記憶 # 體單元的結構所形成’但是閘極區被電連接。 因為電容耦合，所以當在擦除操作期間施加一高擦除電 壓至Ρ井時，浮動之選擇閘極522和52〇上升至高正電位。施 加至ρ井（或其部分）的擦除電壓從該井區耦合至每一選擇閘 極。在許多NAND結構中，可預期90_100%2ρ井電壓耦合 至每一選擇閘極。因此，如果20伏擦除電壓脈衝被施加至ρ 井，則每一選擇閘極上的電壓將上升約〗8伏至2〇伏而達至 18伏至20伏電壓。在圖12中，用箭頭530繪示從ρ井區54〇 至選擇閘極522和520的耦合。NAND串的每一記憶體單元亦 109918.doc -30- 1313867 遭遇到_㈣合效應， 單元之浮動閘極之間的The pole is separated from the floating idle pole. The gate word lines WL0, WL1, WL2, milk 3, WL4, WL5, WL6/=7A of the memory cell share the N+ diffusion region 542 between the adjacent memory cells, thereby connecting the memory cells in series to form a NAND. string. The N+ diffusion regions form the source and drain of each of the memory cells. The Ν+diffusion region is connected to the bit line of the NAND string, and the Ν+diffusion region 528 is connected to the common source line of the plurality of NAND strings. The gates 52A and 522 are selected to be formed by the same structure as the memory cell unit, but the gate regions are electrically connected. Because of the capacitive coupling, the floating select gates 522 and 52A rise to a high positive potential when a high erase voltage is applied to the well during the erase operation. An erase voltage applied to the well (or portion thereof) is coupled from the well region to each of the select gates. In many NAND structures, a 90-100% 2 ρ well voltage can be expected to couple to each select gate. Thus, if a 20 volt erase voltage pulse is applied to the ρ well, the voltage across each of the select gates will rise by about 8 volts to 2 volts to 18 volts to 20 volts. In Figure 12, the coupling from the p-well region 54A to the select gates 522 and 520 is illustrated by arrow 530. Each memory cell of the NAND string also encounters a _(four) junction effect, between the floating gates of the cell, 109918.doc -30- 1313867

閘極電壓之記憶體單元 下，產生約11伏（2〇伏至9伏）之擦除電位。 而言’對於在擦除前具有_丨伏浮動 ，在施加20伏擦除電壓脈衝至p井 NAND串的每—記憶體單元將遭遇到來自鄰近記憶體單 7及/或電晶體的一些電容電荷耦合。此耦合可影響記憶體 早兀之沣動閘極的電位’並且因而影響記憶體單元的擦除 包位。連接至NAND串之第一字線和最後字線（末端字線） 籲的NAND串之末端記憶體單元（例如，圖12中的記憶體單元 502和516)將遭遇到來自鄰近選擇閘極的電容電荷耦合。在 圖12中，用箭頭534繪示從選擇閘極52〇至記憶體單元5〇2 之浮動閘極502f的電容耦合，並且用箭頭538繪示從選擇閘 極522至記憶體單元5丨6之浮動閘極5丨6f的電容耦合。耦合 至記憶體單元502和5 1 6的電壓將使跨彼等記憶體單元之隧 穿介電區（例如，隧穿氧化物）所存在的電場以與各自選擇處 之電壓量成比例方式減小。 箭頭5 3 8和5 3 4所示之耦合係雙向發生，原因係在擦除操 109918.doc 1313867 作期間’選擇閘極亦處於浮動狀態。結果，記 和502的浮動閘極電壓 心 / 選擇間極切和520上的㈣有一 —θ 仁疋’從浮動閘極至選摆門搞沾j人 共Η挥…… 擇閘極的耦合極小於從 ::壤極_合’並且因此，幾乎完 判定選擇閘極電壓。 P开电啟术 在許多NAND實施方安士 方素中，可預期從選擇閘極至1^1^]0串 ^童端記憶體單元之浮動閑極的電容麵合為約2%至5%之 ^如果20伏擦除電屋被施加至P井區，則每-選擇開極 的電厂堅將配合㈣Μ至選擇閉極之輕合而上升约18伏。直 後，由於從選擇開極至鄰近浮動閑極之2_5%輕合，刪 動閑極（例如，5崎502f)上的電麗將上升約0.4至】伏。跨 NAND串之末端記憶體單元的隨穿氧化物之所得電麼將為 約〇·4伏至1伏，其小於圖u所示之理想狀況。請注意，如 上文所述之電容耦合很大夺 柄口很大転度上視下列項目而異：記憶體 =選擇開極的實體尺寸；介於記憶體與選擇閑極之間的間 隔；以及建構中使用的材料介電屬性，諸如随穿介電、介 於控制問極與浮動閑極之間的介電及介於選擇間極與記憶 體单元之間的介電等組份。在一些情況中，舉例而言，如 上文所述之耦合可能大於或小於如上文所述之2_5%範圍。 除了介於鄰近浮動閘極之間的耦合以外，還有一項因數 係介於浮動閘極與鄰近字線或控制閘極之間的耦合。此耦 合亦可能係2-5%之級數，但是視記憶體單元的尺寸及形狀 而可能較大或較小。在一些情況中’尤其係介於選擇問極 與鄰近記憶體單元之間的實體距離相似於介於兩個内側記 109918.doc -32- 1313867 憶體單元之間的距離情況中，… 的耦人n π 4 y ，攸選擇閘極至鄰近浮動閘極 搞入# r円,θ 工制閘極（予線）至浮動閘極的 祸口之乾圍。但是，在捧 閘極相比，與控制閘極與浮動 情體單开M 4如 π方式予以偏壓，所以末端記 口體早7L的沣動閘極電壓 極電塵，並且因此，末維 内側記憶體單元的浮動閑 如下文所述。己憶體單元的擦除電位將較低， 圓^繪示在圖Π)之偏壓條件下，料—擦除操作，在施 ㈣電魏衝期間，對於_Ν細串之典型末端記 ^早以？井£電塵420、浮動閘極電廢似及控制閉極電 ^ ㈣區電心20從G伏上升至峰值職且接著回到0 伏。由於將0伏供應至連接至每—記憶體單元的字線，所以 控制間極電墨424維持在⑽。如同所有的記憶體單元，末 端記憶體單元的浮動閘極係以約.㈣之級數而電_合 P井區田假。又5〇/0耗合時，由於p井區電壓增大至別伏， 所以此電容麵合促使浮動閘極電壓上升約财。此外，末 端記憶體單元還具有耗合至其之鄰近選擇閑極處的電壓之 邛刀。因此，彼等浮動閘極上的電壓將不僅以與其電容 麵合之p井電Μ成比例方式增大，而且還由於來自選擇閉極 的2-5%耦合而增大。在圖13中’假設來自選擇閘極之耦合 將額外1伏加至浮動閘極電壓。據此，相對於圖12所示之理 想狀況的取大值9伏，在擦除電壓脈衝開始時，浮動閘極電 壓422上升至最大值1G伏。圖13的圖表下方提供跨末端記憶 體單元之隧穿介電區的擦除電位。在擦除電壓脈衝開始 109918.doc -33 - 1313867 時，擦除電位係約] 电1知灼10伙，或比理想狀況的η伏擦除電位 約1伏。 _在本文中，一 NAND串中之非相鄰於選擇閘極的記憶體單 几（即，除-NAND串之末端記憶體單元外的所有記憶體單 兀)可ί冉為該NAND串的内側記憶體單元。在圖12中，财勘 串的内側記憶體單元係504、506、508、510、512和514。 虽:然内側記憶體單元將遭遇到來自鄰近浮動閘極的電容搞 • ° ’山而此將減小其擦除電位（如下文所述），但是其程度小於 ^而。己It體單元。因此，内側記憶體單元的運作模式將實 質上如同上文所述的理想狀況，並且具有約11伏之擦除電 位(:又没在擦除電壓脈衝之前，記憶體單元已處於已程式化 狀態且具有約]伏之浮動閘極電壓)。因為與内侧記憶體單 元相比，跨末端記憶體單元之隨穿氧化物層的電位較低’ 、在轭加或多個擦除電壓脈衝之後，末端記憶體單元 之擦除較緩慢並且擦除深度（從其浮動閘極轉移的電子較 # 少）不如内側記憶體單元。 當浮動問極上的電荷高於—預先決定位準（臨限電壓低 於一預先決定位準）時，則NAND串的記憶體單元被驗證為 “除因為至末端§己憶體單元之浮動閘極的額外輕合 7以增加擦除操作的總時間，以充分擦除彼等末端記憶體 早兀。在施加數量為？^個的擦除電壓脈衝後，内側記憶體單 元可被充刀擦除，然而除非施加N+ i個或以上的擦除電壓脈 衝，否則NAND串的末端記憶體單元未被充分擦除。 圖12藉由箭頭536繪示介於之個別記憶體單元之 i099I8.doc -34- 1313867 浮動閘極之間的額外電容耦合效應。舉例而言，介於wl〇 及WL1上之鄰近浮動閘極之間的耦合亦可能係2_5%之級 數，但疋視§己憶體單元的尺寸及形狀而可能較大或較小。 結果，記憶體單元5 16之浮動閘極上所存在的電壓將影響圮 憶體單元514之浮動閘極的電壓，反之亦然。類似的耦合將 存在於連接至WL2的記憶體單元514與5】2之浮動閘極之 間，以此類推。耦合係雙向存在，如箭頭536上的雙箭頭所 示。在各種位準下，在NAND串的所有記憶體單元之間都將 發現到彼等躺合效應，但是由於鄰近控制間極與浮動閉極 上的偏壓電壓不同於選擇閘極上的偏塵條件，所以叙合衝 擊將小㈣末端記憶體單元之衝擊。於擦除㈣脈衝存在 期間，每-浮動閘極的電壓顯著小於選擇閘極處存在的電 壓。因此，由於介於個別記憶體單元之浮動閉極之間的搞 合所導致每一浮動閘極中所引發的電壓量，將小於由於搞 合至鄰近選擇閑極所導致末端記憶體單元之浮動閑極中所 引發的電壓。不過’可預期⑽仙串的每一記憶體單元且有 稍微不同的淨電荷存在於其浮動閉極，並且由於此編合而 具有相對應之不同擦除運作模式。 圖14A繪示在已將資料寫入至記憶體陣列後，一種四狀能 或四級位式記憶體裝置的已擦除⑻與已程式化（A，B，C)臨 限電壓Vy分佈。圓】输+大。^卜 ’’、在已元成擦除操作後的該四狀態 式記憶體裳置。分開緣示内側字線與末端字線的記憶體單 7G之S品限電1^：分你。昨眼Φ间、、 t i佈43 0繪示内側字線之臨限 電壓分佈，其擦除深度深於末端字線(如臨限電屢分佈432 109918.doc -35- ί313867 所不）。在一些NAND記憶體裝置實施方案中，因為來自選 擇閘極的電容電荷耦合，所以肉側記憶體單元之擦除深度 比末端記憶體單元之擦除深度深約〇·5至1伏。内側字線與 末端字線的記憶體單元之擦除深度通常深於所需的深度。 I為了保證在若干寫入/擦除循環後’可用一個擦除電壓脈衝 來擦除所有或大多數記憶體單元，第_擦除電塵脈衝的所 k大小通常大於所需之大小，以在一個脈衝中擦除全新記 憶體褒置(尚未經受許多寫入/擦除循環)的所有記憶體單 70因此，全新記憶體裴置在經受一擦除操作後可具有如 圖14所示之臨限電壓分佈。 田在NAND串層級或以上（例如，對一區塊或其他串單位） 執行若干記憶體單元之擦除驗證時，記憶體單元之間相異 的擦除時間或運作模式可導致過施加應力或過擦除某些^ 憶體單元。舉例而言’當嘗試充分擦除N A N D串的末端記憶 體單元時’可能會過擦除該NAND串的内側記憶體單元 上文所述，内側記憶體單元的擦除速率快於末端記憶體單 元的擦除速率。如果在财仙串層級執行驗證，則該从仙 串將在P井繼續接收擦除電壓脈衝，直到該nand串的每— 記憶體單元被擦除。因&，即使在施加數量少於末端記憶 體單元的《電屡脈衝之後充分擦除内側記憶體單元，内 側記憶體単，將接收額外擦除電壓脈衝’直到該财仙串的 每一記憶體單元被驗證為已擦除。 ’ 端 因為 所以對内側記憶體單元施加的應力大於: 記憶體單元施加的應力。因此末端記憶體單元之較緩; l〇991S.doc -36- 1313867 it、除日寸間可縮短内側$情體單亓芬效—^ 側°己隐體早凡及整個非揮發性記憶體系 的…所以過擦除内側記憶體單元。如此項 孰 ^跨電晶體⑽穿氧化物層施加大電位會施加應力Μ 化物材料。跨隨穿氧化物層施加足夠高的電位，或在若干 時段施加較低電位，最終可導致氧化物層擊穿。 體單元之間相異的擦除運作模式亦可導致增加 =除=作時間，原因係可執行的額外操作變更正被擦除後 ⑯m%的臨限電壓。當擦除快閃記憶體單元時，目 =於所有被擦除之記憶體單μ具有在敎義負臨限電 一耗圍内的負臨限電壓。然而’如所示，擦除程序可導致 「些記憶體單元具有低於該狀義範圍的負臨限電壓。立 後，具有太低臨限電壓的記憶體單元可能未適當程式化了 或可能造成其他記憶體單元未適當程式化（例如，由於增加 1化干擾發生的可能性）。因此，過擦除裝置通常將經受 斤月的軟H私式化。具有在預定義範圍内顯著較低值之臨 限電屢的記憶體單元將接收一少量程式化，使得臨限電塵 t升成為在預定義範圍内。軟性程式化程序需要執行額外 刼作，並且由於軟性程式化通常被視為擦除操作部分，所 以由於增加的擦除時間而降低記憶體效能。 根據一具體實施例，正被擦除之一記憶體單元集合的字 線被剑=成單獨驗證的若干子集，使得可提供額外擦除脈 衝，以選擇具有較緩慢擦除之記憶體單元的字線。在此方 式中，較快速擦除之字線未被過擦除，並且在擦除操作之 後歧集D中所有字線的記憶體單元具有相同（或實質上相 I099I8.doc •37- 1313867 同）臨限電壓分佈。 圖15繪示根據一具體實施例之擦除—記憶體單元集合方 法的流程圖。熟悉此項技術者應明白，根據圖15之^；:， 可並行操作多個NAND串，諸如擦除—區塊之記憶體單元’。 此外，亦可根據所描述之具體實施例來操作其他記憶2單 元單位。在-具體實施例中，對於圖7之擦除步驟⑽，可 執订根據圖15之流程圖的擦除。在—具體實施例中，在控 制器318接收到來自主機的擦除或程式化一記憶體單元^ 合的要求後，執行根據圖15之擦除。 〃 在步驟440，财卿串的位元線、源極線、源極選擇閉極 線及汲極選擇閘極線皆為浮動狀態。在步驟料2，零伏（或 接地）被施加至NAND串的每一字線。步驟44〇及44^使得二 夠擦除整記憶體單元集合，其可包括細D串或並行的多： NAND串。在步驟444，將擦除電壓脈衝u加至—或多 個NAND串的p井區。在步驟州，驗證連接至内側字線之吃 憶體單元的已擦除狀態。排除驗證連接至末端字線的記憶 體早凡’使得僅驗證内側記憶體單元。藉由施加足以開啟 記憶體單元（無論是㈣除該記憶體單元）的㈣，即可排除 驗：末i而子線。此電壓可大於施加至内側字線的擦除驗證 電壓Everify。在步驟446可使用許多電壓位準。舉例而言， 可：用足夠大以開啟經程式化為最高狀態之記憶體單元的 而在一些具體實施例中，稍微大於擦除驗證電壓 的包C即足夠。重點在於，當驗證内側字線時，連接至末 端字線的記憶體單元係傳導狀態。 ^9918.()01 -38· 1313867 在步驟448 ’判定在步驟446是否每一 NAND串被成功驗證 為其内側記憶體單元已被擦除。在一具體實施例中，只有 所有NAND串被成功驗證為其内侧記憶體單元已被擦除，步 驟448及内側記憶體單元擦除才確實成功。在另一具體實施 例中’只有預先決定數量之NAND串被成功驗證為其内側記 憶體單元已被擦除，步驟448及内側記憶體單元擦除才確實 成功。藉由依據預先決定數量之NAND串（而非依據所有 • NAND串）來判定内側記憶體單元擦除為成功，可以驗證程 序可在到達最大擦除迴圈數之前停止（步驟45〇)。這可避免 由於少數難以擦除或有缺陷之NAND串而導致過擦除 NAND串。 如果在步驟448，所有或預先決定數量之NAND串未被成 功驗證，則方法分支至步驟45〇，在此步驟比對一擦除限制 值來檢查驗證計數HVC。驗證計數器係用來限制擦除循環 的反後人數。一項擦除限制實例為8，但是可使用其他值。 如果驗證計數器小於擦除限制值，則將驗證計數器^加 1 ’並且按一第一步進大小或增量值來遞增擦除電壓 脈衝verase之值。在一具體實施例中，係約〇5伏至！ 伏。 β在-具體實施例中，選擇在步驟444所施加的第一擦除電 ί脈衝之振巾田’使付在寫擦除循環前後，在施加第—脈衝 後僅僅t、除連接至内側字線的記憶體單元，而不會被過 擦除。在此方式中，可"力—加γ ^ 中了在一個脈衝中擦除内側記憶體單元， 使付在大夕數時間’僅僅—次反覆進行步驟㈣到州後驗 109918.doc -39- 1313867 證内側記憶體單元。據此，△Vera〗可能係相對小值，以在 需要進一步反覆的案例中（例如，許多寫擦除循環之後）僅僅 擦除内側記憶體單元。關於根據具體實施例可使用之各種 步進大小的細節，將參考圖18A及18B予以論述。 如果該驗證計數器不小於8，則方法進行至步驟452，在 此步驟比較未經驗證之NAND串數量與預先決定數量。如果 未經驗證之NAND串數量小於或等於預先決定數量，則方法 • 進行至步驟458。如果未經驗證之NAND亊數量不小於預先 决疋數置，則在步驟454報告操作失敗狀態。步驟452係選 用步驟。舉例而言，在依據少於所有NAND串來判定步驟料8 心成功的具體實施例中，可忽略步驟4 5 2。 π在步驟448或452的「是」分支之後’内側字線之記憶體 單元已被驗s登為已擦除。此外，由於步驟44〇或446，連接 至正被擦除之該集合所有字線的所有記憶體單元之浮動閘 極電何已增加（隨著電子被移除而使電荷增加）。但是，末端 春記憶體單元尚未被驗證為處於已擦除狀態。如上文所述， 故些末端記憶體單元的擦除速率慢於内側記憶體單元的擦 除速率。因此，經證實較快速之記憶體單元現在被擦除， 因此注意力可指向記憶體元件以提供額外擦除。在此方式 中’在完成擦除操作後’一記憶體單元集合的内側記憶體 單元與末端記憶體單元將被擦除至約相同位準。 在步驟458，驗證計數器vc被重設為零。此外，按第二 增里大小AVERA2來遞增擦除電壓。△Vuw可大於 △VERA】。在一具體實施例十，伏至2伏。較佳 109918.doc -40· 1313867 方式為’選擇八、2以使得在施加一增加位準 電壓脈衝後，在寫/捧除猶 ίτ、除 除。在步驟460,位元線及記憶體單元將被擦 選擇_…線、源極線、源極選擇閘極線及沒極 =擇閉極線再次為浮動狀態。在步驟咐，禁止進—步棒除 側字線，並且啟用末端字線以進行進—步擦除。藉由使 =側字線成為浮動狀態，可禁止於後續擦除_ 擦除内側記憶體單元。藉由施加〇伏至末端字線，可 ^己憶體單元以進行擦除。在設定此條件之後，將增加位 >的第-擦除電璧脈衝施加至該記憶體單元集合。在步驟 466,驗證末端字線的已擦除狀態，同時排除驗證内=字 線。再次，如同步驟446,達成驗證末端字線的已擦除狀態 同寺排除驗》且内側子線之方式為，施加擦除驗證電壓至末 端^線，同時施加足以開啟内側字線（不顧及其狀態）之記憶 體單元的電塵至内側字線。施加至内側字線的電壓將大於 施加至末端字線的擦除驗證電壓。但是，請注意，在一些 具體實施例中，在步驟466可驗證整個的nand串的已擦除 狀態。内側記憶體單元已被驗證為已擦除，並且因此應在 施加擦除驗證電壓下成為傳導狀態。因此，在此替代具體 實施例中’在步驟466驗證NAND串的每一記憶體單元。但 疋’較佳方式為’施加較大電壓至内側記憶體單元，以使 付可僅僅對尚未驗證的末端字線執行驗證。 在步驟468 ’判定每一 NAND串是否已被成功驗證為其末 令而6己憶體單元已被擦除。如同步驟448，當所有NAND串或 僅預先決定數量之N AND串被成功驗證時，可在步驟46 8判 109918.doc -41 - 1313867 定成功。如果所有或預先決定數量之nand串被成功驗證 時，則在步驟470報告通過狀態。如果所有或預先決定數量 之NAND串未被成功驗證，則在步驟472比對該擦除限制值 來檢查驗證§十數器。如果驗證計數器小於擦除限制值，則 方法進行至步驟474，在此步驟將驗證計數器加i，並且按 第二增：!：步進大小△ Vera;3來遞增擦除電壓verase。 在一具體實施例中，ΔνΕΚΑ3之值相同於AVerai之值。在 其他具體實施例中，由於末端記憶體單元擦除較緩慢且可 從較大增量值獲益而加速其擦除，所以大於 △VERA丨。步驟458及474的結果在於，在驗證内側字線之後， 使擦除電壓脈衝大幅增大，以進行第一次施加擦除電壓至 末:記憶體單元。如果需要多次反覆以完全擦除末端記憶 體單兀’則其後在步驟474使擦除電壓脈衝較小幅增大。再 次，下文將論述增量值的細節及替代方案。如果該驗證計 數器不小於8,則在此步驟476比較未經驗證UAnd串數量 與預先決定數量。如同步驟452，步驟稿係選用步驟。如 果未經驗證之NAND由私旦丨ττ ι_ aw串數里小於預先決定數量，則在步驟 〇報Q通過狀態。但是’如果未經驗證之串數量大 於預先決（數量’财步驟454報告失敗狀態。 展示作為擦除操作部分執行之各種子操作的偏壓 表格。爛彻列出用於擦除正被擦除之該集合字線的 子線之5己憶體單元的偏壓條件。欄彻對應於圖㈣步 脉4 4 0至4 4 4。為；坐止 邮單-趙_ 步驟中，藉由從每一字線的所有記憶 月丑單7〇轉移電子，而使I、,主# Μ 1 $ 使其牙動閘極處的電荷增加。位元線、 '099lS.doc -42· 1313867 '、才"線源極選擇閘極線及汲極選擇閘極線皆為浮動狀 態。將〇伏供應至每—字線以啟用其擦除。p井接收擦除電 壓，並且憑藉將0伏施加至字線及將Verase施加至p井所產生 的電位，從該集合中之每一記憶體單元的浮動閘極轉移電 子。 攔482列出僅僅驗證内側字線之已擦除狀態的偏壓條 件。欄482對應於圖15的步驟446。位元線處於浮動狀態， • 而源極線處於V〇D。將足以開啟選擇閘極的正電壓Vsg供應 至汲極選擇閘極線及源極選擇閘極線。VSG典型大於Vdd。 舉例而δ ’在一具體實施例中’ vSG可約4伏至4.5伏。將擦 除驗證電壓（例如，〇伏）提供至内側字線以進行操作。將電 壓vuse,提供至字線WLg及字線WLn。Vusei可能係在如上文所 述之電壓範圍内，但是典型被選擇以確保連接至字線w“ 及WLn之記憶體單元的傳導狀態。舉例而言，可能係 大於一已程式化記憶體單元之任何電位電壓的電壓。但 ® 是，在大多數案例中，由於在施加第一擦除電愿脈衝之後 在定私度上甚至擦除末端記憶體單元，所以使用稍微大於 擦除驗證電壓的電壓即足夠。藉由使用Vuse】作為施加至字 線WU及字線WLn的電壓，使得在步驟446的内側字線驗證 刼作排除末端記憶體單元。為了驗證内側記憶體單元是否 被擦除，攔482的偏壓條件被應用至NAND串並且感測位元 線電壓。如果内側§己憶體單元被充分深度地擦除，則其將 處於開啟狀態並且提供從源極線至位元線的傳導路徑。將 透過NAND串而引發電流，並且位元線電壓將增大。在一段 1099I8.doc -43- 1313867 預先決定時段後，藉由感測放大器來感測或檢查位元線電 j。如果位元線電壓已到達預先決定位準，則内側記憶體 單元被驗證為已擦除。如果内側記憶體單元未被充分深度 地擦除，則其將非處於開啟狀態，並且因此未傳導任何電 流或將傳導太少量電流。結果，位元線電㈣不增大直到 預先決定位準。當在預先決定時段後感測位元線電壓時， 其尚未到達預先決定位準，並且内側記憶體單元未被驗證Under the memory cell of the gate voltage, an erase potential of about 11 volts (2 volts to 9 volts) is generated. In terms of 'having a _ 丨 floating float before erasing, each memory cell that applies a 20 volt erase voltage pulse to the p-well NAND string will encounter some capacitance from the adjacent memory cell 7 and/or transistor. Charge coupled. This coupling can affect the potential of the flip gate of the memory early and thus affect the erased bit of the memory cell. The end memory cells (e.g., memory cells 502 and 516 in Figure 12) of the NAND string connected to the first and last word lines (end word lines) of the NAND string will encounter the neighboring select gates. Capacitive charge coupling. In FIG. 12, capacitive coupling from the select gate 52A to the floating gate 502f of the memory cell 5〇2 is illustrated by arrow 534, and from the select gate 522 to the memory cell 5丨6 is illustrated by arrow 538. The capacitive coupling of the floating gate 5丨6f. The voltages coupled to the memory cells 502 and 516 will cause the electric fields present across the tunneling dielectric regions (e.g., tunneling oxides) of the memory cells to be reduced in proportion to the amount of voltage at the respective selection. small. The couplings shown by arrows 5 3 8 and 5 3 4 occur bidirectionally because the selection gate is also floating during erase operation 109918.doc 1313867. As a result, the floating gate voltage/selection between the sum of 502 and the (4) of 520 have a θ 疋 疋 从 从 从 从 从 从 从 从 从 从 从 从 从 从 从 从 从 从 从 从 从 从 从 从 从 从 从 从 从 从 从 从 从 从 从 从In the following:: the soil pole _ _ ' and therefore, almost complete determination of the selection of the gate voltage. In many NAND implementations, it is expected that the capacitance of the floating idler from the selection gate to the 1^1^]0 string ^child memory unit is about 2% to 5%. ^ If a 20 volt erasing house is applied to the P well zone, each of the power plants selected to open will cooperate with (4) Μ to select the closed polarity and rise by about 18 volts. Straight, due to the 2_5% of the selection from the open pole to the adjacent floating idler, the battery on the idle pole (for example, 5 502f) will rise by about 0.4 to volts. The resulting oxide across the end memory cell of the NAND string will be about 4 volts to 1 volt, which is less than the ideal condition shown in Figure u. Note that the capacitive coupling as described above is very large and varies greatly depending on the following items: memory = physical size of the selected opening; spacing between the memory and the selected idle; The dielectric properties of the material used in the construction, such as the dielectric, the dielectric between the control and the floating idler, and the dielectric between the selected interpole and the memory cell. In some cases, for example, the coupling as described above may be greater or less than the range of 2 - 5% as described above. In addition to the coupling between adjacent floating gates, there is a factor between the floating gate and the adjacent word line or control gate. This coupling may also be a 2-5% order, but may be larger or smaller depending on the size and shape of the memory unit. In some cases, the coupling distance between the selection and the adjacent memory unit is similar to the distance between the two inner sides of the 109918.doc -32-1313867 memory unit. The person n π 4 y , 攸 selects the gate to the adjacent floating gate to engage the # r円, θ working gate (pre-line) to the dry gate of the floating gate. However, compared with the control gate and the floating body single open M 4 as the π mode is biased, the end gate body is 7L early, the swing gate voltage is extremely dust, and therefore, the last dimension The floating of the inner memory unit is as described below. The erase potential of the memory unit will be lower, and the circle is shown under the bias condition of the figure ,), the material-erase operation, during the application of the (four) electric Wei, the typical end of the _Ν string is recorded ^ Early? Wells, electric dust 420, floating gates, and control of closed-circuit power ^ (4) Zone core 20 rises from G volts to peak position and then back to 0 volts. Since 0 volts is supplied to the word line connected to each of the memory cells, the control interelectrode 424 is maintained at (10). Like all memory cells, the floating gate of the terminal memory cell is electrically connected to the P well zone. When 5 〇/0 is consumed, the voltage of the p-well increases to volts, so the capacitance of the capacitor causes the floating gate voltage to rise. In addition, the end memory unit also has a file that is consuming the voltage adjacent to its selected idle pole. Therefore, the voltage on their floating gates will not only increase in proportion to the p-well, which is in contact with their capacitance, but also increase due to the 2-5% coupling from the selective closed-pole. In Figure 13, it is assumed that the coupling from the selected gate adds an additional 1 volt to the floating gate voltage. Accordingly, the floating gate voltage 422 rises to a maximum value of 1 GV at the start of the erase voltage pulse with respect to the ideal value shown in Fig. 12 having a large value of 9 volts. The erase potential across the tunneling dielectric region of the end memory cell is provided below the graph of Figure 13. At the beginning of the erase voltage pulse 109918.doc -33 - 1313867, the erase potential is about 1 volt, or about 1 volt than the ideal condition of the η volt erase potential. _ In this paper, a single memory of a NAND string that is not adjacent to the select gate (ie, all memory cells except the end memory cell of the -NAND string) can be the NAND string. Inner memory unit. In Fig. 12, the inner memory unit units 504, 506, 508, 510, 512, and 514 of the financial series. Although the inner memory unit will encounter a capacitor from the adjacent floating gate, it will reduce its erase potential (as described below), but to a lesser extent than ^. It has a body unit. Therefore, the mode of operation of the inner memory cell will be substantially the same as described above, and has an erase potential of about 11 volts (the memory cell is already in a programmed state before the erase voltage pulse). And has a floating gate voltage of about ] volts). Because the potential of the follow-through oxide layer across the end memory cell is lower than the inner memory cell, after the yoke plus or multiple erase voltage pulses, the erase of the end memory cell is slower and erased. The depth (the electrons transferred from its floating gate is less than #) is not as good as the inner memory unit. When the charge on the floating pole is higher than the pre-determined level (the threshold voltage is below a predetermined level), then the memory cell of the NAND string is verified as "distributed to the floating gate to the end § memory unit" The extra light is added to increase the total time of the erase operation to fully erase the end memory of the end memory. After applying the erase voltage pulse of the number, the inner memory unit can be cleaned by the knife. Except, however, the end memory cells of the NAND string are not sufficiently erased unless N+i or more erase voltage pulses are applied. Figure 12 shows i099I8.doc between the individual memory cells by arrow 536. 34- 1313867 Additional Capacitance Coupling Effect Between Floating Gates. For example, the coupling between adjacent floating gates on wl〇 and WL1 may also be in the order of 2_5%, but derogatory The size and shape of the cell may be larger or smaller. As a result, the voltage present on the floating gate of memory cell 5 16 will affect the voltage of the floating gate of memory cell 514, and vice versa. A similar coupling will Exist in memory connected to WL2 Between the floating cells of the body unit 514 and 5], and so on. The coupling system exists in both directions, as indicated by the double arrow on arrow 536. Under various levels, between all the memory cells of the NAND string The reclining effect will be found, but since the bias voltage on the adjacent control pole and the floating closed pole is different from the dusty condition on the selected gate, the combined impact will be the impact of the small (four) end memory unit. (d) During the presence of the pulse, the voltage of each-floating gate is significantly less than the voltage present at the selected gate. Therefore, each floating gate is induced by the interaction between the floating closed poles of the individual memory cells. The amount of voltage will be less than the voltage induced in the floating idle pole of the end memory cell due to the engagement to the adjacent selected idle pole. However, each memory cell of the (10) fairy string can be expected to have a slightly different net charge. It exists in its floating closed pole and has a corresponding different erase operation mode due to this combination. Figure 14A shows a quadruple or quadruple position after data has been written to the memory array. The erased (8) and programmed (A, B, C) threshold voltage Vy distribution of the memory device. The circle] loses + large. ^b'', the four-state memory after the element has been erased The body is placed. The memory of the inner word line and the end word line is separated. The S product of the 7G is limited to 1^: you. The eye Φ, ti cloth 43 0 shows the threshold voltage distribution of the inner word line. , the erase depth is deeper than the end word line (such as the limited current distribution 432 109918.doc -35- ί313867). In some NAND memory device implementations, because of the capacitive charge coupling from the selected gate, The erase depth of the meat side memory cell is about 至5 to 1 volt deeper than the erase depth of the end memory cell. The erased depth of the memory cells of the inner word line and the end word line is usually deeper than the desired depth. In order to ensure that all or most of the memory cells can be erased by one erase voltage pulse after several write/erase cycles, the size of the first erased dust pulse is usually larger than the required size to All memory banks that erase a new memory device (not yet subjected to many write/erase cycles) in one pulse. Therefore, the new memory device can have the appearance shown in Figure 14 after undergoing an erase operation. Limited voltage distribution. When the NAND string level or above (for example, for a block or other string unit) performs the erase verification of several memory cells, the different erase time or mode of operation between the memory cells may cause overstressing or Over erase some ^ memory unit. For example, 'When attempting to fully erase the end memory cells of the NAND string, the internal memory cells of the NAND string may be erased. The erase memory of the inner memory cells is faster than the end memory cells. The erase rate. If verification is performed at the level of the string, the slave string will continue to receive the erase voltage pulse at the P well until each memory cell of the nand string is erased. Because &, even if the inner memory unit is sufficiently erased after the number of applied electric pulses is less than the end memory unit, the inner memory 単 will receive an additional erase voltage pulse until each memory of the cemetery string The body unit is verified to have been erased. Because the stress applied to the inner memory cell is greater than: the stress applied by the memory cell. Therefore, the end memory unit is slower; l〇991S.doc -36- 1313867 it, in addition to the day and the inch can shorten the inner side of the singularity of the singularity of the sputum - ^ side of the hidden body and the entire non-volatile memory system... Therefore, the inner memory unit is erased. If this is the case, a large potential is applied across the transistor (10) through the oxide layer to apply a stress telluride material. Applying a sufficiently high potential across the oxide layer, or applying a lower potential over a period of time, can ultimately lead to breakdown of the oxide layer. Different erase modes of operation between body units can also result in an increase of = divide = time, because the additional operational changes that can be performed are 16 m% of the threshold voltage after being erased. When the flash memory cell is erased, the target memory μ of all erased memories has a negative threshold voltage within a drain of the negative current limit. However, as shown, the erase procedure can result in "some memory cells having a negative threshold voltage below this range. After that, memory cells with too low threshold voltage may not be properly programmed or possible. Causes other memory cells to be improperly stylized (eg, due to increased likelihood of interference). Therefore, over-erasing devices will typically be subjected to soft H-privatization for a few months. Significantly lower in a predefined range The value of the memory unit will receive a small amount of stylization, so that the threshold is upgraded to a predefined range. Soft stylized programs need to perform additional operations, and because of soft stylization is usually considered Erasing the operational portion, thereby reducing memory performance due to increased erase time. According to one embodiment, the word line of a set of memory cells being erased is Sword = several subsets of individual verification, such that An additional erase pulse is provided to select a word line having a slower erased memory cell. In this manner, the faster erased word line is not over erased and is in an erase operation The memory cells of all word lines in the rear disposition set D have the same (or substantially phase I099I8.doc • 37-1313867) threshold voltage distribution. Figure 15 illustrates an erase-memory cell set in accordance with an embodiment. A flow chart of the method. It should be understood by those skilled in the art that, according to FIG. 15, a plurality of NAND strings, such as an erase-block memory unit, can be operated in parallel. The embodiment operates other memory 2 unit units. In a particular embodiment, for the erasing step (10) of Figure 7, the erasure according to the flow chart of Figure 15 can be performed. In a particular embodiment, at controller 318 After receiving the request from the host to erase or program a memory cell, the erasing according to Fig. 15 is performed. 〃 In step 440, the bit line, the source line, and the source of the fiscal string are closed. Both the line and drain select gate lines are in a floating state. At step 2, zero volts (or ground) is applied to each word line of the NAND string. Steps 44 and 44^ enable two to erase the entire memory cell. Collection, which can include thin D strings or multiple parallel: NAND strings At step 444, the erase voltage pulse u is applied to - or the p-well region of the plurality of NAND strings. In the step state, the erased state of the memory cell connected to the inner word line is verified. Excluding the verification connection to the terminal word The memory of the line is 'previously' to verify only the inner memory unit. By applying (4) enough to turn on the memory unit (whether (4) except the memory unit), the test can be eliminated: the last i and the sub-line. Greater than the erase verify voltage Everify applied to the inner word line. A number of voltage levels can be used in step 446. For example, it can be: large enough to turn on the memory unit that is programmed to the highest state, and in some implementations In the example, a packet C slightly larger than the erase verify voltage is sufficient. The important point is that when the inner word line is verified, the memory cell connected to the end word line is in a conduction state. ^9918.()01 -38· 1313867 At step 448', it is determined at step 446 whether each NAND string was successfully verified as its inner memory unit has been erased. In one embodiment, only all of the NAND strings are successfully verified as their inner memory cells have been erased, and step 448 and the inner memory cell erase are indeed successful. In another embodiment, only a predetermined number of NAND strings are successfully verified as their inner memory cells have been erased, and step 448 and the inner memory cell erase are indeed successful. By determining that the inner memory cell erase is successful based on a predetermined number of NAND strings (rather than on all • NAND strings), it can be verified that the program can be stopped before the maximum erase loop number is reached (step 45A). This avoids over-erasing NAND strings due to a small number of NAND strings that are difficult to erase or defective. If, at step 448, all or a predetermined number of NAND strings are not successfully verified, then the method branches to step 45, where the check limit HVC is checked against an erase limit value. The verification counter is used to limit the number of people behind the erase cycle. An instance of the erase limit is 8, but other values can be used. If the verify counter is less than the erase limit value, the verify counter ^ is incremented by 1 ' and the value of the erase voltage pulse verase is incremented by a first step size or increment value. In one embodiment, the system is about 5 volts to! Volt. In a specific embodiment, the selection of the first erasing electric ί pulse applied in step 444 is made before and after the write erase cycle, after the application of the first pulse, only t, except for the connection to the inner word Line memory cells without being erased. In this way, the inner memory unit can be erased in one pulse in the force-plus γ ^, so that the time is repeated only in the time of the big eve. (4) to the state after the test 109918.doc -39 - 1313867 Card internal memory unit. Accordingly, ΔVera may be relatively small in value to erase only the inner memory cells in cases where further reversal is required (e. g., after many write erase cycles). Details regarding the various step sizes that may be used in accordance with a particular embodiment will be discussed with reference to Figures 18A and 18B. If the verification counter is not less than 8, the method proceeds to step 452 where the number of unverified NAND strings is compared to a predetermined number. If the number of unverified NAND strings is less than or equal to the predetermined number, then the method proceeds to step 458. If the number of unverified NAND ports is not less than the predetermined number, the operation failure status is reported in step 454. Step 452 is an optional step. For example, in a particular embodiment in which it is determined that less than all of the NAND strings are successful, step 425 can be omitted. π After the "YES" branch of step 448 or 452, the memory cell of the inner word line has been verified as being erased. In addition, due to step 44A or 446, the floating gates of all of the memory cells connected to all of the word lines of the set being erased have increased (the charge is increased as the electrons are removed). However, the end Chun memory unit has not been verified to be in an erased state. As noted above, the erase rate of the end memory cells is slower than the erase rate of the inner memory cells. Thus, memory cells that have proven to be faster are now erased, so attention can be directed to memory elements to provide additional erasure. In this mode, the inner memory unit and the end memory unit of a memory cell set will be erased to about the same level after the erase operation is completed. At step 458, the verification counter vc is reset to zero. In addition, the erase voltage is incremented by the second increment size AVERA2. △Vuw can be greater than △VERA]. In a specific embodiment ten, it is volts to 2 volts. Preferably, 109918.doc -40· 1313867 is selected as '8', so that after applying an increased level voltage pulse, it is written/removed and removed. At step 460, the bit line and the memory cell are erased to select the _... line, the source line, the source select gate line, and the immersion = select pole line again in a floating state. In step 咐, the step bar is disabled from the side word line and the end word line is enabled for further step erase. By causing the = side word line to be in a floating state, subsequent erasing_ erasing of the inner memory cell can be prohibited. By applying a sag to the end word line, the body unit can be recalled for erasing. After setting this condition, a first-erase electric pulse of the addition bit > is applied to the set of memory cells. At step 466, the erased state of the end word line is verified while the verify internal = word line is excluded. Again, as in step 446, the method of verifying the erased state of the end word line is the same as the temple exclusion and the inner sub-line is applied by applying an erase verify voltage to the end line while applying enough to turn on the inner word line (regardless of State) The electric dust of the memory unit to the inner word line. The voltage applied to the inner word line will be greater than the erase verify voltage applied to the end word line. However, please note that in some embodiments, the erased state of the entire nand string can be verified at step 466. The inner memory cell has been verified to have been erased and should therefore be in a conductive state upon application of the erase verify voltage. Thus, in this alternative embodiment, each memory cell of the NAND string is verified at step 466. However, 较佳' is preferably applied to apply a larger voltage to the inner memory unit so that verification can be performed only on the end word line that has not been verified. At step 468' it is determined whether each NAND string has been successfully verified as its command and the 6-member cell has been erased. As in step 448, when all of the NAND strings or only a predetermined number of N AND strings are successfully verified, the determination of 109918.doc -41 - 1313867 can be successful in step 46 8 . If all or a predetermined number of nand strings are successfully verified, then the pass status is reported in step 470. If all or a predetermined number of NAND strings have not been successfully verified, then at step 472, the § decator is checked against the erase limit value. If the verification counter is less than the erase limit value, the method proceeds to step 474 where the verification counter is incremented by i and the erase voltage verase is incremented by the second increment: !: step size Δ Vera; In a specific embodiment, the value of ΔνΕΚΑ3 is the same as the value of AVerai. In other embodiments, the end memory cell is greater than ΔVERA丨 because it is slower to erase and can be accelerated from larger increments. The result of steps 458 and 474 is that after verifying the inner word line, the erase voltage pulse is substantially increased to perform the first application of the erase voltage to the memory cell. If multiple iterations are required to completely erase the end memory unit 兀' then the erase voltage pulse is increased by a small increase at step 474. Again, the details and alternatives to the delta values are discussed below. If the verification counter is not less than 8, then at this step 476 the number of unverified UAnd strings is compared to the predetermined number. As in step 452, the step draft is the selection step. If the unverified NAND is less than the predetermined number by the private 丨ττ ι_ aw string, the Q pass status is reported in the step. But 'if the number of unverified strings is greater than the pre-determined (quantity's step 454 report failure status. Demonstrate the bias table for the various sub-operations performed as part of the erase operation. Rough list for erasing is being erased The sub-line of the set word line has a bias condition of 5 elements of the unit cell. The column corresponds to the step (4) of the step 4 4 0 to 4 4 4; for the sit-up mail order - Zhao _ step, by All memory lines of each word line transfer electrons, and I, the main # Μ 1 $ increase the charge at the tooth gate. The bit line, '099lS.doc -42· 1313867 ', The line source selection gate line and the drain selection gate line are all floating. The squat is supplied to each word line to enable its erase. The p well receives the erase voltage and applies 0 volts. To the word line and the potential generated by applying Verase to the p-well, electrons are transferred from the floating gate of each memory cell in the set. Block 482 lists the bias conditions that only verify the erased state of the inner word line. Column 482 corresponds to step 446 of Figure 15. The bit line is in a floating state, • and the source line is at V〇D A positive voltage Vsg sufficient to turn on the select gate is supplied to the drain select gate line and the source select gate line. The VSG is typically greater than Vdd. For example, δ 'in a particular embodiment, 'vSG can be about 4 volts to 4.5 volts. An erase verify voltage (eg, a ramp) is provided to the inner word line for operation. The voltage vs is supplied to word line WLg and word line WLn. Vusei may be within the voltage range as described above, but typically Selected to ensure the conduction state of the memory cell connected to word line w" and WLn. For example, it may be greater than the voltage of any potential voltage of a programmed memory cell. But ® is, in most cases It is sufficient to use a voltage slightly larger than the erase verify voltage, since the voltage is slightly larger than the erase verify voltage after the first erase power pulse is applied. Therefore, by using Vuse as the word line WU and The voltage of word line WLn causes the inner word line verification at step 446 to eliminate the end memory unit. To verify whether the inner memory unit is erased, the bias condition of block 482 is applied to the NAND string and Sensing the bit line voltage. If the inner § memory cell is sufficiently deeply erased, it will be in the on state and provide a conduction path from the source line to the bit line. The current will be induced through the NAND string, and the bit The line voltage will increase. After a predetermined period of time from 1099I8.doc -43 to 1313867, the bit line power is sensed or checked by the sense amplifier. If the bit line voltage has reached a predetermined level, then The inner memory cell is verified to have been erased. If the inner memory cell is not sufficiently deeply erased, it will not be in an on state and therefore will not conduct any current or will conduct too little current. As a result, the bit line power (4) does not increase until the level is predetermined. When the bit line voltage is sensed after a predetermined period of time, it has not reached the predetermined level, and the inner memory unit is not verified.

為已擦除。 —欄4 8 4列出用於僅擦除連接至正被擦除之該集合的末端 子線之記憶體單元的偏壓條件。攔484對應&圖Μ的步驟 460至464。如同擦除所有字線，位元線、源極線、源極選 擇閘極線及汲極選擇閘極線皆為浮動狀態。此外，將擦除 電[Verase供應至p井。為了禁止進一步擦除内側字線的記憶 體單元（其已被驗證為已擦除），内側字線為浮動狀態，並且 將〇伏供應至末端字線。在此方式中，㈣字線將麵合至p 、、’且引起％連接至内側字線的記憶體單元之隨穿介電 ^無擦除電位。但是，葬由Α 精由細加〇伙至末端字線，彼等記憶 肢早元將被啟用以進行擦除。因&，當將擦除電壓脈衝施 加至p井時’僅末端字線的記憶體單元被擦除。 攔4 8 6列出驗證末端京綠 娜對應於圖！ 5的步驟466 /除狀態的偏壓條件。攔 _ 如同攔482之内側字線驗證操 '位7L線處於斤動狀態，而源極線處於％。p井被接地， 、'且藉由繼SG而開啟沒極選擇問極線及源極選擇間極 、'為了驗也末i»而予線，同時排除驗證内側字線，擦除驗 I09918.doc -44 - 1313867 證電壓（例如，〇伏）被施加至字線WLq及WLn，同時將電壓Is erased. - Column 4 8 4 lists the bias conditions for erasing only the memory cells connected to the end stubs of the set being erased. Block 484 corresponds to steps 460 through 464 of & Just like erasing all word lines, the bit line, source line, source select gate line, and drain select gate line are all floating. In addition, the electricity will be erased [Verase supplied to the p well. To inhibit further erasing of the memory cells of the inner word line (which have been verified as erased), the inner word line is floating and the stagnation is supplied to the end word line. In this manner, the (four) word line will face to p, ' and cause the % of the memory cell connected to the inner word line to have a erase potential. However, the funeral will be activated by the fine-grained gang to the end word line, and their memory limbs will be enabled for erasure. Because &, when the erase voltage pulse is applied to the p-well, only the memory cells of the end word line are erased. Block 4 8 6 lists the verification end Jing Lu Na corresponds to the map! Step 466 of 5 / except the state of the bias condition. Block _ Like the inner word line verification operation of 482. The bit 7L line is in the pulsating state, and the source line is in %. The p well is grounded, 'and by the SG to open the immersive selection of the pole line and the source selection pole, 'for the end of the test i» and the line, while eliminating the verification of the inner word line, erase the test I09918. Doc -44 - 1313867 The voltage (eg, crouching) is applied to word lines WLq and WLn while the voltage is applied

Vuse丨知:供至内側子線〇 Vusel將確保内側字線之記憶體單元 的傳導狀態，促使可以測試僅末端字線的已擦除狀態。如 果末端記憶體單元被充分擦除，則在施加Ever*電壓下將開 啟末端記憶體單元。位元線電壓將增大直到或超過預先決 定位準’其指示末端記憶體單元被擦除。如果末端記憶體 單兀未被充分擦除，則其將維持關斷狀態或至少在施加Vuse :: Provided to the inner sub-wire 〇 Vusel will ensure the conduction state of the memory cells of the inner word line, prompting the test of the erased state of only the end word line. If the end memory cell is sufficiently erased, the end memory cell will be turned on when the Ever* voltage is applied. The bit line voltage will increase until or beyond the pre-determined alignment' indicating that the end memory cell is erased. If the end memory unit is not sufficiently erased, it will remain off or at least apply

Everify電壓下未被充分開啟。位元線電壓將不增大到預先決 定位準，其指示末端記憶體單元尚未被擦除。如上文所述， 由於先前已在步驟446驗證内側記憶體單元，所以可視需要 驗證整個NAND串。因此，由於内側字線應在擦除驗證電壓 下為傳導狀態’所以應將擦除驗證電壓施加至内側字線， 以進行末端字線驗證。但是，可能有益的做法係，供應Vuw 以確保傳導狀態’以便僅測試末端記憶體單元的已擦除狀 態。 圖1 7 A至17C繪示根據具體實施例之一記憶體單元集合 的改良式擦除臨限電壓分佈。圖i 7 A繪示在已將資料寫入至 記憶體陣列後，一種四級位式NAND記憶體裝置的已擦除與 已私式化臨限電壓分佈。圖1 7B緣示在施加一單一擦除電愿 脈衝完成後，該記憶體裝置之記憶體單元的已擦除臨限電 壓分佈。舉例而言’圖1 可對應於已按照圖1 6之欄480之 偏£條件元成圖1 5之步驟4 4 4的時間。典型地，並且如圖1 7 b 所不’在施加一第一擦除電壓脈衝後，僅内側字線（如臨限 電壓分佈430所示）的記憶體單元被充分擦除。末端字線（如 109918.doc -45- 1313867 臨限電Μ分佈432所示）的記憶體單元已從其浮動閘極移除 負電荷，但不足以使其處於實際已擦除狀態。此歸因於·· 因為介於選擇閘極與末端字線之浮動閘極之間的耦合，所 以不同字線的擦除運作模式相異。圖17C綠示已將額外擦除 脈衝僅施加至正被擦除之該集合的末端字線後，記憶體單 元子集的已擦除臨限電壓分佈。舉例而言，圖i7c可對應於 完成圖15之步驟464之後的時間。這可能係在一個額外擦除 # 脈衝已被施加至末端字線之後，5戈已透過多次反覆進行步 驟460至474來施加多個擦除脈衝之後。由於使用圖^及^ 所示之方法’所以内側字線及末端字線已將其所連接的記 憶體單元擦除至-相似的臨限電壓。因此，已防止由於較 緩慢擦除之末端字線造成過擦除内側中間字線。藉由劃分 不同記憶體單it子集之驗證，已補償相異之擦除運作模 式’使得所有記憶體單元最終皆處於約相同的臨限 佈。 _ 在其他具體實施例中，可用不同方式來進行一ΝΑΝ〇串之 字線劃分。舉例而言，一 N A N D串的兩個最末端字線（例如， 机。、WLl、WWi和WLn)可被分組在—起為末端字線，並 j其餘字線（WL2至WLn.2)m在一起為内側字線。在此 一具體實施例中，圖15的步驟446將包括驗證字線％至 乳η-m將執行步驟462及466以進—步擦除及驗證字線 :L〇、WLl、WL㈠和乳〆在另—項具體實施例中，可將 /、個或六個以上字線分組在一起為末端字線。亦可實施其 他的分組方式。 109918.doc -46- 1313867 圖18A及18B繪示根據各項具體實施例可使用的擦除電 壓tfi號。圖18績示-具有量值Ve_之第—擦除電麗脈衝 _Sei。第-脈衝可能係在圖15之步驟4料施加至正被擦除 之该記憶體單元集合的第一脈衝。此脈衝係用於擦除該集 =之所有記憶體單元。在-些具體實施例中，擦除脈衝的 弟-值可能係約15伏至20伏。在一具體實施例中，較佳方 式為’選擇第一擦除脈衝之量值之方式係，促使在寫/擦除 :環前後’在施加單一擦除電壓脈衝後，將僅僅擦除内側 字線上的記憶體單元（並且不會被過擦除p但是，在寫/擦 除循％後，或由於個別建構之記憶體裝置的參數相異，在 第一脈衝後可能未擦除所有内側記憶體單元。在其他具體 實施例中’可選擇第-擦除電壓脈衝，促使僅在寫/擦除循 環後，或僅在有限次數寫/擦除循環期間，在施加第一脈衝 後，將擦除内側記憶體單元。在延續之寫/擦除循環後，可 能需要更多脈衝。此項技術可在寫/擦除循環開始時減小過 擦除，代價為在延續之寫/擦除循環後有更多擦除電壓脈 衝。 如圖1 8 A所示，在内側字線被成功驗證為已擦除之前施加 第二脈衝pulse?。擦除電壓訊號係按步進大小Δν^Αΐ從 pulse]遞增至pulse2。按ΔνΕ11Α〗遞增對應於圖15的步驟456。 在一具體實施例中，ΔνΕΙΙΑ1可能係約0·5伏至丨伏。施加第 一擦除電壓脈衝後’所有内側字線被成功驗證。此可對應 於圖1 5的步驟448。在驗證所有内側字線後，僅繼續擦除末 端s己憶體單元。彼等記憶體單元擦除較緩慢，因此按第二 109918.doc -47- 1313867 較大增量步進大小來遞增擦除電壓訊號，用於施加 第二擦除電壓脈衝pulse3。此可對應於圖15的步驟458。較 佳方式為，在一具體實施例中，選擇以使得在施加 第一擦除電壓脈衝（例如，pulsed後，在寫/擦除循環前後， 僅僅末端記憶體單元（所有末端記憶體單元）將被擦除。在一 體貫知例中，ΔνΕΙΙΑ2為約2伏。施加pU〗se3對應於圖15的 步驟464。其後，按第三步進大小來遞增脈衝。此對 • 應於圖15的步驟474。在一具體實施例中，ΔνΕΙΙΑ3可等於（或 在其他具體實施例中，可大於或小於）△ Vera ^。 圖18B繪示擦除電壓訊號之替代具體實施例，當執行圖15 之方法時可使用該擦除電壓訊號。在此具體實施例中，第 一擦除電壓脈衝被選擇為大於第二脈衝。選擇第一擦除電 壓脈衝Pulsei，以引發大電壓偏移（例如，約6伏）。仍然理 想地選擇此擦除電壓脈衝，使得在一定數量之寫/擦除循環 刖後，在施加單一脈衝後，内側記憶體單元將被擦除。但 • X應明白’在一些案例中’可用一個以上脈衝以擦除所 有内側記憶體單元。在其他具體實施例中，可選擇第一擦 除電壓脈衝，促使僅在寫/擦除循環後，或僅在有限次數寫 /擦除循環期間，在施加第一擦除電壓脈衝後，將擦除内側 記憶體單元。在延續之寫/擦除循環後，可能需要更多脈 衝。在圖1 8B之具體實施例中，在所有内側記憶體單元被驗 為已擦除之如，需要第二脈衝及第三脈衝。第二擦除電 壓脈衝pul%比pulseH、一步進大小。遞減擦除電壓 訊號亦對應於圖15的步驟456。但是，按ΔνΕκΑ4之大小來遞 Ϊ099 丨 8.doc -48- 1313867 減（而非遞增）擦㊉電麼Μ。這確保在施加帛二擦除電壓脈 • 衝後’内側記憶體單元未被擦除。使第二脈衝較小，以引 -#記憶體單元之臨限電塵較小偏移。如果需要第三擦除電 塵脈衝（如Ρ—所示），則可按步進大小Μ助來遞增脈 衝’以確保繼續從彼等記憶體單元的浮動閘極轉移電子。 施加第三擦除電壓脈衝後，内側記憶體單元被驗證為已 擦除。圖·之其餘部分相同於圖18Α。自前—擦除電遷脈 • 衝大小按量值來遞增第四擦除電屡脈衝pulSe4,1被 施加至僅末端記憶體單元。此對應於圖Η的步驟458。在圖 1敝具體實施例中’需要額外擦除電壓脈衝以擦除末端記 憶體早兀。因此’按高於第四擦除電壓脈衝值之值 來遞增第五擦除電壓脈衝pulse5。在―具體實施例中，在施 加第-擦除電壓脈衝pulsei後，第二擦除電壓脈衝p—之 大^可能相同於pulsei之大小，而非遞減其大小。在此—具 體貫施例中’其後用以擦除内側記憶體單元所需的任何擦 • 除電壓脈衝將按值ΔνΕΚΑ1予以遞增，如所示。 圖19繪示根據一具體實施例之執行圖15之步驟—的流 紅圖。在圖1 9中，按圖丨8Β之擦除電壓脈衝所示來執行步驟 在圖1 5之步驟45 〇中，首先在步驟49〇判定驗證計數器 VC疋否等於零’其指示出迄今僅一個擦除電壓脈衝已被施 加至忒6己憶體早兀集合。如果驗證計數器等於零(其指示出 這疋弟一次改變擰险| @ # 文①Lf、電壓脈衝之大小），則方法進行至步驟 492在此步驟按值來遞減擦除電壓脈衝大小。這將 會導致在下次反覆操作期間施加—似之脈衝。但是， I09918.doc -49- 1313867 如果驗證計數器不等於零（其指示出這是第二次或多次改 變擦除電壓訊號)’則方法進行至步驟494,在此步驟按 △vERA1來遞增擦除電壓訊號’因而導致似圖刚之的 脈衝k步驟492及494,該方法再次進行到圖丨5之步驟44〇。The Everify voltage is not fully turned on. The bit line voltage will not increase to a pre-determined alignment indicating that the end memory cell has not been erased. As described above, since the inner memory cells have been previously verified at step 446, the entire NAND string can be verified as needed. Therefore, since the inner word line should be in a conducting state at the erase verify voltage', an erase verify voltage should be applied to the inner word line for end word line verification. However, it may be beneficial to supply Vuw to ensure conduction state' so as to test only the erased state of the end memory cells. Figures 177A through 17C illustrate an improved erase threshold voltage distribution for a set of memory cells in accordance with a particular embodiment. Figure i 7A shows the erased and private threshold voltage distribution of a four-level NAND memory device after data has been written to the memory array. Figure 7B illustrates the erased threshold voltage distribution of the memory cells of the memory device after the application of a single erased electrical pulse is completed. For example, Fig. 1 may correspond to the time that has been subjected to step 4 4 4 of Fig. 15 in accordance with the conditional condition of column 480 of Fig. 16. Typically, and as shown in Figure 177, after a first erase voltage pulse is applied, only the memory cells of the inner word line (as indicated by threshold voltage distribution 430) are sufficiently erased. The memory cell of the end word line (shown as 109918.doc -45-1313867 threshold 432) has removed the negative charge from its floating gate, but not enough to put it in an actually erased state. This is attributed to the fact that the erase mode of operation of the different word lines is different because of the coupling between the select gate and the floating gate of the end word line. Figure 17C Green shows the erased threshold voltage distribution of the memory cell subset after the additional erase pulse has been applied only to the end word line of the set being erased. For example, Figure i7c may correspond to the time after completion of step 464 of Figure 15. This may be after an additional erase # pulse has been applied to the end word line, after 5 gram has been applied repeatedly to steps 460 through 474 to apply a plurality of erase pulses. Since the method shown in Figs. 2 and ^ is used, the inner word line and the end word line have erased the memory unit to which they are connected to a similar threshold voltage. Therefore, over-erasing of the inner middle word line due to the slower erased end word line has been prevented. By dividing the verification of different memory single-it subsets, the disparate erase operation mode has been compensated so that all memory cells are ultimately at about the same threshold. _ In other embodiments, the word line division of a string can be performed in different ways. For example, the two most end word lines of a NAND string (eg, machine, WL1, WWi, and WLn) can be grouped together as the end word line, and the remaining word lines (WL2 to WLn.2) m Together for the inner word line. In this embodiment, step 446 of FIG. 15 will include verifying word line % to milk η-m to perform steps 462 and 466 to further erase and verify the word lines: L〇, WL1, WL(1), and chyle In another embodiment, more than one or more than six word lines may be grouped together into an end word line. Other grouping methods can also be implemented. 109918.doc -46- 1313867 Figures 18A and 18B illustrate erase voltage tfi numbers that may be used in accordance with various embodiments. Fig. 18 shows - the first with the magnitude Ve_ - the erased electric pulse _Sei. The first pulse may be applied to the first pulse of the set of memory cells being erased in step 4 of FIG. This pulse is used to erase all memory cells of the set =. In some embodiments, the erase pulse may have a value of about 15 volts to 20 volts. In a specific embodiment, the preferred mode is 'selecting the magnitude of the first erase pulse, causing the eraser to erase only the inner word after applying a single erase voltage pulse before and after the write/erase: loop Memory cells on the line (and will not be erased p. However, after the write/erase cycle %, or due to the different parameters of the individually constructed memory device, all medial memories may not be erased after the first pulse Body unit. In other embodiments, the first-erase voltage pulse can be selected to cause the wipe to be applied only after the write/erase cycle, or only during a limited number of write/erase cycles, after the first pulse is applied. In addition to the inner memory unit, more pulses may be required after a continuation of the write/erase cycle. This technique reduces over-erase at the beginning of the write/erase cycle at the expense of a continuation of the write/erase cycle. There are more erase voltage pulses afterwards. As shown in Figure 18 A, the second pulse is applied before the inner word line is successfully verified as erased. The erase voltage signal is in step size Δν^Αΐ from pulse ] increments to pulse2. Press ΔνΕ11Α to increment Step 456 of Figure 15. In one embodiment, ΔνΕΙΙΑ1 may be about 0.5 volts to 丨. After applying the first erase voltage pulse, all of the inner word lines are successfully verified. This may correspond to Figure 15. Step 448. After verifying all of the inner word lines, only the end s memory cells are continuously erased. Their memory cells are erased more slowly, so the second 109918.doc -47-1313867 is incremented by a larger step size. The erase voltage signal is incremented for applying a second erase voltage pulse pulse3. This may correspond to step 458 of Figure 15. Preferably, in a particular embodiment, the selection is such that the first erase voltage is applied. After the pulse (for example, after pulsed, only the end memory cells (all end memory cells) will be erased before and after the write/erase cycle. In the integrated example, ΔνΕΙΙΑ2 is about 2 volts. Apply pU〗 se3 At step 464 of Figure 15. Thereafter, the pulse is incremented by a third step size. This pair should be at step 474 of Figure 15. In a particular embodiment, Δν ΕΙΙΑ 3 may be equal (or in other embodiments, Can be greater or less than Δ Vera ^ Figure 18B illustrates an alternate embodiment of an erase voltage signal that can be used when performing the method of Figure 15. In this embodiment, the first erase voltage pulse is selected to be greater than Second pulse. The first erase voltage pulse Pulsei is selected to induce a large voltage offset (eg, about 6 volts). This erase voltage pulse is still ideally selected such that after a certain number of write/erase cycles, After applying a single pulse, the inner memory cell will be erased. However, X should understand that 'in some cases' more than one pulse can be used to erase all of the inner memory cells. In other embodiments, the first can be selected. Erasing the voltage pulse causes the inner memory cell to be erased after the first erase voltage pulse is applied, only after a write/erase cycle, or only for a limited number of write/erase cycles. More pulses may be required after a continuation of the write/erase cycle. In the embodiment of Fig. 18B, the second pulse and the third pulse are required if all of the inner memory cells are detected to have been erased. The second erase voltage pulse pul% is larger than pulseH, a step size. The decrementing erase voltage signal also corresponds to step 456 of FIG. However, according to the size of ΔνΕκΑ4, Ϊ099 丨 8.doc -48- 1313867 minus (rather than incrementing). This ensures that the inner memory cell is not erased after the application of the second erase voltage pulse. The second pulse is made smaller to induce a smaller offset of the threshold of the -# memory unit. If a third erased dust pulse is required (as indicated by Ρ-), the pulse can be incremented by step size help to ensure that electrons continue to be transferred from the floating gates of their memory cells. After the third erase voltage pulse is applied, the inner memory cell is verified to have been erased. The rest of the figure is the same as in Figure 18Α. Since the first-erasing pulse, the magnitude of the punch is incremented by the magnitude of the fourth erased electrical pulse pulSe4,1 is applied to only the terminal memory cell. This corresponds to step 458 of Figure 。. In the particular embodiment of Figure 1, an additional erase voltage pulse is required to erase the end memory. Therefore, the fifth erase voltage pulse pulse5 is incremented by a value higher than the fourth erase voltage pulse value. In a particular embodiment, after applying the first-erase voltage pulse pulsei, the second erase voltage pulse p- may be the same as the size of pulsei, rather than decreasing its size. In this embodiment, any erase voltage pulse required to erase the inner memory cell will be incremented by the value Δν ΕΚΑ 1 as shown. Figure 19 illustrates a flow diagram for performing the steps of Figure 15 in accordance with an embodiment. In Fig. 19, the steps are performed as shown by the erase voltage pulse of Fig. 8Β in step 45 of Fig. 15. First, at step 49, it is determined whether the verification counter VC is equal to zero', which indicates that only one wipe has been performed so far. In addition to the voltage pulse has been applied to the 忒6 memory. If the verification counter is equal to zero (which indicates that the brother changed the risk at one time | @#文1Lf, the magnitude of the voltage pulse), the method proceeds to step 492 where the value of the erase voltage pulse is decremented by value. This will cause a similar pulse to be applied during the next repeat operation. However, I09918.doc -49 - 1313867 If the verification counter is not equal to zero (which indicates that this is the second or more change of the erase voltage signal), then the method proceeds to step 494 where the incremental erase is performed by pressing ΔvERA1. The voltage signal 'causes the pulse k steps 492 and 494 which are just like the picture, and the method proceeds again to step 44 of Figure 5.

在所謂軟性程式化操作射[電容_合亦可導致na仙 “記憶體單元之間的運作模式相異。典型地，藉由同時 &力、式化脈衝至所選區塊的所有字線’來實行軟性 程式化操作。在擦除一記憶體單元集合後執行軟性程式 化。執行軟性程式化，以使該記憶體單元集合的已擦除臨 限電塵分佈變窄，並且正規化該記憶體單元集合内個別記 憶體單元的已擦除臨限電壓分佈。軟性程式化脈衝之振幅 低於正規程式化脈衝（例如，如圖6所示），以避免記憶體單 元到達已程式化狀態。所要的軟性程式化結果係，記憶體 單^具有較窄之擦除臨限電愿分佈。據此，非意欲使臨限 電麗偏移至程式化狀態範圍内。 在施加每一軟性程式化脈衝之後，實行一驗證操作，該 驗也知作類似於如圖10所示之典型擦除驗證操作。於驗證 ㈣程式化操作期間’測試通過— NAND串的傳導，而且使 母#憶體單元的閉極接收擦除驗證電麼。在擦除驗證操 作2間，—旦所選區塊中的一定數量NAND串已到達非傳導 =恶（指不出該NAND串的至少一記憶體單元已到達擦除驗 D且位準)’軟性程式化結束。軟性程式化之結果在於，所擦 :之記憶體單元的臨限電壓分佈向上偏移至較接近擦除驗 σ且位準。使用軟性程式化，可使擦除臨限電屢分佈向上偏 109918.doc -50- 1313867 移至接近擦除驗證位準的位準，即使記憶體單元原先 擦除。 因為從選擇問極至NAND串之末端字線之記憶體單元的 電容耗合，所以NAND串之記憶體單元的軟性程式化運作模 式不同。在軟性程式化操作期間，介於選擇間極與末端記 憶體單元之間的電容搞合減緩彼等記憶體單元。因此，可 預期，在軟性程式化後，末端字線之記憶體單元的已擦除 狀態深於内側字線之記憶體單元的已擦除狀態。 圖別繪示在歷經軟性程式化之後一 NAN/串之記憶體單 -的已擦除臨限電壓分佈。臨限電壓分佈伽會示在歷經軟 性程式化之後内側字線記憶體單元的已擦除臨限電壓分 佈。軟性程式化已使此已擦除臨限電壓分佈偏移至較接近 擦除驗證位準。由於如果在施加擦除驗證電壓下，預先決 定數量之NAND串係處於非料狀態，則對於軟性程式化之 驗證將-記憶體單元群組驗證為已被成功軟性程式化’所 以-定數量之記憶體單元的臨限電麗偏移至超過擦除驗證 位準。臨限電壓高於擦除驗證位準的實際記憶體單元數量 取決於所採用的實際驗證方案。舉例而言，如果該方案在 -單-财ND串變成非傳導狀態時將軟性程式化驗證為完 成’則δ玄群組中僅·^個倍；^ 们。己隐體早兀可能高於驗證位準。在 其他方案巾，該群組内的上千個記憶體單元之臨限電壓僅 僅偏移至超過擦除驗證位準。臨限電壓分佈彻會示末端記 憶體單元的臨限電麼。因為末端記憶體單元的較緩慢軟性 程式化時間’所以末端記憶體單元的臨限電塵尚未偏移為 109918.doc 51 1313867 接近擦除驗證位準。 根據-具體實施例，一記 分成子集，使彳m㈣^ 的子線再次被劃 用種適應個別字線子集 實行軟性程式化。此方法類似於圖15所亍：要的方式來 法。正被軟性程式化的該記情 *除驗證方 -些初始軟性程式化。驗”二集5之所有字線歷經 驗祖該圯憶體單元集合或1 被成功軟性程式化之後， /、集已 性程式化，以使末端字線腕離較J =子線的額外軟 近擦除驗證位準。 “度的已擦除狀態且較接 圖21繪不在—具體實施例中用於軟性程式化的方法。舉 例而言’圖21之方法可用於軟性程式化-區塊記憶體單元 的複數個NAND串。在一具體實施例中，對於，之軟性程 式化步驟342’可執行根據圖21之的軟性程式化。在步驟 602車人性紅式化電壓訊號被設定為其起始值，並且 軟性程式化計數器SPC被設定為零。在步驟6G4，源極線、 ，元線及源極選_極線被接地。此外，將〜供應至汲極 遥擇閉極線。若需要’可在正要施加軟性程式化脈衝之前 先降低汲極選擇閘極線電壓至約2·5伏，以允許推動軟性程 式化禁止（步驟61 7)。在其他案例中則並非如此。藉由將被 偏壓至VDD的通道，仍然可在程度上使軟性程式化禁止發生 (步驟6 1 7)。在步驟606，第一軟性程式化脈衝被施加至正被 軟性程式化之該記憶體單元集合的所有字線。在步驟6〇8， 使用擦除驗證電壓位準，來驗證所有字線之記憶體單元的 已擦除狀態。在一具體實施例中，步驟6〇8可包括僅驗證内 I099l8.doc -52- 1313867 7字線的記憶體單元，同時確保末端記憶體單元的傳導狀 “仁π在大多數案例中，由於末端字線的記憶體單元 之軟性程式化速度比内側字線的記憶體單元之軟性程式化 速度，慢，所以在施加至擦除驗證電壓下，末端字線的記 憶體單元無論如何都將處於傳導狀態。 在步驟㈣’比較被軟性料化之區塊中的非傳導狀態 :AND串數量與預先決定數量。如果非傳導狀態财仙串數 籲里不大於預先決定數量’則在步驟612比較軟性程式化計數 器SPC與預先決定限制值（例如，2〇)。如果軟性程式化計數 …於20 ’則在步驟614報告軟性程式化操作失敗狀態。 如果軟性程式化計數器小於20，貝4方法進行至步驟616，在 此步驟將軟性程式化計數器SPCW，並且按—預先決定值 來遞增軟性程式化電壓訊號。在步驟617,在步驟608之驗 ^期間處於非傳導狀態（被成功軟性程式化）之NAND串被 予X進步軟性釭式化。藉由施加較高電壓（諸如Vdd) 籲至相對應之位元線，可禁止軟性程式化特定nand串。在下 專人性轾式化循環期間，藉由使位元線電壓上升，被禁止 之NAND串的通道區域將被增壓至一高電壓。介於記憶體單 :之浮動閘極與被禁止之NAND串的通道區域之間的電壓 差將太低，而造成進一步軟性程式化彼等記憶體單元。接 著方法進行至步驟604 ’以施加額外軟性程式化脈衝至該 等記憶體單元。 如果非傳導狀態NAND串數量大於預先決定數量（指示出 °亥等。己憶體單元已成功歷經軟性程式化），則在步驟ό 1 8重 109918.doc -53 - 1313867 設軟性程式化計數器SPC。在一具體實施例中，步驟618可 進一步包括遞增軟性程式化電壓訊號。在一具體實施例 中，步驟618之增量可相同於步驟616之增量或其他值。舉 例而言’在一具體實施例中，軟性程式化電壓訊號係按步 驟616之步進大小△▽5{^„11予以遞增。在步驟618，可按步進 大小△Vspgmd可大於AVspgml)進行遞增。在一具體實施例 中’可使用相似於圖1 8 A之擦除電壓訊號的軟性程式化電壓 訊號。 在步驟620，位元線、源極線及源極選擇閘極線被接地， 且將VSG施加至汲極選擇閘極線。在步驟622，禁止軟性程 式化内側字線。藉由施加約〇伏至3伏之級數的小正電壓至 内側字線，可禁止軟性程式化内側字線。在一具體實施例 中’施加至内側字線的電愿較大且係約5伏至1 〇伏之級數。 舉例而言，該電壓可能係一通電壓（pass voltage ; vpass)， 典型施加該電壓以增大NAND串的通道區域的電壓，以禁止 紅式化或軟性程式化。對於擬被禁止進一步軟性程式化（已 驗證為已被軟性程式化）的NAND串，在進一步反覆進行步 驟6 1 8至634中，較高電壓將足以確保被禁止之NAND串的通 I區域被充分增壓，以避免進一步軟性程式化。在步驟 624 ’权性程式化脈衝被施加至正被擦除之該記憶體單元集 合的僅僅末端字線，以進—步軟性程式化末端記憶體單 兀在步驟626，驗證末端記憶體單元字線#已擦除狀態， :時確保不管内側字線之狀態，内側字線皆係處於傳導狀 態(排除驗證内側字線)。擦除驗證電壓位準可被施加至末端 109918.doc -54- 1313867 字線，同時電壓v ^ 加内側字線。在此“中：内側字線之傳導狀態)被施 證内側字線。方式中’僅驗證末端字線，同時排除驗In the so-called soft stylized operation shots [capacitance-combination can also result in a different operation mode between the memory cells. Typically, all the word lines of the selected block are simultaneously pulsed by & force. To perform a soft stylization operation, perform soft stylization after erasing a set of memory cells, perform soft stylization to narrow the erased threshold dust distribution of the memory cell set, and normalize the memory The erased threshold voltage distribution of individual memory cells within the set of body cells. The amplitude of the soft stylized pulses is lower than the normal stylized pulses (eg, as shown in Figure 6) to avoid the memory cells reaching the programmed state. The desired soft stylized result is that the memory single has a narrower erased limit distribution, and accordingly, it is not intended to shift the threshold to the stylized state range. After the pulse, a verify operation is performed, which is also known to be similar to the typical erase verify operation shown in Figure 10. During the verification (iv) stylization operation, the 'test passes' - the conduction of the NAND string, and The closed-end reception erase verification of the mother-memory unit. During the erase verification operation 2, a certain number of NAND strings in the selected block have reached non-conduction = evil (not indicating at least one of the NAND strings) The memory unit has reached the erasure test D and the level) 'soft stylization is finished. The result of the soft stylization is that the threshold voltage distribution of the memory cell is shifted upwards to be closer to the erase test σ and bit Using soft stylization, the erased throttling power distribution can be moved up to 109918.doc -50-1313867 to the level close to the erase verify level, even if the memory cell was originally erased. The capacitance of the memory cell to the end word line of the NAND string is different, so the soft stylized operation mode of the memory cell of the NAND string is different. During the soft stylization operation, between the selected interpole and the end memory cell The capacitors are combined to slow down their memory cells. Therefore, it is expected that after soft programming, the erased state of the memory cells of the end word lines is deeper than the erased state of the memory cells of the inner word lines. Don't show it at The erased threshold voltage distribution of a memory bank of a NAN/string after soft programming. The threshold voltage distribution gamma shows the erased threshold voltage distribution of the inner word line memory cell after soft programming Soft stylization has shifted this erased threshold voltage distribution closer to the erase verify level. Since a predetermined number of NAND strings are in an unanticipated state when an erase verify voltage is applied, then for softness Stylized verification will verify that the memory cell group has been successfully soft-programmed 'so-the number of memory cells of the threshold is shifted to exceed the erase verify level. The threshold voltage is higher than the erase The actual number of memory cells to verify the level depends on the actual verification scheme used. For example, if the scheme verifies the soft stylization as complete when the -single-finance ND string becomes non-conducting, then the δ 玄 group Only ^^ times; ^ us. The invisible body may be higher than the verification level. In other schemes, the threshold voltage of thousands of memory cells in the group is only shifted to exceed the erase verification level. The threshold voltage distribution will show the threshold power of the end memory unit. Because of the slower soft stylized time of the end memory cell, the threshold current of the end memory cell has not been shifted to 109918.doc 51 1313867 close to the erase verify level. According to a specific embodiment, a sub-set is divided into sub-sets such that the sub-lines of 彳m(4)^ are again adapted to the individual word line subsets for soft stylization. This method is similar to the one shown in Figure 15: the way to do it. This sensation being soft-programmed *In addition to the verifier - some initial soft stylization. After the "two sets of 5" all the word line experience experience ancestor memory unit set or 1 is successfully soft stylized, /, set has been programmed to make the end word line wrist away from J = sub-line extra soft Near erase verification level. "The erased state of degrees and not depicted in Figure 21 - a method for soft stylization in a particular embodiment. For example, the method of Figure 21 can be used for a plurality of NAND strings of soft stylized-block memory cells. In one embodiment, the soft programming step 342' may perform soft stylization in accordance with FIG. At step 602, the vehicle humanized reddening voltage signal is set to its starting value, and the soft stylized counter SPC is set to zero. In step 6G4, the source line, the source line, and the source select_pole line are grounded. In addition, ~ will be supplied to the bungee remote selection closed line. If desired, the drain select line voltage can be lowered to about 2.5 volts before the soft stylized pulse is being applied to allow the soft mode disable to be pushed (step 61 7). This is not the case in other cases. Soft stylization prohibition can still occur to a certain extent by the channel to be biased to VDD (step 6 17). At step 606, a first soft stylized pulse is applied to all of the word lines of the set of memory cells being soft-programmed. In step 6〇8, the erase verify voltage level is used to verify the erased state of the memory cells of all word lines. In a specific embodiment, step 6〇8 may include verifying only the memory cells of the inner I099l8.doc -52-1313867 7 word line while ensuring the conduction of the end memory cell "ren π in most cases due to The soft stylized speed of the memory cell of the end word line is slower than the soft stylization speed of the memory cell of the inner word line, so the memory cell of the end word line will be in any case when applied to the erase verify voltage. Conduction state. In step (4) 'Compare the non-conducting state in the softened block: the number of AND strings and the predetermined number. If the non-conducting state is not greater than the predetermined number, then compare in step 612. The soft stylized counter SPC is pre-determined with a limit value (for example, 2 〇). If the soft stylized count is ... at 20 ′, the soft stylization operation failure status is reported in step 614. If the soft stylized counter is less than 20, the Bay 4 method is performed. To step 616, the soft stylized counter SPCW is incremented at this step, and the soft stylized voltage signal is incremented by a predetermined value. At step 617, The NAND string in the non-conducting state (successfully soft-stylized) during the test period of step 608 is softened by X. By applying a higher voltage (such as Vdd) to the corresponding bit line, it can be prohibited. Soft stylizes a specific nand string. During the next-person humanization loop, the channel region of the disabled NAND string is boosted to a high voltage by raising the bit line voltage. The voltage difference between the gate and the channel region of the inhibited NAND string will be too low, causing further soft programming of their memory cells. The method then proceeds to step 604' to apply additional soft stylized pulses to the memories. If the number of non-conducting NAND strings is greater than a predetermined number (indicating that the hexadecimal unit has successfully passed the soft stylization), then the soft program is set in step ό 18 8 109918.doc -53 - 1313867 The counter SPC. In a specific embodiment, step 618 can further include incrementing the soft stylized voltage signal. In a specific embodiment, the increment of step 618 can be the same as the increment of step 616. Or other values. For example, in one embodiment, the soft stylized voltage signal is incremented by the step size Δ▽5{^„11 of step 616. In step 618, the increment may be performed by the step size ΔVspgmd may be greater than AVspgml). In a specific embodiment, a soft stylized voltage signal similar to the erase voltage signal of Figure 18A can be used. At step 620, the bit line, source line, and source select gate lines are grounded and VSG is applied to the drain select gate line. At step 622, soft programming of the inner word line is inhibited. The soft stylized inner word line can be inhibited by applying a small positive voltage of about 3 volts to the inner word line. In one embodiment, the power applied to the inner word line is greater and is in the order of about 5 volts to 1 volt. For example, the voltage may be a pass voltage (vpass) that is typically applied to increase the voltage of the channel region of the NAND string to disable red or soft programming. For a NAND string that is to be inhibited from further soft stylization (which has been verified to have been soft-programmed), in a further iteration of steps 6 1 8 to 634, a higher voltage will be sufficient to ensure that the pass I region of the disabled NAND string is Fully boosted to avoid further soft stylization. At step 624, a weighted stylized pulse is applied to only the end word line of the set of memory cells being erased, to further soften the end memory block in step 626, verifying the end memory cell word. Line # erased state, : ensures that the inner word line is in conduction regardless of the state of the inner word line (excluding the verification inner word line). The erase verify voltage level can be applied to the terminal 109918.doc -54-1313867 word line while the voltage v ^ is added to the inner word line. In this "middle: conduction state of the inner word line" is authenticated inside the word line. In the mode 'only verifies the end word line, while eliminating the test

比較步驟626中所判定之非傳導狀態 串ί里Ί先心數f。如料料㈣NAThe non-conducting state string ί in the comparison step 626 is compared with the first heart number f. Such as material (four) NA

預先決定數量（指示出太令山—括AA 出末知子線的記憶體單元現在已向上 偏移至接近擦除驗證位準)，則方法進行至步驟㈣，在此 步驟報告通過狀態。如果㈣導狀態NAND串數量不大於預 先決定數量，則比較軟性程式化計數器與㈣決定限制 值。如果軟性程式化計數器大於預先決定限制值，則在步 驟6 1 4報告操作失敗壯能。# s 卜天敗狀態但疋，如果軟性程式化計數器小 於預先決定限制值，則在步驟634，將軟性程式化計數器加 1並且遞增軟性程式化電屢訊號。在步驟奶，在步驟似The pre-determined quantity (indicating that the memory unit of the Tailingshan-AA ending sub-line has now been shifted upwards to approach the erasure verification level), the method proceeds to step (4), where the pass status is reported. If the number of (4) conduction state NAND strings is not greater than the predetermined number, the soft stylized counter is compared with (4) the limit value is determined. If the soft stylized counter is greater than the predetermined limit value, then in step 6 1 4 the reported operation fails. # s 卜天败状态 However, if the soft stylized counter is less than the predetermined limit value, then in step 634, the soft stylized counter is incremented by one and the soft stylized electrical iteration is incremented. In the step milk, in the steps like

之驗證期間處於非傳導狀態（被成功軟性程式化）之n A N D 串被禁止予以進一步軟性程式化。接著，方法進行至步驟 620，以進一步軟性程式化末端記憶體單元。 在一具體實施例中，步驟634係按相同於步驟616之大小 來遞私权性程式化電壓訊號；然而，在其他具體實施例中， 則使用其他值舉例而言，如果使用相似於圖18B之擦除電壓 訊號的軟性程式化電壓訊號’則步驟634可包括按△Vsww (相似於avERA3)之大小進行遞增，步驟618可包括按 (相似於AVera2)之大小進行遞增’以及步驟61 6可包括按 △Vspgml (相似於AVera1)之大小進行遞增。在此一具體實施 例中，步驟01 6可進一步包括：在第一次反覆期間，按Δν£ρ^4 109918.doc -55- 1313867 (相似於ΔνΕΚΑ4)之大小進行遞減；以及在後續反覆期間，按 △ V S p g m I之大小進行遞增。 在不同具體實施例中，可用不同方式來進行__NAND串之 字線劃分’以進行軟性程式化。舉例而言，—NAND串的兩 個最末端字線（例如，WL。、WL1、WLn·,和WLn)可被分組在 -起為末端字線，並且其餘字線(WL2iD被分組在一 起為内側子線。在此>—^ j-i- /1 1 仗此具體實施例中，圖21的步驟622將包 括禁止字線脱2至乳以，並且將執行步驟_及咖以進一 步軟性程式化及驗證字線WL〇、乳！、I!和％。在另 一項具體實施例中，可將六個或六個以上字線被分組在一 起為末端字線。亦可實施其他的分組方式。 圓22係展不用於圖2】所示之流程圖之各種操作的偏塵條 件。攔640列出正被擦除之該集合的所有記憶體單元的軟性 程式化操作之偏麗條件。攔64〇對應於圖21的步驟6〇4至 :?為了進行軟性程式化’位元線、源極線及P井係在〇 。圖中緣示在圓括號中的Vdd係用於位元線電塵，以指示 被施加至擬被禁止軟性程式化的财啊。源極側選 、甲極線係在0伏，而汲極側選擇間極線係在VsG。軟性程 式2脈衝vspgm被施加至該記憶體單元集合的每一字線，以 使字線所連接的每一記憶體單元的臨限電壓上升。 欄642列出用於驗證該集合之所有記憶體單元之軟性浐 二=壓條件。爛⑷對應於圖21的步侧。彼等㈣ 之捧除的=於驗證一記憶體單元集合中所有記憶體單元 -爲壓條件。位元線處於浮動狀態且p井係在〇伏， 109918.doc -56- 1313867 而vDD被提供至源極線。彼等兩 、，nn M k释閘極皆係稭由ν予 以開啟。擦除驗證電壓被施加至每—始The n A N D string in the non-conducting state (successfully soft programmed) during the verification period is prohibited from further soft programming. Next, the method proceeds to step 620 to further soften the end memory unit. In one embodiment, step 634 is to privilege the stylized voltage signal in the same manner as step 616; however, in other embodiments, other values are used, for example, if used similar to FIG. 18B. The soft stylized voltage signal of the erase voltage signal 'step 634 may include incrementing by ΔVsww (similar to avERA3), step 618 may include incrementing by (similar to AVera2) and step 61 6 This includes incrementing by ΔVspgml (similar to AVera1). In this embodiment, step 01 6 may further include: during the first iteration, decrementing by Δν£ρ^4 109918.doc -55-1313867 (similar to ΔνΕΚΑ4); and during subsequent iterations , increment by Δ VS pgm I. In various embodiments, the word line division of the __NAND string can be performed in different ways for soft stylization. For example, the two most end word lines of the NAND string (eg, WL., WL1, WLn·, and WLn) can be grouped at - as the end word line, and the remaining word lines (WL2iD are grouped together The inner sub-line. Here, in the specific embodiment, step 622 of FIG. 21 will include disabling the word line to 2, and the step _ and the coffee will be further soft-stylized. And verify word lines WL〇, 乳!, I!, and %. In another embodiment, six or more word lines can be grouped together into end word lines. Other grouping methods can also be implemented. The circle 22 is not used for the dusty conditions of the various operations of the flow chart shown in Figure 2. The block 640 lists the partial conditions of the soft stylized operation of all memory cells of the set being erased. 64〇 corresponds to steps 6〇4 to: in Fig. 21: In order to perform soft programming, the bit line, the source line, and the P-well are in the frame. The Vdd in the parentheses in the figure is used for the bit line. Electric dust, in order to be applied to the money that is to be banned from soft stylization. The source side is selected, the armor line is at 0 volts, and the bungee The inter-polar line is selected in VsG. The soft program 2 pulse vspgm is applied to each word line of the memory cell set such that the threshold voltage of each memory cell to which the word line is connected rises. To verify the softness of all memory cells of the set = pressure condition. Rotten (4) corresponds to the step side of Figure 21. The sum of (4) of the memory = verify all memory cells in a memory cell set - for pressure Condition: The bit line is in a floating state and the p-well is in the dormant, 109918.doc -56-1313867 and the vDD is supplied to the source line. The two, nn M k release gates are all opened by ν The erase verification voltage is applied to each start

主母一子線’以判定NAND 串疋否處於非傳導狀態，並因此 .卫U此有至少一記憶體單元已到 達擦除驗證位準。The main mother has a sub-line ' to determine whether the NAND string is in a non-conducting state, and therefore, at least one of the memory cells has reached the erasure verify level.

欄…列出用於軟性程式化僅末端字線的偏塵條件。欄 :4對應於圖21的步驟㈣至624。藉由供應一極側選 擇問極線而開啟汲極侧選擇間極線，並且藉由供應。伏至源 極側選擇間極線而關斷源極側選擇閘極線。將低正電堡 \el(例如，0伏至5伏）提供至内侧字線。藉由施加小正電 壓至内側字線，可禁止在施加軟性程式化脈衝下而進一步 程式化連接至内側字線的記憶體單元。末端字線接收軟性 程式化脈衝VSPGM，以歷經進—步敕性程式化。當擬禁止進 v軟I·生私式化已驗證為已被軟性程式化的串時，施 加至内側字線的Vusel之值可能係相對高電壓（例如，八…= 5伏至10伏），而非小正電壓。因為亦將Vdd施加至被禁止之 NAND串的位几線，所以在下一軟性程式化循環期間，相對 高電壓將造成被禁止之NAND串的通道區域被增壓至一高 電[此使’丨於s己憶體單元之浮動閘極與被禁止之NAND 串的通道區域之間的電壓差足夠低，使得不會發生進一步 軟性程式化彼等記憶體單元。 搁646列出僅末端字線的軟性程式化驗證偏壓條件。欄 646可對應於圖2〗的步驟626。位元線處於浮動狀態，而源 極線處於VDD。p井係在0伏。藉由供應Vsg至汲極選擇閘極 線及源極選擇閘極線，而開啟彼等兩個選擇閘極。v^e!被 1099I8.doc • yi · 1313867 供應至内側字線。如上文所述，在一些案例中’於軟性程 式化（欄644)期間使用的n可大於〇伏至3伏。用於驗證 ' us^值係’力0伏至3伏。其僅需要高於擦除驗證電壓，以 便確疋已το成軟性程式化之内側字線的記憶體單元係處於 傳導狀態。在此方式中，可單獨判定及驗證末端字線上之 记隐Μ單7L的狀態。因此，於軟性程式化期間使用的丨 值（例如’ 5伏至10伏）可不同於於軟性程式化驗證期間使用 的值(例如〇伏至3伏)。將擦除驗證電壓或。伏施加至末端 字線。在此方式巾，排除軟性程式化驗證内側字線，同時 末端字線歷經驗證。 圖23繪不在歷經根據圖幻及22之軟性程式化之後的一記 憶體單元集合之臨限電廢分佈。如圖Μ所示，内側字線及 末端字線的擦除臨限電壓分佈已向上移至接近擦除驗證位 準^側字線臨限電壓分佈43G已向上偏移至接近擦除驗證 4準士同正吊叙生之狀況。由於額外軟性程式化（步驟6工8 至63 5)，末端字線臨限電壓分佈432亦已向上移至接近擦除 驗證位準。 上文提供之實例係關於财_型快閃記憶體。但是，本發 明原理適用於利用串聯結構之其他類型非揮發性記憶體， 包括現有記憶體及考慮使用已開發中新技術的記憶體。 基於圖解及說明的目，前文已提出本發明的實施方式。 它不是預計詳細說明本發明或使本發明限定於發表的確切 形式。可按照前面的講授進行許多修改及變化。選取的具 體實施例係為了最佳地解說本發明的原理及其實務應用， 109918.doc -58- 1313867 使熟悉此項技術者以各種具體實施 並且各種修改皆適用於所考量的特定土〗運用本發明， 藉由隨附的巾請專利範圍予以定義μ途。本發明範脅擬 【圖式簡單說明】 圖1繪示_ NAND串的俯視圖。 電路圖 圖2繪示圖i所示之NAND串的同等 圖3繪示三個NAND串的電路圖。Column... lists the dust conditions for soft stylized only the end word line. Columns: 4 correspond to steps (4) to 624 of FIG. The drain line is selected by the supply of one pole side to select the polarity line and is supplied by the drain side. Select the interpole line from the volts to the source side and turn off the source side to select the gate line. A low positive power castle \el (eg, 0 volts to 5 volts) is provided to the inner word line. By applying a small positive voltage to the inner word line, it is possible to inhibit the further stylization of the memory cell connected to the inner word line by applying a soft stylized pulse. The end word line receives the soft stylized pulse VSPGM, which is programmed in a step-by-step manner. The value of the Vusel applied to the inner word line may be relatively high (for example, eight...=5 volts to 10 volts) when it is intended to disable the soft-synchronized string that has been verified as being soft-stylized. Instead of a small positive voltage. Since Vdd is also applied to the bit lines of the disabled NAND string, during the next soft stylization cycle, the relatively high voltage will cause the channel region of the disabled NAND string to be boosted to a high voltage [this makes '丨The voltage difference between the floating gate of the suffix cell and the channel region of the inhibited NAND string is sufficiently low that further memory programming of the memory cells does not occur. The shelf 646 lists the soft stylized verification bias conditions for only the end word lines. Column 646 may correspond to step 626 of Figure 2. The bit line is floating and the source line is at VDD. The p well is at 0 volts. The two select gates are turned on by supplying Vsg to the drain select gate and the source select gate. v^e! is supplied to the inner word line by 1099I8.doc • yi · 1313867. As noted above, in some cases 'n used during soft programming (column 644) may be greater than 〇 to 3 volts. Used to verify the 'us^ value' force from 0 volts to 3 volts. It only needs to be higher than the erase verify voltage in order to ensure that the memory cell that has been softly stylized on the inner word line is in a conducting state. In this mode, the state of the concealment order 7L on the end word line can be individually determined and verified. Therefore, the 丨 value used during soft stylization (e.g., '5 volts to 10 volts) may be different from the value used during soft stylization verification (e.g., crouching to 3 volts). The verify voltage or will be erased. Volts are applied to the end word line. In this mode, the soft stylized verification of the inner word line is excluded, and the end word line is verified. Figure 23 depicts the limited electrical waste distribution of a set of memory cells that have not been programmed according to the softness of Figure and 22. As shown in Figure ,, the erase threshold voltage distribution of the inner word line and the end word line has been moved up to the proximity erase verify level. The word line threshold voltage distribution 43G has been shifted upward to close to the erase verify 4 The same is the situation of the singer. Due to the additional soft stylization (steps 6 to 63), the end wordline threshold voltage distribution 432 has also moved up to near the erase verify level. The examples provided above are related to fiscal-type flash memory. However, the principles of the present invention are applicable to other types of non-volatile memory that utilize a tandem structure, including existing memory and memory that is considered to be using new technologies that have been developed. Embodiments of the present invention have been presented above for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention. Many modifications and variations are possible in light of the above teachings. The specific embodiments are chosen to best explain the principles of the present invention and the practical application, 109918.doc -58-1313867. In the present invention, the scope of the patent is defined by the accompanying towel. BRIEF DESCRIPTION OF THE DRAWINGS [Simplified Schematic] FIG. 1 illustrates a top view of a _ NAND string. Circuit Diagram Figure 2 shows the equivalent of the NAND string shown in Figure i. Figure 3 shows the circuit diagram of three NAND strings.

圖憎示可實施本發明各項態樣 之具體實施例的方塊圖。 u it體系統 圖5繪示記憶體陣列的示範性組織。 圖6繪示根據具體實施例可 程式化/驗證電壓訊號。 所選子線的示範性 請示用於執行程式化操作之示範性流程圖。 圖轉不一記憶體群組的示範性 圖9緣示儲存兩位元杳 限電歷分佈。 貝科的-記憶體群組之示範性臨 擦除操作的示範性偏壓條 圖1 〇係展不根據先前技術執行 件之表格。 圖11係繪示在1想擦除操作期間-NAND串之各種部 分處電壓的圖表。 圖12係繪示一· n aΝη * βη # AND串内各種電容耦合電壓的ΝΑΝΕ»串 之剖面圖。 圖1 3係續'示在—执w 4 擦除插作期間一 NAND串之末端記憶體 單元的各種電壓之圖表。 109918.doc -59- 1313867 圖14A及14B繪示在完成一擦除操作後一 NAND串之末端 與内侧δ己憶體早元的示範性個別臨限電壓分佈。 圖15繪示根據一具體實施例之擦除一非揮發性儲存元件 集合的流程圖。 圖16係繪示根據一具體實施例之擦除及驗證擦除一非揮 、發性儲存元件集合之偏壓條件的表格。 圖17Α至17C繪示根據一具體實施例在一擦除操作期間 • 之各時間點，一 NAND串之末端記憶體單元與内側記憶體單 元的臨限電壓分佈。 圖18A至18B係繪示根據一具體實施例之擦除.電壓訊號 的圖表。 圖19繪示根據一具體實施例之執行圖15之步驟456的流 程圖。 圖20繪示根據先前技術在軟性程式化後，一 nand串之末 柒5己憶體單元與内側s己憶體單元的示範性臨限電壓分佈。 鲁圖2 1繪不根據一具體實施例之軟性程式化一非揮發性儲 存元件集合的流程圖。 圖22係繪示根據一具體實施例之軟性程式化及驗證軟性 程式化一非揮發性儲存元件集合之偏壓條件的表格。 圖23繪示根據一具體實施例在軟性程式化後，一 串之末端記憶體單元與内側記憶體單元的示範性臨限電壓 分佈。 【主要元件符號說明】 1〇〇, 102, 104, 106 電晶體 109918.doc -60- 1313867 100CG, 102CG, 104CG, 106CG 100FG, 102FG, 104FG, 106FG 120The figure shows a block diagram of a specific embodiment in which aspects of the invention may be practiced. u it body system Figure 5 illustrates an exemplary organization of a memory array. Figure 6 illustrates a programmable/verified voltage signal in accordance with a particular embodiment. Exemplary of selected sub-lines An exemplary flow chart for performing stylized operations is provided. Figure 1 shows an example of a memory group. Figure 9 shows the storage of two-digit 限 limit power distribution. An exemplary bias strip for an exemplary temporary erase operation of a Becco-memory group. Figure 1 is not based on a table of prior art implementations. Figure 11 is a graph showing the voltage at various portions of the -NAND string during an erase operation. Figure 12 is a cross-sectional view showing the ΝΑΝΕ» string of various capacitive coupling voltages in a n n Ν η * βη # AND string. Figure 1 is a diagram showing the various voltages of the end memory cells of a NAND string during the erasing of the w4 erasing insertion. 109918.doc -59- 1313867 Figures 14A and 14B illustrate exemplary individual threshold voltage distributions at the end of a NAND string and the inner δ hexon precursor after completing an erase operation. Figure 15 is a flow diagram of erasing a collection of non-volatile storage elements in accordance with an embodiment. 16 is a table showing the bias conditions for erasing and verifying a set of non-volatile storage elements in accordance with an embodiment. 17A through 17C illustrate threshold voltage distributions of the end memory cells and the inner memory cells of a NAND string at various points in time during an erase operation, in accordance with an embodiment. 18A through 18B are diagrams showing erased voltage signals in accordance with an embodiment. 19 is a flow diagram of performing step 456 of FIG. 15 in accordance with an embodiment. Figure 20 illustrates an exemplary threshold voltage distribution of the end of a nand string and the inner s-resonant unit after soft stylization according to the prior art. Lutu 2 1 depicts a flow diagram of a non-volatile stylized set of non-volatile storage elements not according to one embodiment. 22 is a table showing soft biasing and verifying soft biasing of a set of non-volatile storage elements in accordance with an embodiment. Figure 23 illustrates an exemplary threshold voltage distribution of a string of end memory cells and inner memory cells after soft stylization, in accordance with an embodiment. [Main component symbol description] 1〇〇, 102, 104, 106 Transistor 109918.doc -60- 1313867 100CG, 102CG, 104CG, 106CG 100FG, 102FG, 104FG, 106FG 120

120CG 122120CG 122

122CG 126 128 控制閘極 浮動閘極 第一選擇閘極 控制閘極 第二選擇閘極 控制閘極 位元線 源極線 202, 204, 206 NAND 串 220, 230, 240, 250 選擇電晶體（選擇閘極） 222, 224, 226, 228, 242，記憶體單元 244, 246, 248, 252 302 φ 304 306 308 3 10 3 12 3 14 315 316 318 記憶體單元陣列 行控制電路 列控制電路（列控制器或解碼器） P井控制電路 共同源極線控制電路 資料輸入/輸出缓衝器 命令電路 控制電路 狀態機 控制器 109918.doc • 61 - 1313867 330, 332 程式化脈衝 334 第一驗證脈衝 336 第二驗證脈衝 338 第三驗證脈衝 380 第一臨限電壓分佈 382 第二臨限電壓分佈 384, 386, 388, 390 臨限電壓分佈 410 接收擦除電壓訊號之P井區的電壓 412 浮動閘極電壓 414 控制閘極電壓 420 p井區電產 422 浮動閘極電壓 424 控制閘極電壓 430 内側字線臨限電壓分佈 432 末端字線臨限電壓分佈 502, 504, 506, 508, 510, 512, 514, 516 記憶體單元 502c, 504c, 506c, 508c, 510c, 512c, 514c, 516c 控制間極 502f, 504f, 506f, 510f， 512f, 514f, 516f 浮動閘極 520, 522 選擇閘極 526, 528, 542 N+擴散區 532 p井至浮動閘極之耦合 109918.doc -62- 1313867122CG 126 128 Control gate floating gate First select gate control gate Second select gate control gate bit line source line 202, 204, 206 NAND string 220, 230, 240, 250 Select transistor (select Gate 222, 224, 226, 228, 242, memory unit 244, 246, 248, 252 302 φ 304 306 308 3 10 3 12 3 14 315 316 318 memory cell array row control circuit column control circuit (column control Or decoder) P-well control circuit common source line control circuit data input/output buffer command circuit control circuit state machine controller 109918.doc • 61 - 1313867 330, 332 stylized pulse 334 first verification pulse 336 2 verification pulse 338 third verification pulse 380 first threshold voltage distribution 382 second threshold voltage distribution 384, 386, 388, 390 threshold voltage distribution 410 voltage 412 floating gate voltage of P well receiving the erase voltage signal 414 control gate voltage 420 p well area electricity production 422 floating gate voltage 424 control gate voltage 430 inner word line threshold voltage distribution 432 end word line threshold voltage distribution 502, 504, 506, 508, 510, 512 , 514, 516 memory cells 502c, 504c, 506c, 508c, 510c, 512c, 514c, 516c control interpoles 502f, 504f, 506f, 510f, 512f, 514f, 516f floating gates 520, 522 select gates 526, 528 , 542 N+ diffusion zone 532 p well to floating gate coupling 109918.doc -62- 1313867

534, 538 從選擇閘極至記憶體單元之浮動閑 極的電容耦合 536 NAND串之個別記憶體單元之浮動 閘極之間的額外電容耦合效應 540 P井區 A，B，C 已程式化臨限電壓分佈 E 已擦除臨限電壓分佈 BLe 偶數位元線 BLo 奇數位元線 PC 程式化計數器 pulse]5 pulse2, pulse3, 擦除電壓脈衝 pulse4, pulse5 SGD,SGS 選擇線 SPC 軟性程式化計數器 VC 驗證計數器 Verase 擦除電壓訊號 V fg 浮動閘極電壓 Vpgm 程式化脈衝電壓位準 VSG 選擇閘極電壓 V SPGM 軟性程式化電壓訊號 VT 臨限電壓 WLO, WL1, WL2, WL3 字線 Δ V ERA 1 , Δ VeRA2, 步進大小（差量） A V ERA3 5 Δ VeRA4 109918.doc -63- LM ΜΘ752號專利申請案 ---- ，中文圖式替換頁(98年4月） 似Η月3日修正替換頁534, 538 Capacitive coupling from the selection gate to the floating idle of the memory cell 536 The additional capacitive coupling effect between the floating gates of the individual memory cells of the NAND string 540 P Well A, B, C Stylized Pro Limit voltage distribution E erased threshold voltage distribution BLe even bit line BLo odd bit line PC stylized counter pulse]5 pulse2, pulse3, erase voltage pulse pulse4, pulse5 SGD, SGS select line SPC soft stylized counter VC Verification Counter Verase Erase Voltage Signal V fg Floating Gate Voltage Vpgm Stylized Pulse Voltage Level VSG Selects Gate Voltage V SPGM Soft Stylized Voltage Signal VT Threshold Voltage WLO, WL1, WL2, WL3 Word Line Δ V ERA 1 , Δ VeRA2, step size (difference) AV ERA3 5 Δ VeRA4 109918.doc -63- LM ΜΘ 752 Patent Application -----, Chinese pattern replacement page (April 1998) page

來自步驟450 (圖 15)From step 450 (Figure 15)

至步驟440 (圖 15) 聶19 109918-fig-980409.doc 14-Go to step 440 (Fig. 15) Nie 19 109918-fig-980409.doc 14-