TWI322575B - Delay locked loop circuit - Google Patents

1322575 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種延遲鎖定迴路電路，且更特定言之， 本發明係關於一種用於根據諸如壓力或溫度之操作條件來 控制同步動態隨機存取記憶體（SDRAM)中延遲鎖定迴路電 路之輸出的記憶體裝置。 【先前技術】 通常’延遲鎖定迴路（DLL)為用於藉由使用一外部輸入時 脈訊號來控制自諸如動態隨機存取記憶體（dram)之半導 體記憶體裝置至一外部裝置之輸出資料的時序的電路。為 了自半導體記憶體裝置傳輸資料至晶片組或cpu而無任何 錯誤，該半導體記憶體裝置之輸出與自該晶片組或該cpu 所產生之時脈訊號同步。 當一時脈訊號傳輸至半導體記憶體裝置中之内部控制區 塊/自半導體記憶體裝置中之内部控制區塊傳輸時，該時脈 訊號由於其中一輸入時脈緩衝器、一線路負載、—資料輸 出緩衝器及其他區塊而延遲。因此，一外部時脈訊號與該 半導體記憶體裝置内部所產生之一内部時脈訊號之間存在 一相位差。為了同步該内部時脈訊號與該外部時脈訊號， DLL用於補償該相位差。 該DLL補償自半導體記憶體裝置中内部區塊之内部時脈 的延遲引起之時脈誤差（clock skew) ’進而同步來自半導體 記憶體裝置之資料之輸出時序與外部時脈訊號。結果，由 半導體記憶體裝置之核心區域所感測之根據内部時脈訊號 112632.doc 1322575 經由資料輸出緩衝器之資料輸出時序與外部時脈訊號同 步。 已知DLL可分類為類比DLL及數位DLL·電路。數位DLL·電 路可為各種建構，其包括暫存器控制DL]L、混合DIX、同步 鏡射DLL、估計控制DLL及其類似物。 圖1為展示習知延遲鎖定迴路的方塊圖。 該習知延遲鎖定迴路包括輸入時脈緩衝器丨〇至2〇、一相 位比較器30、一延遲線40、一虛設延遲線5〇、一延遲控制 器60、一複製模型電路70、一時脈訊號線8〇及一輸出緩衝 器90 〇 包括一上升緣時脈緩衝器1〇及一下降緣時脈緩衝器丨丨之 輸入時脈緩衝器緩衝外部時脈山匕及Clkb以產生一内部上升 時脈rdk及一内部下降時脈fclk。該上升緣時脈緩衝器丨〇產 生與所輸入之時脈Cik之上升緣同步的内部上升時脈rclk， 且下降緣時脈緩衝器11產生與所輸入之時脈clkb之下降緣 同步之内部下降時脈fclk。 該相位比較器30比較該内部上升時脈rcik之相位與自複 衣模型電路70輸出之反饋時脈的相位以偵測内部上升 時脈rxlk與反饋時脈fbdk之間的相位差。為了減少功率消 耗，相位比較器30可取代比較内部上升時脈rcUc與反饋時脈 fbclk,而比較一由時脈除頻器（未圖示）產生、具有—低頻 率的經除頻時脈與反饋時脈fbclke根據比較結果，相位比 較器30產生一用於控制延遲控制器6〇之輸出訊號。該輸出 訊號呈現三種狀態之一者，意即，一滯後狀 — %則狀 Π 2632.doc ·： 3 1322575 態及一鎖定狀態。 a亥延遲控制器60包括複數個移位暫存器且基於自相位比 較器30所接收之輸出訊號來控制延遲線4〇及虛設延遲線 5〇。該延遲線40在延遲控制器60之控制下延遲該内部上升 時脈rclk及該内部下降時脈fcik。同樣地，虛設延遲線5〇延 遲該輸入時脈緩衝器20之輸出時脈，進而將該經延遲時脈 傳送至複製模型電路70中從而產生反饋時脈fbclk。虛設延 遲線5 0之内部結構類似於延遲線4 〇之結構，但是當輸入經 除頻時脈時，虛設延遲線5 0可減少功率消耗。 該複製模型電路70將虛設延遲線50之輸出延遲一預定 置’其精由模型化時脈傳遞之延遲量而估計，在外部時脈 自外部裝置輸入之後’由外部時脈轉換之内部時脈在該時 脈傳遞中被輸出至外部裝置。該時脈傳遞包括複數個延遲 部件（delay element) ’諸如虛設時脈緩衝器、輸出緩衝器、 時脈除頻器等。此等延遲部件確定誤差值作為DLL特徵。 可藉由收縮、簡化或複製複數個延遲部件來模型化複製模 型電路70。 時脈訊號線80用作一時脈驅動器，其用於產生一驅動訊 號以用於基於自延遲線40輸出之輸出訊號ρουτ來控制該 輸出緩衝器90。輸出緩衝器90將經由資料匯流排由半導體 記憶體裝置之核心區域輸入之資料與驅動訊號同步地輸出 至輸出端子。 圖2為描繪延遲線40之示意性電路圖。 3亥延遲線40包括複數個单位延遲單元元件（unit delayBACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a delay locked loop circuit, and more particularly to a method for controlling synchronous dynamic random access based on operating conditions such as pressure or temperature. A memory device that delays the output of a locked loop circuit in a memory (SDRAM). [Prior Art] A 'delay lock loop (DLL) is generally used to control output data from a semiconductor memory device such as a dynamic random access memory (dram) to an external device by using an external input clock signal. Timing circuit. In order to transfer data from the semiconductor memory device to the chip set or cpu without any errors, the output of the semiconductor memory device is synchronized with the clock signal generated from the chip set or the cpu. When a clock signal is transmitted to an internal control block in the semiconductor memory device/internal control block transmission from the semiconductor memory device, the clock signal is due to one of the input clock buffers, a line load, and the data. Output buffers and other blocks are delayed. Therefore, there is a phase difference between an external clock signal and an internal clock signal generated inside the semiconductor memory device. In order to synchronize the internal clock signal with the external clock signal, the DLL is used to compensate for the phase difference. The DLL compensates for the clock skew caused by the delay of the internal clock of the internal block in the semiconductor memory device and thereby synchronizes the output timing of the data from the semiconductor memory device with the external clock signal. As a result, the data output timing of the data output buffer is synchronized with the external clock signal by the internal clock signal 112632.doc 1322575 sensed by the core region of the semiconductor memory device. DLLs are known to be classified as analog DLLs and digital DLL circuits. The digital DLL circuit can be constructed in various ways, including a register control DL]L, a hybrid DIX, a synchronous mirror DLL, an estimation control DLL, and the like. 1 is a block diagram showing a conventional delay locked loop. The conventional delay locked loop includes an input clock buffer 丨〇 to 2 〇, a phase comparator 30, a delay line 40, a dummy delay line 5 〇, a delay controller 60, a replica model circuit 70, and a clock. The signal line 8〇 and an output buffer 90 〇 include a rising edge clock buffer 1〇 and a falling edge clock buffer 丨丨 input clock buffer buffering the external clock ridge and Clkb to generate an internal rise Clock rdk and an internal falling clock fclk. The rising edge clock buffer 丨〇 generates an internal rising clock rclk synchronized with the rising edge of the input clock Cik, and the falling edge clock buffer 11 generates an internal phase synchronized with the falling edge of the input clock clkb Decrease the clock fclk. The phase comparator 30 compares the phase of the internal rising clock rcik with the phase of the feedback clock output from the rewound model circuit 70 to detect the phase difference between the internal rising clock rxlk and the feedback clock fbdk. In order to reduce the power consumption, the phase comparator 30 can replace the internal rising clock rcUc and the feedback clock fbclk, and compare a de-frequency clock with a low frequency generated by a clock divider (not shown). The feedback clock fbclke generates a output signal for controlling the delay controller 6 according to the comparison result. The output signal assumes one of three states, that is, a hysteresis - % is then 2632.doc ·: 3 1322575 state and a locked state. The a delay controller 60 includes a plurality of shift registers and controls the delay line 4 〇 and the dummy delay line 5 基于 based on the output signals received from the phase comparator 30. The delay line 40 delays the internal rising clock rclk and the internal falling clock fcik under the control of the delay controller 60. Similarly, the dummy delay line 5 delays the output clock of the input clock buffer 20, and the delayed clock is transferred to the replica model circuit 70 to generate the feedback clock fbclk. The internal structure of the dummy delay line 50 is similar to the structure of the delay line 4 ,, but the dummy delay line 50 can reduce power consumption when the frequency-divided clock is input. The replica model circuit 70 delays the output of the dummy delay line 50 by a predetermined amount, which is estimated by the delay amount of the modeled clock transmission. After the external clock is input from the external device, the internal clock is converted by the external clock. It is output to the external device during the clock transmission. The clock pass includes a plurality of delay elements such as a dummy clock buffer, an output buffer, a clock divider, and the like. These delay components determine the error value as a DLL feature. The replica model circuit 70 can be modeled by shrinking, simplifying, or replicating a plurality of delay components. The clock signal line 80 is used as a clock driver for generating a drive signal for controlling the output buffer 90 based on the output signal ρουτ output from the delay line 40. The output buffer 90 outputs the data input from the core area of the semiconductor memory device via the data bus to the output terminal in synchronization with the drive signal. FIG. 2 is a schematic circuit diagram depicting delay line 40. 3 Hai delay line 40 includes a plurality of unit delay unit elements (unit delay

112632.doc C S 1322575 umt cell) UDC1至UDC5及複數個「反及」（NAND)閘ND11 至ND15。該複數個單位延遲單元元件ud C1至UD C 5之每一 者皆對應於自延遲控制器60輸出之複數個暫存器訊號112632.doc C S 1322575 umt cell) UDC1 to UDC5 and a plurality of "NAND" gates ND11 to ND15. Each of the plurality of unit delay unit elements ud C1 to UD C 5 corresponds to a plurality of register signals output from the delay controller 60

Reg_i^Reg—0之每一者及複數個r反及」閘ndii至ND15 的每一者 0 複數個「反及」閘ND 11至ND15之每一者執行複數個暫存 器訊號Reg一η至Reg 一 〇之每一者與内部上升時脈rclk及内部 下降時脈fclk之一者之一邏輯「反及」運算。由於該邏輯「反 及」運算’參考時脈訊號（意即，内部上升時脈“比及内部 下降時脈fclk之一者）輸入至一接收對應之暫存器訊號（意 即，Reg_nS Reg一 〇之一者，其具有一邏輯高位準）的單位延 遲單元元件中》因此’延遲傳遞形成於延遲線4〇之内部。 例如UDC1之每一單位延遲單元元件均包括一第一「反 及」閘ND1及一第二「反及」閘ND2。該第一「反及」閘 ND1執行電源電壓vdD與對應之「反及」閘（意即，NDU) 之輸出之一邏輯「反及」運算；且該第二「反及」閘ND2 執行電源電壓VDD與第一「反及」閘ND1<輸出之一邏輯 「反及」運算。由於其他單位延遲單元元件具有相同結構， 因此省略其詳細描述β 延遲線40可針對内部上升時脈rclk及内部下降時脈 包括具有以上所描述之結構的兩個延遲線單元。在此情況 下，延遲線40可同時對内部上升時脈^化及内部下降時脈 fclk執行延遲補償操作。結果，可最大化抑制占空率失真。 習知DLL產生僅具有一相位之肌輸出時脈，且該肌 I12632.doc 丄以y/5 輸出時脈用於控制自半導體記憶體裝置輸出之資料的時序 且用於驅動其令複數個控制電路。然而，若^^:輸出時脈 之操作裕度在高頻率操作或諸如壓力、溫度或輸入電壓位 準之操作條件之變化下減小，則當具有一相位之一DLL輸 出時脈用於控制複數個控制電路時，半導體記憶體裝置之 操作可靠性下降。 【發明内容】Each of Reg_i^Reg—0 and a plurality of r are reversed to each of the gates ndii to ND15. Each of the plurality of “reverse” gates ND 11 to ND15 executes a plurality of register signals Reg-η. Each of Reg has a logical "reverse" operation with one of the internal rising clock rclk and the internal falling clock fclk. Since the logic "reverse" operation 'reference clock signal (that is, one of the internal rising clock "and one of the internal falling clocks fclk" is input to a receiving corresponding register signal (ie, Reg_nS Reg one) In one of the unit delay unit elements, which has a logic high level, the 'delay transfer' is formed inside the delay line 4〇. For example, each unit delay unit element of UDC1 includes a first "reverse". Gate ND1 and a second "reverse" gate ND2. The first "reverse" gate ND1 performs a logical "reverse" operation on the output of the power supply voltage vdD and the corresponding "reverse" gate (ie, NDU); and the second "reverse" gate ND2 performs a power supply The voltage VDD is logically "reverse" with the first "reverse" gate ND1< Since other unit delay unit elements have the same structure, a detailed description thereof will be omitted. The β delay line 40 may include two delay line units having the above-described structure for the internal rising clock rclk and the internal falling clock. In this case, the delay line 40 can perform a delay compensation operation on the internal rising clock and the internal falling clock fclk at the same time. As a result, the duty ratio distortion can be maximally suppressed. The conventional DLL generates a muscle output clock having only one phase, and the muscle I12632.doc is used to control the timing of the data output from the semiconductor memory device with a y/5 output clock and is used to drive the plurality of controls. Circuit. However, if the operating margin of the output clock is reduced under high frequency operation or operating conditions such as pressure, temperature or input voltage level, then one of the DLL output clocks is used for control. When a plurality of control circuits are used, the operational reliability of the semiconductor memory device is degraded. [Summary of the Invention]

本發明之一目標為提供一種半導體記憶體裝置，其藉由 使用具有不同於DLL輸出時脈之相位的輸出時脈來增強延 遲鎖定迴路的操作裕度。 本發明之另-目標為提供—種半導體記憶體裝置，該半 導體記憶體裝置用於控制一以高頻率或在諸如廢力、溫度 或輸入電壓位準之操作條件變化的情況下操作之延遲鎖定 迴路（DLL)的輸出。 根據本發明之-態樣提供-種延遲鎖定迴路，該延 定迴路包括一時脈延遲補償區塊，其用於接收一自夕 入之時脈訊號，進而產生一第一多時脈及一第二多時脈 ::位控制區塊比較-第-多時脈與該第二多時脈以產, :制-移位操作之相位控制訊號一多相延遲控制區力 :於相位控制訊號來執行移位操作以控制時脈延遲箱 塊0 【貫施方式】 描述根據本發明之特定 下文中，將參看隨附圖式來詳細 實施例之記憶體裝置。 U2632.doc 1322575 根據本發明之半導體記憶體裝置尤其提供增強的延遲鎖 定迴路（DLL)功能。 圖3為展示根據本發明之實施例之供半導體記憶體裝置 使用之延遲鎖定迴路的方塊圖。 該延遲鎖定迴路包括一時脈延遲補償區塊、一相位控制 器180及一多相延遲控制器13〇。該時脈延遲補償區塊包括 時脈緩衝益1 〇 〇、1 〇 1及11 0、一相位比較器丨2 〇、一延遲 控制器160、一多相延遲線14〇、一虛設延遲線15〇、一複製 模型170及一輸出緩衝器2〇〇。 時脈延遲補償區塊接收一自外部輸入之時脈訊號及 clkb，以產生一第一多時脈MpCLK及一第二多時脈 MPOUT »藉由接收該第一多時脈MpCLK &該第二多時脈 MPOUT，該相位控制器1 8〇比較第一多時脈MpCLK與該第 一夕％脈MPOUT，且基於比較結果，產生相位控制訊號 价、src、slo及Sle。該等相位控制訊號sre、爪、si〇及a 用於控制一移位操作。多相延遲控制器13〇基於該等相位控 制訊號sre、Src、sl〇及sle執行移位操作，從而控制時脈延 遲補償區塊。 時脈緩衝器1 00及1 〇 1接收該時脈訊號elk& ^以且緩衝該 等時脈訊號elk及clkb ’以產生上升時脈㈣及下降時脈 felk。6亥b^·脈緩衝器包括一上升緣時脈緩衝器1 及一下降 緣時脈緩衝器10卜藉由接收該等時脈訊號仙及⑽，上升 T時脈緩衝器1〇1產生與時脈訊號clk之上升緣同步的上升 k脈rxlk »同樣地’藉由接收時脈訊號仙及具有與時脈訊 112632.doc 1322575 號elk之相位相反的時脈訊號cUcb，下降緣時脈緩衝器 產生與時脈訊號elk之下降緣同步的下降時脈feUc。 相位比較器1 20比較上升時脈rclk、下降時脈fclk咬兩者 與反饋内部時脈fbclk ’以將一比較結果輸出至延遲控制器 - 160中。在另一實施例中’相位比較器120接收自一時脈除 . 頻器（未圖示）輸出之經除頻時脈，且比較該經除頻時脈與該 反饋内部時脈fbclk，以減少功率消耗。由於自時脈除頻器 輸出之經除頻時脈的頻率低於上升時脈rclk或下降時脈 ® fclk的頻率，故相位比較器120可減少比較操作中之功率消 耗。根據比較結果而自相位比較器12〇輸出至延遲控制器 160的輸出訊號表示三種狀態之一：超前、滞後或鎖定。 基於相位比較器12 0之比較結果，延遲控制器！ 6 〇執行一 移位操作，以將暫存器訊號Reg—η至Reg_0輸出至多相延遲 線140及虛設延遲線丨5〇，以用於控制相位延遲量。在本文 中，η為正整數。延遲控制器16〇包括複數個移位暫存器， 且該複數個移位暫存器可確定多相延遲線Μ〇及虛設延遲 線15 0的初始最大或最小相位延遲量。 包括複數個雙向移位暫存器之多相延遲控制器13〇根據 自相位控制器180輸出之相位控制訊號sre、sr〇、31〇及3丨6 , 來將延遲控制訊號oc<1:n>輸出至多相延遲線14〇。相位控 制訊號包括一偶數右移位訊號sre及一奇數右移位訊號 sro、一偶數左移位訊號sie及一奇數左移位訊號$丨〇。 根據延遲控制訊號oe<1:n>及暫存器訊號Reg_n至 Reg_〇，夕相延遲線14〇延遲上升時脈rc^及下降時脈&1]<：之 112632.doc 1322575 相位，以產生第一多時脈]^?(：1^尺及第二多時脈Μρ〇υΊ^第 一多時脈MPCLK的相位不同於第二多時脈Μρ〇υτ的相 位》多相延遲線140基於比較結果來延遲上升時脈及下降時 脈以產生第二多時脈MP0UT，且回應於自多相延遲控制器 130輸出之延遲控制訊號〇c<1:n>來產生第一多時脈 MPCLK。 由延遲控制器160控制之虛設延遲線15〇延遲接收時脈訊 號elk之時脈緩衝器UG之輸出訊號以將經延遲訊號輸出至 複製模型17G。複製模型17〇將虛設延遲線15Q之輸出延遲一 基於延遲部件所模型化之預定量以產生反饋内部訊號 fbclk 。 在外部時脈輸入與内部時脈輸出之間的時脈路徑中，除 了延遲鎖定迴路内部之—部分（意即，多相延遲線"Ο)，延 遲Η牛還包括複數個單元，以將與第二多時脈丁同步 的資料輸出與外部時脈訊號同步。結果，延遲部件之精確 模型化確定被視作半導體記憶體裝置之關鍵效能因數的誤 f。對於精確模型化而言，複製模型170可具有用於收縮、 間化或硬製諸如時脈緩衝器、時脈除頻器、輸出緩衝器及 其類似物之延遲部件的結構。 如以上所描述’相位控制器刚根據第二多時脈MPOUT 及第一多時脈MPCLK產㈣於控制多相延遲控制器13〇之 制―一該相位控制 調整白/於諸如製造製程、電壓位準或溫度之PVT條件來 夕相延遲線14G輸出之第—多時脈MPCLK的相位。 I12632.doc 12 日^脈訊號線190將來自多相延遲線14〇之第二多時脈 MPOUT傳送至輸出緩衝器2〇〇。該輸出緩衝器2〇〇接收經由 資料匯流排所傳輸之資料訊號且將該資料訊號與該第二多 時脈MPOUT同步地向外輸出。 圖4為描述圖3中所展示之時脈緩衝器100或10 1之實施例 的示意性電路圖。 該時脈緩衝器1〇〇包括一具有PM〇S電晶體P1及ρ2、 NMOS電晶體Ml、N2及N3及反轉器ινί的差動放大器。該 等時脈訊號elk及clkb輸入至差動放大器之輸入端子，意 即，NMOS電晶體N1及N2之閘極。啟用訊號εν輸入至NMOS 電晶體N3之閘極以用於啟用差動放大器。PM〇s電晶體p ! 及P2介於NMOS電晶體N1及N2與電源電壓VDD之間《在 NMOS電晶體N2之汲極處輸出的差動放大器之輸出訊號由 反轉器ινι反轉且產生為上升時脈rclk。 時脈緩衝器101與110具有類似結構。與時脈緩衝器1〇〇 相比’在時脈緩衝器i 〇丨中，時脈訊號他及clkb以相反次序 輸入至差動玫大器之輸入端子以產生下降時脈fclk。 圖5為圖3中所展示之相位比較器120之實施例的示意性 電路圖。 相位比較器120包括一相位比較單元121及一移位暫存器 控制器125。該相位比較單元12丨包括複數個延遲元件（deUy cell) DC1至DC3、複數個邏輯「反及」閘ND16至ND44、複 數個反轉器IV2至IV7、邏輯「或」（〇R)閘〇Ri、邏輯「反 或」（NOR)閘NOR1及邏輯「及」（And)閘AND1。例如DC1 I12632.doc 13 1322575 之延遲元件將上升時脈rclk及下降時脈fclk延遲一預定時 間。 相位比較單元i 2 1比較反饋内部訊號fbcik、上升時脈rclk 或下降時脈fclk及第二多時脈MPOUT，且基於比較結果輸 出指不超前、滯後、鎖定之資訊。藉由比較訊號PC 1及PC3 確定右移位操作且藉由比較訊號PC2及PC4確定左移位操 作。執行右移位操作及左移位操作以用於控制多相延遲線 140及虛設延遲線15〇的延遲量。 在相位比較單元丨21中，延遲元件DC1至DC3將反饋内部 號及上升時脈或下降時脈延遲一預定時間。組態至複數 個邏輯「反及」閘及複數個反轉器之邏輯區塊比較反饋内 部訊號fbclk、上升時脈rclk或下降時脈fclk與自延遲元件 DC 1至DC3輸出的經延遲反饋内部訊號及經延遲上升時脈 或下降時脈以輸出比較結果。為了縮短鎖定操作時間，當 上升時脈rclk或下降時脈fcik與反饋内部訊號比(;以之間存 在大的相位差時，延遲加速模式控制單元接收第二多時脈 MPOUT且比較自邏輯區塊輸出之比較結果AC與第二多時 脈MPOUT以啟用一延遲加速模式。 s亥相位比較單元！ 2 1基於第二多時脈Μρ〇υτ或上升時脈 rclk或下降時脈fclk與反饋内部訊號fbcik2比較結果來確 定疋否執行移位操作。舉例而言，若使用具有1/8比率之除 頻器，則藉由使用八單位延遲元件來比較兩個時脈之間的 相位。根據用於右或左移位操作之比較結果使用經除頻時 脈或未經除頻時脈。It is an object of the present invention to provide a semiconductor memory device that enhances the operational margin of the delay locked loop by using an output clock having a phase different from the DLL output clock. Another object of the present invention is to provide a semiconductor memory device for controlling a delay lock operating at high frequencies or under varying operating conditions such as waste force, temperature or input voltage levels. The output of the loop (DLL). According to the aspect of the present invention, a delay locked loop is provided, the extended loop including a clock delay compensation block for receiving a clock signal from a eve, thereby generating a first multi-clock and a first Two more clocks:: bit control block comparison - first-multiple clock and the second multi-clock to produce, phase control signal of the system-shift operation - multi-phase delay control zone force: in the phase control signal The shift operation is performed to control the clock delay block 0. [Detailed Description] DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the memory device of the detailed embodiment will be described with reference to the accompanying drawings. U2632.doc 1322575 A semiconductor memory device in accordance with the present invention provides, inter alia, an enhanced delay locked loop (DLL) function. 3 is a block diagram showing a delay locked loop for use with a semiconductor memory device in accordance with an embodiment of the present invention. The delay locked loop includes a clock delay compensation block, a phase controller 180, and a polyphase delay controller 13A. The clock delay compensation block includes a clock buffer 1 〇〇, 1 〇 1 and 11 0, a phase comparator 丨 2 〇, a delay controller 160, a polyphase delay line 14 〇, and a dummy delay line 15 〇, a copy model 170 and an output buffer 2〇〇. The clock delay compensation block receives a clock signal and clkb from the external input to generate a first multi-clock MpCLK and a second multi-clock MPOUT » by receiving the first multi-clock MpCLK & The two-phase clock MPOUT, the phase controller 1 8 〇 compares the first multi-time clock MpCLK with the first eve % pulse MPOUT, and based on the comparison result, generates a phase control signal price, src, slo, and Sle. The phase control signals sre, claws, si 〇 and a are used to control a shift operation. The multiphase delay controller 13 performs a shift operation based on the phase control signals sre, Src, sl, and sle to control the clock delay compensation block. The clock buffers 1 00 and 1 〇 1 receive the clock signal elk& and buffer the clock signals elk and clkb' to generate a rising clock (4) and a falling clock felk. The 6th b^ pulse buffer includes a rising edge clock buffer 1 and a falling edge clock buffer 10. By receiving the clock signals and (10), the rising T clock buffer 1〇1 is generated and The rising edge of the clock signal clk is synchronized with the rising k-pulse rxlk » Similarly, by receiving the clock signal and the clock signal cUcb having the opposite phase to the e-mail of 112632.doc 1322575, the falling edge clock buffer The device generates a falling clock feUc synchronized with the falling edge of the clock signal elk. The phase comparator 1 20 compares both the rising clock rclk and the falling clock fclk bite with the feedback internal clock fbclk ' to output a comparison result to the delay controller - 160. In another embodiment, the 'phase comparator 120 receives the divided clock output from a clock divider (not shown) and compares the divided clock with the feedback internal clock fbclk to reduce Power consumption. Since the frequency of the frequency-divided clock output from the clock divider is lower than the frequency of the rising clock rclk or the falling clock ® fclk, the phase comparator 120 can reduce the power consumption in the comparison operation. The output signal output from the phase comparator 12A to the delay controller 160 based on the comparison result indicates one of three states: lead, lag, or lock. Based on the comparison result of the phase comparator 120, the delay controller! 6 〇 A shift operation is performed to output the register signals Reg_η to Reg_0 to the polyphase delay line 140 and the dummy delay line 丨5〇 for controlling the phase delay amount. In this paper, η is a positive integer. The delay controller 16A includes a plurality of shift registers, and the plurality of shift registers determine the initial maximum or minimum phase delay amount of the polyphase delay line 虚 and the dummy delay line 150. The multi-phase delay controller 13 including a plurality of bidirectional shift registers stores the delay control signals oc<1:n> based on the phase control signals sre, sr〇, 31〇, and 3丨6 output from the phase controller 180. ; Output to the polyphase delay line 14〇. The phase control signal includes an even right shift signal sre and an odd right shift signal sro, an even left shift signal sie and an odd left shift signal $丨〇. According to the delay control signal oe<1:n> and the register signals Reg_n to Reg_〇, the phasic delay line 14〇 delays the rising clock rc^ and the falling clock &1]<: 112632.doc 1322575 phase To generate the first multi-clock]^?(:1^foot and the second multi-clock Μρ〇υΊ^ the phase of the first multi-clock MPCLK is different from the phase of the second multi-cycle Μρ〇υτ” The line 140 delays the rising clock and the falling clock based on the comparison result to generate the second multi-clock MPOUT, and generates the first multi-step in response to the delay control signal 〇c<1:n> output from the multi-phase delay controller 130. The clock MPCLK. The dummy delay line 15 controlled by the delay controller 160 delays the output signal of the clock buffer UG receiving the clock signal elk to output the delayed signal to the replica model 17G. The replica model 17 虚 dummy delay line The output delay of 15Q is based on a predetermined amount modeled by the delay component to generate a feedback internal signal fbclk. In the clock path between the external clock input and the internal clock output, in addition to delaying the internal portion of the locked loop (ie , multi-phase delay line "Ο), delayΗ The cow also includes a plurality of units to synchronize the data output synchronized with the second multi-time clock with the external clock signal. As a result, the accurate modeling of the delay component determines the error of the critical performance factor of the semiconductor memory device. For accurate modeling, the replication model 170 may have structures for shrinking, inter-sequencing, or hardening delay components such as clock buffers, clock dividers, output buffers, and the like. Description 'The phase controller has just been based on the second multi-clock MPOUT and the first multi-clock MPCLK (four) to control the multi-phase delay controller 13 - one of the phase control adjustments / such as manufacturing process, voltage level or The PVT condition of the temperature is the phase of the multi-clock MPCLK outputted by the phasing delay line 14G. I12632.doc 12-day pulse line 190 transmits the second multi-time pulse MPOUT from the polyphase delay line 14〇 to the output buffer The output buffer 2 receives the data signal transmitted via the data bus and outputs the data signal in synchronization with the second multi-clock MPOUT. FIG. 4 is a diagram showing the display in FIG. It A schematic circuit diagram of an embodiment of a pulse buffer 100 or 10. The clock buffer 1 includes a difference between a PM〇S transistor P1 and a ρ2, NMOS transistors M1, N2 and N3, and an inverter ινί. The operational amplifier signals are input to the input terminals of the differential amplifier, that is, the gates of the NMOS transistors N1 and N2. The enable signal εν is input to the gate of the NMOS transistor N3 for enabling the difference. The dynamic amplifier. PM〇s transistor p ! and P2 are between the NMOS transistors N1 and N2 and the power supply voltage VDD. The output signal of the differential amplifier outputted at the drain of the NMOS transistor N2 is reversed by the inverter ινι It is generated as a rising clock rclk. The clock buffers 101 and 110 have a similar structure. In contrast to the clock buffer 1 ’, in the clock buffer i ,, the clock signal and clkb are input to the input terminals of the differential amplifier in reverse order to generate the falling clock fclk. FIG. 5 is a schematic circuit diagram of an embodiment of the phase comparator 120 shown in FIG. The phase comparator 120 includes a phase comparison unit 121 and a shift register controller 125. The phase comparison unit 12A includes a plurality of delay elements (deUy cells) DC1 to DC3, a plurality of logic "reverse" gates ND16 to ND44, a plurality of inverters IV2 to IV7, and a logical "or" (〇R) gate. Ri, logical "NOR" gate NOR1 and logical "And" (AND) gate AND1. For example, the delay element of DC1 I12632.doc 13 1322575 delays the rising clock rclk and the falling clock fclk by a predetermined time. The phase comparison unit i 2 1 compares the feedback internal signal fbcik, the rising clock rclk or the falling clock fclk, and the second multi-time pulse MPOUT, and outputs information indicating no advance, lag, and lock based on the comparison result. The right shift operation is determined by comparing signals PC 1 and PC 3 and the left shift operation is determined by comparing signals PC2 and PC4. A right shift operation and a left shift operation are performed for controlling the amount of delay of the polyphase delay line 140 and the dummy delay line 15A. In the phase comparison unit 丨21, the delay elements DC1 to DC3 delay the feedback internal number and the rising clock or the falling clock by a predetermined time. The logic block configured to a plurality of logical "reverse" gates and a plurality of inverters compares the feedback internal signal fbclk, the rising clock rclk or the falling clock fclk with the delayed feedback of the self-delay element DC 1 to DC3 output The signal is delayed by the rising clock or the falling clock to output a comparison result. In order to shorten the locking operation time, when the rising clock rclk or the falling clock fcik is compared with the feedback internal signal (; when there is a large phase difference between, the delay acceleration mode control unit receives the second multi-time pulse MPOUT and compares from the logic region The block output comparison result AC and the second multi-time pulse MPOUT to enable a delay acceleration mode. sHai phase comparison unit! 2 1 based on the second multi-cycle Μρ〇υτ or rising clock rclk or falling clock fclk and feedback internal The signal fbcik2 compares the result to determine whether or not to perform the shift operation. For example, if a frequency divider having a 1/8 ratio is used, the phase between the two clocks is compared by using eight unit delay elements. The comparison result of the right or left shift operation uses a divided or undivided clock.

Il2632.doc 1322575 回應於自相位比較單元12丨輸出之三種狀態，移位暫存器 控制器125產生相位比較訊號SR1、SR2、儿1及儿2之不同 組合。若資訊表示一鎖定狀態，則不啟動一相位控制訊號。 圖6為圖3中所展示之延遲控制器16〇的示意性電路圖。 組態於複數個級中之延遲控制器16〇包括複數個邏輯「反 或j閉N0R2至N0R7、複數個邏輯r反及」閘腦57至則62、 複數個邏輯NMOS電晶體N4至N27及複數個反轉器ivil至 IV16 〇 例如輸出暫存器訊號Reg_l之級的每一級皆包括一反轉 鎖存器、一切換單元及一邏輯單元。該切換單元包含四個 NMOS電晶體（例如>^8至！^11)，以回應於複數個相位比較訊 號SRI、SR2、SL1及SL2來控制左移位或右移位操作。反轉 鎖存器包含一例如ND58之邏輯「反及」閘及一例如IV12之 反轉器’以鎖存切換單元之輸出。例如N〇R3之邏輯單元接 收先前級及下一級之輸出且執行一邏輯運算，進而產生例 如Reg_l之暫存器訊號。 複數個級之邏輯單元回應於複數個相位比較訊號SRi、 SR2、SL1及SL2而執行移位操作且產生暫存器訊號Reg_n· i 至Reg-〇。根據一初始條件，延遲控制器160可確定多相延 遲線140及虛設延遲線15〇之最小或最大延遲量。再者，為 了執行恰當移位操作（例如避免移位摺疊（shifting collapse))，延遲控制器16〇防止複數個相位比較訊號sri、 SR2、SL1及SL2的重疊。 圖7為圖3中所展示之多相延遲線14〇之示意性電路圖。 112632.doc 15 1322575 該多相延遲線140包括一第一邏輯組合單元141、複數個 延遲單元元件UDC6至UDC10及輸出控制器142。 第一邏輯組合單元14 1包含複數個「反及」閘以執行上升 時脈rclk或下降時脈fcik與暫存器訊號Reg—n」至Reg_〇i 一邏輯運算’以將結果輸出至每一延遲單元元件中。因此， 藉由複數個延遲單元元件UDC6至UDC10中一接收一具有 邏輯高位準之暫存器訊號的延遲單元元件來形成一延遲路 徑。複數個延遲單元元件UDC6至UDC10之每一者對應於暫 存器訊號Reg一η-1至Reg_0之每一者。 包含複數個邏輯「反及」閘ND63至ND72之複數個延遲 單元元件UDC6至UDC10基於第一邏輯組合單元141之輸出 來控制第二多時脈MPOUT的延遲量。舉例而言，延遲單元 元件UDC6包括兩個邏輯「反及」閘ND63及ND64。該邏輯 「反及」閘ND63接收電源電壓VDD及邏輯「反及」閘73之 輸出且產生至邏輯「反及」閘ND64的邏輯「反及」運算之 輸出；且’同樣地，邏輯「反及」閘ND65執行電源電壓VDD 與邏輯「反及」閘63之輸出之邏輯「反及」運算，且將結 果輸出至輸出控制器142及下一延遲單元元件UDC7。最末 延遲單元元件UDC10將第二多時脈MPOUT輸出至時脈訊 號線19(N延遲單元元件UDC 7至1 0具有類似結構，且因此， 不再進一步詳細描述。 輸出控制器142包括複數個傳輸閘T1至Τη及複數個反轉 器1V17至1V20。回應於延遲控制訊號oc<n: ι>而選擇性接通 複數個傳輸閘之每一者，從而用於將自複數個延遲單元元 112632.doc 1322575 件UDC6至UDC10產生之複數個訊號作為第一多時脈 MPCLK予以輸出。本文中，η為正整數。 圖8為圖3申所展示之多相延遲控制器13〇之示意性電路 圖。 具有複數個級之該多相延遲控制器13〇包括複數個邏輯 「反或」閘NOR8至N0R12、複數個邏輯「反及」閘nd78 至ND83、複數個NM0S電晶體n28至N51及複數個反轉器 IV21至IV26。多相延遲控制器13〇之每一級均包括一反轉鎖 存器L、一切換單元s及一第二邏輯單元 在輸出延遲控制訊號oc[n_l]之級中，反轉鎖存器L具有一 邏輯「反及」閘79及一反轉器IV22e為了初始化，將一重 設訊號輸入該邏輯「反及」閘79。該切換單元s回應於自相 位控制器180所輸出之相位控制訊號sre、sr〇、si〇、sU而控 制反轉鎖存器L中所鎖存之邏輯值。每一級之第二邏輯單元 C接收先前級及下一級中之每一第二邏輯單元之輪出且執 行一邏輯運异，進而產生延遲控制訊號〇c[n_丨]。 在切換單元S中，NMOS電晶體N32由偶數右移位訊號sre 控制，且由先刖級之反轉鎖存器控制之NM〇s電晶體N33用 於藉由NMOS電晶體N32將一接地電壓供應至反轉鎖存器 L。同樣地，奇數右移位訊號sr〇控制之NM〇s電晶體N34及 下一在前的反轉鎖存器所控制之NM〇s電晶體用於將一接 地電壓供應至該反轉鎖存器L。 參看圖8,每一級之切換單元3由相位控制訊號订6、sr〇、 slo、sle之不同組合（例如sr_sle、…與山、⑽與a等） 112632.doc •17· 1322575 來控制。本文中’根據初始條件，多相延遲控制器1 3 〇可確 定多相延遲線140及虛設延遲線150之最小或最大延遲量。 再者’為了執行恰當移位操作，例如，避免移位摺疊，延 遲控制器160防止相位控制訊號sre、sro、slo、sle出現兩邏 輯高狀態訊號重疊。 圖9為圖3中所展示之相位控制器180之示意性電路圖。 5亥相位控制器1 8 0包括一相位比較區塊1 8 1、一正反器區 塊183及一第三邏輯區塊184。 包括一延遲元件182、複數個邏輯「反及」閘ND84至ND90 及複數個反轉器IV27及IV28的相位比較區塊181比較第一 多時脈MPCLK與第二多時脈MP0UT。相位比較區塊1 8 1將 該比較結果輸出至該第三邏輯區塊丨84。 包含複數個邏輯「反及」閘及複數個反轉器IV29至IV31 之正反器區塊183接收第一多時脈MPCLK且將經正反改變 之多時脈輸出至第三邏輯區塊184。 接收自相位比較區塊1 8 1輸出之比較結果及自正反器區 塊1 83輸出之經正反改變之多時脈，第三邏輯區塊1 84執行 不同邏輯組合以產生相位控制訊號 sre 、 sro 、 slo ' sle » 圖10為圖9中所展示之延遲元件182的示意性電路圖。 延遲元件182包括一具有複數個反轉器IV32及IV33、暫存 器R及電容器C之RC延遲元件。該延遲元件182基於暫存器R 及電容器C將第二多時脈MP0UT延遲一預定時間。 操作描述如下。相位控制器1 80比較第一多時脈MPCLK 之相位與第二多時脈MP0UT之相位以基於比較結果產生 -18* 112632.doc 相位控制訊號sre、sro、slo及sle之不同組合。相位控制器 180具有一由模式暫存器設定（MRS)或熔絲斷路器所設定之 預定延遲量。 如先前所插述，偶數右移位訊號sre及奇數右移位訊號sr〇 係用於右移位操作’即，增強多相延遲線140及虛設延遲線 150之延遲量。偶數左移位訊號sle及奇數左移位訊號sl〇係 用於左移位操作，即’減少多相延遲線140及虛設延遲線15〇 之延遲量。此等訊號（意即相位控制訊號sre、sr〇、si〇及sle) 之每一者係以脈衝形狀予以交替產生。 相位控制器18〇偵測第一多時脈]viPCLK與第二多時脈 MP〇UT之間的相位差’且將相位控制訊號sre、sro、slo及 sle輸出至多相延遲控制器13〇 ,從而用於控制第一多時脈 MPCLK及第二多時脈Μρ〇υτ的延遲量。 回應於相位控制訊號sre、sro、sl〇及sie，多相延遲控制 器130控制一移位操作且將該延遲控制訊號〇c<1:n>輸出至 多相延遲線140 » 根據延遲控制訊號oc<l:n>，多相延遲線14〇中之複數個 傳輸閘T1至Τη之一者被接通。因此，多相延遲線140產生第 一多時脈MPCLK，其具有比自延遲單元元件UDC1〇輸出之 第二多時脈MP0UT更提前之相位。此時，當初始操作期間 輸入一重設訊號時，延遲控制訊號oc<1>變成邏輯高位準， 且回應於相位控制訊號s 1 e及s 1 〇 ’第一多時脈mpCLK之相位 超前於第二多時脈MP0UT的相位。 根據本發明之一實施例之多相延遲線14〇可根據包括壓 112632.doc 19 力、電壓位準、溫度及類似項之條件予以控制。根據本發 明之另一實施例之多相延遲線選擇複數個延遲控制訊號 (丨如oc<1 .n>)之一者且經由諸如相位控制器之反饋迴路 將其輸出，即，用於反映輸出MPOUT之比較結果 的反饋迴路被消除。可由模式暫存器設定腿§及炫絲來選 ，複數個延遲控制訊號之一者。另外，藉由使用模式暫存 器設定MRS及溶絲，可調整延遲鎖定迴路中所體現之反饋 迴路的延遲量。 雖然根據圖3中所展不之本發明之實施例僅自多相延遲 線140額外輸出—個相位資訊，但是根據本發明之另一實施 例，藉由使用多相延遲線中之傳輸閘丁丨至乃之複數個輸出 可產生至少一個相位資訊， 如以上所描述，藉由使用具有多相之時脈訊號，根據本 發明之半導體記憶體裝置可根據高頻率操作或諸如壓力、 溫度或所輸入電壓位準之操作條件之一變化來控制延遲鎖 定迴路（DLL)電路之輸出，且改良半導體記憶體裝置中之延 遲鎖定迴路的操作裕度。 本申請案含有與韓國專利申請案第KR 2〇〇5_〇〇9〇951及 KR 2005-01 17134 (分別在2005年9月29日及2〇〇5變12月2日 在韓國專利局中請）相關之發明，其整個内容以引用方式併 入本文中。 雖然已參看特定較佳實施例來描述本發明，但是熟習此 項技術者將明白可在不偏離如以下申請專利範圍所界定之 本發明的精神及範疇情況下做出各種變化及修改。 II2632.doc 1322575 【圖式簡單說明】 圖1為習知延遲鎖定迴路之方塊圖； 圖2為延遲線之示意性電路圖； 圖3為根據本發明之—實施例之供半導體記憶體裝置使 用的延遲鎖定迴路之方塊圖； 圖4為圖3中所展示之時脈緩衝器之實施例的示意性電路 園， 圖5為圖3中所展示之相位比較器之實施例的示意性電路Il2632.doc 1322575 In response to the three states of the output from the phase comparison unit 12, the shift register controller 125 generates different combinations of phase comparison signals SR1, SR2, 1 and 2. If the information indicates a locked state, a phase control signal is not activated. FIG. 6 is a schematic circuit diagram of the delay controller 16A shown in FIG. The delay controller 16 configured in the plurality of stages includes a plurality of logics "reverse or j closed N0R2 to N0R7, a plurality of logics r are reversed", the gates 57 to 62, the plurality of logic NMOS transistors N4 to N27, and A plurality of inverters ivil to IV16, for example, each stage of the stage of the output register signal Reg_l includes a reverse latch, a switching unit and a logic unit. The switching unit includes four NMOS transistors (e.g., >^8 to !^11) to control the left shift or the right shift operation in response to the plurality of phase comparison signals SRI, SR2, SL1, and SL2. The inverting latch includes a logic "reverse" gate such as ND58 and an inverter such as IV12 to latch the output of the switching unit. For example, the logic unit of N〇R3 receives the output of the previous stage and the next stage and performs a logic operation to generate a register signal such as Reg_l. The logic units of the plurality of stages perform a shift operation in response to the plurality of phase comparison signals SRi, SR2, SL1, and SL2 and generate register signals Reg_n·i to Reg-〇. Based on an initial condition, delay controller 160 may determine the minimum or maximum amount of delay for polyphase delay line 140 and dummy delay line 15A. Furthermore, in order to perform an appropriate shift operation (e.g., to avoid shifting collapse), the delay controller 16 prevents overlap of the plurality of phase comparison signals sri, SR2, SL1, and SL2. Figure 7 is a schematic circuit diagram of the polyphase delay line 14A shown in Figure 3. 112632.doc 15 1322575 The multiphase delay line 140 includes a first logic combining unit 141, a plurality of delay unit elements UDC6 to UDC10, and an output controller 142. The first logical combination unit 14 1 includes a plurality of "reverse" gates to perform a rising clock rclk or a falling clock fcik and a register logic Reg_n" to Reg_〇i for a logical operation 'to output the result to each In a delay unit element. Therefore, a delay path is formed by receiving a delay cell element having a logic high level register signal from a plurality of delay cell elements UDC6 to UDC10. Each of the plurality of delay unit elements UDC6 to UDC10 corresponds to each of the register signals Reg_n-1 to Reg_0. The plurality of delay unit elements UDC6 to UDC10 including a plurality of logical "reverse" gates ND63 to ND72 control the delay amount of the second multi-time clock MPOUT based on the output of the first logic combining unit 141. For example, delay unit element UDC6 includes two logical "reverse" gates ND63 and ND64. The logic "reverse" gate ND63 receives the output of the power supply voltage VDD and the logic "reverse" gate 73 and produces an output of a logical "reverse" operation to the logical "reverse" gate ND64; and "samely, the logic "reverses" The gate ND65 performs a logical "reverse" operation of the power supply voltage VDD and the output of the logic "reverse" gate 63, and outputs the result to the output controller 142 and the next delay unit element UDC7. The last delay cell element UDC10 outputs the second multi-clock pulse MPOUT to the clock signal line 19 (the N delay cell elements UDC 7 to 10 have a similar structure and, therefore, will not be described in further detail. The output controller 142 includes a plurality of Transmitting gates T1 to Τη and a plurality of inverters 1V17 to 1V20. Selectively turning on each of the plurality of transmission gates in response to the delay control signal oc<n: ι>, thereby using the plurality of delay unit elements 112632.doc 1322575 The plurality of signals generated by UDC6 to UDC10 are output as the first multi-clock MPCLK. Here, η is a positive integer. Figure 8 is a schematic diagram of the multi-phase delay controller 13 shown in Figure 3. The multi-phase delay controller 13 having a plurality of stages includes a plurality of logical "reverse" gates NOR8 to N0R12, a plurality of logic "reverse" gates nd78 to ND83, a plurality of NM0S transistors n28 to N51, and a plurality of Inverters IV21 to IV26. Each of the stages of the multi-phase delay controller 13 includes an inverting latch L, a switching unit s and a second logic unit in the stage of outputting the delay control signal oc[n_l] , reverse latch L For logic initialization, a logic "reverse" gate 79 and an inverter IV22e are input to the logic "reverse" gate 79. The switching unit s is responsive to the phase control signal sre output from the phase controller 180, Sr〇, si〇, sU control the logic value latched in the inversion latch L. The second logic unit C of each stage receives the rotation and execution of each of the second logic unit in the previous stage and the next stage. A logic difference, and then a delay control signal 〇c[n_丨] is generated. In the switching unit S, the NMOS transistor N32 is controlled by the even right shift signal sre, and is controlled by the inverting latch of the first stage. The NM〇s transistor N33 is used to supply a ground voltage to the inverting latch L through the NMOS transistor N32. Similarly, the odd right shift signal sr〇 controls the NM〇s transistor N34 and the next previous The NM〇s transistor controlled by the inverting latch is used to supply a ground voltage to the inverting latch L. Referring to Fig. 8, the switching unit 3 of each stage is phase-controlled by signal 6, sr〇, Different combinations of slo and sle (eg sr_sle, ... and mountains, (10) and a, etc.) 112632.doc •17· 1 322575 to control. Herein, according to the initial conditions, the polyphase delay controller 13 can determine the minimum or maximum delay amount of the polyphase delay line 140 and the dummy delay line 150. Again, in order to perform an appropriate shift operation, for example, To avoid shift folding, the delay controller 160 prevents the two phase high signal signal overlaps of the phase control signals sre, sro, slo, sle. Figure 9 is a schematic circuit diagram of the phase controller 180 shown in Figure 3. The 5H phase controller 1 800 includes a phase comparison block 181, a flip flop block 183 and a third logic block 184. A phase comparison block 181 including a delay element 182, a plurality of logic "reverse" gates ND84 to ND90 and a plurality of inverters IV27 and IV28 compares the first multi-time clock MPCLK with the second multi-time clock MPOUT. The phase comparison block 181 outputs the comparison result to the third logic block 丨84. The flip-flop block 183 including the plurality of logical "reverse" gates and the plurality of inverters IV29 to IV31 receives the first multi-clock MPCLK and outputs the multi-clock that is changed positively and negatively to the third logic block 184. . Receiving the comparison result of the output from the phase comparison block 1 8 1 and the multi-clockwise change of the positive and negative changes from the output of the flip-flop block 1 83, the third logic block 184 performs different logic combinations to generate the phase control signal sre , sro , slo ' sle » FIG. 10 is a schematic circuit diagram of the delay element 182 shown in FIG. Delay element 182 includes an RC delay element having a plurality of inverters IV32 and IV33, a register R and a capacitor C. The delay element 182 delays the second multi-time pulse MPOUT for a predetermined time based on the register R and the capacitor C. The operation is described below. The phase controller 180 compares the phase of the first multi-clock MPCLK with the phase of the second multi-clock MPOUT to generate different combinations of phase control signals sre, sro, slo, and sle based on the comparison result. Phase controller 180 has a predetermined amount of delay set by a mode register setting (MRS) or a fuse breaker. As previously explained, the even right shift signal sre and the odd right shift signal sr are used for the right shift operation 'i.e., the delay amount of the polyphase delay line 140 and the dummy delay line 150 is enhanced. The even left shift signal sle and the odd left shift signal sl are used for the left shift operation, i.e., to reduce the delay amount of the polyphase delay line 140 and the dummy delay line 15A. Each of these signals (meaning phase control signals sre, sr〇, si, and sle) is alternately generated in a pulse shape. The phase controller 18 detects the phase difference between the first multi-clock]viPCLK and the second multi-clock MP〇UT and outputs the phase control signals sre, sro, slo, and sle to the multi-phase delay controller 13A. Thereby, it is used to control the delay amount of the first multi-clock MPCLK and the second multi-cycle Μρ〇υτ. In response to the phase control signals sre, sro, sl〇, and sie, the polyphase delay controller 130 controls a shift operation and outputs the delay control signal 〇c<1:n> to the polyphase delay line 140 » according to the delay control signal oc<;l:n>, one of the plurality of transmission gates T1 to Τn in the polyphase delay line 14A is turned on. Thus, polyphase delay line 140 produces a first multi-clock MPCLK having a phase that is more advanced than the second multi-time pulse MPOUT output from delay unit element UDC1. At this time, when a reset signal is input during the initial operation, the delay control signal oc<1> becomes a logic high level, and the phase of the first multi-clock mpCLK is advanced in response to the phase control signals s 1 e and s 1 〇 The phase of the two-time clock MP0UT. The polyphase delay line 14A in accordance with an embodiment of the present invention can be controlled based on conditions including voltage 112632.doc 19 force, voltage level, temperature, and the like. A multiphase delay line according to another embodiment of the present invention selects one of a plurality of delay control signals (e.g., oc <1.n>) and outputs it via a feedback loop such as a phase controller, i.e., for reflection The feedback loop that outputs the comparison result of MPOUT is eliminated. It can be selected by the mode register to set the leg § and the glare, and one of the plurality of delay control signals. In addition, the delay of the feedback loop embodied in the delay-locked loop can be adjusted by setting the MRS and the dissolved wire using the mode register. Although an embodiment of the present invention not shown in FIG. 3 additionally outputs only one phase information from the polyphase delay line 140, according to another embodiment of the present invention, by using a transmission gate in a polyphase delay line The plurality of outputs may generate at least one phase information. As described above, the semiconductor memory device according to the present invention may operate according to a high frequency or such as pressure, temperature or by using a multi-phase clock signal. One of the operating conditions of the input voltage level changes to control the output of the delay locked loop (DLL) circuit and to improve the operational margin of the delay locked loop in the semiconductor memory device. This application contains Korean Patent Application No. KR 2〇〇5_〇〇9〇951 and KR 2005-01 17134 (respectively on September 29, 2005 and February 5, 2005 at the Korean Patent Office) The related invention is hereby incorporated by reference in its entirety. Although the present invention has been described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the invention as defined by the following claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a conventional delay locked loop; FIG. 2 is a schematic circuit diagram of a delay line; FIG. 3 is a diagram of a semiconductor memory device for use in accordance with an embodiment of the present invention. Block diagram of a delay locked loop; FIG. 4 is a schematic circuit diagram of an embodiment of the clock buffer shown in FIG. 3, and FIG. 5 is a schematic circuit of an embodiment of the phase comparator shown in FIG.

ran · 圃， 圖6為描繪圖3中所展示之延遲控制器的示意性電路圖； 圖7為圖3中所展示之多相延遲線140的示意性電路圖； 圖為圖3中所展示之多相延遲控制器130的示意性電路 ΙΞ! · 圔， 圖9為圖3中所展示之相位控制器的示意性電路圖；及 圖10為圖9中所展示之延遲元件的示意性電路圖。Ran 圃, FIG. 6 is a schematic circuit diagram depicting the delay controller shown in FIG. 3; FIG. 7 is a schematic circuit diagram of the polyphase delay line 140 shown in FIG. 3; Illustrative circuit diagram of phase delay controller 130: Figure 9, is a schematic circuit diagram of the phase controller shown in Figure 3; and Figure 10 is a schematic circuit diagram of the delay element shown in Figure 9.

【主要元件符號說明】 10 11 20 30 40 50 60 70 時脈缓衝器 時脈緩衝器 時脈緩衝器 相位比較器 延遲線 虛設延遲線 延遲控制器 複製模型 112632.doc 1322575[Main component symbol description] 10 11 20 30 40 50 60 70 Clock buffer Clock buffer Clock buffer Phase comparator Delay line Dummy delay line Delay controller Copy model 112632.doc 1322575

80 時脈訊號線 90 輸出緩衝器 100 時脈緩衝器 101 時脈緩衝器 110 時脈緩衝器 120 相位比較器 121 相位比較單元 125 移位暫存器控制器 130 多相延遲控制器 140 多相延遲線 141 第一邏輯組合單元 142 輸出控制器 150 虛設延遲線 160 延遲控制器 170 複製模型 180 相位控制器 181 相位比較區塊 182 延遲元件 183 正反器區塊 184 第三邏輯區塊 190 時脈訊號線 200 輸出緩衝器 DC1〜DC3 延遲元件 IV1-IV33 反轉器 «*· I12632.doc -22- 1322575 N卜N3 NMOS電晶體 ND16 〜ND44 邏輯「 反及」 閘 ND57 〜ND62 邏輯「 反及」 閘 ND78 〜ND83 邏輯「 反及」 閘 NOR2-NOR7 邏輯「 反或」 閘 N0R8 〜N0R12 邏輯「 反或」 閘 P1 〜P2 PMOS 電晶體 UDC1 〜UDC5 單位延遲單元元 UDC6〜UDC10 延遲單元元件80 clock signal line 90 output buffer 100 clock buffer 101 clock buffer 110 clock buffer 120 phase comparator 121 phase comparison unit 125 shift register controller 130 multi-phase delay controller 140 multi-phase delay Line 141 first logic combination unit 142 output controller 150 dummy delay line 160 delay controller 170 replica model 180 phase controller 181 phase comparison block 182 delay element 183 flip-flop block 184 third logic block 190 clock signal Line 200 Output Buffer DC1 ~ DC3 Delay Element IV1-IV33 Inverter «*· I12632.doc -22- 1322575 N Bu N3 NMOS Transistor ND16 ~ ND44 Logic "Reverse" Gate ND57 ~ ND62 Logic "Reverse" Gate ND78 ~ ND83 logic "reverse" gate NOR2-NOR7 logic "reverse" gate N0R8 ~ N0R12 logic "reverse" gate P1 ~ P2 PMOS transistor UDC1 ~ UDC5 unit delay cell UDC6 ~ UDC10 delay cell components

H2632.doc •23 ·H2632.doc •23 ·