TWI477078B - Capacitive load driving circuit and pulse generating device - Google Patents

電容性負載驅動電路以及脈衝激發裝置Capacitive load drive circuit and pulse excitation device

本發明係有關於驅動電路，特別是關於用於驅動電容性負載的驅動電路。The present invention relates to drive circuits, and more particularly to drive circuits for driving capacitive loads.

壓電傳感器(piezoelectronic transducer)利用壓電效應量測物理性變化，被廣泛應用於超音波，工程力學、生物醫學等技術領域。壓電傳感器需要高電壓的脈衝激發設備，以超音波探頭所需之的驅動電路為例，必須有操作於百萬赫茲的頻率範圍內的能力。傳統產生此脈衝的驅動電路採用高壓簡單脈衝波或步階波來驅動傳輸，對系統產生不必要之高階諧波；而使用線性放大器作為驅動電路時，可降低高頻諧波以改善基頻諧波訊號的線性度，但不可避免的消耗大量靜態功率。因此，在提昇超音波成像對比度與高次諧波成像等需求上，需要一種驅動電路可以提供壓電傳感器乾淨的基頻傳輸諧波，並能夠將功率消耗控制在理想的範圍之內。Piezoelectronic transducers are widely used in ultrasonic, engineering mechanics, biomedical and other technical fields by measuring physical changes using piezoelectric effects. Piezoelectric sensors require a high-voltage pulse-excitation device. For example, the drive circuit required for an ultrasonic probe must have a capability to operate in the frequency range of one million Hz. The driving circuit that generates this pulse traditionally uses high-voltage simple pulse wave or step wave to drive transmission, which generates unnecessary high-order harmonics to the system. When a linear amplifier is used as the driving circuit, the high-frequency harmonics can be reduced to improve the fundamental harmonic. The linearity of the wave signal, but inevitably consumes a lot of static power. Therefore, in order to improve the requirements of ultrasonic imaging contrast and high-order harmonic imaging, a driving circuit is required to provide a clean fundamental frequency transmission harmonic of the piezoelectric sensor, and to control the power consumption within an ideal range.

有鑒於此，本發明之一實施範例揭露了一種驅動電路，用以驅動一電容性負載，上述驅動電路包括：一線性電源裝置，耦接於一訊號源與一輸出節點之間，並接收該訊號源之發出之輸入訊號，據以輸出一第一脈衝訊號至該輸出節點，其中該輸出節點耦接該電容性負載；一回饋單 元，耦接該輸出節點，擷取對應於該輸出節點的一電性訊號而產生一回饋訊號；一前饋單元，耦接該訊號源，產生一前饋訊號；一控制單元，耦接該回饋單元及該前饋單元，使用該前饋訊號對該回饋訊號進行相位補償以產生一控制訊號；以及一可變電源裝置，耦接於該控制單元與該線性電源裝置之間，依據該控制訊號而輸出一第二脈衝訊號至線性電源裝置的電源端，以驅動該線性電源裝置對該電容性負載輸出一驅動訊號。In view of this, an embodiment of the present invention discloses a driving circuit for driving a capacitive load. The driving circuit includes: a linear power supply device coupled between a signal source and an output node, and receiving the The input signal sent by the signal source outputs a first pulse signal to the output node, wherein the output node is coupled to the capacitive load; a feedback form a signal is coupled to the output node to generate a feedback signal corresponding to the electrical signal of the output node; a feedforward unit coupled to the signal source to generate a feedforward signal; and a control unit coupled to the signal The feedback unit and the feedforward unit use the feedforward signal to phase compensate the feedback signal to generate a control signal; and a variable power supply device coupled between the control unit and the linear power supply device, according to the control And outputting a second pulse signal to the power terminal of the linear power supply device to drive the linear power supply device to output a driving signal to the capacitive load.

本發明之另一實施範例揭露了一種脈衝激發裝置，包括：一波束形成單元，具有一激發訊號源；一電容性負載；以及，前述實施範例之驅動電路，耦接該波束形成單元以接收該激發源輸出之該輸入訊號，用以輸出該驅動訊號至該電容性負載。Another embodiment of the present invention discloses a pulse excitation device, including: a beam forming unit having an excitation signal source; a capacitive load; and the driving circuit of the foregoing embodiment coupled to the beam forming unit to receive the The input signal outputted by the excitation source is used to output the driving signal to the capacitive load.

以下揭露之內容可與圖式對照，其中相對應的部件大致以相同的標號註明於圖式上。且其中等效電路的示意圖僅揭示元件之間的連接關係，並未限制元件之相對位置。於以下敘述中，為使易於理解，加入了許多特定的設置細節。然而，具有一般技術知識之人應可理解僅需參考本發明所揭示的部分範例內容便可以實現本發明。於部分範例中，習知的結構與元件以方塊圖的方式呈現，以使內容簡明易懂。The following disclosure may be compared with the drawings, wherein corresponding parts are generally designated by the same reference numerals. The schematic diagram of the equivalent circuit only discloses the connection relationship between the components, and does not limit the relative positions of the components. In the following description, a number of specific setting details have been added for ease of understanding. However, it should be understood by those having ordinary skill in the art that the present invention can be implemented by referring only to some of the examples disclosed herein. In some examples, well-known structures and components are presented in the form of a block diagram to make the content concise.

第1圖為本發明一實施例中，用以驅動電容性負載之驅動電路10的結構方塊圖。該驅動電路10包括一訊號源 110，產生一輸入訊號Vin；該輸入訊號Vin可以是任何形式的交流電訊號或脈衝電訊號。該驅動電路10亦包括一線性電源裝置120耦接於該訊號源110與一輸出節點n_out 之間；該線性電源裝置120接收該輸入訊號Vin，並根據該輸入訊號Vin而形成一第一脈衝訊號Ia，該第一脈衝訊號Ia經由該輸出節點n_out 輸出至一電容性負載180。該線性電源裝置120可包括一轉導放大器(transconductance amplifier)，接收該輸入訊號Vin而產生電流形式的該第一脈衝訊號Ia，並保持訊號之線性度。1 is a block diagram showing the structure of a driving circuit 10 for driving a capacitive load in an embodiment of the present invention. The driving circuit 10 includes a signal source 110 for generating an input signal Vin; the input signal Vin can be any form of alternating current signal or pulsed electrical signal. The driving circuit 10 also includes a linear power supply unit 120 coupled between the signal source 110 and an output node n _out ; the linear power supply unit 120 receives the input signal Vin and forms a first pulse according to the input signal Vin. The first pulse signal Ia is output to a capacitive load 180 via the output node n _out . The linear power supply device 120 can include a transconductance amplifier that receives the input signal Vin to generate the first pulse signal Ia in the form of current and maintains the linearity of the signal.

該驅動電路10更包括一回饋單元140以及一前饋單元160。該回饋單元140耦接於輸出節點n_out ，擷取對應於輸出節點n_out 的電性訊號而產生一回饋訊號S_FB ；該前饋單元160，耦接於該訊號源110，擷取該輸入訊號Vin並將之轉換為一相對應的前饋訊號S_FF 。該回饋單元140可以直接擷取(如第1圖所示)該輸出節點n_out 上的電性訊號；或是透過檢測該線性電源裝置120之電源端(輸入端)的電性訊號，而產生對應於該輸出節點n_out 之電性訊號的該回饋訊號S_F 。The driving circuit 10 further includes a feedback unit 140 and a feedforward unit 160. The feedback unit 140 is coupled to the output node n _out and captures an electrical signal corresponding to the output node n _out to generate a feedback signal S _FB . The feedforward unit 160 is coupled to the signal source 110 and captures the input. The signal Vin is converted into a corresponding feedforward signal S _FF . The feedback unit 140 can directly capture (as shown in FIG. 1) the electrical signal on the output node n _out ; or generate the electrical signal of the power terminal (input) of the linear power supply device 120 to generate The feedback signal S _F corresponding to the electrical signal of the output node n _out .

該驅動電路10更包括一控制單元150，與回饋單元140以及前饋單元160耦接。控制單元150接收該回饋訊號S_FB 以及該前饋訊號S_FF ，並根據該前饋訊號S_FF 對該回饋訊號S_FB 進行相位補償以產生一控制訊號CS。於部份實施例中，控制單元150可為一減法器或比較單元，接收該前饋訊號S_FF 與該回饋訊號S_FB 以取得兩者間的差異值，作為該控制訊號CS。The driving circuit 10 further includes a control unit 150 coupled to the feedback unit 140 and the feedforward unit 160. The control unit 150 receives the feedback signal S _FB and the feedforward signal S _FF , and performs phase compensation on the feedback signal S _FB according to the feedforward signal S _FF to generate a control signal CS. In some embodiments, the control unit 150 can be a subtractor or a comparison unit that receives the feedforward signal S _FF and the feedback signal S _FB to obtain a difference between the two as the control signal CS.

該驅動電路10更包括一可變電源裝置170，耦接於該 控制單元150與線性電源裝置120之間。該可變電源裝置170依據該控制訊號CS而輸出一第二脈衝訊號Is至線性電源裝置120的電源端，進而輔助該線性電源裝置120輸出該第一脈衝訊號Ia。以該第一脈衝訊號Ia作為驅動訊號Id，經由輸出節點n_out 輸出以驅動該電容性負載180。於部份實施例中，該可變電源裝置170可為一可變電流或電壓源，依控制訊號CS輸出電流或電壓形式的該第二脈衝訊號Is，用以供給該線性電源裝置120運作所需電源。The driving circuit 10 further includes a variable power supply device 170 coupled between the control unit 150 and the linear power supply device 120. The variable power supply device 170 outputs a second pulse signal Is to the power supply end of the linear power supply device 120 according to the control signal CS, thereby assisting the linear power supply device 120 to output the first pulse signal Ia. The first pulse signal Ia is used as the driving signal Id, and is output via the output node n _out to drive the capacitive load 180. In some embodiments, the variable power supply device 170 can be a variable current or voltage source, and the second pulse signal Is in the form of a current or voltage output according to the control signal CS for supplying the linear power device 120. Power is required.

第2圖為本發明一實施例中，用以驅動電容性負載之驅動電路100的結構方塊圖。該驅動電路100包括一訊號源110，產生一輸入訊號Vin。於本實施例中，訊號源110例如為一波束形成單元(beam former)，具有一激發訊號源；該訊號源110(波束形成單元)所產生的輸入訊號Vin可以是具有任意振幅及頻率的交流電訊號或脈衝電訊號。該驅動電路100更包括線性電源裝置120，耦接於訊號源110與一電容負載180之間。於本實施例中，該線性電源裝置120為一轉導放大器(transconductance amplifier)，接收該輸入訊號Vin，並根據該輸入訊號Vin形成電流形式的第一脈衝訊號Ia，並保持該第一脈衝訊號Ia對應於該輸入訊號Vin之線性度。該第一脈衝訊號Ia則耦接至輸出節點n_out 。FIG. 2 is a block diagram showing the structure of a driving circuit 100 for driving a capacitive load according to an embodiment of the present invention. The driving circuit 100 includes a signal source 110 for generating an input signal Vin. In this embodiment, the signal source 110 is, for example, a beam former having an excitation signal source; the input signal Vin generated by the signal source 110 (beamforming unit) may be an alternating current having an arbitrary amplitude and frequency. Signal or pulse signal. The driving circuit 100 further includes a linear power supply device 120 coupled between the signal source 110 and a capacitive load 180. In this embodiment, the linear power supply device 120 is a transconductance amplifier, receives the input signal Vin, and forms a first pulse signal Ia in the form of a current according to the input signal Vin, and maintains the first pulse signal. Ia corresponds to the linearity of the input signal Vin. The first pulse signal Ia is coupled to the output node n _out .

該驅動電路100更包括一回饋單元140，以及一前饋單元160。該回饋單元140耦接於輸出節點n_out ，擷取對應於輸出節點n_out 的一電壓訊號，並根據該電壓訊號產生一回饋電壓訊號V_FB 。該回饋單元140亦可包括一線性調變器(linear modulator)先將回饋訊號V_FB 調變後再輸出給第 一、第二比較單元(152a、152b)。該前饋單元160，耦接於訊號源110，前饋單元160擷取該輸入訊號Vin並將之轉換為一相對應的前饋電壓訊號V_FF 。於部份實施例中，為了利用前饋電壓訊號V_FF 對回饋電壓訊號V_FB 進行相位補償，回饋單元140以及前饋單元160更包括進一步將該回饋電壓訊號V_FB 以及該前饋電壓訊號V_FF 的振幅分別做適當的調整，使兩者可以於相同的基準下比較。於部分實施例中，該前饋單元160更可包括一調變器(modulator)，線性調變該前饋電壓訊號V_FF 後再予以輸出，以於下一階段進行比較。於部分其他實施例中，前饋單元160亦可以僅是一導線。The driving circuit 100 further includes a feedback unit 140 and a feedforward unit 160. The feedback unit 140 is coupled to the output node n _out , draws a voltage signal corresponding to the output node n _out , and generates a feedback voltage signal V _FB according to the voltage signal. The feedback unit 140 may further include a linear modulator that first modulates the feedback signal V _FB and then outputs the signal to the first and second comparison units (152a, 152b). The feedforward unit 160 is coupled to the signal source 110. The feedforward unit 160 captures the input signal Vin and converts it into a corresponding feedforward voltage signal V _FF . In some embodiments, in order to phase compensate the feedback voltage signal V _FB by using the feedforward voltage signal V _FF , the feedback unit 140 and the feedforward unit 160 further include the feedback voltage signal V _FB and the feedforward voltage signal V. _FF amplitudes are adjusted appropriately, so that both may be at the same reference comparison. In some embodiments, the feedforward unit 160 further includes a modulator that linearly modulates the feedforward voltage signal V _FF and outputs it for comparison in the next stage. In some other embodiments, the feedforward unit 160 can also be just a wire.

該回饋單元140，亦可以直接擷取該線性電源裝置120的電源輸入端所接收的電流訊號，而產生該回饋電壓訊號V_FB 。The feedback unit 140 can also directly capture the current signal received by the power input terminal of the linear power supply device 120 to generate the feedback voltage signal V _FB .

該驅動電路100更包括一第一控制單元150a以及一第二控制單元150b。該第一、第二控制單元150a、150b，分別包括該第一比較單元152a以及該第二比較單元152b，皆與該回饋單元140以及該前饋單元160耦接。於本實施例中，該第一比較單元152a例如為一減法器電路，接收回饋電壓訊號V_FB 以及前饋電壓訊號V_FF ，並根據回饋電壓訊號V_FB 以及前饋電壓訊號V_FF 的差值產生一第一比較結果Ra，即Ra=(V_FF -V_FB )；該第二比較單元152b亦例如為一減法器電路，接收該回饋電壓訊號V_FB 以及該前饋電壓訊號V_FF ，並根據該回饋電壓訊號V_FB 以及該前饋電壓訊號V_FF 的差值產生一第二比較結果Rb，即Rb=(V_FF -V_FB )。The driving circuit 100 further includes a first control unit 150a and a second control unit 150b. The first and second control units 150a and 150b respectively include the first comparison unit 152a and the second comparison unit 152b, and are coupled to the feedback unit 140 and the feedforward unit 160. In this embodiment, the first comparing unit 152a is, for example, a subtractor circuit, and receives the feedback voltage signal V _FB and the feedforward voltage signal V _FF , and according to the difference between the feedback voltage signal V _FB and the feedforward voltage signal V _FF A first comparison result Ra is generated, that is, Ra=(V _FF -V _FB ); the second comparison unit 152b is also a subtractor circuit, for example, receiving the feedback voltage signal V _FB and the feedforward voltage signal V _FF , and A second comparison result Rb is generated according to the difference between the feedback voltage signal V _FB and the feedforward voltage signal V _FF , that is, Rb=(V _FF −V _FB ).

該第一控制單元150a更包括第一訊號處理單元155a，耦接於該第一比較單元152a。該第一訊號處理單元155a接收來自該第一比較單元152a的第一比較結果Ra，並根據第一比較結果Ra進行格式轉換，產生一相對應的第一控制訊號CSa。The first control unit 150a further includes a first signal processing unit 155a coupled to the first comparison unit 152a. The first signal processing unit 155a receives the first comparison result Ra from the first comparison unit 152a, and performs format conversion according to the first comparison result Ra to generate a corresponding first control signal CSa.

需注意的是，該第一比較單元152a和該第二比較單元152b可使用單一個比較單元進行實作(未圖示)。例如，在實施上僅使用該第一比較單元152a的情況下，該第一比較單元152a則為該第一及第二控制單元150a、150b的共同部分，而該第一比較單元152a的比較結果Ra分別提供給該第一及第二訊號處單元155a、155b，亦能獲得如第2圖架構所示的功能。同理，在實施上僅使用該第二比較單元152a的情況下，該第二比較單元152b的比較結果Rb分別提供給該第一及第二訊號處單元155a、155b亦能獲得如第2圖架構所示的功能。It should be noted that the first comparison unit 152a and the second comparison unit 152b may be implemented using a single comparison unit (not shown). For example, in the case where only the first comparison unit 152a is used for implementation, the first comparison unit 152a is a common portion of the first and second control units 150a, 150b, and the comparison result of the first comparison unit 152a Ra is provided to the first and second signal unit units 155a, 155b, respectively, and the functions as shown in the structure of Fig. 2 are also obtained. Similarly, in the case where only the second comparison unit 152a is used for the implementation, the comparison result Rb of the second comparison unit 152b is provided to the first and second signal unit units 155a, 155b, respectively, as shown in FIG. The features shown in the architecture.

該驅動電路100更包括第一可變電源裝置170a，耦接於該第一訊號處理單元155a。該第一可變電源裝置170a根據該第一控制訊號CSa而調整輸出的訊號。於第2圖之實施例中，該第一可變電源裝置170a例如可為一多階脈衝產生器，包括複數個開關Sp1至Sp4，分別耦接於複數個電流源或電壓源Ip1至Ip4，其中電流源或電壓源Ip1至Ip4所產生的電流為第一方向。在此實施例中，Ip1至Ip4係使用電流源，但是並非限定於此。該第一可變電源裝置170a根據第一控制訊號CSa，控制該等開關Sp1至Sp4之導通-關閉組態，而產生一對應於該第一比較結果Ra的脈衝訊號 Ip，脈衝訊號Ip進而輸出至線性電源裝置120的第一電源端，作為該驅動線性電源裝置120的電源之一。The driving circuit 100 further includes a first variable power supply device 170a coupled to the first signal processing unit 155a. The first variable power supply device 170a adjusts the output signal according to the first control signal CSa. In the embodiment of FIG. 2, the first variable power supply device 170a can be, for example, a multi-stage pulse generator, and includes a plurality of switches Sp1 to Sp4 coupled to a plurality of current sources or voltage sources Ip1 to Ip4, respectively. The current generated by the current source or voltage sources Ip1 to Ip4 is the first direction. In this embodiment, Ip1 to Ip4 use a current source, but are not limited thereto. The first variable power supply device 170a controls the on-off configuration of the switches Sp1 to Sp4 according to the first control signal CSa to generate a pulse signal corresponding to the first comparison result Ra. Ip, the pulse signal Ip is in turn outputted to the first power terminal of the linear power supply unit 120 as one of the power sources for driving the linear power supply unit 120.

於一實施例中，第一訊號處理單元155a包括複數個滯後(Hysteresis)單元，分別接收來自該第一比較單元152a的該第一比較結果Ra，並根據該第一比較結果Ra產生一相對應的控制訊號，分別控制開關Sp1至Sp4。舉例而言，以第一至第四滯後單元(H₁ ~H₄ ，未圖示)分別控制開關Sp1至Sp4進行說明，但是並非限定於此。該第k滯後單元(H_k ，k=1~4)被設定為當第一比較結果Ra大於一第k臨界值TH_k _a時，輸出一第一邏輯狀態的控制訊號至開關Spk(k=1~4)，使開關導通；而當第k比較結果Ra小於一第二臨界值TH_k _b時，輸出一第二邏輯狀態態的控制訊號至開關Spk，使開關關閉，其中該第二臨界值TH_k _b小於或等於該第一臨界值TH_k _a。該第一臨界值TH_k _a與該第二臨界值TH_k _b的值可根據驅動電路的應用而自行設定不同的數值。在此例如設定為TH₁ _a<TH₂ _a<TH₃ _a<TH₄ _a，以及TH₁ _b<TH₂ _b<TH₃ _b<TH₄ _b，但是並非限定於此。In an embodiment, the first signal processing unit 155a includes a plurality of hysteresis units, respectively receiving the first comparison result Ra from the first comparison unit 152a, and generating a corresponding image according to the first comparison result Ra. The control signals respectively control the switches Sp1 to Sp4. For example, the switches Sp1 to Sp4 are respectively controlled by the first to fourth hysteresis units (H ₁ to H ₄ , not shown), but are not limited thereto. The kth lag unit (H _k , k=1~4) is set to output a control signal of the first logic state to the switch Spk when the first comparison result Ra is greater than a kth threshold TH _k _a (k= 1~4), the switch is turned on; and when the kth comparison result Ra is less than a second threshold TH _k _b, a control signal of the second logic state state is outputted to the switch Spk to turn off the switch, wherein the second threshold The value TH _k _b is less than or equal to the first critical value TH _{k — a} . The values of the first threshold TH _{k — a} and the second threshold TH _{k —} b can be set differently according to the application of the driving circuit. Here, for example, TH ₁ _a<TH ₂ _a<TH ₃ _a<TH ₄ _a, and TH ₁ _b<TH ₂ _b<TH ₃ _b<TH ₄ _b are set, but are not limited thereto.

於另一實施例中，該第一訊號處理單元155a可根據該第一比較結果Ra產生一組N位元的第一控制訊號CSa，其中該位元數N係對應於開關的數量，例如於第2圖之實施例中，該第一控制訊號CSa為四位元；而第一可變電源裝置170a根據第一控制訊號CSa，控制該等開關Sp1至Sp4之導通-關閉組態，而產生一對應的該脈衝訊號Ip。例如第一訊號處理單元155a被設定為當第一比較結果Ra大於一第三臨界值TH_k _c時，輸出四位元的第一控制訊號CSa至 第一可變電源裝置170a，該第一控制訊號CSa例如為”0101”；而第一可變電源裝置170a進而根據第一控制訊號CSa，關閉開關Sp2及Sp4並導通開關Sp1及Sp3，使電流源Ip1與Ip3連接至第一可變電源裝置170a，以輸出一第一方向的脈衝訊號Ip，其中Ip=Ip1+Ip3。In another embodiment, the first signal processing unit 155a may generate a set of N-bit first control signals CSa according to the first comparison result Ra, where the number of bits N corresponds to the number of switches, for example, In the embodiment of FIG. 2, the first control signal CSa is four bits; and the first variable power supply device 170a controls the on-off configuration of the switches Sp1 to Sp4 according to the first control signal CSa. A corresponding pulse signal Ip. For example, the first signal processing unit 155a is set to a first comparison result, when Ra is greater than a third threshold value TH _k _c, outputs a first control signal to the first four yuan CSa the variable power supply apparatus 170a, the first control The signal CSa is, for example, "0101"; and the first variable power supply device 170a further turns off the switches Sp2 and Sp4 and turns on the switches Sp1 and Sp3 according to the first control signal CSa, so that the current sources Ip1 and Ip3 are connected to the first variable power supply device. 170a, to output a pulse signal Ip in a first direction, where Ip=Ip1+Ip3.

該第二控制單元150b則更包括第二訊號處理單元155b則耦接於該第二比較單元152b。其中，該第二訊號處理單元155b接收來自該第二比較單元152b的第二比較結果Rb，並根據第二比較結果Rb進行格式轉換，產生一相對應的第二控制訊號CSb以控制相對應的多階脈衝產生器。The second control unit 150b further includes a second signal processing unit 155b coupled to the second comparison unit 152b. The second signal processing unit 155b receives the second comparison result Rb from the second comparison unit 152b, and performs format conversion according to the second comparison result Rb to generate a corresponding second control signal CSb to control the corresponding Multi-order pulse generator.

於一實施例中，該第二訊號處理單元155b包括複數個滯後(Hysteresis)單元，分別接收來自第二比較單元152b的第二比較結果Rb，並根據第二比較結果Rb產生相對應的控制訊號，分別控制開關Sn1至Sn4。以第一至第四滯後單元(G₁ ~G₄ ，未圖示)分別控制開關Sn1至Sn4進行說明，但是並非限定於此。該第m滯後單元(G_m ，p=1~4)被設定為當第二比較結果Ra大於一第p臨界值VH_m _a時，輸出一第一邏輯狀態的控制訊號至開關Spm(m=1~4)，使開關導通；而當第m比較結果Ra小於一第二臨界值VH_m _b時，輸出一第二邏輯狀態態的控制訊號至開關Spm，使開關關閉，其中第二臨界值VH_m _b小於或等於第一臨界值VH_m _a。第一臨界值VH_m _a與第二臨界值VH_m _b的值可根據驅動電路的應用而自行設定不同的數值。在此例如設定為VH₁ _a<VH₂ _a<VH₃ _a<VH₄ _a，以及VH₁ _b<VH₂ _b <VH₃ _b<VH₄ _b，但是並非限定於此。In an embodiment, the second signal processing unit 155b includes a plurality of hysteresis units, respectively receiving the second comparison result Rb from the second comparison unit 152b, and generating a corresponding control signal according to the second comparison result Rb. , respectively controlling the switches Sn1 to Sn4. The switches Sn1 to Sn4 are respectively controlled by the first to fourth hysteresis units (G ₁ to G ₄ , not shown), but are not limited thereto. The mth lag unit (G _m , p=1~4) is set to output a control signal of the first logic state to the switch Spm when the second comparison result Ra is greater than a pth threshold VH _m _a (m= 1 to 4), the switch is turned on; when the first comparison result m Ra is less than a second threshold value VH _m _b, the output control signal of a second logic state to switch Spm state, the switch is closed, wherein the second threshold value VH _m _b is less than or equal to the first critical value VH _m _a. The values of the first threshold value VH _{m — a} and the second threshold value VH _{m —} b can be set differently according to the application of the driving circuit. Here, for example, VH ₁ _a<VH ₂ _a<VH ₃ _a<VH ₄ _a, and VH ₁ _b<VH ₂ _b <VH ₃ _b<VH ₄ _b are set, but are not limited thereto.

於部分實施例中，該第一訊號處理單元155a及該第二訊號處理單元155b可以為脈衝寬度調變(PWM)控制器、脈衝寬度/期間調變(PDM)控制器或脈衝頻率調變(PFM)控制器。In some embodiments, the first signal processing unit 155a and the second signal processing unit 155b may be a pulse width modulation (PWM) controller, a pulse width/period modulation (PDM) controller, or a pulse frequency modulation ( PFM) controller.

當上述訊號處理單元(155a或155b)使用前述PWM控制器時，是將前述比較結果(Ra或Rb)與三角波訊號進行比較而產生一脈寬調變訊號，再將該脈寬調變訊號輸入至一計數器以產生對應於脈寬之開關訊號作為該控制訊號(CSa或CSb)以控制開關(Sp1-Sp4或Sn1-Sn4)的導通組合狀態。When the signal processing unit (155a or 155b) uses the PWM controller, the comparison result (Ra or Rb) is compared with the triangular wave signal to generate a pulse width modulation signal, and then the pulse width modulation signal is input. A counter is generated to generate a switching signal corresponding to the pulse width as the control signal (CSa or CSb) to control the conduction combined state of the switches (Sp1-Sp4 or Sn1-Sn4).

當上述訊號處理單元(155a或155b)使用前述PDM控制器時，是將前述比較結果(Ra或Rb)與三角波訊號進行比較而產生一脈衝寬度/期間調變調變訊號，再將該脈寬調變訊號輸入至一計數器以產生對應於脈衝期間之開關訊號作為該控制訊號(CSa或CSb)以控制開關(Sp1-Sp4或Sn1-Sn4)的導通組合狀態。When the signal processing unit (155a or 155b) uses the PDM controller, the comparison result (Ra or Rb) is compared with the triangular wave signal to generate a pulse width/period modulation signal, and then the pulse width is adjusted. The change signal is input to a counter to generate a switching signal corresponding to the pulse period as the control signal (CSa or CSb) to control the conduction combined state of the switch (Sp1-Sp4 or Sn1-Sn4).

當上述訊號處理單元(155a或155b)使用前述PFM控制器時，是將前述比較結果(Ra或Rb)與一參考訊號進行比較，而產生PFM訊號。之後將該PFM訊號進行溫度計碼(Thermal-meter code)、格雷碼(Gray code)、二元碼(Binary code)等之編碼，而作為該控制訊號(CSa或CSb)以控制開關(Sp1-Sp4或Sn1-Sn4)的導通組合狀態。When the signal processing unit (155a or 155b) uses the PFM controller, the comparison result (Ra or Rb) is compared with a reference signal to generate a PFM signal. Then, the PFM signal is encoded by a Thermo-meter code, a Gray code, a Binary code, etc., and is used as the control signal (CSa or CSb) to control the switch (Sp1-Sp4). Or the combined state of Sn1-Sn4).

該驅動電路100更包括第二可變電源裝置170b，耦接於第二訊號處理單元155b。該第二訊號處理單元155b、該第二可變電源裝置170b的結構特徵與該第一訊號處理單 元155a、該第一可變電源裝置170a類似，差異之處在於第一可變電源裝置170a中之電流源或電壓源Ip1至Ip4所產生的電流為第一方向，其中該第二可變電源裝置170b例如可為一多階脈衝產生器。因此，第一可變電源裝置170a所輸出的脈衝訊號Ip為第一方向的電流；第二可變電源裝置170b中之電流源或電壓源In1至In4所產生的電流為第二方向，因此，第二可變電源裝置170b輸出的脈衝訊號In為第二方向的電流。在此實施例中，In1至In4係使用電流源，但是並非限定於此。脈衝訊號In進而輸出至線性電源裝置120的第二電源端，作為驅動線性電源裝置120的電源之一。The driving circuit 100 further includes a second variable power supply device 170b coupled to the second signal processing unit 155b. The second signal processing unit 155b, the second variable power supply device 170b, and the first signal processing unit The first variable power supply device 170a is similar to the first variable power supply device 170a, and the difference is that the current generated by the current source or voltage sources Ip1 to Ip4 in the first variable power supply device 170a is the first direction, wherein the second variable power supply Device 170b can be, for example, a multi-stage pulse generator. Therefore, the pulse signal Ip outputted by the first variable power supply device 170a is the current in the first direction; the current generated by the current source or the voltage sources In1 to In4 in the second variable power supply device 170b is the second direction, therefore, The pulse signal In output by the second variable power supply device 170b is a current in the second direction. In this embodiment, In1 to In4 use a current source, but are not limited thereto. The pulse signal In is in turn outputted to the second power supply terminal of the linear power supply device 120 as one of the power sources for driving the linear power supply device 120.

在此實施例中，以該訊號源110之該輸出訊號Vin為弦波為例，該轉導放大器(線性電源裝置120)輸出弦波電流Ia，而該脈衝訊號Ip是對應於該弦波電流之一半周期(例如正半周)而輸出之脈衝訊號；而該脈衝訊號In是對應於該弦波電流之另一半周期(例如負半周)而輸出之脈衝訊號。In this embodiment, taking the output signal Vin of the signal source 110 as a sine wave, the transduction amplifier (linear power supply device 120) outputs a sine wave current Ia, and the pulse signal Ip corresponds to the sine wave current. The pulse signal outputted in one half cycle (for example, positive half cycle); and the pulse signal In is a pulse signal output corresponding to the other half cycle (for example, negative half cycle) of the sine wave current.

脈衝訊號Ip及In共同提供驅動線性電源裝置120的電源，使線性電源裝置120(轉導放大器)能夠將該訊號Vin放大輸出而產生該第一脈衝訊號Ia。該第一脈衝訊號Ia經由輸出節點n_out ，作為一驅動訊號Id，輸出至電容性負載180。本發明之一實施例之特徵在於比較該回饋電壓訊號V_FB 以及該前饋電壓訊號V_FF 並根據比較結果修正該驅動訊號Id。一般而言，線性電源裝置的功率消耗大於多階脈衝產生器；因此，當線性電源裝置輸出的功率過大時，可透過第一及/或第二訊號處理單元155a、155b分別控制該第一 及/或第二可變電源裝置170a、170b動態地提供所需電源，以將該驅動訊號Id輸出至電容性負載180，相較於提供固定電源給該線性電源裝置的方式，更可降低驅動電路的整體功率消耗。The pulse signals Ip and In provide a power supply for driving the linear power supply device 120, so that the linear power supply device 120 (transduction amplifier) can amplify and output the signal Vin to generate the first pulse signal Ia. The first pulse signal Ia is output to the capacitive load 180 via the output node n _out as a driving signal Id. An embodiment of the present invention is characterized in that the feedback voltage signal V _FB and the feedforward voltage signal V _FF are compared and the driving signal Id is corrected according to the comparison result. In general, the power consumption of the linear power supply device is greater than that of the multi-stage pulse generator; therefore, when the power output from the linear power supply device is excessive, the first and/or second signal processing units 155a, 155b can respectively control the first and / or the second variable power supply device 170a, 170b dynamically supplies the required power to output the drive signal Id to the capacitive load 180, and the drive circuit can be reduced compared to the manner in which the fixed power supply is provided to the linear power supply device Overall power consumption.

第3圖為本發明另一實施例中，用以驅動電容性負載之驅動電路200的結構方塊圖。該驅動電路200包括一訊號源210，產生一輸入訊號Vin。於本實施例中，該訊號源210例如為一波束形成單元，所產生的該輸入訊號Vin可以是具有任意振幅及頻率的交流電訊號或脈衝電訊號。FIG. 3 is a block diagram showing the structure of a driving circuit 200 for driving a capacitive load according to another embodiment of the present invention. The driving circuit 200 includes a signal source 210 for generating an input signal Vin. In this embodiment, the signal source 210 is, for example, a beam forming unit, and the input signal Vin generated may be an alternating current signal or a pulsed electrical signal having an arbitrary amplitude and frequency.

該驅動電路200更包括線性電源裝置220，耦接於訊號源210與一輸出節點n_out 之間。於本實施例中，線性電源裝置220為一轉導放大器(transconductance amplifier)，接收該輸入訊號Vin，根據該輸入訊號Vin形成電流形式的第一脈衝訊號Ia，並保持該驅動訊號之線性度。該第一脈衝訊號Ia經由該輸出節點n_out 輸出，以驅動一電容性負載280。The driving circuit 200 further includes a linear power supply device 220 coupled between the signal source 210 and an output node n _out . In this embodiment, the linear power supply device 220 is a transconductance amplifier that receives the input signal Vin, forms a first pulse signal Ia in the form of a current according to the input signal Vin, and maintains the linearity of the driving signal. The first pulse signal Ia is output through the output node n _out to drive a capacitive load 280.

該驅動電路200更包括第一及第二回饋單元240a、240b所構成。第一及第二回饋單元240a、240b例如可以是第一及第二電流取樣單元，分別耦接於該線性電源裝置220的第一及第二電源端，以分別擷取該線性電源裝置220的第一及第二電源端的供應電流，並分別根據該供應電流產生回饋電流訊號I_FB+ 與I_FB- 。該驅動電路200更包括前饋單元260，耦接於該訊號源210。前饋單元260可以是一轉導單元，擷取該輸入訊號Vin並將之轉換為一相對應的輸入電流訊號Iin。於本實施例中，為了利用前饋電流訊號Iin 對回饋電流訊號I_FB+ 以及I_FB- 分別進行相位補償，該第一及第二回饋單元240a、240b以及該前饋單元260更包括分別將該回饋電流訊號I_FB+ 與I_FB- 以及該前饋電流訊號Iin的振幅做適當的調整，使該等訊號可以於相同的基準下進行比較。於部分實施例中，該前饋單元260更可包括一低頻濾波器(low-pass filter)，用以降低該前饋電流訊號Iin的雜訊。The driving circuit 200 further includes first and second feedback units 240a and 240b. The first and second feedback units 240a and 240b are, for example, first and second current sampling units respectively coupled to the first and second power terminals of the linear power supply unit 220 to respectively capture the linear power supply unit 220. The first and second power terminals supply current, and respectively generate feedback current signals I _FB+ and I _FB- according to the supply current. The driving circuit 200 further includes a feedforward unit 260 coupled to the signal source 210. The feedforward unit 260 can be a transduction unit that captures the input signal Vin and converts it into a corresponding input current signal Iin. In this embodiment, in order to perform phase compensation on the feedback current signals I _FB+ and I _FB- respectively by using the feedforward current signal Iin, the first and second feedback units 240a, 240b and the feedforward unit 260 further include The amplitudes of the feedback current signals I _FB+ and I _FB- and the feedforward current signal Iin are appropriately adjusted so that the signals can be compared under the same reference. In some embodiments, the feedforward unit 260 may further include a low-pass filter for reducing noise of the feedforward current signal Iin.

該驅動電路200更包括一第一控制單元250a以及一第二控制單元250b，而第一控制單元250a更包括第一比較單元252a，第二控制單元250b更包括第二比較單元252b。該第一比較單元252a與該第一回饋單元240a以及該前饋單元260耦接；該第二比較單元252b與該第二回饋單元240b以及該前饋單元260耦接。於本實施例中，該第一控制單元250a例如為一減法器電路，接收回饋電流訊號I_FB+ 以及前饋電流訊號Iin，並根據回饋電流訊號I_FB+ 以及前饋電流訊號Iin的差值產生一第一比較結果Ra，即Ra=I_in -I_FB+ ；第二比較單元250b例如亦為一減法器電路，接收回饋電流訊號I_FB- 以及前饋電流訊號Iin，並根據該回饋電流訊號I_FB- 以及前饋電流訊號Iin的差值產生一第二比較結果Rb，即Rb=I_in -I_FB- 。The driving circuit 200 further includes a first control unit 250a and a second control unit 250b, and the first control unit 250a further includes a first comparing unit 252a, and the second control unit 250b further includes a second comparing unit 252b. The first comparison unit 252a is coupled to the first feedback unit 240a and the feedforward unit 260. The second comparison unit 252b is coupled to the second feedback unit 240b and the feedforward unit 260. In this embodiment, the first control unit 250a is, for example, a subtractor circuit, and receives the feedback current signal I _FB+ and the feedforward current signal Iin, and generates a difference according to the difference between the feedback current signal I _FB+ and the feedforward current signal Iin. The first comparison result Ra, that is, Ra=I _in -I _FB+ ; the second comparison unit 250b is also a subtractor circuit, for example, receiving the feedback current signal I _FB- and the feedforward current signal Iin, and according to the feedback current signal I _{FB -} and the difference of the feedforward current signal Iin produces a second comparison result Rb, ie Rb = I _{in -} I _{FB -} .

該第一控制單元250a更包括第一訊號處理單元255a，耦接於第一比較單元252a。該第一訊號處理單元255a接收來自該第一比較單元252a的該第一比較結果Ra，並根據該第一比較結果Ra產生一相對應的第一控制訊號CSa。The first control unit 250a further includes a first signal processing unit 255a coupled to the first comparison unit 252a. The first signal processing unit 255a receives the first comparison result Ra from the first comparison unit 252a, and generates a corresponding first control signal CSa according to the first comparison result Ra.

該驅動電路200更包括第一可變電源裝置270a，耦接於該第一訊號處理單元255a。於第3圖之實施例中，第一 可變電源裝置270a可以是一多階脈衝產生器，包括複數個開關Sp1至Sp4，分別耦接於複數個電流源或電壓源Ip1至Ip4之間，其中電流源或電壓源Ip1至Ip4所產生的電流為第一方向。其中第一可變電源裝置270a根據第一控制訊號CSa，控制該等開關Sp1至Sp4之導通-關閉組態，而產生一對應的具有第一方向的脈衝訊號Ip，脈衝訊號Ip進而輸出至該線性電源裝置220的第一電源端，作為驅動該線性電源裝置220的電源之一。The driving circuit 200 further includes a first variable power supply unit 270a coupled to the first signal processing unit 255a. In the embodiment of Figure 3, the first The variable power supply device 270a may be a multi-stage pulse generator, including a plurality of switches Sp1 to Sp4, respectively coupled between a plurality of current sources or voltage sources Ip1 to Ip4, wherein the current source or voltage sources Ip1 to Ip4 are generated. The current is in the first direction. The first variable power supply device 270a controls the on-off configuration of the switches Sp1 to Sp4 according to the first control signal CSa, and generates a corresponding pulse signal Ip having a first direction, and the pulse signal Ip is further outputted to the switch signal Ip. The first power terminal of the linear power supply unit 220 serves as one of the power sources for driving the linear power supply unit 220.

該第二控制單元250b則更包括第二訊號處理單元255b，耦接於第二比較單元252b。該第二訊號處理單元255b接收來自該第二比較單元252b的該第二比較結果Rb，並根據該第二比較結果Rb產生一相對應的第二控制訊號CSb。The second control unit 250b further includes a second signal processing unit 255b coupled to the second comparison unit 252b. The second signal processing unit 255b receives the second comparison result Rb from the second comparison unit 252b, and generates a corresponding second control signal CSb according to the second comparison result Rb.

於一實施例中，該第一及第二訊號處理單元255a、255b可分別包括複數個滯後(Hysteresis)單元，分別接收來自第一及第二比較單元252a、252b的第一及第二比較結果Ra、Rb，並分別根據該第一及第二比較結果Ra、Rb，分別產生相對應的控制訊號，分別控制開關Sp1~Sp4和Sn1~Sn4。在此，該第一及第二訊號處理單元255a、255b係採用與第2圖中該第一及第二訊號處理單元155a、155b相同的架構，故不再予以贅述。In an embodiment, the first and second signal processing units 255a, 255b may respectively include a plurality of hysteresis units respectively receiving first and second comparison results from the first and second comparing units 252a, 252b. Ra and Rb respectively generate corresponding control signals according to the first and second comparison results Ra and Rb, respectively controlling the switches Sp1 to Sp4 and Sn1 to Sn4. Here, the first and second signal processing units 255a, 255b adopt the same architecture as the first and second signal processing units 155a, 155b in FIG. 2, and therefore will not be described again.

此外，於部分實施例中，該第一及第二訊號處理單元255a、255b可為脈衝寬度調變(PWM)控制器、脈衝寬度/期間調變(PDM)控制器或脈衝頻率調變(PFM)控制器。In addition, in some embodiments, the first and second signal processing units 255a, 255b may be a pulse width modulation (PWM) controller, a pulse width/period modulation (PDM) controller, or a pulse frequency modulation (PFM). ) Controller.

該驅動電路200更包括第二可變電源裝置270b，耦接 於第二訊號處理單元255b。該第一訊號處理單元255a、該第一可變電源裝置270a、該第二訊號處理單元255b、及該第二可變電源裝置270b的結構特徵與第2圖之實施例實質上相同。該第二可變電源裝置270b輸出的脈衝訊號In為第二方向的電流。脈衝訊號In進而輸出至該線性電源裝置220的第二電源端，作為驅動線性電源裝置220的電源之一。The driving circuit 200 further includes a second variable power supply device 270b coupled The second signal processing unit 255b. The structural features of the first signal processing unit 255a, the first variable power supply unit 270a, the second signal processing unit 255b, and the second variable power supply unit 270b are substantially the same as those of the embodiment of FIG. The pulse signal In output by the second variable power supply device 270b is a current in the second direction. The pulse signal In is further outputted to the second power supply terminal of the linear power supply device 220 as one of the power sources for driving the linear power supply device 220.

該脈衝訊號Ip及In輸入至該線性電源裝置220，以驅動線性電源裝置220產生第一脈衝訊號Ia。該第一脈衝訊號Ia作為一驅動訊號Id，經由輸出節點n_out 輸出至電容性負載280。本發明一實施例之特徵在於比較該回饋電流訊號I_FB+ 、I_FB- 以及該前饋電流訊號Iin並根據結果修正驅動訊號Id。一般而言，線性電源裝置的功率消耗大於多階脈衝產生器；因此，當線性電源裝置輸出的功率過大時，可透過第一及/或第二訊號處理單元255a、255b分別控制第一及/或第二可變電源裝置270a、270b動態地提供所需電源，以將該驅動訊號Id輸出至電容性負載280，相較於提供固定電源給線性電源裝置的方式，更可降低驅動電路的整體功率消耗。The pulse signals Ip and In are input to the linear power supply device 220 to drive the linear power supply device 220 to generate the first pulse signal Ia. The first pulse signal Ia is output as a driving signal Id to the capacitive load 280 via the output node n _out . An embodiment of the invention is characterized in that the feedback current signals I _FB+ , I _FB− and the feedforward current signal Iin are compared and the driving signal Id is corrected according to the result. In general, the power consumption of the linear power supply device is greater than that of the multi-stage pulse generator; therefore, when the power output from the linear power supply device is excessive, the first and/or second signal processing units 255a, 255b can respectively control the first and/or Or the second variable power supply device 270a, 270b dynamically supplies the required power supply to output the driving signal Id to the capacitive load 280, which can reduce the overall driving circuit as compared with the manner of providing a fixed power supply to the linear power supply device. Power consumption.

根據模擬實驗的結果，傳統的二階脈衝驅動電路在振幅90V，頻率10MHz的設定下，傳統的二階脈衝驅動電路所輸出之驅動訊號的基頻波與三次諧波(third harmonic distortion)之間僅相差11dB；本發明實施例中的驅動電路在振幅90V，頻率10MHz的設定下，驅動電路所輸出訊號的基頻波與三次諧波之間相差51dB，顯著的降低了諧波所 造成的失真。而傳統的線性放大器驅動電路在振幅90V，頻率10MHz的設定下，交流功率的消耗為15W；本發明實施例中的驅動電路在振幅90V，頻率10MHz的設定下，交流功率的消耗為6.5W。因此，本發明一實施例所提供的驅動電路不但改善了傳統步階脈衝驅動電路的諧波失真，功耗更低於傳統的線性放大器驅動電路。According to the results of the simulation experiment, the conventional second-order pulse driving circuit has a difference between the fundamental frequency wave and the third harmonic distortion of the driving signal output by the conventional second-order pulse driving circuit at the amplitude of 90V and the frequency of 10MHz. 11dB; in the driving circuit of the embodiment of the present invention, when the amplitude is 90V and the frequency is 10MHz, the fundamental frequency wave and the third harmonic of the output signal of the driving circuit are 51dB apart, which significantly reduces the harmonics. The distortion caused. The conventional linear amplifier driving circuit has an AC power consumption of 15 W at an amplitude of 90 V and a frequency of 10 MHz. The driving circuit in the embodiment of the present invention has an AC power consumption of 6.5 W at an amplitude of 90 V and a frequency of 10 MHz. Therefore, the driving circuit provided by an embodiment of the invention not only improves the harmonic distortion of the conventional step pulse driving circuit, but also consumes less power than the conventional linear amplifier driving circuit.

請參照第4圖，本發明另揭露了一種脈衝激發裝置400，包括：一波束形成單元402，用以產生例如上述實施例中的輸入訊號Vin；一電容性負載404；以及，如上實施例所述之該驅動電路10、100或200，耦接該波束形成單元402。該驅動電路10、100或200接收該輸入訊號Vin，用以輸出驅動訊號至該電容性負載404；其中，該電容性負載404例如為壓電元件或超音波探頭。在此實例中，該脈衝激發裝置400例如是超音波換能器，該電容性負載404是超音探頭，但是並非限定於此。該驅動電路10、100或200已詳述如前在此不再予以贅述。Referring to FIG. 4, the present invention further discloses a pulse excitation device 400, including: a beam forming unit 402 for generating, for example, the input signal Vin in the above embodiment; a capacitive load 404; and, as in the above embodiment The driving circuit 10, 100 or 200 is coupled to the beam forming unit 402. The driving circuit 10, 100 or 200 receives the input signal Vin for outputting a driving signal to the capacitive load 404; wherein the capacitive load 404 is, for example, a piezoelectric element or an ultrasonic probe. In this example, the pulse excitation device 400 is, for example, an ultrasonic transducer, and the capacitive load 404 is a supersonic probe, but is not limited thereto. The drive circuit 10, 100 or 200 has been described in detail as it is not described herein.

以上描述揭露了本發明的概念。應可理解於相關領域具有一般知識技術之人可以根據上述內容做各種修改，而並未悖離本發明的精神與範疇。再者，所有的實例與敘述僅作為範例之用，讓閱讀之人可以更容易理解本發明，並未限制專利保護的範圍。所有在此描述之準則，情境，以及實施例，亦僅作為範例之用，等同於任何結構上或功能上相同的替代物，包括現有的或尚未被發明的。The above description discloses the concept of the invention. It should be understood that those having ordinary skill in the relevant art can make various modifications based on the above, without departing from the spirit and scope of the invention. Furthermore, all of the examples and descriptions are for illustrative purposes only, and the reader may have a better understanding of the invention and the scope of the patent protection is not limited. All of the guidelines, the context, and the examples described herein are also used as examples only, and are equivalent to any structurally or functionally equivalent alternatives, including existing or not yet invented.

上述內容僅為示範之用，實際的專利保護範圍請參考以下的專利請求項。The above content is for demonstration purposes only. For the actual patent protection scope, please refer to the following patent claims.

10‧‧‧驅動電路10‧‧‧Drive circuit

100‧‧‧驅動電路100‧‧‧ drive circuit

110‧‧‧訊號源110‧‧‧Signal source

120‧‧‧線性電源裝置120‧‧‧Linear power supply unit

140‧‧‧回饋單元140‧‧‧Return unit

150‧‧‧控制單元150‧‧‧Control unit

150a‧‧‧第一控制單元150a‧‧‧First Control Unit

150b‧‧‧第二控制單元150b‧‧‧second control unit

152a‧‧‧第一比較單元152a‧‧‧ first comparison unit

152b‧‧‧第二比較單元152b‧‧‧Second comparison unit

155a‧‧‧第一訊號處理單元155a‧‧‧First Signal Processing Unit

155b‧‧‧第二訊號處理單元155b‧‧‧second signal processing unit

160‧‧‧前饋單元160‧‧‧Feed-forward unit

170‧‧‧可變電源裝置170‧‧‧Variable power supply unit

170a‧‧‧第一可變電源裝置170a‧‧‧First variable power supply unit

170b‧‧‧第二可變電源裝置170b‧‧‧Second variable power supply unit

180‧‧‧電容性負載180‧‧‧capacitive load

200‧‧‧驅動電路200‧‧‧ drive circuit

210‧‧‧訊號源210‧‧‧Signal source

220‧‧‧線性電源裝置220‧‧‧Linear power supply unit

240a‧‧‧第一回饋單元240a‧‧‧First feedback unit

240b‧‧‧第二回饋單元240b‧‧‧second feedback unit

250a‧‧‧第一控制單元250a‧‧‧First Control Unit

250b‧‧‧第二控制單元250b‧‧‧second control unit

252a‧‧‧第一比較單元252a‧‧‧ first comparison unit

252b‧‧‧第二比較單元252b‧‧‧Second comparison unit

255a‧‧‧第一訊號處理單元255a‧‧‧First Signal Processing Unit

255b‧‧‧第二訊號處理單元255b‧‧‧second signal processing unit

260‧‧‧前饋單元260‧‧‧Feed-forward unit

270a‧‧‧第一可變電源裝置270a‧‧‧First variable power supply unit

270b‧‧‧第二可變電源裝置270b‧‧‧Second variable power supply unit

280‧‧‧電容性負載280‧‧‧capacitive load

400‧‧‧脈衝激發裝置400‧‧‧pulse excitation device

402‧‧‧波束形成單元402‧‧‧beamforming unit

404‧‧‧電容性負載404‧‧‧Capacitive load

CS‧‧‧控制訊號CS‧‧‧Control signal

CSa‧‧‧第一控制訊號CSa‧‧‧First control signal

CSb‧‧‧第二控制訊號CSb‧‧‧second control signal

Ia‧‧‧第一脈衝訊號Ia‧‧‧ first pulse signal

Id‧‧‧驅動訊號Id‧‧‧ drive signal

Iin‧‧‧前饋電流訊號Iin‧‧‧ Feedforward current signal

Ip、In‧‧‧脈衝訊號Ip, In‧‧‧ pulse signal

Ip1-Ip4‧‧‧電流(電壓)源Ip1-Ip4‧‧‧current (voltage) source

In1-In4‧‧‧電流(電壓)源In1-In4‧‧‧current (voltage) source

Is‧‧‧第二脈衝訊號Is‧‧‧second pulse signal

I_FB+ 、I_FB- ‧‧‧回饋電流訊號I _FB+ , I _FB- ‧‧‧ feedback current signal

n_out ‧‧‧輸出節點n _out ‧‧‧output node

Ra‧‧‧第一比較結果Ra‧‧‧ first comparison result

Rb‧‧‧第二比較結果Rb‧‧‧ second comparison result

S_FB ‧‧‧回饋訊號S _FB ‧‧‧ feedback signal

S_FF ‧‧‧前饋訊號S _FF ‧‧‧Feedback signal

Sn1-Sn4‧‧‧開關Sn1-Sn4‧‧‧ switch

Sp1-Sp4‧‧‧開關Sp1-Sp4‧‧‧ switch

Vin‧‧‧輸入訊號Vin‧‧‧ input signal

V_FB ‧‧‧回饋電壓訊號V _FB ‧‧‧ feedback voltage signal

V_FF ‧‧‧前饋電壓訊號V _FF ‧‧‧Feed-for voltage signal

本發明所揭露之說明書內容可搭配以下圖式閱讀以使更容易理解。須注意的是圖式之部分特徵並未根據業界的實際產品比例所規劃。事實上，這些特徵的長寬比例都可以任意增減，並不影響發明的本質。本發明中相同的特徵皆以相同的標號表示。The content of the description disclosed in the present invention can be read with the following drawings to make it easier to understand. It should be noted that some of the features of the schema are not planned according to the actual product ratio of the industry. In fact, the aspect ratio of these features can be arbitrarily increased or decreased without affecting the essence of the invention. The same features in the present invention are denoted by the same reference numerals.

第1圖為本發明一實施例中，驅動電路10的結構方塊圖。Fig. 1 is a block diagram showing the structure of a drive circuit 10 in accordance with an embodiment of the present invention.

第2圖為本發明一實施例中，驅動電路100的結構方塊圖。FIG. 2 is a block diagram showing the structure of a driving circuit 100 according to an embodiment of the present invention.

第3圖為本發明一實施例中，驅動電路200的結構方塊圖。FIG. 3 is a block diagram showing the structure of a driving circuit 200 according to an embodiment of the present invention.

第4圖為本發明一實施例中，使用本發明之驅動電路之脈衝激發裝置的結構方塊圖。Fig. 4 is a block diagram showing the structure of a pulse excitation device using a driving circuit of the present invention in an embodiment of the present invention.

10‧‧‧驅動電路10‧‧‧Drive circuit

110‧‧‧訊號源110‧‧‧Signal source

120‧‧‧線性電源裝置120‧‧‧Linear power supply unit

140‧‧‧回饋單元140‧‧‧Return unit

150‧‧‧控制單元150‧‧‧Control unit

160‧‧‧前饋單元160‧‧‧Feed-forward unit

170‧‧‧可變電源裝置170‧‧‧Variable power supply unit

180‧‧‧電容性負載180‧‧‧capacitive load

CS‧‧‧控制訊號CS‧‧‧Control signal

Ia‧‧‧第一脈衝訊號Ia‧‧‧ first pulse signal

Id‧‧‧驅動訊號Id‧‧‧ drive signal

Is‧‧‧第二脈衝訊號Is‧‧‧second pulse signal

S_FB ‧‧‧回饋訊號S _FB ‧‧‧ feedback signal

S_FF ‧‧‧前饋訊號S _FF ‧‧‧Feedback signal