TWI496421B - Analog to digital converter - Google Patents

類比/數位轉換器Analog/digital converter

本發明係有關一種信號處理系統，特別關於一種類比/數位轉換器。The present invention relates to a signal processing system, and more particularly to an analog/digital converter.

在資料擷取應用領域中，複數個類比信號可同時或並列地被擷取，並將其在一定的時間間隔中轉換成數位信號。In the field of data acquisition applications, a plurality of analog signals can be captured simultaneously or in parallel and converted into digital signals at certain time intervals.

在一種傳統架構中，每個輸入通道需要一個採樣(sample)/保持(hold)模組。來自輸入通道的所有類比信號將同時被進行採樣，然後進入保持狀態。在保持階段，類比/數位轉換器(ADC)可用來將採樣而得之類比信號依次轉換成數位信號，直到所有輸入通道的採樣信號轉換成為數位信號。這種架構存在許多缺點。例如，多個通道需要多個採樣/保持模組，而這些模組對高頻率雜訊較為敏感且不具有低通濾波能力。In a conventional architecture, one sample/hold module is required for each input channel. All analog signals from the input channel will be sampled simultaneously and then put into hold. In the hold phase, an analog/digital converter (ADC) can be used to sequentially convert the sampled analog signal into a digital signal until the sampled signals of all input channels are converted to digital signals. This architecture has many drawbacks. For example, multiple channels require multiple sample/hold modules that are sensitive to high frequency noise and do not have low pass filtering capabilities.

在另一種傳統架構中，每個輸入通道採用單獨的類比/數位轉換器。因此，具有多個輸入通道的資料擷取系統，需要多個類比/數位轉換器。平均型之類比/數位轉換器可用於這種架構來實現多個輸入通道的同步。然而，如果採用多個類比/數位轉換器，資料擷取系統的能量損耗、晶片面積和成本都會增加。另外，不同的類比/數位轉換器可導致多個輸入通道之間的不匹配。In another conventional architecture, a separate analog/digital converter is used for each input channel. Therefore, a data capture system with multiple input channels requires multiple analog/digital converters. An analog analog/digital converter can be used in this architecture to synchronize multiple input channels. However, if multiple analog/digital converters are used, the energy consumption, chip area and cost of the data acquisition system will increase. In addition, different analog/digital converters can result in mismatch between multiple input channels.

本發明要解決的技術問題在於提供一種將類比信號轉換為數位信號的類比/數位轉換器。The technical problem to be solved by the present invention is to provide an analog/digital converter that converts an analog signal into a digital signal.

為解決上述技術問題，本發明提供一種類比/數位轉換器，包含：一輸入通道，接收一類比信號；一第一採樣-積分單元，從該輸入通道接收該類比信號，對該類比信號進行採樣，對一第一回授信號和該類比信號的一第一採樣信號的一重疊部分進行積分，並產生一第一輸出信號；一第二採樣-積分單元，以接收該第一輸出信號、對該第一輸出信號進行採樣、及對一第二回授信號和該第一輸出信號的一採樣信號的一重疊部分進行積分，並產生一第二輸出信號，其中，該第一採樣-積分單元和該第二採樣-積分單元中的每個單元包含一第一能量存儲單元及與第一能量存儲單元耦接之一第一開關陣列以控制該第一能量存儲單元；以及一回授電路，與該第一採樣-積分單元及該第二採樣-積分單元耦接，根據該第二輸出信號產生一數位信號，並提供分別表示該數位信號的該第一回授信號和該第二回授信號至該第一採樣-積分單元和該第二採樣-積分單元。To solve the above technical problem, the present invention provides an analog/digital converter comprising: an input channel for receiving an analog signal; a first sample-integration unit for receiving the analog signal from the input channel, and performing the analog signal Sampling, integrating an overlap portion of a first feedback signal and a first sampling signal of the analog signal, and generating a first output signal; and a second sampling-integrating unit to receive the first output signal, Sampling the first output signal, integrating an overlap portion of a second feedback signal and a sample signal of the first output signal, and generating a second output signal, wherein the first sample-integration Each of the unit and the second sampling-integrating unit includes a first energy storage unit and a first switch array coupled to the first energy storage unit to control the first energy storage unit; and a feedback circuit And coupled to the first sampling-integrating unit and the second sampling-integrating unit, generating a digital signal according to the second output signal, and providing respectively to represent the digital signal The first feedback signal and the second feedback signal to the first sample-integration unit and the second sample-integration unit.

本發明的類比/數位轉換器相對于現有技術的類比/數位轉換器，具有更高的信噪比和更高的類比/數位轉換精度。The analog/digital converter of the present invention has a higher signal to noise ratio and a higher analog/digital conversion accuracy than prior art analog/digital converters.

以下結合附圖和具體實施例對本發明的技術方案進行詳細的說明，以使本發明的特性和優點更為明顯。The technical solutions of the present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments to make the features and advantages of the present invention more obvious.

以下將對本發明的實施例給出詳細的說明。雖然本發明將結合實施例進行闡述，但應理解這並非意指將本發明限定於這些實施例。相反地，本發明意在涵蓋由後附申請專利範圍所界定的本發明精神和範圍內所定義的各種變化、修改和均等物。此外，在以下對本發明的詳細描述中，闡明大量的具體細節以提供針對本發明的全面理解。然而，本技術領域中具有通常知識者應理解，沒有這些具體細節，本發明同樣可以實施。在其他實例中，對於習知方法、流程、元件和電路未作詳細描述，以便於凸顯本發明之主旨。A detailed description of the embodiments of the present invention will be given below. While the invention will be described in conjunction with the embodiments, it is understood that the invention is not limited to the embodiments. Rather, the invention is to cover various modifications, equivalents, and equivalents of the invention as defined by the scope of the appended claims. In addition, in the following detailed description of the embodiments of the invention However, it will be understood by those of ordinary skill in the art that the present invention may be practiced without these specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail in order to facilitate the invention.

多通道類比/數位轉換器(ADC)能夠將來自多個輸入通道的多個類比信號轉換為多個數位輸出信號，例如，在交錯模式(interleaved mode)下，多個類比輸入電壓轉換為多個數位輸出電壓。多通道類比/數位轉換器可以被應用在各種類比到數位轉換的資料處理應用中，例如，視訊系統，音訊系統或者信號感測器等。A multi-channel analog/digital converter (ADC) converts multiple analog signals from multiple input channels into multiple digital output signals, for example, multiple interleaved input voltages into multiple interleaved modes Digital output voltage. Multi-channel analog/digital converters can be used in a variety of analog to digital conversion data processing applications, such as video systems, audio systems or signal sensors.

圖1所示為本發明的一實施例的多通道類比/數位轉換器100的架構示意圖。在一實施例中，多通道類比/數位轉換器100可以是一階Δ-Σ類比/數位轉換器(delta-sigma ADC)。FIG. 1 is a block diagram showing the architecture of a multi-channel analog/digital converter 100 according to an embodiment of the present invention. In an embodiment, the multi-channel analog/digital converter 100 can be a first order delta-sigma analog-to-digital converter.

在一實施例中，多通道類比/數位轉換器100可以有多個輸入通道，例如，4個輸入通道包含通道1、通道2、通道3和通道4以將類比信號，例如，類比電壓信號V₁ 、V₂ 、V₃ 和V₄ 在交錯模式下分別轉換為數位信號。每個輸入通道與一個開關耦接，例如，開關S_1A 與通道1耦接；開關S_2A 與通道2耦接；開關S_3A 與通道3耦接；開關S_4A 與通道4耦接。在一實施例中，開關S_1A 、S_2A 、S_3A 和S_4A 能夠被系統時脈信號S_CLK 所控制。在一實施例中，根據系統時脈信號在一個時脈週期內一個輸入通道被選擇。在一實施例中，在一個時脈週期內，與選擇的輸入通道所耦接的開關將被導通，其他開關被斷開。In an embodiment, the multi-channel analog/digital converter 100 can have multiple input channels. For example, four input channels include channel 1, channel 2, channel 3, and channel 4 to classify signals, for example, analog voltage signals V. _1. V ₂ , V ₃ and V ₄ are respectively converted into digital signals in the interleaved mode. Each input channel is coupled to a switch, for example, switch S _1A is coupled to channel 1; switch S _2A is coupled to channel 2; switch S _3A is coupled to channel 3; and switch S _4A is coupled to channel 4. In an embodiment, switches S _1A , S _2A , S _{3A ,} and S _4A can be controlled by system clock signal S _CLK . In one embodiment, an input channel is selected during a clock cycle based on the system clock signal. In one embodiment, during one clock cycle, the switches coupled to the selected input channel will be turned "on" and the other switches will be turned "off".

多通道類比/數位轉換器100包含一個調變器110，以將類比信號，例如，電壓信號V₁ 、V₂ 、V₃ 或者V₄ 轉換為數位信號。調變器110可以從所選擇的輸入通道中接收類比信號，並提供相應的數位信號給與輸入通道耦接的濾波器，例如，數位濾波器F₁ 、數位濾波器F₂ 、數位濾波器F₃ 和數位濾波器F₄ 。類比信號可以是各種類型的信號，例如，電流或者電壓信號。The multi-channel analog/digital converter 100 includes a modulator 110 to convert an analog signal, such as a voltage signal V ₁ , V ₂ , V ₃ or V _{4 ,} into a digital signal. The modulator 110 can receive an analog signal from the selected input channel and provide a corresponding digital signal to the filter coupled to the input channel, for example, a digital filter F ₁ , a digital filter F ₂ , and a digital filter F ₃ and digital filter F ₄ . The analog signal can be various types of signals, such as current or voltage signals.

在調變器110中，類比信號被輸入到採樣-積分單元130，在採樣-積分單元130中，採樣電路可以在預設的採樣頻率下對所接收的類比信號進行採樣，例如，採樣頻率等於Fs*OSR，其中Fs是耐奎斯特頻率，OSR是對耐奎斯特頻率的過採樣率。例如，當FS為16赫茲，OSR為4096，採樣頻率是65536赫茲。類比信號可以在採樣頻率下被調變器110轉換為數位信號。在一實施例中，數位信號可以是包含由採樣頻率，例如，Fs*OSR確定比率的邏輯1和邏輯0組成的連續1位元資料串。In the modulator 110, the analog signal is input to the sample-integration unit 130. In the sample-integration unit 130, the sampling circuit can sample the received analog signal at a preset sampling frequency, for example, the sampling frequency is equal to Fs*OSR, where Fs is the Nyquist frequency and OSR is the oversampling rate for the Nyquist frequency. For example, when the FS is 16 Hz, the OSR is 4096, and the sampling frequency is 65536 Hz. The analog signal can be converted to a digital signal by the modulator 110 at the sampling frequency. In an embodiment, the digital signal may be a continuous 1-bit data string consisting of a logical one and a logical zero determined by a sampling frequency, for example, a Fs*OSR determined ratio.

在一實施例中，採樣電路包含一能量存儲單元，例如，一採樣電容120，與被選擇的輸入通道耦接以從被選擇的輸入通道儲存電荷；採樣電路更進一步包含具有開關122、開關124、開關126和開關128的一開關陣列，以控制能量存儲單元120。開關122和開關124被信號PH₂ 所控制。開關126和開關128被信號PH₁ 所控制。在一實施例中，信號PH₁ 和信號PH₂ 是非重疊的時脈信號。例如，當信號PH₂ 是高電位準時，信號PH₁ 是低電位準。其中開關122和開關124被導通，且開關126和開關128被斷開。當信號PH₁ 是高電位準，信號PH₂ 是低電位準，開關122和開關124被斷開，開關126和開關128被導通。In one embodiment, the sampling circuit includes an energy storage unit, for example, a sampling capacitor 120 coupled to the selected input channel to store charge from the selected input channel; the sampling circuit further includes a switch 122, the switch 124 A switch array of switches 126 and switches 128 controls the energy storage unit 120. Switch 122 and a switch 124 controlled by the signal PH _2. Switch 126 and switch 128 is controlled by a signal PH _1. In an embodiment, signal PH ₁ and signal PH ₂ are non-overlapping clock signals. For example, when signal PH ₂ is high potential, signal PH ₁ is low potential. Where switch 122 and switch 124 are turned "on" and switch 126 and switch 128 are turned "off". When the signal PH ₁ is a high potential level, signal PH ₂ is a low potential level, the switch 122 and the switch 124 is turned off, the switch 126 and the switch 128 are turned on.

採樣-積分單元130更進一步包含與採樣電路耦接的一積分電路以接收輸入類比信號的採樣信號和回授信號111，並對回授信號111和輸入類比信號的採樣信號的重疊部分進行積分。積分電路可以根據重疊部分的積分結果產生一個輸出信號170。在圖1所示的實施例中，積分電路包含一組積分電容(例如，積分電容C_i1 、C_i2 、C_i3 、C_i4 )以及誤差放大器102。The sampling-integrating unit 130 further includes an integrating circuit coupled to the sampling circuit to receive the sampling signal and the feedback signal 111 of the input analog signal, and integrate the overlapping portion of the sampling signal of the feedback signal 111 and the input analog signal. The integrating circuit can generate an output signal 170 based on the integration result of the overlapping portion. In the embodiment shown in FIG. 1, the integrating circuit includes a set of integrating capacitors (eg, integrating capacitors C _i1 , C _i2 , C _i3 , C _i4 ) and an error amplifier 102.

積分電容C_i1 、C_i2 、C_i3 、C_i4 係並聯耦接。積分電容C_i1 、C_i2 、C_i3 、C_i4 能分別從輸入通道中積累電荷。每個積分電容C_i1 、C_i2 、C_i3 、C_i4 可以與一個開關串聯，例如，積分電容C_i1 與開關S_1B 耦接，積分電容C_i2 與開關S_2B 耦接，積分電容C_i3 與開關S_3B 耦接，積分電容C_i4 與開關S_4B 耦接。The integrating capacitors C _i1 , C _i2 , C _i3 , and C _i4 are coupled in parallel. The integrating capacitors C _i1 , C _i2 , C _i3 , C _i4 can accumulate charge from the input channels, respectively. Each integrating capacitor C _i1 , C _i2 , C _i3 , C _i4 may be connected in series with a switch. For example, the integrating capacitor C _{i1 is} coupled to the switch S _1B , the integrating capacitor C _{i2 is} coupled to the switch S _2B , and the integrating capacitor C _{i3 is} coupled to The switch S _{3B is} coupled, and the integrating capacitor C _{i4 is} coupled to the switch S _4B .

在一實施例中，調變器110可以在轉換週期中相繼對每個輸入通道完成類比/數位轉換。在一實施例中，在轉換週期的開始時候，積分電容可以是隨機分配給輸入通道。例如，積分電容C_i1 可以存儲來自通道2的電荷，積分電容C_i2 可以存儲來自通道3的電荷，積分電容C_i3 可以存儲來自通道4的電荷，積分電容C_i4 可以存儲來自通道1的電荷等等。這種輸入通道和積分電容的柔性組成可以減少由於積分電容的不匹配導致的不同通道之間的不匹配。在一實施例中，採樣-積分單元130的輸出信號170代表相應的積分電容在之前的轉換週期內所存儲的電荷，和回授信號111與輸入類比信號的採樣信號的重疊部分進行積分的結果。In an embodiment, the modulator 110 may perform analog/digital conversion on each input channel in succession during the conversion cycle. In an embodiment, the integration capacitor may be randomly assigned to the input channel at the beginning of the conversion cycle. For example, the integrating capacitor C _i1 can store the charge from channel 2, the integrating capacitor C _i2 can store the charge from channel 3, the integrating capacitor C _i3 can store the charge from channel 4, and the integrating capacitor C _i4 can store the charge from channel 1 etc. Wait. This flexible arrangement of input channels and integrating capacitors reduces mismatch between different channels due to mismatch in integrating capacitance. In one embodiment, the output signal 170 of the sample-integral unit 130 represents the charge stored by the corresponding integrated capacitor during the previous conversion period, and the result of integrating the feedback signal 111 with the overlap of the sampled signal of the input analog signal. .

誤差放大器102可以透過反相輸入端接收輸入信號，透過非反向輸入端接收第一參考信號，並產生誤差信號，例如，輸入信號是輸入類比信號的採樣信號與回授信號111的重疊部分。在一實施例中，非反向輸入端接地，這樣第一參考信號的電壓位準基本等於零。The error amplifier 102 can receive the input signal through the inverting input terminal, receive the first reference signal through the non-inverting input terminal, and generate an error signal. For example, the input signal is an overlapping portion of the sampling signal of the input analog signal and the feedback signal 111. In an embodiment, the non-inverting input is grounded such that the voltage level of the first reference signal is substantially equal to zero.

調變器110更進一步包含一回授電路，以根據採樣-積分單元130的輸出信號170產生一個數位信號，並產生表示積分電路的數位信號的回授信號111。在圖1所示的實施例中，回授電路更進一步包含一比較器104、一多工器108和一數位/類比轉換器(DAC)106。也就是說，積分電路、比較器104、多工器108和數位/類比轉換器106一起組成了一個回授回路。回授回路包含由積分電路、比較器104和多工器108組成的一前饋順向(feed forward)路徑和包含數位/類比轉換器106組成的一逆饋(backward)路徑。The modulator 110 further includes a feedback circuit for generating a digital signal from the output signal 170 of the sampling-integrating unit 130 and generating a feedback signal 111 representative of the digital signal of the integrating circuit. In the embodiment shown in FIG. 1, the feedback circuit further includes a comparator 104, a multiplexer 108, and a digital/analog converter (DAC) 106. That is, the integrating circuit, comparator 104, multiplexer 108, and digital/analog converter 106 together form a feedback loop. The feedback loop includes a feed forward path consisting of an integrating circuit, a comparator 104 and a multiplexer 108 and a backward path comprising a digital/analog converter 106.

與採樣-積分單元130耦接的比較器104可以將採樣-積分單元130的輸出信號170與第二參考信號進行比較，並根據一比較結果產生一個比較輸出信號。比較器104可以由信號PH₂ 控制，並且當PH₂ 是高電位準的時候比較器104操作。在一實施例中，比較器104的非反向輸入端被接地。因此，第二參考信號電壓位準基本等於零。比較器104可以根據比較結果產生一位元數位信號，例如，邏輯1或者邏輯0。比較器的輸出信號，例如，1位元數位信號進一步被輸送到多工器108。The comparator 104 coupled to the sample-integral unit 130 may compare the output signal 170 of the sample-integral unit 130 with a second reference signal and generate a comparison output signal based on a comparison result. Comparator 104 can be controlled by signal PH ₂ and comparator 104 operates when PH ₂ is high. In an embodiment, the non-inverting input of comparator 104 is grounded. Therefore, the second reference signal voltage level is substantially equal to zero. Comparator 104 may generate a one-bit digital signal, such as a logical one or a logical zero, based on the comparison. The comparator output signal, for example, a 1-bit digital signal, is further passed to the multiplexer 108.

在一實施例中，多工器108可以是由系統時脈信號S_CLK 控制的柱形位移暫存器(barrel shift register)。多工器108能夠讓來自比較器104的數位信號，例如，1位元的數位信號到達相應的輸出通道，例如，根據系統時脈信號S_CLK ，數位濾波器與伴隨被選擇的輸入通道結合。輸出通道可以包含數位濾波器F₁ 、F₂ 、F₃ 和F₄ ，例如，從比較器104將數位信號，例如，1位元數位信號抽取成多位元數位輸出信號的降頻濾波器(decimation filter)。因此，可以從數位濾波器，例如，F₁ 、F₂ 、F₃ 和F₄ 中分別得到與多個輸入通道相關的多個數位輸出信號。In an embodiment, multiplexer 108 may be a column shift register controlled by system clock signal S _CLK . The multiplexer 108 is capable of causing a digital signal from the comparator 104, for example, a 1-bit digital signal, to arrive at a corresponding output channel, for example, in accordance with the system clock signal S _CLK , which is coupled to the input channel associated with the selection. The output channel may include digital filters F ₁ , F ₂ , F _{3 ,} and F ₄ , for example, a down-converting filter that extracts a digital signal, such as a 1-bit digital signal, into a multi-bit digital output signal from comparator 104 ( Decimation filter). Thus, a plurality of digital output signals associated with a plurality of input channels can be derived from digital filters, for example, F ₁ , F ₂ , F _{3 ,} and F ₄ , respectively.

另外，多工器108可以栓鎖住(latch)來自比較器104與每個輸入通道相關的1位元數位信號。因此，在電流轉換週期中，先前轉換週期中每個輸入通道產生的1位元數位信號被鎖定在多工器108中，直到新的1位元數位信號產生。當在電流轉換週期根據系統時脈信號S_CLK 選擇了一個輸入通道，多工器108可以將在先前的轉換週期中產生的被選擇的輸入通道的1位元數位信號傳送給數位/類比轉換器106。在一實施例中，在第一轉換週期，多工器108可以將1位元數位信號，例如，邏輯0傳送給數位/類比轉換器106。Additionally, multiplexer 108 can latch a 1-bit digital signal associated with each input channel from comparator 104. Therefore, in the current conversion period, the 1-bit digital signal generated by each input channel in the previous conversion period is locked in the multiplexer 108 until a new 1-bit digital signal is generated. When an input channel is selected according to the system clock signal S _CLK during the current conversion period, the multiplexer 108 can transmit the 1-bit digital signal of the selected input channel generated in the previous conversion cycle to the digital/analog converter. 106. In an embodiment, multiplexer 108 may transmit a 1-bit digital signal, such as logic 0, to digital/analog converter 106 during the first conversion cycle.

在一實施例中，數位/類比轉換器106可以是一位數位/類比轉換器。數位/類比轉換器106可以接收來自多工器108的1位元數位信號，並根據參考電壓V_REF 將1位元數位信號轉換為類比信號，例如，電壓信號。由數位/類比轉換器106產生的類比信號可以作為傳送給積分器150的回授信號111。在一實施例中，數位/類比轉換器106可以當1位元數位信號為邏輯1的時候將回授信號111設定為-V_REF ，當1位元數位信號為邏輯0的時候將回授信號111設定為V_REF 。數位/類比轉換器106可以被信號PH₁ 和信號PH₂ 控制。於是，回授信號111的值可以根據來自多工器108的1位元數位信號控制。In an embodiment, the digital/analog converter 106 can be a one-bit digital/analog converter. The digital/analog converter 106 can receive a 1-bit digital signal from the multiplexer 108 and convert the 1-bit digital signal to an analog signal, such as a voltage signal, based on the reference voltage V _REF . The analog signal generated by the digital/analog converter 106 can be used as the feedback signal 111 that is transmitted to the integrator 150. In an embodiment, the digital/analog converter 106 can set the feedback signal 111 to -V _REF when the 1-bit digital signal is logic 1, and the feedback signal when the 1-bit digital signal is logic 0. 111 is set to V _REF . The digital/analog converter 106 can be controlled by signal PH ₁ and signal PH ₂ . Thus, the value of the feedback signal 111 can be controlled based on a 1-bit digital signal from the multiplexer 108.

更進一步，當通道1根據電流轉換週期的每一個時脈週期的系統時脈信號S_CLK 被選擇時，調變器110可以從通道1中接收類比信號，例如，類比電壓信號V₁ 和來自數位/類比轉換器106的回授信號111，並產生1位元的數位信號。在一實施例中，來自數位/類比轉換器106的回授信號111根據通道1中先前轉換週期產生的1位元數位信號和參考電壓V_REF 而產生。比較器104可以給多工器108產生1位元數位信號。因此，多工器108中與通道1相關聯的先前的1位元數位信號被電流轉換週期中新的1位元數位信號所代替。多工器108可以將電流轉換週期中產生的1位元數位信號輸出給相應的數位濾波器F₁ 。下一個輸入通道，例如，通道2可以在系統時脈信號S_CLK 的下一個時脈週期被選擇，相應的1位元數位信號可以被相應的濾波器所接收。例如，通道1、通道2、通道3和通道4相繼被選擇，通道1、通道2、通道3和通道4的相應的1位元數位信號相繼被數位濾波器F₁ 、數字濾波器F₂ 、數字濾波器F₃ 和數位濾波器F₄ 所接收。數位濾波器，例如，數位濾波器F₁ 、數位濾波器F₂ 、數位濾波器F₃ 和數位濾波器F₄ 可以將相應輸入通道中的1位元數位信號進行累加，並產生多位元數字輸出信號。Further, when the channel 1 is selected according to the system clock signal S _CLK of each clock cycle of the current conversion period, the modulator 110 can receive an analog signal from the channel 1, for example, the analog voltage signal V ₁ and from the digital The analog converter 106 returns a signal 111 and generates a 1-bit digital signal. In one embodiment, the feedback signal 111 from the digital/analog converter 106 is generated based on the 1-bit digital signal generated by the previous conversion cycle in channel 1 and the reference voltage V _REF . Comparator 104 can generate a 1-bit digital signal to multiplexer 108. Thus, the previous 1-bit digital signal associated with channel 1 in multiplexer 108 is replaced by a new 1-bit digital signal in the current conversion period. The multiplexer 108 can output a 1-bit digital signal generated in the current conversion period to the corresponding digital filter F ₁ . The next input channel, for example, channel 2, can be selected in the next clock cycle of the system clock signal S _CLK , and the corresponding 1-bit digital signal can be received by the corresponding filter. For example, channel 1, channel 2, channel 3, and channel 4 are successively selected, and corresponding 1-bit digital signals of channel 1, channel 2, channel 3, and channel 4 are successively subjected to digital filter F ₁ , digital filter F ₂ , digital filters and digital filter F ₃ F ₄ received. A digital filter, for example, a digital filter F ₁ , a digital filter F ₂ , a digital filter F _{3 ,} and a digital filter F ₄ can accumulate 1-bit digital signals in respective input channels and generate multi-bit numbers output signal.

儘管圖1所示為多通道類比/數位轉換器100，但本發明並不局限於此。例如，調變器110也可以用於單通道類比/數位轉換器。Although the multi-channel analog/digital converter 100 is shown in FIG. 1, the present invention is not limited thereto. For example, modulator 110 can also be used with a single channel analog/digital converter.

多通道類比/數位轉換器100的操作將參考圖2A所示的波形圖200A進行舉例描述。圖2A顯示在一實施例中，系統時脈信號S_CLK 的波形、開關S_1A 、S_2A 、S_3A 、S_4A 、S_1B 、S_2B 、S_3B 和S_4B 的狀態、多通道類比/數位轉換器100操作過程中的信號PH₂ 和信號PH₁ 。圖2A只是為說明作用，本發明將不限於圖2A所示的操作。在圖2A所示的實施例中，當相應的狀態波形處於高電位準時開關導通，當相應的狀態波形處於低電位準時開關斷開。The operation of the multi-channel analog/digital converter 100 will be described by way of example with reference to the waveform diagram 200A shown in FIG. 2A. 2A shows the waveform of the system clock signal S _CLK , the states of the switches S _1A , S _2A , S _3A , S _4A , S _1B , S _2B , S _{3B ,} and S _4B , multi-channel analog / digital in one embodiment. Signal PH ₂ and signal PH ₁ during operation of converter 100. FIG. 2A is for illustrative purposes only, and the present invention is not limited to the operation shown in FIG. 2A. In the embodiment shown in FIG. 2A, the switch is turned on when the corresponding state waveform is at a high potential, and the switch is turned off when the corresponding state waveform is at a low potential.

在圖2A所示的實施例中，系統時脈信號S_CLK 的時脈週期被分成兩個階段，這兩個階段包含系統時脈信號S_CLK 是低電位準的S₁ 階段和系統時脈信號S_CLK 是高電位準的S₂ 階段。例如，每個時脈週期，例如，T₁ 、T₂ 、T₃ 、T₄ 和T₅ 等等，包含S₁ 階段和S₂ 階段。在每個時脈週期的階段S₁ ，信號PH₁ 被設定為高電位準，信號PH₂ 被設定為低電位準。類似的，在每個時脈週期的S₂ 階段，信號PH₁ 被設定為低電位準，信號PH₂ 被設定為高電位準。在一實施例中，因為信號PH₁ 和信號PH₂ 是非重疊的時脈信號。信號PH₁ 和信號PH₂ 的脈寬比系統時脈信號S_CLK 的脈寬小以避免重疊。In the embodiment shown in FIG. 2A, the clock period of the system clock signal S _CLK is divided into two phases, which include the S ₁ phase of the system clock signal S _CLK being low potential and the system clock signal. S _CLK is a high potential S ₂ stage. For example, each clock cycle, for example, T ₁ , T ₂ , T ₃ , T _{4 ,} and T _{5 ,} etc., includes the S ₁ phase and the S ₂ phase. At stage S _{1 of} each clock cycle, signal PH ₁ is set to a high potential and signal PH ₂ is set to a low potential. Similarly, at the S ₂ phase of each clock cycle, signal PH ₁ is set to a low potential and signal PH ₂ is set to a high potential. In an embodiment, because signal PH ₁ and signal PH ₂ are non-overlapping clock signals. The pulse widths of signal PH ₁ and signal PH ₂ are smaller than the pulse width of system clock signal S _CLK to avoid overlap.

在一實施例中，在時脈週期T₁ ，當多通道類比/數位轉換器100被啟動後，通道1將首先被選擇。與通道1相關的開關S_1A 和開關S_1B 將被導通。與其他輸入通道，例如，通道2、通道3和通道4相關的開關將被斷開。在一實施例中，開關S_1B 被延時半個時脈週期後導通，例如，開關S_1A 在時脈週期T₁ 導通，開關S_1B 在時脈週期T₁ 的S₂ 階段和時脈週期T₂ 的S₁ 階段導通。開關122和開關124根據信號PH₂ 的高電位準在時脈週期T₁ 的S₂ 階段導通。同時，開關126和開關128將根據信號PH₁ 的低電位準在時脈週期T₁ 的S₂ 階段而斷開。因此，來自通道1的類比信號，例如，類比電壓信號V₁ ，透過導通的開關S_1A 、開關124和開關122，可以被傳送到採樣電容120，並且被採樣。與類比電壓信號V₁ 所對應的來自通道1的電荷，可以被儲存在採樣電容120中。In one embodiment, in the clock cycle T _1, when the multi-channel analog / digital converter 100 is activated, the channel 1 will be selected first. Switch S _1A and switch S _1B associated with channel 1 will be turned on. Switches associated with other input channels, such as Channel 2, Channel 3, and Channel 4, will be disconnected. In one embodiment, the switch S _1B is turned on after a delay of half a clock period. For example, the switch S _1A is turned on during the clock period T ₁ , and the switch S _{1B is} in the S ₂ phase of the clock period T ₁ and the clock period T The S ₁ phase of ₂ is turned on. The switch 122 and the switch 124 are turned on in the S ₂ phase of the clock period T ₁ in accordance with the high potential of the signal PH ₂ . Meanwhile, switch 126 and switch 128 when the signal PH ₁ in accordance with the low potential in the quasi-phase pulse period T S _{2 1} is disconnected. Thus, the analog signal from channel 1, e.g., analog voltage signals V _1, through conductive switch S _1A, the switches 124 and 122, may be transferred to the sampling capacitor 120 and be sampled. The charge from channel 1 corresponding to the analog voltage signal V ₁ can be stored in the sampling capacitor 120.

在時脈週期T₂ 的S₁ 階段，開關122和開關124根據信號PH₂ 的低電位準被斷開，並且開關126和開關128根據信號PH₁ 的高電位準被導通。因此，存儲在採樣電容120中的電荷可以透過該導通的開關126、開關128和開關S_1B 被傳送到積分電容C_i1 。At stage S ₁ of the clock cycle T _2, the switch 122 and the switch 124 is turned off according to a low potential level signal PH _2, and the switch 126 and the switch 128 are turned on according to a high potential level signal PH _1. Therefore, the charge stored in the sampling capacitor 120 can be transferred to the integrating capacitor C _i1 through the turned-on switch 126, the switch 128, and the switch S _1B .

另外，數位/類比轉換器106根據先前轉換週期中通道1中的1位元數位信號產生回授信號111到積分電路。在時脈週期T₂ 的S₂ 階段，當信號PH₂ 是高電位準，比較器104將採樣-積分單元130的輸出信號170與第二參考信號進行比較，產生通道1的1位元數位信號，並將其鎖定在多工器108中。數位濾波器F₁ 接收1位元數位信號。In addition, the digital/analog converter 106 generates a feedback signal 111 to the integrating circuit based on the 1-bit digital signal in channel 1 in the previous conversion cycle. In the S ₂ phase of the clock cycle T ₂ , when the signal PH ₂ is high, the comparator 104 compares the output signal 170 of the sample-integral unit 130 with the second reference signal to generate a 1-bit digital signal of the channel 1. And lock it in the multiplexer 108. The digital filter F ₁ receives a 1-bit digital signal.

在時脈週期T₂ ，通道2被選擇。通道2的操作次序與通道1的操作次序類似。根據時脈週期T₂ 的S₂ 階段中信號PH₂ 的高電位準，開關S_2A 、開關122和開關124導通，開關126和開關128斷開。來自通道2的輸入類比信號，例如，類比電壓信號V₂ 被傳送到採樣電容120並被採樣。在時脈週期T₃ 的S₁ 階段，根據信號PH₁ 的高電位準，開關122和開關124斷開，開關126和開關128導通。因為在時脈週期T₂ 的S₁ 階段以後，開關S_1B 被斷開，在時脈週期T₂ 的S₂ 階段和時脈週期T₃ 的S₁ 階段時，開關S_2B 被導通，在時脈週期T₃ 的S₁ 階段時，存儲在採樣電容120中的電荷被傳輸到積分電容C_i2 。然後比較器104可以在時脈週期T₃ 的S₂ 階段操作，並給多工器108產生通道2的1位元數位信號。數位濾波器F₂ 接收1位元數位信號。At clock cycle T ₂ , channel 2 is selected. The order of operation of channel 2 is similar to the order of operation of channel 1. According to the high potential of the signal PH ₂ in the S ₂ phase of the clock cycle T ₂ , the switch S _2A , the switch 122 and the switch 124 are turned on, and the switch 126 and the switch 128 are turned off. Analog signal input from the channel 2, for example, analog voltage signal V ₂ is transferred to the sampling capacitor 120 and sampled. In the clock cycle T S ₁ Stage _3, the high potential level according to the signal PH _1, the switch 122 and the switch 124 open, switch 126 and switch 128 is turned on. Because after the clock cycle T stage S _{1 2,} the switch S _1B is turned off, the clock period T S ₂ in phase ₂ and the clock period T of stages ₁ S ₃ and the switch S _2B is turned, while when the clock cycle T stage ₁ S _3, the charge stored in the sampling capacitor 120 is transferred to the integrating capacitor C _i2. Then the comparator 104 can be in the clock cycle T S ₂ Stage ₃ operation, and produce one bit digital signal of channel 2 to the multiplexer 108. The digital filter F ₂ receives a 1-bit digital signal.

類似的，可以在時脈週期T₃ 選擇通道3，並在時脈週期T₄ 的S₂ 階段產生1位元數位信號，可以在時脈週期T₄ 選擇通道4，並在時脈週期T₅ 的S₂ 階段產生1位元數位信號。如果有更多的輸入通道可用，那麼可以在相繼的時脈週期中相繼選擇這些輸入通道。於是，來自這些輸入通道的類比信號可以相繼地和迴圈地被轉換為數位信號。例如，如果有4個輸入通道，那麼就會使用至少4個時脈週期T₁ 、時脈週期T₂ 、時脈週期T₃ 和時脈週期T₄ 以完成所有輸入通道的轉換的迴圈。數位濾波器，例如，數位濾波器F₁ 、數位濾波器F₂ 、數位濾波器F₃ 或數位濾波器F₄ 可以在每個轉換週期接收與輸入通道，例如，通道1、通道2、通道3或通道4相關的1位元數位信號。然後下一個轉換週期從時脈週期T₅ 開始。類似地，每個輸入通道相繼被選擇，每個類比信號相繼被採樣。於是，每個數位濾波器可以在多個轉換週期積累相關輸入通道的一位元數位信號，並抽取一位元數位信號以在一預設的速度下(例如，F_S )產生多位元數字輸出信號。Similarly, it is T ₃ select the channel 3, and to produce one bit digital signal at the phase at the clock cycle T ₄ S ₂ of the clock cycle and to be in the clock cycle T ₄ Select Channel 4, and in the clock cycle T ₅ The S ₂ phase produces a 1-bit digital signal. If more input channels are available, these input channels can be selected successively in successive clock cycles. Thus, analog signals from these input channels can be converted to digital signals sequentially and in a loop. For example, if there are 4 input channels, then at least 4 clock cycles T ₁ , clock cycle T ₂ , clock cycle T _{3 ,} and clock cycle T _{4 are used} to complete the transition of all input channels. Digital filter, e.g., a digital filter F _1, the digital filter F _2, the digital filter or digital filter F ₃ F ₄ can be received in each conversion cycle of the input channel, e.g., channel 1, channel 2, channel 3 Or channel 1 associated 1-bit digital signal. Then a next conversion cycle starts from the clock cycle T _5. Similarly, each input channel is successively selected, and each analog signal is sequentially sampled. Thus, each digital filter can accumulate a one-bit digital signal of the associated input channel over multiple conversion cycles and extract a one-bit digital signal to generate a multi-bit digital at a predetermined speed (eg, F _S ). output signal.

在一實施例中，假設一過採樣率為OSR，一轉換週期所需要的時間為N*OSR個時脈週期，其中N表示通道的總數。優點在於，在一實施例中，在一個轉換週期，來自輸入通道的類比信號可以被採樣並被分別相繼轉換為1位元數位信號。於是，多個輸入通道的多位元數字輸出信號可以以同步的方式在多個轉換週期內獲得。結果，在一實施例中，多通道數位/類比轉換器100可以提升效率並減小能量消耗。In one embodiment, assuming an oversampling rate of OSR, the time required for a conversion cycle is N*OSR clock cycles, where N represents the total number of channels. Advantageously, in one embodiment, the analog signal from the input channel can be sampled and successively converted to a 1-bit digital signal, respectively, during one conversion cycle. Thus, the multi-bit digital output signals of the plurality of input channels can be obtained in a plurality of conversion cycles in a synchronized manner. As a result, in one embodiment, the multi-channel digital/analog converter 100 can increase efficiency and reduce energy consumption.

圖2B本發明的另一實施例的多通道類比/數位轉換器100的信號的波形圖200B。例如，波形202表示來自相應輸入通道的輸入類比信號。波形204表示輸出自數位/類比轉換器106的回授信號111和從採樣電容120獲得的輸入類比信號的採樣信號的重疊。波形206表示積分電路的輸出信號170。波形208表示比較器104的輸出信號。波形210表示從相應的數位濾波器獲得的表示輸入類比信號的輸出信號，例如，多位元數字信號。波形212表示輸入類比信號的採樣率。2B is a waveform diagram 200B of signals of the multi-channel analog/digital converter 100 of another embodiment of the present invention. For example, waveform 202 represents an input analog signal from a corresponding input channel. Waveform 204 represents the overlap of the sampled signal output from the feedback signal 111 of the digital/analog converter 106 and the input analog signal obtained from the sampling capacitor 120. Waveform 206 represents the output signal 170 of the integrating circuit. Waveform 208 represents the output signal of comparator 104. Waveform 210 represents an output signal representative of the input analog signal obtained from the corresponding digital filter, for example, a multi-bit digital signal. Waveform 212 represents the sampling rate of the input analog signal.

另外，為了加速轉換，可以透過增加其他的開關陣列(例如，增加類似於開關122、124、126和128)以及增加其他採樣電容(例如，增加類似於採樣電容120)，並採用互補的控制時脈信號PH₁ 和PH₂ ，來實現雙重採樣技術(double sampling technique)。採用這種拓撲架構，數位/類比轉換器的轉換速度可以加倍，而不會增加靜態功耗。其他的採樣技術，例如，三重採樣技術(triple sampling technique)也可以被採用以實現數位/類比轉換器100更高的轉換速度。In addition, in order to speed up the conversion, other switching arrays can be added (eg, similar to switches 122, 124, 126, and 128) and other sampling capacitors can be added (eg, similar to sampling capacitor 120), and complementary control is employed. The pulse signals PH ₁ and PH _{2 are} used to implement a double sampling technique. With this topology, the conversion speed of a digital/analog converter can be doubled without increasing static power. Other sampling techniques, such as a triple sampling technique, can also be employed to achieve higher conversion speeds for the digital/analog converter 100.

圖3所示為本發明一實施例的數位/類比轉換器，例如，多通道數位/類比轉換器100操作的流程圖300。圖3將結合圖1進行描述。多通道數位/類比轉換器100選擇一個輸入通道在系統時脈信號S_CLK 的一個時脈週期來接收類比信號，輸入通道，例如，是通道1、通道2、通道3或者通道4。在步驟302，由一採樣-積分單元130的一輸入通道接收一類比信號。在步驟310，由採樣-積分單元130中的一採樣電路在開關陣列的控制下在同樣的時脈週期中對類比信號進行採樣。在步驟320，輸入類比信號的採樣信號在相關開關，例如，開關S_1B 、S_2B 、S_3B 或S_4B 的控制下，被傳送到其中的一個積分電容，例如，電容C_i1 、C_i2 、C_i3 或者C_i4 。採樣-積分單元130中的積分電路可以對輸入類比信號的採樣信號和回授信號111的重疊部分進行積分。積分電容可以在轉換週期的開始時刻隨機地分別分配給輸入通道。在步驟330，積分電路根據重疊部分的積分結果產生輸出信號170。3 is a flow diagram 300 of a digital/analog converter, such as multi-channel digital/analog converter 100, in accordance with an embodiment of the present invention. Figure 3 will be described in conjunction with Figure 1. The multi-channel digital/analog converter 100 selects an input channel to receive an analog signal at a clock cycle of the system clock signal S _CLK , for example, channel 1, channel 2, channel 3, or channel 4. At step 302, an analog signal is received by an input channel of a sample-integration unit 130. At step 310, the analog signal is sampled by the sampling circuit in the sampling-integration unit 130 under the control of the switch array in the same clock cycle. At step 320, the sampling signal of the input analog signal is transmitted to one of the integrating capacitors under the control of an associated switch, for example, switch S _1B , S _2B , S _3B or S _4B , for example, capacitors C _i1 , C _i2 , C _i3 or C _i4 . The integrating circuit in the sampling-integration unit 130 can integrate the overlapping portion of the sampling signal of the input analog signal and the feedback signal 111. The integrating capacitors can be randomly assigned to the input channels at the beginning of the conversion cycle. At step 330, the integration circuit produces an output signal 170 based on the integration result of the overlap portion.

在步驟340，比較器，例如，比較器104可以根據輸出信號170產生一個一位元數位信號。更具體的，比較器104將輸出信號170與一個參考信號進行比較以產生一個1位元數位信號，並將該1位元數位信號傳送給多工器，例如，多工器108。在步驟350，多工器108可以將1位元數位信號輸出給數位/類比轉換器106和相應的數位濾波器，例如，數位濾波器F₁ 、數位濾波器F₂ 、數字濾波器F₃ 、或者數字濾波器F₄ ，同時也產生表示1位元數位信號的回授信號111。在步驟360，相應的數位濾波器可以根據1位元數位信號產生多位元數字輸出信號。更具體地說，相應地數位濾波器可以將多個轉換週期中相應輸入通道中的1位元數位信號進行累積，然後產生多位元數字輸出信號。At step 340, a comparator, such as comparator 104, can generate a one-bit digital signal from output signal 170. More specifically, comparator 104 compares output signal 170 to a reference signal to produce a 1-bit digital signal and transmits the 1-bit digital signal to a multiplexer, such as multiplexer 108. At step 350, the multiplexer 108 can output a 1-bit digital signal to the digital/analog converter 106 and a corresponding digital filter, for example, a digital filter F ₁ , a digital filter F ₂ , a digital filter F ₃ , Alternatively, the digital filter F ₄ also produces a feedback signal 111 representing a 1-bit digital signal. At step 360, the corresponding digital filter can generate a multi-bit digital output signal based on the 1-bit digital signal. More specifically, the digital filter can respectively accumulate 1-bit digital signals in respective ones of the plurality of conversion periods, and then generate a multi-bit digital output signal.

圖4所示為本發明的一實施例的電子系統400的架構示意圖。在一實施例中，電子系統400採用上述的多通道類比/數位轉換器100。多通道類比/數位轉換器100有多個輸入通道，例如，通道1、通道2、通道3、......通道N，以從多個裝置，例如，裝置402、裝置404、裝置406、......裝置408接收類比信號，並將類比信號分別轉換為數位輸出信號，例如，輸出1、輸出2、輸出3、......輸出N。數位輸出信號可以被各種接收器接收，例如，接收器422、接收器424、接收器426、......接收器428。多個裝置可以是各種類型的產生類比信號的裝置。例如，多通道類比/數位轉換器100可以用來將表示電池電壓的類比電壓監測信號轉換為數位信號。電池管理系統可以接收數位信號並控制電池。FIG. 4 is a schematic block diagram of an electronic system 400 according to an embodiment of the present invention. In one embodiment, electronic system 400 employs multi-channel analog/digital converter 100 described above. The multi-channel analog/digital converter 100 has multiple input channels, for example, channel 1, channel 2, channel 3, ... channel N, from a plurality of devices, such as device 402, device 404, device 406 The device 408 receives the analog signal and converts the analog signal to a digital output signal, for example, output 1, output 2, output 3, ... output N. The digital output signals can be received by various receivers, such as receiver 422, receiver 424, receiver 426, ... receiver 428. Multiple devices may be various types of devices that generate analog signals. For example, multi-channel analog/digital converter 100 can be used to convert an analog voltage monitoring signal representative of a battery voltage into a digital signal. The battery management system can receive digital signals and control the battery.

因此，在一實施例中，用來將類比信號轉換為數位信號的數位/類比轉換器，例如，多通道類比/數位轉換器100，包含：多輸入通道，例如，通道1、通道2、通道3、通道4等，採樣-積分單元130，與採樣-積分單元130耦接的回授電路。當相應開關導通時多個輸入通道的其中一個被選擇。採樣-積分單元130包含對所選擇的輸入通道的類比信號進行採樣的採樣電路。採樣電路包含包含一個能量存儲單元120。採樣-積分單元130更進一步包含與採樣電路耦接的積分電路以接收輸入類比信號的採樣信號和回授電路的回授信號111，並對輸入類比信號的採樣信號和回授信號的重疊部分進行積分。積分電路包含多個並聯耦接的電容，例如，積分電容和一個誤差放大器。積分電容分別與多個開關進行耦接。當相應開關導通時，其中一個積分電容可以儲存來自能量儲存單元120的電荷。Thus, in one embodiment, a digital/analog converter for converting an analog signal to a digital signal, such as multi-channel analog/digital converter 100, includes: multiple input channels, eg, channel 1, channel 2, channel 3. Channel 4 and the like, sampling-integrating unit 130, and feedback circuit coupled to sampling-integrating unit 130. One of the plurality of input channels is selected when the corresponding switch is turned on. The sample-integration unit 130 includes a sampling circuit that samples an analog signal of the selected input channel. The sampling circuit includes an energy storage unit 120. The sampling-integrating unit 130 further includes an integrating circuit coupled to the sampling circuit to receive the sampling signal of the input analog signal and the feedback signal 111 of the feedback circuit, and perform overlapping portions of the sampling signal and the feedback signal of the input analog signal. integral. The integrating circuit includes a plurality of capacitors coupled in parallel, such as an integrating capacitor and an error amplifier. The integrating capacitors are respectively coupled to a plurality of switches. One of the integrating capacitors can store the charge from the energy storage unit 120 when the respective switches are turned on.

回授電路包含與採樣-積分單元130的積分電路耦接的比較器104，與比較器104耦接的多工器108，耦接在多工器108和採樣-積分單元130之間的數位/類比轉換器。比較器104可以將採樣-積分單元130的輸出信號170與參考信號進行比較，並根據比較結果產生比較輸出信號。多工器108可以根據比較輸出信號提供數位信號。多通道數位/類比轉換器110可以進一步包含輸出通道以提供多位元數字輸出信號。The feedback circuit includes a comparator 104 coupled to the integrating circuit of the sampling-integrating unit 130, a multiplexer 108 coupled to the comparator 104, and a digital number coupled between the multiplexer 108 and the sampling-integrating unit 130. Analog converter. The comparator 104 may compare the output signal 170 of the sample-integral unit 130 with a reference signal and generate a comparison output signal based on the comparison result. The multiplexer 108 can provide a digital signal based on the comparison output signal. The multi-channel digital/analog converter 110 can further include an output channel to provide a multi-bit digital output signal.

優點在於，多通道類比/數位轉換器100可以在交錯模式下執行類比到數位的轉變。在一實施例中，不需要多個採樣/保持模組或者多個類比/數位轉換器來將多個輸入通道的類比信號進行轉換。因此，可以減小電路系統的成本並提高電路系統的效率。另外，多個類比/數位轉換器之間的不匹配可以減少或者避免。An advantage is that the multi-channel analog/digital converter 100 can perform analog to digital conversions in an interlaced mode. In an embodiment, multiple sample/hold modules or multiple analog/digital converters are not required to convert analog signals of multiple input channels. Therefore, the cost of the circuit system can be reduced and the efficiency of the circuit system can be improved. In addition, mismatches between multiple analog/digital converters can be reduced or avoided.

圖5所示為本發明的一實施例的多通道類比/數位轉換器500的架構示意圖。多通道類比/數位轉換器500可以是多階Σ-Δ類比/數位轉換器，例如，2階Σ-Δ類比/數位轉換器。與圖1中有同樣圖號標記的元件具有類似功能。圖5將結合圖1進行描述。FIG. 5 is a block diagram showing the architecture of a multi-channel analog/digital converter 500 according to an embodiment of the present invention. The multi-channel analog/digital converter 500 can be a multi-order sigma-delta analog/digital converter, such as a 2nd order sigma-delta analog/digital converter. Elements having the same reference numerals as in Figure 1 have similar functions. Figure 5 will be described in conjunction with Figure 1.

如圖5所示，調變器510將來自相應輸入通道，例如，包含通道1、通道2、通道3和通道4的4個輸入通道的類比信號，例如，類比電壓信號V₁ 、類比電壓信號V₂ 、類比電壓信號V₃ 或者類比電壓信號V₄ 轉換為相應的數位信號。調變器510可以是多階Σ-Δ調變器，例如，2階Σ-Δ調變器。調變器510包含多個串聯耦接的採樣-積分單元，例如，串聯耦接的採樣-積分單元530和採樣-積分單元550。採樣-積分單元530和採樣-積分單元550與圖1中的採樣-積分單元130功能類似。採樣-積分單元530從所選擇的輸入通道，例如，通道1和相關的開關，例如，開關S_1A 接收類比信號。在採樣-積分單元530中，第一採樣積分電路可以在預設的採樣頻率下對所接收的類比信號進行採樣。在一實施例中，第一採樣電路包含能量存儲單元520(例如，採樣電容)以儲存來自所選擇的輸入通道的電荷，更進一步包含包含有開關522、開關524、開關526和開關528的開關陣列以控制能量儲存單元520。類似的，開關522和開關524被信號PH₂ 控制，開關526和528被信號PH₁ 控制。在一實施例中，信號PH₁ 和信號PH₂ 是非重疊的時脈信號。5, the modulator 510 from the corresponding input channel, e.g., comprising channel 1, channel 2, channel 4 channel analog input signal channels 3 and 4, for example, analog voltage signals V _1, analog voltage signal V ₂ , the analog voltage signal V ₃ or the analog voltage signal V _{4 are} converted into corresponding digital signals. The modulator 510 can be a multi-stage sigma-delta modulator, such as a 2nd order sigma-delta modulator. The modulator 510 includes a plurality of sample-integration units coupled in series, for example, a sample-integration unit 530 and a sample-integration unit 550 coupled in series. The sample-integration unit 530 and the sample-integration unit 550 function similarly to the sample-integration unit 130 in FIG. The sample-integration unit 530 receives an analog signal from the selected input channel, for example, channel 1 and associated switches, for example, switch S _1A . In the sample-integration unit 530, the first sample integration circuit can sample the received analog signal at a preset sampling frequency. In an embodiment, the first sampling circuit includes an energy storage unit 520 (eg, a sampling capacitor) to store charge from the selected input channel, and further includes a switch including switch 522, switch 524, switch 526, and switch 528. The array controls the energy storage unit 520. Similarly, switch 522 and switch 524 are controlled by signal PH ₂ and switches 526 and 528 are controlled by signal PH ₁ . In an embodiment, signal PH ₁ and signal PH ₂ are non-overlapping clock signals.

採樣-積分單元530更進一步包含與第一採樣電路耦接的第一積分電路以接收輸入類比信號的採樣信號和回授信號111。第一積分電路對輸入類比信號的採樣信號和回授信號111的重疊部分進行積分，並根據重疊部分的積分結果產生輸出信號570。第一積分電路包含一組積分電容，例如，積分電容C_i1 A、C_i2 A、C_i3 A、C_i4 A和誤差放大器502。The sample-integration unit 530 further includes a first integration circuit coupled to the first sampling circuit to receive the sampling signal and the feedback signal 111 of the input analog signal. The first integrating circuit integrates the overlapping portion of the sampling signal of the input analog signal and the feedback signal 111, and generates an output signal 570 based on the integration result of the overlapping portion. The first integrating circuit includes a set of integrating capacitors, for example, integrating capacitors C _i1 A, C _i2 A, C _i3 A, C _i4 A and error amplifier 502.

積分電容C_i1 A、C_i2 A、C_i3 A和C_i4 A並聯耦接。積分電容C_i1 A、C_i2 A、C_i3 A和C_i4 A可以分別從輸入通道積累電荷。每一個積分電容C_i1 A、積分電容C_i2 A、積分電容C_i3 A和積分電容C_i4 A可以與一個開關串聯，例如，積分電容C_i1 A與開關S_1B 耦接，積分電容C_i2 A與開關S_2B 耦接，積分電容C_i3 A與開關S_3B 耦接，積分電容C_i4 A與開關S_4B 耦接。The integrating capacitors C _i1 A, C _i2 A, C _i3 A and C _i4 A are coupled in parallel. The integrating capacitors C _i1 A, C _i2 A, C _i3 A, and C _i4 A can accumulate charge from the input channels, respectively. Each of the integrating capacitor C _i1 A, the integrating capacitor C _i2 A, the integrating capacitor C _i3 A and the integrating capacitor C _i4 A may be connected in series with a switch, for example, the integrating capacitor C _i1 A is coupled to the switch S _1B , and the integrating capacitor C _i2 A coupled with the switch S _2B, the integrating capacitor C _i3 A is coupled to the switch S _3B, and the integrating capacitor C _i4 A switch S _4B coupled.

在一個轉換週期中，積分電容可以在轉換週期的開始時候隨機分配給輸入通道。在一實施例中，採樣-積分單元530的輸出信號570表示在先前的轉換週期中儲存在相應積分電容中的電荷和輸入類比信號的採樣信號和回授信號111的重疊部分積分結果。In one conversion cycle, the integrating capacitor can be randomly assigned to the input channel at the beginning of the conversion cycle. In one embodiment, the output signal 570 of the sample-integral unit 530 represents the overlapped partial integration result of the charge stored in the respective integrating capacitor and the sampled signal of the input analog signal and the feedback signal 111 in the previous conversion cycle.

在一實施例中，誤差放大器502可以根據分別來自反相輸入端的和非反相輸入端的輸入信號和第一參考信號產生一個誤差信號。輸入信號是輸入類比信號的採樣信號和回授信號111的重疊部分。在一實施例中，反相輸入端接地，於是第一參考信號的電壓位準實質上等於0。In an embodiment, the error amplifier 502 can generate an error signal based on the input signal from the inverting input and the non-inverting input, respectively, and the first reference signal. The input signal is an overlapping portion of the sampled signal of the input analog signal and the feedback signal 111. In one embodiment, the inverting input is grounded such that the voltage level of the first reference signal is substantially equal to zero.

採樣-積分單元550從採樣積分單元530接收輸出信號570。採樣-積分單元550與採樣積分單元530有類似的架構和功能。因此，輸出信號570可以由採樣-積分單元550中的第二採樣電路用預設的採樣頻率進行採樣。第二採樣電路包含一能量儲存單元540(例如，採樣電容)，更進一步包含一個包含有開關542、開關544、開關546和開關548的開關陣列以控制能量儲存單元540。在一實施例中，開關542和開關544由信號PH₂ 控制，開關546和開關548由信號PH₁ 控制。在一實施例中，採樣-積分單元530與採樣積分單元550分別使用同樣的採樣頻率對輸入類比信號和輸出信號570進行採樣。Sample-integration unit 550 receives output signal 570 from sample integration unit 530. The sample-integration unit 550 has a similar architecture and function as the sample integration unit 530. Therefore, the output signal 570 can be sampled by the second sampling circuit in the sample-integration unit 550 with a predetermined sampling frequency. The second sampling circuit includes an energy storage unit 540 (eg, a sampling capacitor), and further includes an array of switches including a switch 542, a switch 544, a switch 546, and a switch 548 to control the energy storage unit 540. In one embodiment, the switch 542 and a switch 544 controlled by a signal PH _2, switch 546 and switch 548 is controlled by a signal PH _1. In one embodiment, the sample-integral unit 530 and the sample integration unit 550 sample the input analog signal and the output signal 570 using the same sampling frequency, respectively.

採樣-積分單元550更進一步包含與第二採樣電路耦接的第二積分電路，以接收輸出信號570的採樣信號和回授信號例如，回授信號111。第二積分電路對輸出信號570的採樣信號和回授信號111的重疊部分進行積分，並根據對重疊部分進行積分的結果產生輸出信號572。The sample-integration unit 550 further includes a second integration circuit coupled to the second sampling circuit to receive the sampled signal and the feedback signal of the output signal 570, for example, the feedback signal 111. The second integrating circuit integrates the overlapping portion of the sampling signal of the output signal 570 and the feedback signal 111, and produces an output signal 572 based on the result of integrating the overlapping portion.

第二積分電路包含一組積分電容，例如，積分電容C_i1B 、積分電容C_i2B 、積分電容C_i3B 和積分電容C_i4B ，以及誤差放大器512。積分電容C_i1B 、積分電容C_i2B 、積分電容C_i3B 和積分電容C_i4B 並聯耦接。積分電容C_i1B 、積分電容C_i2B 、積分電容C_i3B 和積分電容C_i4B 可以累積分別與通道1、通道2、通道3和通道4相關的輸出信號570的電荷。每個積分電容C_i1B 、積分電容C_i2B 、積分電容C_i3B 和積分電容C_i4B 與一個開關串聯。例如，積分電容C_i1B 與開關S_1C 耦接；積分電容C_i2B 與開關S_2C 耦接；積分電容C_i3B 與開關S_3C 耦接；積分電容C_i4B 與開關S_4C 耦接。The second integrating circuit includes a set of integrating capacitors, for example, an integrating capacitor C _i1B , an integrating capacitor C _i2B , an integrating capacitor C _{i3B ,} and an integrating capacitor C _i4B , and an error amplifier 512 . The integrating capacitor C _i1B , the integrating capacitor C _i2B , the integrating capacitor C _i3B and the integrating capacitor C _i4B are coupled in parallel. The integrating capacitor C _i1B , the integrating capacitor C _i2B , the integrating capacitor C _{i3B ,} and the integrating capacitor C _i4B can accumulate the charge of the output signal 570 associated with channel 1, channel 2, channel 3, and channel 4, respectively. Each of the integrating capacitor C _i1B , the integrating capacitor C _i2B , the integrating capacitor C _{i3B ,} and the integrating capacitor C _{i4B are} connected in series with one switch. For example, the integrating capacitor C _{i1B is} coupled to the switch S _1C ; the integrating capacitor C _{i2B is} coupled to the switch S _2C ; the integrating capacitor C _{i3B is} coupled to the switch S _3C ; and the integrating capacitor C _{i4B is} coupled to the switch S _4C .

如上述的描述，積分電容C_i1A 、積分電容C_i2A 、積分電容C_i3A 和積分電容C_i4A 可以在轉換週期的開始時候隨機分配給輸入通道；與之類似，積分電容C_i1B 、積分電容C_i2B 、積分電容C_i3B 和積分電容C_i4B 也可以在轉換週期的開始時候隨機分配給輸入通道。在一實施例中，分配給相應通道的積分電容C_inA 和C_ikB ，例如，n=1、2、3或4;k=1、2、3或4，被同時導通或者斷開。例如，如果積分電容C_i1A 和C_i3B 被分配給通道1，當通道1被選擇時，積分電容C_i1A 和C_i3B 都被導通。As described above, the integrating capacitor C _i1A , the integrating capacitor C _i2A , the integrating capacitor C _{i3A ,} and the integrating capacitor C _i4A can be randomly assigned to the input channel at the beginning of the conversion period; similarly, the integrating capacitor C _i1B and the integrating capacitor C _i2B The integrating capacitor C _i3B and the integrating capacitor C _i4B can also be randomly assigned to the input channel at the beginning of the conversion period. In an embodiment, the integrating capacitances C _inA and C _ikB assigned to the respective channels, for example, n = 1, 2, 3 or 4; k = 1, 2, 3 or 4, are simultaneously turned on or off. For example, if integrating capacitors C _i1A and C _i3B are assigned to channel 1, when channel 1 is selected, integrating capacitors C _i1A and C _i3B are both turned on.

類似的，誤差放大器512可以根據分別來自反相輸入端和非反相輸入端的輸入信號和第二參考信號之間的差值生產誤差信號。輸入信號可以是輸出信號570的採樣信號和回授信號111的重疊部分。在一實施例中，非反相輸入端接地，於是第二參考信號的電壓位準實質上等於0。Similarly, error amplifier 512 can produce an error signal based on the difference between the input signal from the inverting input and the non-inverting input, respectively, and the second reference signal. The input signal may be an overlapping portion of the sampled signal of the output signal 570 and the feedback signal 111. In one embodiment, the non-inverting input is grounded such that the voltage level of the second reference signal is substantially equal to zero.

此外，回授電路包含比較器104、多工器108和數位/類比轉換器(簡稱DAC)。回授電路可以根據採樣-積分單元550的輸出信號572產生數位信號，並產生表示採樣-積分單元530和採樣-積分單元550數位信號的回授信號111。與採樣-積分單元550耦接的比較器104將採樣-積分單元550的輸出信號572與第三參考信號進行比較，並根據比較結果產生比較器輸出信號。在一實施例中，比較器104可以被信號PH₂ 控制，並且當PH₂ 是高電位準時操作。在一實施例中，比較器104的非反相輸入端接地，於是第三參考信號的電壓位準實質上等於0。比較器104可以根據比較結果產生一位元數位信號，例如，邏輯1或者邏輯0。比較器104之輸出信號，例如，1位元數位信號被輸送到多工器108。In addition, the feedback circuit includes a comparator 104, a multiplexer 108, and a digital/analog converter (DAC). The feedback circuit can generate a digital signal from the output signal 572 of the sample-integration unit 550 and generate a feedback signal 111 representative of the digital signal of the sample-integration unit 530 and the sample-integration unit 550. The comparator 104 coupled to the sample-integration unit 550 compares the output signal 572 of the sample-integration unit 550 with a third reference signal and generates a comparator output signal based on the comparison. In one embodiment, comparator 104 may be the _second control signal PH, and PH ₂ is a time when the operation of the high potential. In one embodiment, the non-inverting input of comparator 104 is grounded such that the voltage level of the third reference signal is substantially equal to zero. Comparator 104 may generate a one-bit digital signal, such as a logical one or a logical zero, based on the comparison. The output signal of comparator 104, for example, a 1-bit digital signal, is delivered to multiplexer 108.

多工器108將來自比較器104的數位信號傳遞到與根據系統時脈信號S_CLK 選擇的輸入通道相關的數位濾波器F₁ 、數位濾波器F₂ 、數位濾波器F₃ 和數位濾波器F₄ 的其中一個。於是，與多個輸入通道相關的多個數位輸出信號可以分別從數位濾波器F₁ 、數位濾波器F₂ 、數位濾波器F₃ 和數位濾波器F₄ 獲得。The multiplexer 108 passes the digital signal from the comparator 104 to the digital filter F ₁ , the digital filter F ₂ , the digital filter F _{3 ,} and the digital filter F associated with the input channel selected according to the system clock signal S _CLK . _{One of the four} . Thus, a plurality of digital output signals associated with the plurality of input channels can be obtained from the digital filter F ₁ , the digital filter F ₂ , the digital filter F _{3 ,} and the digital filter F _{4 , respectively} .

在一個新的轉換週期，當根據系統時脈信號S_CLK 選定一個輸入通道時，多工器108將該輸入通道的先前轉換週期產生的1位元數位信號傳送給數位/類比轉換器106。數位/類比轉換器106將1位元數位信號轉換為類比信號，該類比信號可以作為回授信號111被傳送到採樣-積分單元530和採樣-積分單元550。In a new conversion cycle, when an input channel is selected based on the system clock signal S _CLK , the multiplexer 108 transmits a 1-bit digital signal generated by the previous conversion cycle of the input channel to the digital/analog converter 106. The digital/analog converter 106 converts the 1-bit digital signal into an analog signal, which can be transmitted as a feedback signal 111 to the sample-integral unit 530 and the sample-integral unit 550.

對不同階數的類比/數位轉換器，例如，1階類比/數位轉換器100和2階類比/數位轉換器500，類比/數位轉換器信噪比(signal-to-noise ratio，簡稱SNR)的最大值會隨著過採樣率和預設的類比/數位轉換器的階數而改變。預設的階數為L的類比/數位轉換器的SNR由公式(1)確定：Analog/digital converters of different orders, for example, 1st order analog/digital converter 100 and 2nd order analog/digital converter 500, analog-to-noise ratio (SNR) The maximum value will vary with the oversampling rate and the order of the preset analog/digital converter. The SNR of the analog/digital converter with a preset order of L is determined by equation (1):

其中OSR表示類比/數位轉換器的過採樣率，N表示數位化的解析度。圖6表示在不同的類比/數位轉換器階次下相對於過採樣率OSR的SNR曲線圖600。對於固定階次的類比/數位轉換器，例如，階次為0、1、2、3、4或者5，SNR隨著OSR的增加而增加。對於同樣的OSR，例如，OSR=64，類比/數位轉換器的階次越高，在輸入信號的類比/數位轉換過程中更多的噪音將被抑制。因此，對於更高階的類比/數位轉換器，輸入信號的頻寬將會增加，時脈頻率也會增加，輸出信號的精度將被加強。Where OSR represents the oversampling rate of the analog/digital converter and N represents the resolution of the digitization. Figure 6 shows an SNR plot 600 versus oversampling rate OSR at different analog/digital converter orders. For a fixed order analog/digital converter, for example, the order is 0, 1, 2, 3, 4 or 5, the SNR increases as the OSR increases. For the same OSR, for example, OSR = 64, the higher the order of the analog/digital converter, the more noise will be suppressed during the analog/digital conversion of the input signal. Therefore, for higher order analog/digital converters, the bandwidth of the input signal will increase, the clock frequency will increase, and the accuracy of the output signal will be enhanced.

另外，在一實施例中，採樣-積分單元530的積分電路的輸出信號不是直接輸入給採樣-積分單元550的積分電路，而是被採樣-積分單元550的採樣電路進行採樣。當採樣-積分單元550的採樣電路將採樣信號傳送給信號PH₁ 控制的採樣-積分單元550的積分電路時，採樣-積分單元550的採樣電路將會與信號PH₂ 控制下的採樣-積分單元550的積分電路脫離關係。於是，在不同採樣-積分單元中的積分電路獨立操作，增強了系統的穩定性。Further, in an embodiment, the output signal of the integrating circuit of the sampling-integrating unit 530 is not directly input to the integrating circuit of the sampling-integrating unit 550, but is sampled by the sampling circuit of the sampling-integrating unit 550. When the sampling circuit of the sampling-integrating unit 550 transmits the sampling signal to the integrating circuit of the sampling-integrating unit 550 controlled by the signal PH ₁ , the sampling circuit of the sampling-integrating unit 550 and the sampling-integrating unit under the control of the signal PH ₂ The 550's integration circuit is disconnected. Thus, the integration circuits in the different sample-integration units operate independently, enhancing the stability of the system.

圖7所示為本發明一實施例多通道類比/數位轉換器700的架構示意圖。多通道類比/數位轉換器700可以是多階Σ-Δ類比/數位轉換器，例如，2階Σ-Δ類比/數位轉換器。與圖1和圖5有著同樣圖號標記的元件有著類似的功能。圖7將結合圖1和圖5進行描述。FIG. 7 is a block diagram showing the architecture of a multi-channel analog/digital converter 700 according to an embodiment of the present invention. The multi-channel analog/digital converter 700 can be a multi-order sigma-delta analog/digital converter, such as a 2nd order sigma-delta analog/digital converter. Elements having the same reference numerals as in Figures 1 and 5 have similar functions. Figure 7 will be described in conjunction with Figures 1 and 5.

如圖7所示，調節器710更進一步包含前饋順向電路730以採集接收自所選擇的輸入通道的輸入類比信號，並將輸入類比信號的採樣信號傳送給採樣-積分單元550的積分電路。前饋順向電路730包含能量儲存單元720(例如，採樣電容)以儲存來自所選輸入通道的電荷，前饋順向電路730更進一步包含具有開關722、開關724、開關726和開關728的開關陣列以控制能量儲存單元720。開關722和開關724由信號PH₂ 控制，開關726和開關728由信號PH₁ 控制。因此，開關722、開關724和開關726、開關728將會交替導通。As shown in FIG. 7, the regulator 710 further includes a feedforward forward circuit 730 for acquiring an input analog signal received from the selected input channel, and transmitting the sampling signal of the input analog signal to the integrating circuit of the sampling-integrating unit 550. . The feedforward forward circuit 730 includes an energy storage unit 720 (eg, a sampling capacitor) to store charge from a selected input channel, and the feedforward forward circuit 730 further includes a switch having a switch 722, a switch 724, a switch 726, and a switch 728. The array controls the energy storage unit 720. Switch 722 and a switch 724 controlled by a signal PH _2, the switch 726 and the switch 728 is controlled by a signal PH _1. Therefore, the switch 722, the switch 724, the switch 726, and the switch 728 will be alternately turned on.

在操作過程中，當輸入通道，例如，通道1被選擇，當開關722和724導通時，能量儲存單元720儲存來自通道1的類比信號的電荷；當開關726和728導通時，儲存在能量儲存單元720的電荷被傳送到採樣-積分單元550的積分電路。於是，採樣-積分單元550的積分電路可以對輸出信號570的採樣信號、輸入類比信號的採樣信號和回授信號的重疊部分進行積分以產生輸出信號572。During operation, when an input channel, for example, channel 1 is selected, when switches 722 and 724 are turned on, energy storage unit 720 stores the charge of the analog signal from channel 1; when switches 726 and 728 are turned on, stored in energy storage. The charge of unit 720 is passed to the integration circuit of sample-integration unit 550. Thus, the integrating circuit of the sample-integral unit 550 can integrate the overlapped portion of the sampled signal of the output signal 570, the sampled signal of the input analog signal, and the feedback signal to produce an output signal 572.

此外，調節器710包含數位/類比轉換器(digital to analog converter，簡稱DAC)706和數位/類比轉換器714以根據來自於多工器108的先前轉換週期的所選擇輸入通道的1位元數位信號產生回授信號711和回授信號713。回授信號711和回授信號713被分別提供給採樣-積分單元530的採樣電路和採樣-積分單元550的採樣電路。In addition, the regulator 710 includes a digital to analog converter (DAC) 706 and a digital/analog converter 714 to convert 1-bit digits of the selected input channel from the previous conversion period of the multiplexer 108. The signal generates a feedback signal 711 and a feedback signal 713. The feedback signal 711 and the feedback signal 713 are supplied to the sampling circuit of the sampling-integrating unit 530 and the sampling circuit of the sampling-integrating unit 550, respectively.

優點在於，透過將輸入類比信號的採樣信號透過前饋順向電路730提供給採樣-積分單元550的積分電路。採樣-積分單元550的輸出信號572的幅值被控制在一個特定範圍內。於是，多階類比/數位轉換器700的穩定性增加了。另外，數位/類比轉換器706和數位/類比轉換器714可以獨立地產生和提供回授信號711和回授信號713，也能幫助提高多階類比/數位轉換器700的穩定性。An advantage is that the sampling circuit of the input analog signal is supplied to the integrating circuit of the sampling-integrating unit 550 through the feedforward forward circuit 730. The amplitude of the output signal 572 of the sample-integration unit 550 is controlled within a specific range. Thus, the stability of the multi-stage analog/digital converter 700 is increased. In addition, the digital/analog converter 706 and the digital/analog converter 714 can independently generate and provide the feedback signal 711 and the feedback signal 713, and can also help improve the stability of the multi-stage analog/digital converter 700.

圖8所示為本發明一實施例多通道類比/數位轉換器，例如，多通道類比/數位轉換器500的流程圖800。圖8將結合圖5進行描述。多通道類比/數位轉換器500在系統時脈信號S_CLK 的一個時脈週期選擇一個輸入通道，例如，通道1、通道2、通道3或者通道4以接收類比信號。在步驟802，類比信號被輸入到採樣-積分單元，例如，採樣-積分單元530。在步驟804，類比信號在開關陣列的控制下在同樣的時脈週期被採樣-積分單元530的採樣電路所採樣。在步驟806，採樣-積分單元530的積分電路對輸入類比信號的採樣信號和回授信號的重疊部分進行積分。在步驟808，積分電路根據對重疊部分的積分結果生產輸出信號。FIG. 8 shows a flow diagram 800 of a multi-channel analog/digital converter, such as multi-channel analog/digital converter 500, in accordance with an embodiment of the present invention. Figure 8 will be described in conjunction with Figure 5. The multi-channel analog/digital converter 500 selects an input channel, for example, channel 1, channel 2, channel 3 or channel 4, to receive an analog signal during a clock cycle of the system clock signal S _CLK . At step 802, the analog signal is input to a sample-integration unit, such as sample-integration unit 530. At step 804, the analog signal is sampled by the sampling circuit of the sample-integration unit 530 during the same clock cycle under the control of the switch array. At step 806, the integration circuit of the sample-integration unit 530 integrates the overlapping portion of the sampled signal and the feedback signal of the input analog signal. At step 808, the integration circuit produces an output signal based on the integration result for the overlap portion.

在步驟810，如果電流採樣-積分單元是多通道類比/數位轉換器500的上一個採樣-積分單元，那麼執行步驟814，否則執行步驟812。在步驟812，電流採樣-積分單元的輸出信號可以被輸入到下一個採樣-積分單元，例如，採樣-積分單元550。然後返回到步驟804。At step 810, if the current sample-integration unit is the previous sample-integration unit of multi-channel analog/digital converter 500, then step 814 is performed, otherwise step 812 is performed. At step 812, the output signal of the current sample-integration unit can be input to the next sample-integration unit, such as sample-integration unit 550. Then it returns to step 804.

在步驟814，比較器，例如，比較器104，根據上一個採樣-積分單元的輸出信號，例如，採樣-積分單元550的輸出信號572，產生1位元數位信號。更具體地，比較器104將採樣-積分單元550的輸出信號572與一個參考信號進行比較並產生1位元數位信號，並將該1位元數位信號傳送到多工器，例如，多工器108。在步驟816，多工器108將1位元數位信號輸出到數位/類比轉換器106和相應的數位濾波器，例如，濾波器F₁ 、濾波器F₂ 、濾波器F₃ 或濾波器F₄ 。同時，表示1位元數位信號的回授信號111也被產生。在步驟818，相應的數位濾波器根據1位元數位信號產生多位元數字輸出信號。更具體地，相應的數位濾波器累積相應輸入通道的幾個轉換週期的1位元數位信號，並產生多位元數字輸出信號。At step 814, a comparator, such as comparator 104, generates a 1-bit digital signal based on the output signal of the previous sample-integration unit, for example, the output signal 572 of sample-integration unit 550. More specifically, the comparator 104 compares the output signal 572 of the sample-integration unit 550 with a reference signal and generates a 1-bit digital signal, and transmits the 1-bit digital signal to a multiplexer, for example, a multiplexer 108. In step 816, the multiplexer 108 1 yuan digital signal is output to the digital / analog converter 106 and the corresponding digital filter, e.g., filter F _1, the filter F _2, the filter or filters F ₃ F ₄ . At the same time, a feedback signal 111 representing a 1-bit digital signal is also generated. At step 818, the corresponding digital filter produces a multi-bit digital output signal based on the 1-bit digital signal. More specifically, the corresponding digital filter accumulates a 1-bit digital signal of several conversion periods of the corresponding input channel and produces a multi-bit digital output signal.

因此，根據本發明的實施例，多通道類比/數位轉換器透過相應的輸入通道將多個類比信號轉換為相應的數位信號。在一實施例中，多通道類比/數位轉換器包含多個並聯耦接的採樣-積分單元。依靠包含多個採樣-積分單元，類比/數位轉換器可以有更高的階次，類比/數位轉換器的信噪比被提升，類比/數位轉換器的精度被提高。Thus, in accordance with an embodiment of the present invention, a multi-channel analog/digital converter converts a plurality of analog signals into corresponding digital signals through respective input channels. In an embodiment, the multi-channel analog/digital converter comprises a plurality of sample-integration units coupled in parallel. By including multiple sample-integration units, the analog/digital converter can have a higher order, the signal-to-noise ratio of the analog/digital converter is improved, and the accuracy of the analog/digital converter is improved.

上文具體實施方式和附圖僅為本發明之常用實施例。顯然，在不脫離申請專利範圍所界定的本發明精神和發明範圍的前提下可以有各種增補、修改和替換。本領域技術人員應該理解，本發明在實際應用中可根據具體的環境和工作要求在不背離發明準則的前提下在形式、架構、佈局、比例、材料、元件、元件及其它方面有所變化。因此，在此披露之實施例僅說明而非限制，本發明之範圍由後附申請專利範圍及其合法等同物界定，而不限於此前之描述。The above detailed description and the accompanying drawings are only typical embodiments of the invention. It is apparent that various additions, modifications and substitutions are possible without departing from the spirit and scope of the invention as defined by the appended claims. It should be understood by those skilled in the art that the present invention may be modified in form, structure, arrangement, ratio, material, component, component, and other aspects in accordance with the specific conditions of the invention. Therefore, the embodiments disclosed herein are to be construed as illustrative and not restricting

100．．．多通道類比/數位轉換器100. . . Multichannel analog/digital converter

102．．．誤差放大器102. . . Error amplifier

104．．．比較器104. . . Comparators

106．．．數位/類比轉換器106. . . Digital/analog converter

108．．．多工器108. . . Multiplexer

110．．．調變器110. . . Modulator

111．．．回授信號111. . . Feedback signal

120．．．採樣電容120. . . Sampling capacitor

122~128．．．開關122~128. . . switch

130．．．採樣-積分單元130. . . Sampling-integration unit

170．．．輸出信號170. . . output signal

200A~200B．．．波形圖200A~200B. . . Waveform

202~212．．．波形202~212. . . Waveform

300．．．流程圖300. . . flow chart

302~360．．．步驟302~360. . . step

400．．．電子系統400. . . electronic system

402~408．．．裝置402~408. . . Device

422~428．．．接收器422~428. . . receiver

500．．．類比/數位轉換器500. . . Analog/digital converter

502．．．誤差放大器502. . . Error amplifier

510．．．調變器510. . . Modulator

512．．．誤差放大器512. . . Error amplifier

520．．．能量儲存單元520. . . Energy storage unit

522~528．．．開關522~528. . . switch

530．．．採樣-積分單元530. . . Sampling-integration unit

540．．．能量儲存單元540. . . Energy storage unit

542~548．．．開關542~548. . . switch

550．．．採樣-積分單元550. . . Sampling-integration unit

570．．．輸出信號570. . . output signal

572．．．輸出信號572. . . output signal

600．．．曲線圖600. . . Graph

700．．．多通道類比/數位轉換器700. . . Multichannel analog/digital converter

706．．．數位/類比轉換器706. . . Digital/analog converter

710．．．調節器710. . . Regulator

711．．．回授信號711. . . Feedback signal

713．．．回授信號713. . . Feedback signal

714．．．數位/類比轉換器714. . . Digital/analog converter

720．．．能量儲存單元720. . . Energy storage unit

722~728．．．開關722~728. . . switch

730．．．前饋順向電路730. . . Feedforward forward circuit

800．．．流程圖800. . . flow chart

802~818．．．步驟802~818. . . step

C_i1 ~C_i4 ．．．積分電容C _i1 ~C _i4 . . . Integral capacitor

C_i1A ~C_i4A ．．．積分電容C _i1A ~C _i4A . . . Integral capacitor

C_i1B ~C_i4B ．．．積分電容C _i1B ~C _i4B . . . Integral capacitor

S₁ ~S₂ ．．．階段S ₁ ~S ₂ . . . stage

S_1A ~S_4A ．．．開關S _1A ~ S _4A . . . switch

S_1B ~S_4B ．．．開關S _1B ~S _4B . . . switch

S_1C ~S_4C ．．．開關S _1C ~S _4C . . . switch

S_CLK ．．．時脈信號S _CLK . . . Clock signal

F₁ ~F₄ ．．．數位濾波器F ₁ ~F ₄ . . . Digital filter

T₁ ~T₅ ．．．時脈週期T ₁ ~T ₅ . . . Clock cycle

PH₁ ~PH₂ ．．．信號PH ₁ ~ PH ₂ . . . signal

V₁ ~V₄ ．．．類比電壓信號V ₁ ~V ₄ . . . Analog voltage signal

V_REF ．．．參考電壓V _REF . . . Reference voltage

圖1所示為本發明的一實施例的多通道類比/數位轉換器的架構示意圖；1 is a schematic structural diagram of a multi-channel analog/digital converter according to an embodiment of the present invention;

圖2A所示為本發明的一實施例的多通道類比/數位轉換器信號的波形圖；2A is a waveform diagram of a multi-channel analog/digital converter signal according to an embodiment of the present invention;

圖2B所示為本發明的另一實施例的多通道類比/數位轉換器信號的波形圖；2B is a waveform diagram of a multi-channel analog/digital converter signal according to another embodiment of the present invention;

圖3所示為本發明的一實施例的多通道類比/數位轉換器操作流程圖；3 is a flow chart showing the operation of a multi-channel analog/digital converter according to an embodiment of the present invention;

圖4所示為本發明的一實施例的電子系統的架構示意圖；4 is a schematic structural diagram of an electronic system according to an embodiment of the present invention;

圖5所示為本發明的另一實施例的多通道類比/數位轉換器的架構示意圖；FIG. 5 is a schematic structural diagram of a multi-channel analog/digital converter according to another embodiment of the present invention; FIG.

圖6所示為本發明的一實施例的類比/數位轉換器不同階次的過採樣率的信噪比曲線；6 is a signal to noise ratio curve of an oversampling ratio of different orders of an analog/digital converter according to an embodiment of the present invention;

圖7所示為本發明的另一實施例的多通道類比/數位轉換器的架構示意圖；以及7 is a block diagram showing the architecture of a multi-channel analog/digital converter according to another embodiment of the present invention;

圖8所示為本發明的一實施例的多通道類比/數位轉換器操作流程圖。FIG. 8 is a flow chart showing the operation of a multi-channel analog/digital converter according to an embodiment of the present invention.

104．．．比較器104. . . Comparators

106．．．數位/類比轉換器106. . . Digital/analog converter

108．．．多工器108. . . Multiplexer

111．．．回授信號111. . . Feedback signal

500．．．類比/數位轉換器500. . . Analog/digital converter

502．．．誤差放大器502. . . Error amplifier

510．．．調變器510. . . Modulator

512．．．誤差放大器512. . . Error amplifier

520．．．能量儲存單元520. . . Energy storage unit

522~528．．．開關522~528. . . switch

530．．．採樣-積分單元530. . . Sampling-integration unit

540．．．能量儲存單元540. . . Energy storage unit

542~548．．．開關542~548. . . switch

550．．．採樣-積分單元550. . . Sampling-integration unit

570．．．輸出信號570. . . output signal

572．．．輸出信號572. . . output signal

C_i1A ~C_i4A ．．．積分電容C _i1A ~C _i4A . . . Integral capacitor

C_i1B ~C_i4B ．．．積分電容C _i1B ~C _i4B . . . Integral capacitor

F₁ ~F₄ ．．．數位濾波器F ₁ ~F ₄ . . . Digital filter

PH₁ ~PH₂ ．．．信號PH ₁ ~ PH ₂ . . . signal

S_1A ~S_4A ．．．開關S _1A ~ S _4A . . . switch

S_1B ~S_4B ．．．開關S _1B ~S _4B . . . switch

S_1C ~S_4C ．．．開關S _1C ~S _4C . . . switch

S_CLK ．．．時脈信號S _CLK. . . Clock signal

V₁ ~V₄ ．．．類比電壓信號V ₁ ~V ₄ . . . Analog voltage signal

V_REF ．．．參考電壓V _REF . . . Reference voltage