TWI514590B - Erasable programmable single-ploy nonvolatile memory - Google Patents
- ️Mon Dec 21 2015
TWI514590B - Erasable programmable single-ploy nonvolatile memory - Google Patents
Erasable programmable single-ploy nonvolatile memory Download PDFInfo
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- TWI514590B TWI514590B TW102145911A TW102145911A TWI514590B TW I514590 B TWI514590 B TW I514590B TW 102145911 A TW102145911 A TW 102145911A TW 102145911 A TW102145911 A TW 102145911A TW I514590 B TWI514590 B TW I514590B Authority
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- 2013-05-14
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- 239000000758 substrate Substances 0.000 claims description 55
- 229910052732 germanium Inorganic materials 0.000 claims description 29
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 29
- 238000000034 method Methods 0.000 claims description 16
- 230000000694 effects Effects 0.000 description 15
- 230000004888 barrier function Effects 0.000 description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 11
- 229920005591 polysilicon Polymers 0.000 description 11
- 230000008901 benefit Effects 0.000 description 10
- 238000010586 diagram Methods 0.000 description 8
- 238000002955 isolation Methods 0.000 description 8
- 230000015556 catabolic process Effects 0.000 description 7
- 239000000969 carrier Substances 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 230000008859 change Effects 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- YZCKVEUIGOORGS-OUBTZVSYSA-N Deuterium Chemical group [2H] YZCKVEUIGOORGS-OUBTZVSYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 229910052805 deuterium Inorganic materials 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000002784 hot electron Substances 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
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- Non-Volatile Memory (AREA)
Description
本發明是有關於一種非揮發性記憶體(nonvolatile memory)，且特別是有關於一種具可程式可抹除的單一多晶矽層非揮發性記憶體。The present invention relates to a nonvolatile memory, and more particularly to a single polycrystalline germanium layer non-volatile memory with programmable erasability.
請參照第1圖，其所繪示為習知具可程式的雙多晶矽層非揮發性記憶體(programmable dual-poly nonvolatile memory)示意圖。此具可程式的雙多晶矽層的非揮發性記憶體又稱為浮動閘極電晶體(floating-gate transistor)。此非揮發性記憶體包括堆疊且不相接觸的二個閘極，上方為控制閘極(control gate)12連接至控制線(C)、下方為浮動閘極(floating gate)14。而在p型基板(P-substrate)中包括一n型源極摻雜區域(n type source doped region)連接至源極線(S)以及一n型汲極摻雜區域(n type drain doped region)連接至汲極線(D)。Please refer to FIG. 1 , which is a schematic diagram of a programmable dual-poly nonvolatile memory. The non-volatile memory of the programmable dual polysilicon layer is also referred to as a floating-gate transistor. The non-volatile memory includes two gates that are stacked and not in contact, with a control gate 12 connected to the control line (C) and a floating gate 14 below. In the p-substrate, an n-type source doped region is connected to the source line (S) and an n-type drain doped region (n type drain doped region) ) Connect to the bungee line (D).
舉例來說，於程式狀態(programmed state)時，汲極線(D)提供一高電壓(例如+16V)、源極線(S)提供一接地電壓(Ground)、控制線(C)提供一控制電壓(例如+25V)。因此，當電子由源極線(S)經過n通道(n-channel)至汲極線(D)的過程，熱載子(hot carrier)，例如熱電子(hot electron)，會被控制閘極12上的控制電壓所吸引並且注入(inject)浮動閘極14中。此時，浮動閘極14累積許多載子(carrier)，因此可視為第一儲存狀態(例如“0”)。For example, in the programmed state, the drain line (D) provides a high voltage (eg, +16V), the source line (S) provides a ground voltage (Ground), and the control line (C) provides a Control voltage (eg +25V). Therefore, when electrons pass through the n-channel to the drain line (D) from the source line (S), hot carriers, such as hot electrons, are controlled by the gate. The control voltage on 12 is attracted to and injected into the floating gate 14. At this time, the floating gate 14 accumulates a lot of carriers, and thus can be regarded as the first storage state (for example, "0").
於未程式狀態(not-programmed state)時，浮動閘極 14中沒有任何載子(carrier)，因此可視為第二儲存狀態(例如“1”)。Floating gate in un-programmed state There is no carrier in 14 and therefore can be considered as the second storage state (eg "1").
換句話說，於第一儲存狀態以及第二儲存狀態將造成浮動閘極電晶體的汲極電流(id)與閘極源電壓(Vgs)的特性(id-Vgs characteristic)變化。因此，根據汲極電流(id)與閘極源電壓(Vgs)的特性(id-Vgs characteristic)變化即可得知浮動閘極電晶體的儲存狀態。In other words, the first storage state and the second storage state will cause a change in the drain current (id) of the floating gate transistor and the characteristic (id-Vgs characteristic) of the gate source voltage (Vgs). Therefore, the storage state of the floating gate transistor can be known from the variation of the drain current (id) and the gate source voltage (Vgs) characteristic (id-Vgs characteristic).
然而，雙多晶矽層的非揮發性記憶體由於需要分開製作浮動閘極14以及控制閘極12，因此需要較多的製作步驟才可完成，並且不相容於標準CMOS電晶體的製程。However, the non-volatile memory of the double polysilicon layer requires separate fabrication steps to be completed due to the need to separately fabricate the floating gate 14 and the control gate 12, and is incompatible with the standard CMOS transistor process.
美國專利US6678190揭露一種具可程式的單一多晶矽層非揮發性記憶體。請參照第2A圖，其所繪示為習知具可程式的單一多晶矽層非揮發性記憶體示意圖；第2B圖所繪示為習知具可程式的單一多晶矽層非揮發性記憶體的上視圖；第2C圖所繪示為習知具可程式的單一多晶矽層非揮發性記憶體的電路圖。U.S. Patent 6,678,190 discloses a programmable single polycrystalline germanium layer non-volatile memory. Please refer to FIG. 2A, which is a schematic diagram of a conventional programmable polycrystalline germanium layer non-volatile memory; FIG. 2B is a diagram of a conventional programmable polycrystalline germanium layer non-volatile memory. View; Figure 2C is a circuit diagram of a conventional single polycrystalline germanium non-volatile memory.
如第2A圖至第2C圖所示，習知具可程式的單一多晶矽層非揮發性記憶體係包括二個串接(serially connected)的PMOS電晶體。第一PMOS電晶體係作為選擇電晶體(select transistor)，其選擇閘極(select gate)24連接至一選擇閘極電壓(select gate voltage，VSG )，第一p型源/汲區域(p type source/drain region)21連接至源極線電壓(source line voltage，VSL )。再者，第二p型源/汲區域22可視為第一PMOS電晶體的p型汲極區域(p type drain region)與第二PMOS電晶體的p型源極區域相互連接。第二PMOS電晶體上方包括一浮動閘極26，其第三p型源/汲區域23連接至位元線電壓(bit line voltage，VBL )。再者，該二PMOS電晶體係製作於一N型井區(N-well，NW)其連接至一N型井區電壓(N-well voltage，VNW )。其中，第二PMOS電晶體係作為浮動閘極電晶體。As shown in Figures 2A through 2C, conventional programmable single polysilicon layer non-volatile memory systems include two serially connected PMOS transistors. The first PMOS transistor system is used as a select transistor, and a select gate 24 is connected to a select gate voltage (V SG ), the first p-type source/汲 region (p Type source/drain region 21 is connected to the source line voltage (V SL ). Furthermore, the second p-type source/german region 22 can be considered as a p-type drain region of the first PMOS transistor and a p-type source region of the second PMOS transistor. The second PMOS transistor includes a floating gate 26 above it, and the third p-type source/german region 23 is connected to a bit line voltage ( VBL ). Furthermore, the two PMOS transistor system is fabricated in an N-well (N-well, NW) connected to an N-well voltage (V NW ). Wherein, the second PMOS electro-crystal system acts as a floating gate transistor.
再者，經由適當地控制選擇閘極電壓(VSG )、源極線 電壓(VSL )、位元線電壓(VBL )、以及N型井區電壓(VNW )即可以使習知具可程式的單一多晶矽層非揮發性記憶體進入程式狀態、或者讀取狀態。Furthermore, by appropriately controlling the selection gate voltage (V SG ), the source line voltage (V SL ), the bit line voltage (V BL ), and the N-type well voltage (V NW ), it is possible to make the conventional device The programmable single polysilicon layer non-volatile memory enters the program state or the read state.
由於習知具可程式的單一多晶矽層非揮發性記憶體中，2個PMOS電晶體各僅有一個閘極24、26，因此可完全相容於傳統標準CMOS電晶體的製程。Since the conventional PMOS transistor has only one gate 24 and 26 in the programmable polysilicon layer non-volatile memory, it can be completely compatible with the process of the conventional standard CMOS transistor.
然而，第1圖與第2A至2C圖的非揮發性記憶體僅具備可程式的功能，其僅可利用電氣特性將熱載子注入於浮動閘極中，並無法利用電氣的特性來將浮動閘極中的儲存載子移除，僅可利用紫外光(ultravilote light)照射方式來清除於浮動閘極中的儲存載子，進而達成資料抹除的功能。因此，這類非揮發性記憶體係被稱為具一次程式的記憶體(one time programming memory，簡稱OTP memory)。However, the non-volatile memory of Fig. 1 and Figs. 2A to 2C has only a programmable function, which can only inject thermal carriers into the floating gate using electrical characteristics, and cannot utilize the electrical characteristics to float. The storage carrier in the gate is removed, and only the ultraviolet (ultravilote light) illumination method can be used to remove the storage carrier in the floating gate, thereby achieving the function of data erasing. Therefore, such a non-volatile memory system is called a one-time programming memory (OTP memory).
因此，如何改進上述具可程式的單一多晶矽層非揮發性記憶體，並且達成具可程式可抹除的單一多晶矽層非揮發性記憶體，也就是達成具多次程式的記憶體(multi-times programming memory，簡稱MTP memory)即是本發明所欲達成的目的。Therefore, how to improve the above-mentioned programmable polycrystalline germanium layer non-volatile memory, and achieve a single polycrystalline germanium layer non-volatile memory with programmable erasability, that is, to achieve a multi-time memory (multi-times) Programming memory (MTP memory for short) is the object of the present invention.
本發明的目的係提出一種具可程式可抹除的單一多晶矽層非揮發性記憶體。係針對習知非揮發性記憶體進行改進達成具可程式可抹除的單一多晶矽層非揮發性記憶體。SUMMARY OF THE INVENTION The object of the present invention is to provide a single polycrystalline germanium layer non-volatile memory with programmable erasability. The conventional non-volatile memory is modified to achieve a single polycrystalline germanium layer non-volatile memory with programmable erasability.
本發明係有關於一種具可程式可抹除的單一多晶矽非揮發性記憶體，包括：一基板結構；一浮動閘極電晶體，包括一浮動閘極、一閘極氧化層位於該浮動閘極下方、以及一通道區域位於一N型井區內；以及一抹除閘區域，包括一P型井區與一n型源/汲區域，該n型源/汲區域連接至一抹除線電壓，其中該浮動閘極係向外延伸並相鄰於該抹除閘區域；其中，該P型井區與 該N型井區形成於該基板結構中，該閘極氧化層包括一第一部份位於該通道區域上方，以及一第二部份位於該抹除閘區域上方，並且該閘極氧化層的該第一部份之厚度相異於該閘極氧化層的該第二部份之厚度。The invention relates to a single polycrystalline germanium non-volatile memory with programmable erasability, comprising: a substrate structure; a floating gate transistor comprising a floating gate and a gate oxide layer at the floating gate a lower and a channel region are located in an N-type well region; and a wipe-off region includes a P-type well region and an n-type source/turn region, the n-type source/turn region being connected to a erase line voltage, wherein The floating gate extends outwardly and adjacent to the erase gate region; wherein the P-well region and The N-type well region is formed in the substrate structure, the gate oxide layer includes a first portion above the channel region, and a second portion is above the erase gate region, and the gate oxide layer The thickness of the first portion is different from the thickness of the second portion of the gate oxide layer.
為了對本發明之上述及其他方面有更佳的瞭解，下文特舉較佳實施例，並配合所附圖式，作詳細說明如下：In order to better understand the above and other aspects of the present invention, the preferred embodiments are described below, and in conjunction with the drawings, the detailed description is as follows:
12‧‧‧控制閘極12‧‧‧Control gate
14‧‧‧浮動閘極14‧‧‧Floating gate
21‧‧‧第一p型源/汲區域21‧‧‧First p-type source/汲 area
22‧‧‧第二p型源/汲區域22‧‧‧Second p-type source/汲 area
23‧‧‧第三p型源/汲區域23‧‧‧ Third p-type source/汲 area
24‧‧‧選擇閘極24‧‧‧Select gate
26‧‧‧浮動閘極26‧‧‧Floating gate
31‧‧‧第一p型源/汲區域31‧‧‧First p-type source/汲 area
32‧‧‧第二p型源/汲區域32‧‧‧Second p-type source/汲 area
33‧‧‧第三p型源/汲區域33‧‧‧ Third p-type source/汲 area
34‧‧‧選擇閘極34‧‧‧Select gate
35、65‧‧‧抹除閘區域35, 65‧‧‧ erasing gate area
36‧‧‧浮動閘極36‧‧‧Floating gate
362‧‧‧閘極氧化層362‧‧‧ gate oxide layer
362a‧‧‧第一部份362a‧‧‧ first part
362b‧‧‧第二部份362b‧‧‧ second part
38、62‧‧‧n型源/汲區域38, 62‧‧‧n type source/汲 area
39‧‧‧隔離結構39‧‧‧Isolation structure
64‧‧‧雙擴散汲極摻雜區64‧‧‧Double diffusion doped region
第1圖所繪示為習知具可程式的雙多晶矽層非揮發性記憶體示意圖。Figure 1 is a schematic diagram of a conventional programmable polycrystalline germanium layer non-volatile memory.
第2A圖~第2C圖所繪示為習知具可程式的單一多晶矽層非揮發性記憶體示意圖。2A to 2C are schematic diagrams showing a conventional programmable polycrystalline germanium layer non-volatile memory.
第3A圖~第3D圖所繪示為本發明具可程式可抹除的單一多晶矽層非揮發性記憶體的第一實施例。3A to 3D illustrate a first embodiment of a single polycrystalline germanium layer non-volatile memory having a programmable erasable in the present invention.
第4圖所示之基板結構包括一P型基板與一深N型井區。The substrate structure shown in Fig. 4 includes a P-type substrate and a deep N-type well region.
第5圖所示之基板結構包括一第四p型區域、一n型位障層(NBL)與一P型基板。The substrate structure shown in FIG. 5 includes a fourth p-type region, an n-type barrier layer (NBL) and a P-type substrate.
第6A圖~第6B圖所繪示為另一種抹除閘區域的示意圖。6A to 6B are schematic views showing another erase gate region.
第7圖所示之基板結構包括一P型基板與一深N型井區。The substrate structure shown in Fig. 7 includes a P-type substrate and a deep N-type well region.
第8圖所示之基板結構包括一第四p型區域、一n型位障層(NBL)與一P型基板。The substrate structure shown in FIG. 8 includes a fourth p-type region, an n-type barrier layer (NBL) and a P-type substrate.
第9圖所示為抹除狀態時的二種偏壓方法。Figure 9 shows the two biasing methods in the erased state.
請參照第3A圖~第3D圖，其所繪示為本發明具可程式可抹除的單一多晶矽層非揮發性記憶體的第一實施例。其中，第3A圖為第一實施例的上視圖；第3B圖為第一實施例的第一方向(a1 a2方向)剖面圖；第3C圖為第一實施例的第二方向(b1 b2方向)剖面圖；以及，第3D為第一實施例的等效電路圖。再者，本發明的非揮發性記憶體係利用相容於邏輯CMOS製成的單一多晶程序(single ploy process)來製造完成。Please refer to FIG. 3A to FIG. 3D, which illustrate a first embodiment of a single polycrystalline germanium layer non-volatile memory with programmable erasable in the present invention. 3A is a top view of the first embodiment; FIG. 3B is a first direction (a1 a2 direction) cross-sectional view of the first embodiment; and FIG. 3C is a second direction (b1 of the first embodiment) a b2 direction) sectional view; and, 3D is an equivalent circuit diagram of the first embodiment. Furthermore, the non-volatile memory system of the present invention is fabricated using a single ploy process that is compatible with logic CMOS.
由第3A圖與第3B圖可知，本發明第一實施例中包括二個串接的PMOS電晶體製作於一N型井區(NW)。在N型井區NW中包括三個p型源/汲區域31、32、33，在三個p型源/汲區域31、32、33之間的表面上方包括二個閘極氧化層342、362以及由多晶矽(polysilicon)所組成的閘極34、36。再者，位於N型井區NW上方二個閘極34、36係為p型汲極摻雜的多晶矽(polysilicon)閘極34、36。As can be seen from FIGS. 3A and 3B, the first embodiment of the present invention includes two serially connected PMOS transistors fabricated in an N-type well region (NW). Included in the N-well region NW are three p-type source/deuterium regions 31, 32, 33 comprising two gate oxide layers 342 over the surface between the three p-type source/german regions 31, 32, 33, 362 and gates 34, 36 composed of polysilicon. Furthermore, the two gates 34, 36 above the N-well region NW are p-type drain-doped polysilicon gates 34, 36.
第一PMOS電晶體係作為選擇電晶體，其閘極34(可稱為選擇閘極)連接至一選擇閘極電壓(VSG )，第一p型源/汲區域31連接至源極線電壓(VSL )。再者，第二p型源/汲區域32可視為第一PMOS電晶體的p型汲極區域與第二PMOS電晶體的p型源極區域相互連接。第二PMOS電晶體上方包括一閘極36(可稱為浮動閘極)，其第三p型源/汲區域33連接至位元線電壓(VBL )。而N型井區(NW)係連接至一N型井區電壓(VNW )。其中，第二PMOS電晶體係作為浮動閘極電晶體。The first PMOS transistor system is used as the selection transistor, and its gate 34 (which may be referred to as a selection gate) is connected to a selection gate voltage (V SG ), and the first p-type source/german region 31 is connected to the source line voltage. (V SL ). Furthermore, the second p-type source/german region 32 can be considered as interconnecting the p-type drain region of the first PMOS transistor with the p-type source region of the second PMOS transistor. The second PMOS transistor includes a gate 36 (which may be referred to as a floating gate) and a third p-type source/german region 33 connected to the bit line voltage ( VBL ). The N-type well region (NW) is connected to an N-type well region voltage (V NW ). Wherein, the second PMOS electro-crystal system acts as a floating gate transistor.
由第3A圖與第3C圖可知，本發明第一實施例中更包括一個NMOS電晶體，或者可說包括一浮動閘極36、閘極氧化層362以及一個抹除閘區域(erase gate region)35所組合而成的元件。而NMOS電晶體製作於一P型井區(PW)中。換言之，抹除閘區域35包括P型井區(PW)以及n型源/汲區域38。再者，位於P型井區(PW)上方的浮動閘極36係為一n型摻雜的多晶矽閘極；P型井區(PW)也可以是p型摻雜的井區，N型井區(NW)也可以是n型摻雜的井區。3A and 3C, the first embodiment of the present invention further includes an NMOS transistor, or can include a floating gate 36, a gate oxide layer 362, and an erase gate region. 35 combined components. The NMOS transistor is fabricated in a P-type well region (PW). In other words, the erase gate region 35 includes a P-type well region (PW) and an n-type source/turn region 38. Furthermore, the floating gate 36 located above the P-type well region (PW) is an n-type doped polysilicon gate; the P-type well region (PW) may also be a p-type doped well region, the N-type well The zone (NW) can also be an n-doped well zone.
如第3A圖所示，浮動閘極36係向外延伸並相鄰於抹除閘區域35。因此，浮動閘極36可視為NMOS電晶體的閘極，而n型源/汲區域38可視為n型源極區域與n型汲極區域相互連 接。再者，n型源/汲區域38連接至抹除線電壓(erase line voltage，VEL )。而P型井區(PW)係連接至一P型井區電壓(VPW )。再者，由第3C圖可知，浮動閘極36下方的閘極氧化層362包括二個部份362a、362b。閘極氧化層362的第一部份362a係形成於浮動閘極電晶體(第二PMOS電晶體)上；閘極氧化層362的第二部份362b係形成於NMOS電晶體上或者可說是形成於抹除閘區域35的上方。在本發明的實施例中，可以利用回蝕製程(etching back process)來蝕刻並形成第二部份362b的閘極氧化層362，或是也可以利用熱氧化或是沉積製程來形成。因此，閘極氧化層362第一部份362a的厚度將大於閘極氧化層362第二部份362b的厚度。再者，抹除閘區域35與N型井區(NW)之間形成隔離結構(isolating structure)39，此隔離結構39例如為淺溝槽隔離(shallow trench isolation，STI)。As shown in FIG. 3A, the floating gate 36 extends outwardly and adjacent to the erase gate region 35. Therefore, the floating gate 36 can be regarded as the gate of the NMOS transistor, and the n-type source/german region 38 can be regarded as being connected to the n-type drain region and the n-type drain region. Furthermore, the n-type source/german region 38 is connected to an erase line voltage (V EL ). The P-type well region (PW) is connected to a P-type well region voltage (V PW ). Furthermore, as can be seen from FIG. 3C, the gate oxide layer 362 under the floating gate 36 includes two portions 362a, 362b. The first portion 362a of the gate oxide layer 362 is formed on the floating gate transistor (second PMOS transistor); the second portion 362b of the gate oxide layer 362 is formed on the NMOS transistor or can be said to be Formed above the erase gate region 35. In an embodiment of the invention, the gate oxide layer 362 of the second portion 362b may be etched and formed using an etching back process, or may be formed using a thermal oxidation or deposition process. Therefore, the thickness of the first portion 362a of the gate oxide layer 362 will be greater than the thickness of the second portion 362b of the gate oxide layer 362. Furthermore, an isolating structure 39 is formed between the erase gate region 35 and the N-type well region (NW), and the isolation structure 39 is, for example, shallow trench isolation (STI).
如第3D圖所示，抹除閘區域35實際上可以視為一穿透電容器(tunneling capacitor)用以退出(eject)儲存在浮動閘極36中的載子。As shown in FIG. 3D, the erase gate region 35 can actually be regarded as a tunneling capacitor for ejecting carriers stored in the floating gate 36.
再者，以下將詳細的介紹運用於第一實施例的各種不同的基板結構以及P型井區(PW)。請參照第4圖，基板結構包括一P型基板與一深N型井區(DNW)。其中，深N型井區(DNW)形成於P型基板中，並且深N型井區(DNW)連接於深N型井區電壓(VDNW )。Further, various different substrate structures and P-type well regions (PW) applied to the first embodiment will be described in detail below. Referring to FIG. 4, the substrate structure includes a P-type substrate and a deep N-type well region (DNW). Among them, the deep N-type well region (DNW) is formed in the P-type substrate, and the deep N-type well region (DNW) is connected to the deep N-type well region voltage (V DNW ).
如第4圖所示，第一實施例的N型井區(NW)與P型井區(PW)形成於基板結構中的深N型井區(DNW)內。再者，P型井區(PW)個包括一個第一p型區域(p1)、二個第二p型區域(p2)、與一個第三p型區域(p3)。其中，第二p型區域(p2)的摻雜量大於等於第一p型區域(p1)的摻雜量；且第三p型區域(p3)的摻雜量大於等於第一p型區域(p1)的摻雜量。As shown in Fig. 4, the N-type well region (NW) and the P-type well region (PW) of the first embodiment are formed in a deep N-type well region (DNW) in the substrate structure. Furthermore, the P-type well regions (PW) include a first p-type region (p1), two second p-type regions (p2), and a third p-type region (p3). Wherein, the doping amount of the second p-type region (p2) is greater than or equal to the doping amount of the first p-type region (p1); and the doping amount of the third p-type region (p3) is greater than or equal to the first p-type region ( The doping amount of p1).
再者，第一p型區域(p1)係形成於基板結構的表面下方並且接觸於n型源/汲區域38。第三p型區域(p3)形成於第一 p型區域(p1)的下方。而第一p型區域(p1)與第三p型區域(p3)被第二p型區域(p2)圍繞住，且第二p型區域(p2)形成於二個隔離結構39下方。Furthermore, the first p-type region (p1) is formed below the surface of the substrate structure and is in contact with the n-type source/german region 38. The third p-type region (p3) is formed at the first Below the p-type region (p1). The first p-type region (p1) and the third p-type region (p3) are surrounded by the second p-type region (p2), and the second p-type region (p2) is formed under the two isolation structures 39.
本發明的第4圖結構之第一優點在於，第一p型區域(p1)與n型源/汲區域38之間的接面崩潰電壓可以提高，使得本發明具可程式可抹除的單一多晶矽層非揮發性記憶體之抹除效率將有效地被提升。另外，第二優點在於，二個第二p型區域(p2)能夠改善高溫環境下n型源/汲區域38與N型井區(NW)之間的側面擊穿效應(lateral punch through effect)；第三p型區域(p3)能夠改善高溫環境下n型源/汲區域38與深N型井區(DNW)之間的垂直擊穿效應(vertical punch through effect)。A first advantage of the structure of Fig. 4 of the present invention is that the junction breakdown voltage between the first p-type region (p1) and the n-type source/german region 38 can be increased, so that the present invention has a programmable erasable single The erasing efficiency of the polycrystalline germanium layer non-volatile memory will be effectively improved. In addition, a second advantage is that the two second p-type regions (p2) can improve the lateral punch through effect between the n-type source/german region 38 and the N-type well region (NW) in a high temperature environment. The third p-type region (p3) can improve the vertical punch through effect between the n-type source/german region 38 and the deep N-well region (DNW) in a high temperature environment.
請參照第5圖，基板結構包括一第四p型區域(p4)、一n型位障層(n-type barrier layer，NBL)與一P型基板。而n型位障層即為一n型區域。其中，n型位障層(NBL)形成於P型基板中，並且第四p型區域(p4)位於n型位障層(NBL)上方並且接觸於n型位障層(NBL)。Referring to FIG. 5, the substrate structure includes a fourth p-type region (p4), an n-type barrier layer (NBL), and a P-type substrate. The n-type barrier layer is an n-type region. Wherein, an n-type barrier layer (NBL) is formed in the P-type substrate, and the fourth p-type region (p4) is located above the n-type barrier layer (NBL) and is in contact with the n-type barrier layer (NBL).
如第5圖所示，第一實施例的N型井區(NW)與P型井區(PW)形成於基板結構中的第四p型區域(p4)內。再者，P型井區(PW)個包括一個第一p型區域(p1)、二個第二p型區域(p2)、與一個第三p型區域(p3)。其中，第二p型區域(p2)的摻雜量大於等於第一p型區域(p1)的摻雜量；且第三p型區域(p3)的摻雜量大於等於第一p型區域(p1)的摻雜量。另外，第四p型區域(p4)的摻雜量等於P型基板的摻雜量。或者，第四p型區域(p4)的摻雜量大於等於第三p型區域(p3)的摻雜量；並且第四p型區域(p4)的摻雜量小於等於第二p型區域(p2)的摻雜量。As shown in Fig. 5, the N-type well region (NW) and the P-type well region (PW) of the first embodiment are formed in the fourth p-type region (p4) in the substrate structure. Furthermore, the P-type well regions (PW) include a first p-type region (p1), two second p-type regions (p2), and a third p-type region (p3). Wherein, the doping amount of the second p-type region (p2) is greater than or equal to the doping amount of the first p-type region (p1); and the doping amount of the third p-type region (p3) is greater than or equal to the first p-type region ( The doping amount of p1). In addition, the doping amount of the fourth p-type region (p4) is equal to the doping amount of the P-type substrate. Alternatively, the doping amount of the fourth p-type region (p4) is greater than or equal to the doping amount of the third p-type region (p3); and the doping amount of the fourth p-type region (p4) is less than or equal to the second p-type region ( The doping amount of p2).
再者，第一p型區域(p1)係形成於基板結構的表面下方並且接觸於n型源/汲區域38。第三p型區域(p3)形成於第一p型區域(p1)的下方。而第一p型區域(p1)與第三p型區域(p3)被第二p型區域(p2)圍繞住，且第二p型區域(p2)形成於二個隔離結 構39下方。Furthermore, the first p-type region (p1) is formed below the surface of the substrate structure and is in contact with the n-type source/german region 38. The third p-type region (p3) is formed below the first p-type region (p1). The first p-type region (p1) and the third p-type region (p3) are surrounded by the second p-type region (p2), and the second p-type region (p2) is formed on the two isolation junctions. Below the structure 39.
本發明的第5圖結構之第一優點在於，第一p型區域(p1)與n型源/汲區域38之間的接面崩潰電壓可以提高，使得本發明具可程式可抹除的單一多晶矽層非揮發性記憶體之抹除效率將有效地被提升。另外，第二優點在於，二個第二p型區域(p2)能夠改善高溫環境下n型源/汲區域38與N型井區(NW)之間的側面擊穿效應(lateral punch through effect)；第三p型區域(p3)能夠改善高溫環境下n型源/汲區域38與n型位障層(NBL)之間的垂直擊穿效應(vertical punch through effect)。而第三優點在於，利用第四p型區域(p4)與P型井區(PW)將N型井區(NW)隔離，使N型井區(NW)可獨立的偏壓操作，進而可以降低浮動閘極36與N型井區(NW)之間的電壓應力(voltage stress)。A first advantage of the structure of the fifth embodiment of the present invention is that the junction breakdown voltage between the first p-type region (p1) and the n-type source/german region 38 can be increased, so that the present invention has a programmable erasable single The erasing efficiency of the polycrystalline germanium layer non-volatile memory will be effectively improved. In addition, a second advantage is that the two second p-type regions (p2) can improve the lateral punch through effect between the n-type source/german region 38 and the N-type well region (NW) in a high temperature environment. The third p-type region (p3) can improve the vertical punch through effect between the n-type source/german region 38 and the n-type barrier layer (NBL) in a high temperature environment. The third advantage is that the fourth p-type region (p4) and the P-type well region (PW) are used to isolate the N-type well region (NW), so that the N-type well region (NW) can be independently biased, and thus The voltage stress between the floating gate 36 and the N-type well region (NW) is reduced.
請參照第6A圖與第6B圖，其所繪示為另一種抹除閘區域的示意圖。此抹除閘區域65可以取代第一實施例中的抹除閘區域35。而第一PMOS電晶體(選擇電晶體)與第二PMOS電晶體(浮動閘極電晶體)的結構與第3B圖相同，不再贅述。Please refer to FIG. 6A and FIG. 6B , which are schematic diagrams showing another erase gate region. This erase gate region 65 can replace the erase gate region 35 in the first embodiment. The structure of the first PMOS transistor (selective transistor) and the second PMOS transistor (floating gate transistor) is the same as that of FIG. 3B and will not be described again.
相較於第3C圖之抹除閘區域35，第6A圖與第6B圖所繪示的抹除閘區域65包括一雙擴散汲極(double diffused drain，DDD)摻雜區64形成於n型摻雜區域62與P型井區(PW)之間，而此雙擴散汲極(DDD)摻雜區64也是一種n型區域。同理，為了具備較低的抹除線電壓(VEL )，第二部份362b的閘極氧化層362之厚度小於第一部份362a的閘極氧化層362之厚度。Compared to the erase gate region 35 of FIG. 3C, the erase gate region 65 illustrated in FIGS. 6A and 6B includes a double diffused drain (DDD) doped region 64 formed in the n-type. The doped region 62 is between the P-type well region (PW) and the double diffused drain (DDD) doped region 64 is also an n-type region. Similarly, in order to have a lower erase line voltage (V EL ), the thickness of the gate oxide layer 362 of the second portion 362b is less than the thickness of the gate oxide layer 362 of the first portion 362a.
第6B圖所繪示為具備第一PMOS電晶體、第二PMOS電晶體、以及抹除閘區域65之非揮發性記憶體的等效電路。FIG. 6B illustrates an equivalent circuit of the non-volatile memory including the first PMOS transistor, the second PMOS transistor, and the erase gate region 65.
再者，以下將詳細的介紹運用於第6A圖之實施例的各種不同的基板結構以及P型井區(PW)。請參照第7圖，基板結構包括一P型基板與一深N型井區(DNW)。其中，深N型井區(DNW)形成於P型基板中，並且深N型井區(DNW)連接於深N型 井區電壓(VDNW )。Further, various substrate structures and P-type well regions (PW) applied to the embodiment of Fig. 6A will be described in detail below. Referring to FIG. 7, the substrate structure includes a P-type substrate and a deep N-type well region (DNW). Among them, the deep N-type well region (DNW) is formed in the P-type substrate, and the deep N-type well region (DNW) is connected to the deep N-type well region voltage (V DNW ).
如第7圖所示，N型井區(NW)與P型井區(PW)形成於基板結構中的深N型井區(DNW)內。再者，P型井區(PW)個包括一個第一p型區域(p1)、二個第二p型區域(p2)、與一個第三p型區域(p3)。其中，第二p型區域(p2)的摻雜量大於等於第一p型區域(p1)的摻雜量；且第三p型區域(p3)的摻雜量大於等於第一p型區域(p1)的摻雜量。第一p型區域(p1)的摻雜量等於小於雙擴散汲極(DDD)摻雜區64的摻雜量。As shown in Fig. 7, an N-type well region (NW) and a P-type well region (PW) are formed in a deep N-type well region (DNW) in the substrate structure. Furthermore, the P-type well regions (PW) include a first p-type region (p1), two second p-type regions (p2), and a third p-type region (p3). Wherein, the doping amount of the second p-type region (p2) is greater than or equal to the doping amount of the first p-type region (p1); and the doping amount of the third p-type region (p3) is greater than or equal to the first p-type region ( The doping amount of p1). The doping amount of the first p-type region (p1) is equal to the doping amount smaller than the double diffusion drain (DDD) doping region 64.
再者，第一p型區域(p1)係形成於基板結構的表面下方並且接觸於雙擴散汲極(DDD)摻雜區64。第三p型區域(p3)形成於第一 p型區域(p1)的下方。而第一p型區域(p1)與第三p型區域(p3)被第二p型區域(p2)圍繞住，且第二p型區域(p2)形成於二個隔離結構39下方。Furthermore, the first p-type region (p1) is formed below the surface of the substrate structure and is in contact with the double diffused drain (DDD) doped region 64. Third p-type region (p3) is formed below the first p-type region (p1) of. The first p-type region (p1) and the third p-type region (p3) are surrounded by the second p-type region (p2), and the second p-type region (p2) is formed under the two isolation structures 39.
本發明的第7圖結構之第一優點在於，第一p型區域(p1)與雙擴散汲極(DDD)摻雜區64之間的接面崩潰電壓可以提高，使得本發明具可程式可抹除的單一多晶矽層非揮發性記憶體之抹除效率將有效地被提升。另外，第二優點在於，二個第二p型區域(p2)能夠改善高溫環境下雙擴散汲極(DDD)摻雜區64與N型井區(NW)之間的側面擊穿效應；第三p型區域(p3)能夠改善高溫環境下雙擴散汲極(DDD)摻雜區64與深N型井區(DNW)之間的垂直擊穿效應。A first advantage of the structure of Figure 7 of the present invention is that the junction breakdown voltage between the first p-type region (p1) and the double-diffused-drain (DDD) doped region 64 can be increased, so that the present invention is programmable The erase efficiency of the erased single polysilicon layer non-volatile memory will be effectively improved. In addition, the second advantage is that the two second p-type regions (p2) can improve the side breakdown effect between the double diffused drain (DDD) doped region 64 and the N-type well region (NW) in a high temperature environment; The triple p-type region (p3) can improve the vertical breakdown effect between the double diffused drain (DDD) doped region 64 and the deep N-type well region (DNW) in a high temperature environment.
請參照第8圖，基板結構包括一第四p型區域(p4)、一n型位障層(NBL)與一P型基板。而n型位障層即為一n型區域。其中，n型位障層(NBL)形成於P型基板中，並且第四p型區域(p4)位於n型位障層(NBL)上方並且接觸於n型位障層(NBL)。Referring to FIG. 8, the substrate structure includes a fourth p-type region (p4), an n-type barrier layer (NBL), and a P-type substrate. The n-type barrier layer is an n-type region. Wherein, an n-type barrier layer (NBL) is formed in the P-type substrate, and the fourth p-type region (p4) is located above the n-type barrier layer (NBL) and is in contact with the n-type barrier layer (NBL).
如第8圖所示，N型井區(NW)與P型井區(PW)形成於基板結構中的第四p型區域(p4)內。再者，P型井區(PW)個包括一個第一p型區域(p1)、二個第二p型區域(p2)、與一個第三p型區域(p3)。其中，第二p型區域(p2)的摻雜量大於等於第一p 型區域(p1)的摻雜量；且第三p型區域(p3)的摻雜量大於等於第一p型區域(p1)的摻雜量。另外，第四p型區域(p4)的摻雜量等於P型基板的摻雜量。或者，第四p型區域(p4)的摻雜量大於等於第三p型區域(p3)的摻雜量；或者第四p型區域(p4)的摻雜量小於等於第二p型區域(p2)的摻雜量。As shown in Fig. 8, an N-type well region (NW) and a P-type well region (PW) are formed in the fourth p-type region (p4) in the substrate structure. Furthermore, the P-type well regions (PW) include a first p-type region (p1), two second p-type regions (p2), and a third p-type region (p3). Wherein the doping amount of the second p-type region (p2) is greater than or equal to the first p The doping amount of the type region (p1); and the doping amount of the third p-type region (p3) is greater than or equal to the doping amount of the first p-type region (p1). In addition, the doping amount of the fourth p-type region (p4) is equal to the doping amount of the P-type substrate. Alternatively, the doping amount of the fourth p-type region (p4) is greater than or equal to the doping amount of the third p-type region (p3); or the doping amount of the fourth p-type region (p4) is less than or equal to the second p-type region ( The doping amount of p2).
再者，第一p型區域(p1)係形成於基板結構的表面下方並且接觸於雙擴散汲極(DDD)摻雜區64。第三p型區域(p3)形成於第一p型區域(p1)的下方。而第一p型區域(p1)與第三p型區域(p3)被第二p型區域(p2)圍繞住，且第二p型區域(p2)形成於二個隔離結構39下方。Furthermore, the first p-type region (p1) is formed below the surface of the substrate structure and is in contact with the double diffused drain (DDD) doped region 64. The third p-type region (p3) is formed below the first p-type region (p1). The first p-type region (p1) and the third p-type region (p3) are surrounded by the second p-type region (p2), and the second p-type region (p2) is formed under the two isolation structures 39.
本發明的第8圖結構之第一優點在於，第一p型區域(p1)與雙擴散汲極(DDD)摻雜區64之間的接面崩潰電壓可以提高，使得本發明具可程式可抹除的單一多晶矽層非揮發性記憶體之抹除效率將有效地被提升。另外，第二優點在於，二個第二p型區域(p2)能夠改善高溫環境下雙擴散汲極(DDD)摻雜區64與N型井區(NW)之間的側面擊穿效應(lateral punch through effect)；第三p型區域(p3)能夠改善高溫環境下雙擴散汲極(DDD)摻雜區64與深N型井區(DNW)之間的垂直擊穿效應(vertical punch through effect)。而第三優點在於，利用第四p型區域(p4)與P型井區(PW)將N型井區(NW)隔離，使N型井區(NW)得獨立的偏壓操作，進而可以降低浮動閘極36與N型井區(NW)之間的電壓應力。A first advantage of the structure of Figure 8 of the present invention is that the junction breakdown voltage between the first p-type region (p1) and the double-diffused-drain (DDD) doped region 64 can be increased, so that the present invention is programmable. The erase efficiency of the erased single polysilicon layer non-volatile memory will be effectively improved. In addition, the second advantage is that the two second p-type regions (p2) can improve the side breakdown effect between the double diffused drain (DDD) doped region 64 and the N-type well region (NW) in a high temperature environment (lateral Punch through effect); the third p-type region (p3) can improve the vertical punch through effect between the double diffused drain (DDD) doped region 64 and the deep N-type well region (DNW) in a high temperature environment. ). The third advantage is that the fourth p-type region (p4) and the P-type well region (PW) are used to isolate the N-type well region (NW), so that the N-type well region (NW) is independently biased, and thus The voltage stress between the floating gate 36 and the N-type well region (NW) is reduced.
再者，當本發明的實施例建構於第4圖與第7圖中基板結構的深N型井區(DNW)之中時，可以有多種的偏壓方法用用於抹除狀態。如第9圖所示，為其中二種偏壓方法。當第一方法運用於抹除狀態時，源極線電壓(VSL )與位元線電壓(VBL )為0V~VEE ，N型井區電壓(VNW )與字元線電壓(VWL )與深N型井區電壓(VDNW )為VEE ，抹除線電壓(VEL )P型井區電壓(VPW )為-Vee 。其中，VEE 為介於+6.5V~+20V之間的正電壓，-Vee 為介於-6.5V~-20V之間的負電壓。並且，第一方法係以Fowler-Nordhiem(FN)效應 來退出熱載子。Further, when the embodiment of the present invention is constructed in the deep N-type well region (DNW) of the substrate structure in Figs. 4 and 7, a variety of biasing methods can be used for the erased state. As shown in Figure 9, there are two methods of biasing. When the first method is applied to the erase state, the source line voltage (V SL ) and the bit line voltage (V BL ) are 0V to V EE , the N type well voltage (V NW ) and the word line voltage (V) WL ) and deep N-type well voltage (V DNW ) is V EE , erase line voltage (V EL ) P-type well voltage (V PW ) is -V ee . Among them, V EE is a positive voltage between +6.5V~+20V, and -V ee is a negative voltage between -6.5V~-20V. Also, the first method exits the hot carrier with the Fowler-Nordhiem (FN) effect.
當第二方法運用於抹除狀態時，源極線電壓(VSL )為浮接(floating)，位元線電壓(VBL )為0V，N型井區電壓(VNW )與字元線電壓(VWL )與深N型井區電壓(VDNW )為VEE ，抹除線電壓(VEL )P型井區電壓(VPW )為-Vee 。其中，VEE 為介於+6.5V~+20V之間的正電壓，-Vee 為介於-6.5V~-20V之間的負電壓。並且，第二方法係以熱電洞(Hot Hole，簡稱HH)效應來退出熱載子。而HH效應可為帶間熱電洞(band-to-band hoe hole，簡稱BBHH)效應，基板熱電洞(Substrate hoe hole，簡稱SHH)效應，以及汲極崩潰熱電洞(drain avalanche hoe hole，簡稱DAHH)效應。When the second method is applied to the erase state, the source line voltage (V SL ) is floating, the bit line voltage (V BL ) is 0V, the N-type well voltage (V NW ) and the word line The voltage (V WL ) and the deep N-type well region voltage (V DNW ) are V EE , and the erase line voltage (V EL ) P-type well region voltage (V PW ) is -V ee . Among them, V EE is a positive voltage between +6.5V~+20V, and -V ee is a negative voltage between -6.5V~-20V. Moreover, the second method exits the hot carrier with the effect of Hot Hole (HH). The HH effect may be a band-to-band hoe hole (BBHH) effect, a Substrate hoe hole (SHH) effect, and a drain avalanche hoe hole (DAHH). )effect.
由以上的說明可知，本發明的單一多晶矽層非揮發性記憶體能夠有效地降低抹除線電壓(VEL)。也就是說，本發明可以利用較低的抹除線電壓(VEL)並且改變非揮發性記憶體的儲存狀態。As apparent from the above description, the single polysilicon layer non-volatile memory of the present invention can effectively reduce the erase line voltage (VEL). That is, the present invention can utilize a lower erase line voltage (VEL) and change the storage state of the non-volatile memory.
綜上所述，雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明。本發明所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作各種之更動與潤飾。因此，本發明之保護範圍當視後附之申請專利範圍所界定者為準。In conclusion, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.
36‧‧‧浮動閘極36‧‧‧Floating gate
362‧‧‧閘極氧化層362‧‧‧ gate oxide layer
362a‧‧‧第一部份362a‧‧‧ first part
362b‧‧‧第二部份362b‧‧‧ second part
38‧‧‧n型源/汲區域38‧‧‧n type source/汲 area
39‧‧‧隔離結構39‧‧‧Isolation structure
Claims (15)
一種具可程式可抹除的單一多晶矽非揮發性記憶體，包括：一基板結構；一浮動閘極電晶體，包括一浮動閘極、一閘極氧化層位於該浮動閘極下方、以及一通道區域位於一N型井區內；以及一抹除閘區域，包括一P型井區與一n型源/汲區域，該n型源/汲區域連接至一抹除線電壓，其中該浮動閘極係向外延伸並相鄰於該抹除閘區域；其中，該P型井區與該N型井區形成於該基板結構中，該閘極氧化層包括一第一部份位於該通道區域上方，以及一第二部份位於該抹除閘區域上方，並且該閘極氧化層的該第一部份之厚度大於該閘極氧化層的該第二部份之厚度。 A single polycrystalline germanium non-volatile memory with programmable erasability, comprising: a substrate structure; a floating gate transistor comprising a floating gate, a gate oxide layer under the floating gate, and a channel The region is located in an N-type well region; and a wipe-off region includes a P-type well region and an n-type source/turn region, the n-type source/turn region is connected to a erase line voltage, wherein the floating gate system Extending outwardly and adjacent to the erase gate region; wherein the P-type well region and the N-type well region are formed in the substrate structure, the gate oxide layer including a first portion located above the channel region And a second portion is located above the erase gate region, and a thickness of the first portion of the gate oxide layer is greater than a thickness of the second portion of the gate oxide layer. 如申請專利範圍第1項所述之具可程式可抹除的單一多晶矽非揮發性記憶體，其中，該抹除閘區域更包括一第一n型區域位於該P型井區以及該n型源/汲區域之間。 The single polycrystalline germanium non-volatile memory having the programmable erasable according to claim 1, wherein the erase gate region further comprises a first n-type region located in the P-type well region and the n-type Between source/汲 areas. 如申請專利範圍第2項所述之具可程式可抹除的單一多晶矽非揮發性記憶體，其中，該第一n型區域為一雙擴散汲極摻雜區。 A single polycrystalline germanium non-volatile memory having a programmable erasable memory as described in claim 2, wherein the first n-type region is a double-diffused germanium doped region. 如申請專利範圍第2項所述之具可程式可抹除的單一多晶矽非揮發性記憶體，其中，該P型井包括：一第一p型區域，形成於該基板結構的表面下方並且接觸於該第一n型區域；多個第二p型區域；以及一第三p型區域，形成於該第一p型區域的下方；其中，該些第二p型區域圍繞住該第一p型區域與該第三p 型區域。 The single polycrystalline non-volatile memory having a programmable erasable method according to claim 2, wherein the P-type well comprises: a first p-type region formed under the surface of the substrate structure and contacting The first n-type region; the plurality of second p-type regions; and a third p-type region formed under the first p-type region; wherein the second p-type regions surround the first p-type region Type area and the third p Type area. 如申請專利範圍第4項所述之具可程式可抹除的單一多晶矽非揮發性記憶體，其中，該第二p型區域的摻雜量大於等於該第一p型區域的摻雜量；且該第三p型區域的摻雜量大於等於該第一p型區域的摻雜量。 The method of claim 4, wherein the doping amount of the second p-type region is greater than or equal to the doping amount of the first p-type region; And the doping amount of the third p-type region is greater than or equal to the doping amount of the first p-type region. 如申請專利範圍第4項所述之具可程式可抹除的單一多晶矽非揮發性記憶體，其中，該基板結構包括：一P型基板；以及一深N型井區形成於該P形基板內，其中該深N型井區接觸於該N型井區、該些第二p型區域、與該第三p型區域，並且該深N型井區連接至一深N型井區電壓。 The single polycrystalline germanium non-volatile memory with programmable erasable according to claim 4, wherein the substrate structure comprises: a P-type substrate; and a deep N-type well region is formed on the P-shaped substrate The deep N-type well region is in contact with the N-type well region, the second p-type regions, and the third p-type region, and the deep N-type well region is connected to a deep N-type well region voltage. 如申請專利範圍第4項所述之具可程式可抹除的單一多晶矽非揮發性記憶體，其中，該基板結構包括：一P型基板；一第二n型區域，形成於該P型基板內；以及一第四p型區域，形成於該第二n型區域上方，且該第四p型區域接觸於該第二n型區域；其中，該第四p型區域更接觸於該N型井區、該些第二p型區域、與該第三p型區域。 The single polycrystalline germanium non-volatile memory with programmable erasable according to claim 4, wherein the substrate structure comprises: a P-type substrate; and a second n-type region formed on the P-type substrate And a fourth p-type region formed over the second n-type region, wherein the fourth p-type region is in contact with the second n-type region; wherein the fourth p-type region is more in contact with the N-type region a well region, the second p-type regions, and the third p-type region. 如申請專利範圍第7項所述之具可程式可抹除的單一多晶矽非揮發性記憶體，其中，該第四p型區域的摻雜量大於等於該P型基板的摻雜量。 The single polycrystalline germanium non-volatile memory having a programmable erasable method according to claim 7, wherein the doping amount of the fourth p-type region is greater than or equal to the doping amount of the P-type substrate. 如申請專利範圍第7項所述之具可程式可抹除的單一多晶矽非揮發性記憶體，其中，該第四p型區域的摻雜量大於等於 該第三p型區域的摻雜量，且該第四p型區域的摻雜量小於等於該第二p型區域的摻雜量。 A single polycrystalline germanium non-volatile memory with programmable erasability as described in claim 7 wherein the doping amount of the fourth p-type region is greater than or equal to a doping amount of the third p-type region, and a doping amount of the fourth p-type region is less than or equal to a doping amount of the second p-type region. 如申請專利範圍第1項所述之具可程式可抹除的單一多晶矽非揮發性記憶體，其中，該P型井區包括：一第一p型區域，形成於該基板結構的表面下方並且接觸於該n型源/汲區域；多個第二p型區域；以及一第三p型區域，形成於該第一p型區域的下方；其中，該些第二p型區域圍繞住該第一p型區域與該第三p型區域。 The single polycrystalline germanium non-volatile memory of the programmable erasable method according to claim 1, wherein the P-type well region comprises: a first p-type region formed under the surface of the substrate structure and Contacting the n-type source/german region; a plurality of second p-type regions; and a third p-type region formed under the first p-type region; wherein the second p-type regions surround the first A p-type region and the third p-type region. 如申請專利範圍第10項所述之具可程式可抹除的單一多晶矽非揮發性記憶體，其中，該第二p型區域的摻雜量大於等於該第一p型區域的摻雜量；且該第三p型區域的摻雜量大於等於該第一p型區域的摻雜量。 The single polycrystalline germanium non-volatile memory having the programmable erasable according to claim 10, wherein the doping amount of the second p-type region is greater than or equal to the doping amount of the first p-type region; And the doping amount of the third p-type region is greater than or equal to the doping amount of the first p-type region. 如申請專利範圍第10項所述之具可程式可抹除的單一多晶矽非揮發性記憶體，其中，該基板結構包括：一P型基板；以及一深N型井區形成於該P形基板內，其中該深N型井區接觸於該N型井區、該些第二p型區域、與該第三p型區域。 The single polycrystalline germanium non-volatile memory with programmable erasable according to claim 10, wherein the substrate structure comprises: a P-type substrate; and a deep N-type well region is formed on the P-shaped substrate The deep N-type well region is in contact with the N-type well region, the second p-type regions, and the third p-type region. 如申請專利範圍第10項所述之具可程式可抹除的單一多晶矽非揮發性記憶體，其中，該基板結構包括：一P型基板；一第二n型區域，形成於該P型基板內；以及一第四p型區域，形成於該第二n型區域上方，且該第四p型區域接觸於該第二n型區域； 其中，該第四p型區域更接觸於該N型井區、該些第二p型區域、與該第三p型區域。 The single polycrystalline germanium non-volatile memory with programmable erasable according to claim 10, wherein the substrate structure comprises: a P-type substrate; and a second n-type region formed on the P-type substrate And a fourth p-type region formed over the second n-type region, and the fourth p-type region is in contact with the second n-type region; The fourth p-type region is further in contact with the N-type well region, the second p-type regions, and the third p-type region. 如申請專利範圍第13項所述之具可程式可抹除的單一多晶矽非揮發性記憶體，其中，該第四p型區域的摻雜量大於等於該P型基板的摻雜量。 The programmable polymorphizable non-volatile memory according to claim 13 , wherein the fourth p-type region has a doping amount greater than or equal to a doping amount of the P-type substrate. 如申請專利範圍第13項所述之具可程式可抹除的單一多晶矽非揮發性記憶體，其中，該第四p型區域的摻雜量大於等於該第三p型區域的摻雜量，且該第四p型區域的摻雜量小於等於該第二p型區域的摻雜量。The single polycrystalline germanium non-volatile memory having the programmable erasable according to claim 13 , wherein the doping amount of the fourth p-type region is greater than or equal to the doping amount of the third p-type region, And the doping amount of the fourth p-type region is less than or equal to the doping amount of the second p-type region.
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| US11282844B2 (en) * | 2018-06-27 | 2022-03-22 | Ememory Technology Inc. | Erasable programmable non-volatile memory including two floating gate transistors with the same floating gate |
| CN111276485A (en) * | 2020-02-14 | 2020-06-12 | 上海华虹宏力半导体制造有限公司 | MTP device manufacturing method and MTP device |
| US11980029B2 (en) * | 2021-11-15 | 2024-05-07 | Ememory Technology Inc. | Erasable programmable single-ploy non-volatile memory cell and associated array structure |
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