TWI581105B - Integrated circuit and control method thereof - Google Patents

積體電路及其控制方法Integrated circuit and control method thereof

本發明係有關於積體電路，特別是有關於可控制複數從屬元件之積體電路。The present invention relates to integrated circuits, and more particularly to integrated circuits that control a plurality of dependent elements.

內部積體電路(Inter Integrated Circuit，I2C)匯流排是飛利浦(PHILIPS)公司所開發的串列式傳輸匯流排標準，用來作為積體電路之間的一種溝通協定，例如微控制器及其週邊元件。一般而言，位於內部積體電路匯流排上的主控(Master)元件會先發出接收端專屬的從屬元件位址，用以表示主控元件欲與哪一個從屬(Slave)元件進行溝通。接著，主控元件才會送出資料，此時只有該從屬元件會接收資料。因此，主控元件可對每個從屬元件進行查詢及控制。然而，當從屬元件的數量增加時，主控元件需要使用更多的時間來對每一從屬元件進行控制。The Inter Integrated Circuit (I2C) bus is a tandem transmission bus standard developed by Philips (PHILIPS) to serve as a communication protocol between integrated circuits, such as microcontrollers and their peripherals. element. In general, the master component located on the internal integrated circuit bus will first issue the slave-specific slave address to indicate which slave component the master component wants to communicate with. Then, the master component will send the data, and only the slave component will receive the data. Therefore, the master component can query and control each slave component. However, as the number of slave components increases, the master component needs to use more time to control each slave component.

本發明提供一種積體電路，用以控制複數從屬元件，其中每一上述從屬元件具有一時脈輸入接腳、一資料輸入接腳以及一位址選擇接腳。上述積體電路包括：一處理單元，用以提供欲傳送至上述複數從屬元件之至少一者的一資訊；以及，一控制器，耦接於上述處理單元，用以根據內部積體電路(Inter Integrated Circuit，I2C)匯流排協定而提供上述資訊至每一上述從屬元件的上述時脈輸入接腳及上述資料輸入接腳，並根據上述資訊提供一選擇信號至上述複數從屬元件之至少該者的上述位址選擇接腳。The present invention provides an integrated circuit for controlling a plurality of slave components, wherein each of the slave components has a clock input pin, a data input pin, and an address selection pin. The integrated circuit includes: a processing unit for providing information to be transmitted to at least one of the plurality of slave components; and a controller coupled to the processing unit for performing an internal integrated circuit (Inter Integrated Circuit (I2C) bus routing protocol for providing the above information to the clock input pin of each of the slave components and the data input pin, and providing a selection signal to at least the one of the plurality of slave elements based on the information The above address selects the pin.

再者，本發明提供一種控制方法，適用於用以控制複數從屬元件之一積體電路，其中每一上述從屬元件具有一時脈輸入接腳、一資料輸入接腳以及一位址選擇接腳。上述控制方法包括：接收欲傳送至上述複數從屬元件之一或多者的一資訊；根據內部積體電路(I2C)匯流排協定，提供上述資訊至每一上述從屬元件的上述時脈輸入接腳及上述資料輸入接腳；以及，根據上述資訊，提供一選擇信號至上述複數從屬元件之該者的上述位址選擇接腳。Furthermore, the present invention provides a control method for controlling an integrated circuit of a plurality of slave components, wherein each of the slave components has a clock input pin, a data input pin, and an address selection pin. The control method includes: receiving a message to be transmitted to one or more of the plurality of slave components; providing the information to the clock input pin of each of the slave components according to an internal integrated circuit (I2C) bus protocol And the data input pin; and, according to the above information, providing a selection signal to the address selection pin of the one of the plurality of slave components.

為讓本發明之上述和其他目的、特徵、和優點能更明顯易懂，下文特舉出較佳實施例，並配合所附圖式，作詳細說明如下：The above and other objects, features and advantages of the present invention will become more <RTIgt;

實施例：Example:

第1圖係顯示使用積體電路100來提供不同聲道的應用示意圖。在第1圖中，積體電路100可作為主控(Master)元件來控制四個立體聲數位對類比轉換器(Digital to Analog Converter，DAC)110A-110D，即數位對類比轉換器110A-110D為從屬(slave)元件，以便提供7.1聲道的效果。例如，數位對類比轉換器110A-110D可分別提供前置聲道、環繞聲道、中央/低頻特效聲道以及側環繞聲道等不同聲道。在第1圖中，積體電路100可透過內部積體電路(I2C)匯流排協定與週邊從屬元件進行溝通。舉例來說，對積體電路100而言，每一數位對類比轉換器110A-110D具有各自的從屬元件位址。因此，透過串列時脈線(Serial Clock Line，SCL)信號以及串列資料位址(Serial Data Address，SDA)信號，積體電路100可傳送對應於欲控制之數位對類比轉換器的從屬元件位址，以便選址至該數位對類比轉換器，進而對該數位對類比轉換器進行控制。假設數位對類比轉換器110A-110D為相同型號的積體電路時，積體電路100仍無法同時控制數位對類比轉換器110A-110D。例如，積體電路100無法同時致能全部的數位對類比轉換器110A-110D。換句話說，雖然積體電路100可使用相同的控制指令來致能數位對類比轉換器110A-110D，然而由於數位對類比轉換器110A-110D分別具有不同的從屬元件位址，因此積體電路100仍需依序透過不同的從屬元件位址來傳送相同的致能指令至數位對類比轉換器110A-110D，以便分別對數位對類比轉換器110A-110D進行控制。Figure 1 is a schematic diagram showing the application of the integrated circuit 100 to provide different channels. In Fig. 1, the integrated circuit 100 can be used as a master component to control four stereo to analog converters (DACs) 110A-110D, that is, digital to analog converters 110A-110D. Slave components to provide a 7.1 channel effect. For example, the digital-to-analog converters 110A-110D can provide different channels such as a front channel, a surround channel, a center/low frequency effect channel, and a side surround channel, respectively. In Fig. 1, the integrated circuit 100 can communicate with peripheral slave components through an internal integrated circuit (I2C) bus bar protocol. For example, for integrated circuit 100, each digit has analogy address converters 110A-110D having respective slave component addresses. Therefore, the integrated circuit 100 can transmit the slave component corresponding to the digital-to-analog converter to be controlled through the serial clock line (SCL) signal and the serial data address (SDA) signal. The address is addressed to the digital pair analog converter, which in turn controls the digital to analog converter. Assuming that the digital-to-analog converters 110A-110D are integrated circuits of the same type, the integrated circuit 100 cannot simultaneously control the digital-to-analog converters 110A-110D. For example, integrated circuit 100 cannot simultaneously enable all digital to analog converters 110A-110D. In other words, although the integrated circuit 100 can use the same control commands to enable the digital-to-analog converters 110A-110D, the integrated circuits are different because the digital-to-analog converters 110A-110D have different slave address addresses, respectively. 100 still needs to sequentially transmit the same enable command to the digital-to-analog converters 110A-110D through different slave component addresses to control the digital-to-analog converters 110A-110D, respectively.

第2圖係顯示使用另一積體電路200來提供不同聲道的應用示意圖。在第2圖中，數位對類比轉換器210A-210D為特定元件，其可具有不同的從屬元件位址並可透過元件位址選擇接腳SADDR來進行設定。舉例來說，假如數位對類比轉換器的元件位址選擇接腳SADDR被設定為邏輯位準“0”時，則可設定該數位對類比轉換器的從屬元件位址為ADD0。反之，假如數位對類比轉換器的元件位址選擇接腳SADDR被設定為邏輯位準“1”時，則可設定該數位對類比轉換器的從屬元件位址為ADD1。如第2圖所顯示，積體電路200包括處理單元220、解碼器230以及兩內部積體電路介面單元240與250。內部積體電路介面單元240會提供串列資料信號SDA0以及串列時脈信號SCL0至數位對類比轉換器210A與210B的資料輸入接腳SDIN以及時脈輸入接腳SCLK，而內部積體電路介面單元250會提供串列資料信號SDA1以及串列時脈信號SCL1至數位對類比轉換器210C與210D的資料輸入接腳SDIN以及時脈輸入接腳SCLK。此外，由於數位對類比轉換器210A與210C的元件位址選擇接腳SADDR被設定為邏輯位準“0”且數位對類比轉換器210B與210D的元件位址選擇接腳SADDR被設定為邏輯位準“1”，所以數位對類比轉換器210A與210C的從屬元件位址為ADD0，而數位對類比轉換器210B與210D的從屬元件位址為ADD1。因此，在積體電路200中，透過解碼器230、內部積體電路介面單元240與內部積體電路介面單元250，處理單元220可同時對數位對類比轉換器210A與210C兩者或是數位對類比轉換器210B與210D兩者進行控制。此外，處理單元220亦可分別對每一數位對類比轉換器210A-210D進行控制。值得注意的是，在第2圖中，積體電路200仍然無法同時對全部的數位對類比轉換器210A-210D進行控制。Figure 2 is a schematic diagram showing the application of using another integrated circuit 200 to provide different channels. In FIG. 2, the digital-to-analog converters 210A-210D are specific components that can have different slave component addresses and can be set by the component address selection pin SADDR. For example, if the digital address selection pin SADDR of the analog converter is set to logic level "0", the slave device address of the digital to analog converter can be set to ADD0. On the other hand, if the digital address selection pin SADDR of the analog converter is set to the logic level "1", the subordinate element address of the digital to analog converter can be set to ADD1. As shown in FIG. 2, the integrated circuit 200 includes a processing unit 220, a decoder 230, and two internal integrated circuit interface units 240 and 250. The internal integrated circuit interface unit 240 provides the serial data signal SDA0 and the serial clock signal SCL0 to the data input pin SDIN and the clock input pin SCLK of the analog converters 210A and 210B, and the internal integrated circuit interface The unit 250 provides the serial data signal SDA1 and the serial clock signal SCL1 to the data input pin SDIN and the clock input pin SCLK of the analog to analog converters 210C and 210D. In addition, since the component address selection pins SADDR of the digital pair analog converters 210A and 210C are set to logic level "0" and the component address selection pins SADDR of the digital pair analog converters 210B and 210D are set to logic bits. The quasi "1", so the slave component address of the digit pair analog converters 210A and 210C is ADD0, and the slave component address of the digit pair analog converters 210B and 210D is ADD1. Therefore, in the integrated circuit 200, through the decoder 230, the internal integrated circuit interface unit 240 and the internal integrated circuit interface unit 250, the processing unit 220 can simultaneously pair the digital-to-analog converters 210A and 210C or a digital pair. Both analog converters 210B and 210D are controlled. In addition, the processing unit 220 can also control the analog converters 210A-210D for each digit. It should be noted that in FIG. 2, the integrated circuit 200 still cannot control all of the digital-to-analog converters 210A-210D at the same time.

第3圖係顯示根據本發明一實施例所述之積體電路300的應用示意圖，其可藉由控制複數個從屬元件來提供不同聲道。如先前所描述，積體電路300可作為主控元件來控制四個立體聲數位對類比轉換器310A-310D，以分別提供前置聲道、環繞聲道、中央/低頻特效聲道以及側環繞聲道等不同聲道來達到7.1聲道的效果。在第3圖中，積體電路300包括處理單元320以及控制器360，其中控制器360包括解碼器330、介面單元340以及選擇單元350。介面單元340可透過接腳PIN1提供串列資料信號SDA至每一數位對類比轉換器310A-310D的資料輸入接腳SDIN，並可透過接腳PIN2提供串列時脈信號SCL至每一數位對類比轉換器310A-310D的資料輸入接腳SCLK。此外，選擇單元可透過接腳PIN3_0、PIN3_1、PIN3_2與PIN3_3分別提供選擇信號SEL0、SEL1、SEL2與SEL3至數位對類比轉換器310A、310B、310C與310D的元件位址選擇接腳SADDR。3 is a schematic diagram showing the application of the integrated circuit 300 according to an embodiment of the present invention, which can provide different channels by controlling a plurality of slave elements. As previously described, the integrated circuit 300 can act as a master to control four stereo digital-to-analog converters 310A-310D to provide front, surround, center/low frequency effects, and side surround sound, respectively. Different channels such as the channel to achieve 7.1 channel effect. In FIG. 3, the integrated circuit 300 includes a processing unit 320 and a controller 360, wherein the controller 360 includes a decoder 330, an interface unit 340, and a selection unit 350. The interface unit 340 can provide the serial data signal SDA to the data input pin SDIN of each digit pair analog converter 310A-310D through the pin PIN1, and can provide the serial clock signal SCL to each digit pair through the pin PIN2. The data input pin SCLK of the analog converter 310A-310D. In addition, the selection unit can provide the component address selection pins SADDR of the selection signals SEL0, SEL1, SEL2 and SEL3 to the digital pair analog converters 310A, 310B, 310C and 310D via pins PIN3_0, PIN3_1, PIN3_2 and PIN3_3, respectively.

在第3圖中，處理單元320會提供欲傳送至數位對類比轉換器310A-310D之至少一者的資訊INFO至解碼器330。接著，解碼器330會對來自處理單元320的資訊INFO進行解碼，以得到資訊INFO的識別碼ID，其中識別碼ID指示資訊INFO欲被傳送至數位對類比轉換器310A-310D的何者。接著，介面單元340透過解碼器330接收到資訊INFO，並根據內部積體電路匯流排協定來產生對應於資訊INFO的串列資料信號SDA及串列時脈信號SCL。接著，介面單元340會經由接腳PIN1與接腳PIN2分別提供串列資料信號SDA及串列時脈信號SCL至數位對類比轉換器310A-310D。同時地，選擇單元350會根據所接收的識別碼ID來提供適當的選擇信號至數位對類比轉換器310A-310D。舉例來說，當識別碼ID指示資訊INFO係欲被傳送至數位對類比轉換器310A時，則選擇單元350會提供具有第一邏輯位準的選擇信號SEL0至數位對類比轉換器310A，並提供具有第二邏輯位準的選擇信號SEL1、SEL2與SEL3至數位對類比轉換器310B-310D，以便通知數位對類比轉換器310A來接收串列時脈信號SCL以及串列資料信號SDA。值得注意的是，選擇信號SEL0-SEL3的邏輯位準可根據數位對類比轉換器310A-310D的規格而決定。舉另一例子來說，當識別碼ID指示資訊INFO係欲被傳送至數位對類比轉換器310A以及310B時，則選擇單元350會提供具有第一邏輯位準的選擇信號SEL0以及選擇信號SEL1至數位對類比轉換器310A以及310B，並提供具有第二邏輯位準的選擇信號SEL2與SEL3至數位對類比轉換器310C-310D，以便通知數位對類比轉換器310A以及310B來接收串列時脈信號SCL以及串列資料信號SDA。在一實施例中，第一邏輯位準的選擇信號與第二邏輯位準的選擇信號可為邏輯互補信號。In FIG. 3, processing unit 320 provides information INFO to decoder 330 to be transmitted to at least one of digital to analog converters 310A-310D. Next, the decoder 330 decodes the information INFO from the processing unit 320 to obtain the identification code ID of the information INFO, wherein the identification code ID indicates which of the digital pair analog converters 310A-310D the information INFO is to be transmitted. Next, the interface unit 340 receives the information INFO through the decoder 330, and generates the serial data signal SDA and the serial clock signal SCL corresponding to the information INFO according to the internal integrated circuit bus protocol. Next, the interface unit 340 provides the serial data signal SDA and the serial clock signal SCL to the digital pair analog converters 310A-310D via the pin PIN1 and the pin PIN2, respectively. Simultaneously, selection unit 350 provides an appropriate selection signal to digital pair analog converters 310A-310D based on the received identification code ID. For example, when the identification code ID indication information INFO is to be transmitted to the digital-to-analog converter 310A, the selection unit 350 provides a selection signal SEL0 having a first logic level to the digital-to-analog converter 310A, and provides The selection signals SEL1, SEL2 and SEL3 having the second logic level are coupled to the digital to analog converters 310B-310D to notify the digital pair analog converter 310A to receive the serial clock signal SCL and the serial data signal SDA. It is worth noting that the logic level of the select signals SEL0-SEL3 can be determined according to the specifications of the digital to analog converters 310A-310D. For another example, when the identification code ID indication information INFO is to be transmitted to the digital pair analog converters 310A and 310B, the selection unit 350 provides the selection signal SEL0 having the first logic level and the selection signal SEL1 to Digital to analog converters 310A and 310B, and providing select signals SEL2 and SEL3 having second logic levels to digital to analog converters 310C-310D to notify digital to analog converters 310A and 310B to receive serial clock signals SCL and serial data signal SDA. In an embodiment, the selection signal of the first logic level and the selection signal of the second logic level may be logical complementary signals.

此外，對積體電路300而言，數位對類比轉換器310A-310D具有相同的從屬元件位址。因此，根據本發明之實施例，積體電路300可同時對數位對類比轉換器310A-310D進行控制。例如，當積體電路300欲同時對數位對類比轉換器310A-310D進行控制時，處理單元320會提供欲同時傳送至數位對類比轉換器310A-310D的資訊INFO至解碼器330。接著，解碼器330會對來自處理單元320的資訊INFO進行解碼，並得到資訊INFO的識別碼ID，其中識別碼ID會指示資訊INFO欲被傳送至全部的數位對類比轉換器310A-310D。接著，介面單元340會根據內部積體電路匯流排協定來產生對應於資訊INFO的串列資料信號SDA及串列時脈信號SCL並傳送至數位對類比轉換器310A-310D。同時地，選擇單元350會分別提供具有第一邏輯位準的選擇信號SEL0、SEL1、SEL2與SEL3至數位對類比轉換器310A-310D，以便通知全部的數位對類比轉換器310A-310D來接收串列時脈信號SCL以及串列資料信號SDA，並執行後續程序。在一實施例中，上述資訊INFO係以一對照表(lookup table)的形式存放在一暫存器中，以供解碼器使用。在一實施例中，上述複數數位對類比轉換器310A-310D具有相同的從屬元件位址時，則上述串列資料信號包含上述數位對類比轉換器310A-310D的位址。Moreover, for integrated circuit 300, digital to analog converters 310A-310D have the same slave component address. Thus, in accordance with an embodiment of the present invention, integrated circuit 300 can simultaneously control digital to analog converters 310A-310D. For example, when integrated circuit 300 is to simultaneously control digital to analog converters 310A-310D, processing unit 320 provides information INFO to decoder 330 that is to be simultaneously transmitted to digital pair analog converters 310A-310D. Next, the decoder 330 decodes the information INFO from the processing unit 320 and obtains the identification code ID of the information INFO, wherein the identification code ID indicates that the information INFO is to be transmitted to all of the digital pair analog converters 310A-310D. Next, the interface unit 340 generates a serial data signal SDA and a serial clock signal SCL corresponding to the information INFO according to the internal integrated circuit bus protocol and transmits the digital data to the analog converters 310A-310D. Simultaneously, selection unit 350 provides selection signals SEL0, SEL1, SEL2, and SEL3 having first logic levels to digital to analog converters 310A-310D, respectively, to notify all digits to analog converters 310A-310D to receive strings. The clock signal SCL and the serial data signal SDA are listed, and subsequent procedures are performed. In one embodiment, the information INFO is stored in a register in the form of a lookup table for use by the decoder. In one embodiment, when the complex digits have the same slave component address for the analog converters 310A-310D, then the serial data signal includes the address of the digital to analog converter 310A-310D.

再者，積體電路300亦可透過控制器360提供符合串列週邊介面(Serial Peripheral Interface，SPI)匯流排協定的信號至週邊的從屬元件。舉例來說，當積體電路300與從屬元件以串列週邊介面匯流排協定進行溝通時，介面單元340會透過解碼器330接收到來自處理單元320的資訊INFO，並根據串列週邊介面匯流排協定來產生對應於資訊INFO的串列資料信號SDA及串列時脈信號SCL。同時地，選擇單元350會根據所接收的識別碼ID來提供適當的選擇信號至數位對類比轉換器310A-310D，其中選擇信號SEL0-SEL3可視為數位對類比轉換器310A-310D的晶片選擇(Chip Select，CS)信號。因此，若數位對類比轉換器310A-310D同時支援串列週邊介面(serial peripheral interface，SPI)匯流排協定時，則積體電路300可根據數位對類比轉換器310A-310D所選定之匯流排協定對數位對類比轉換器310A-310D進行控制，而無須進一步變動印刷電路板上的相關設計與應用。Furthermore, the integrated circuit 300 can also provide a signal conforming to the Serial Peripheral Interface (SPI) bus bar protocol to the peripheral slave components through the controller 360. For example, when the integrated circuit 300 communicates with the slave component in a serial peripheral interface bus protocol, the interface unit 340 receives the information INFO from the processing unit 320 through the decoder 330, and according to the serial interface bus. The protocol generates a serial data signal SDA and a serial clock signal SCL corresponding to the information INFO. Simultaneously, selection unit 350 provides an appropriate selection signal to digital pair analog converters 310A-310D based on the received identification code ID, wherein selection signals SEL0-SEL3 can be considered as wafer selection for digital to analog converters 310A-310D ( Chip Select, CS) signal. Therefore, if the digital pair analog converters 310A-310D simultaneously support a serial peripheral interface (SPI) bus protocol, the integrated circuit 300 can select the bus protocol according to the digital pair analog converters 310A-310D. The digital to analog converters 310A-310D are controlled without further variation in the associated design and application on the printed circuit board.

第4圖係顯示根據本發明一實施例所述之適用於一積體電路的控制方法，其中積體電路可控制複數個從屬元件，且每一從屬元件具有一時脈輸入接腳、一資料輸入接腳以及一位址選擇接腳。首先，接收欲傳送至複數從屬元件之一或多者的一資訊(步驟S402)。接著，根據內部積體電路匯流排協定，分別提供對應於上述資訊的串列時脈信號以及串列資料信號至每一從屬元件的串列時脈輸入接腳及串列資料輸入接腳(步驟S404)。接著，對欲傳送之上述資訊進行解碼，並得到一識別碼，其中識別碼係對應於複數從屬元件之該者(即識別碼指示上述資訊欲被傳送至複數從屬元件的何者)(步驟S406)。接著，根據上述識別碼，提供適當的選擇信號至複數從屬元件之該者，以便通知複數從屬元件之該者來接收串列時脈信號以及串列資料信號，並進行後續操作(步驟S408)。值得注意的是，對積體電路而言，每一從屬元件具有相同的從屬元件位址。4 is a diagram showing a control method suitable for an integrated circuit according to an embodiment of the invention, wherein the integrated circuit can control a plurality of slave components, and each slave component has a clock input pin and a data input. Pin and address selection pin. First, a piece of information to be transmitted to one or more of the plurality of dependent elements is received (step S402). Then, according to the internal integrated circuit bus arrangement, respectively, the serial clock signal corresponding to the above information and the serial data signal are respectively supplied to the serial clock input pin and the serial data input pin of each slave component (steps) S404). Then, the above information to be transmitted is decoded, and an identification code is obtained, wherein the identification code corresponds to the one of the plurality of dependent elements (ie, the identification code indicates which of the plurality of dependent elements is to be transmitted to the plurality of dependent elements) (step S406) . Then, according to the identification code, an appropriate selection signal is provided to the one of the plurality of dependent elements to notify the person of the plurality of dependent elements to receive the serial clock signal and the serial data signal, and perform subsequent operations (step S408). It is worth noting that for an integrated circuit, each slave component has the same slave component address.

在一實施例中，若積體電路與週邊從屬元件為單向傳輸，或是從屬元件在接收到來自積體電路的訊息之後，不需進一步傳送回應信號(Acknowledge，ACK)或是不回應信號(Negative-Acknowledge，NAK)給積體電路，則根據本發明實施例所述之積體電路可更快速地對從屬元件進行控制。In an embodiment, if the integrated circuit and the peripheral slave component are unidirectionally transmitted, or the slave component receives the message from the integrated circuit, no further response signal (Acknowledge, ACK) or no response signal is needed. (Negative-Acknowledge, NAK) The integrated circuit according to the embodiment of the present invention can control the slave components more quickly.

雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

100、200、300．．．積體電路100, 200, 300. . . Integrated circuit

110A-110D、210A-210D、310A-310D．．．數位對類比轉換器110A-110D, 210A-210D, 310A-310D. . . Digital to analog converter

220、320．．．處理單元220, 320. . . Processing unit

230、330．．．解碼器230, 330. . . decoder

240、250．．．內部積體電路介面單元240, 250. . . Internal integrated circuit interface unit

340．．．介面單元340. . . Interface unit

350．．．選擇單元350. . . Selection unit

360．．．控制器360. . . Controller

ID．．．識別碼ID. . . Identifier

INFO．．．資訊INFO. . . News

PIN1、PIN2、PIN3_0、PIN3_1、PIN3_2、PIN3_3．．．接腳PIN1, PIN2, PIN3_0, PIN3_1, PIN3_2, PIN3_3. . . Pin

SCL、SCL0、SCL1．．．串列時脈信號SCL, SCL0, SCL1. . . Serial clock signal

SDA、SDA0、SDA1．．．串列資料信號SDA, SDA0, SDA1. . . Serial data signal

以及as well as

SEL0-SEL3．．．選擇信號SEL0-SEL3. . . Selection signal

第1圖係顯示使用積體電路來提供不同聲道的應用示意圖；Figure 1 is a schematic diagram showing the application of using integrated circuits to provide different channels;

第2圖係顯示使用另一積體電路來提供不同聲道的應用示意圖；Figure 2 is a schematic diagram showing the application of using another integrated circuit to provide different channels;

第3圖係顯示根據本發明一實施例所述之積體電路的應用示意圖，其可藉由控制複數個從屬元件來提供不同聲道；以及3 is a schematic diagram showing the application of an integrated circuit according to an embodiment of the present invention, which can provide different channels by controlling a plurality of slave components;

第4圖係顯示根據本發明一實施例所述之適用於一積體電路的控制方法。Figure 4 is a diagram showing a control method suitable for an integrated circuit according to an embodiment of the present invention.

300．．．積體電路300. . . Integrated circuit

310A-310D．．．數位對類比轉換器310A-310D. . . Digital to analog converter

320．．．處理單元320. . . Processing unit

330．．．解碼器330. . . decoder

340．．．介面單元340. . . Interface unit

350．．．選擇單元350. . . Selection unit

360．．．控制器360. . . Controller

ID．．．識別碼ID. . . Identifier

INFO．．．資訊INFO. . . News

PIN1、PIN2、PIN3_0、PIN3_1、PIN3_2、PIN3_3．．．接腳PIN1, PIN2, PIN3_0, PIN3_1, PIN3_2, PIN3_3. . . Pin

SCL．．．串列時脈信號SCL. . . Serial clock signal

SDA．．．串列資料信號SDA. . . Serial data signal

SEL0-SEL3．．．選擇信號SEL0-SEL3. . . Selection signal