TWI644417B - Flash memories and methods for manufacturing the same - Google Patents

快閃記憶體的製造方法包含在半導體基底上形成第一導電層，在第一導電層上形成圖案化遮罩層，其中圖案化遮罩層之開口暴露出第一導電層，在圖案化遮罩層上形成第二導電層，其中第二導電層延伸進入開口，對第二導電層實施第一蝕刻製程，以在開口之側壁上形成間隙物，實施氧化製程以在開口內形成氧化物結構，以氧化物結構作為遮罩，實施第二蝕刻製程以形成浮置閘極，以及在半導體基底內形成源極區和汲極區。 A method of fabricating a flash memory includes forming a first conductive layer on a semiconductor substrate, and forming a patterned mask layer on the first conductive layer, wherein the opening of the patterned mask layer exposes the first conductive layer, and the patterned conductive layer Forming a second conductive layer on the cover layer, wherein the second conductive layer extends into the opening, performing a first etching process on the second conductive layer to form a spacer on the sidewall of the opening, and performing an oxidation process to form an oxide structure in the opening The oxide structure is used as a mask, a second etching process is performed to form a floating gate, and a source region and a drain region are formed in the semiconductor substrate.

快閃記憶體及其製造方法 Flash memory and manufacturing method thereof

本發明是關於快閃記憶體，特別是關於具有尖端之浮置閘極的嵌入式快閃記憶體及其製造方法。 The present invention relates to flash memory, and more particularly to an embedded flash memory having a tipped floating gate and a method of fabricating the same.

快閃記憶體為非揮發性的記憶體的一種型態。一般而言，一個快閃記憶體包含兩個閘極，第一個閘極為儲存資料的浮置閘極(floating gate)，而第二個閘極為進行資料的輸入和輸出的控制閘極(control gate)。浮置閘極係位於控制閘極之下方且為「漂浮」的狀態。所謂漂浮係指以絕緣材料環繞且隔離浮置閘極以防止電荷流失。控制閘極係連接至字元線(word line，WL)以控制裝置。快閃記憶體的優點之一為可以區塊-區塊抹除資料(block-by-block erasing)。快閃記憶體廣泛地用於企業伺服器、儲存和網路科技，以及廣泛的消費電子產品，例如隨身碟(USB)快閃驅動裝置、行動電話、數位相機、平板電腦、筆記型電腦的個人電腦插卡(PC cards)和嵌入式控制器等等。 Flash memory is a type of non-volatile memory. In general, a flash memory contains two gates, the first gate is the floating gate that stores the data, and the second gate is the control gate for the input and output of the data. Gate). The floating gate is located below the control gate and is "floating". By floating is meant surrounding the insulating material and isolating the floating gate to prevent charge loss. The control gate is connected to a word line (WL) to control the device. One of the advantages of flash memory is block-by-block erasing. Flash memory is widely used in enterprise server, storage and networking technologies, as well as a wide range of consumer electronics such as flash drives (USB) flash drives, mobile phones, digital cameras, tablets, laptops PC cards and embedded controllers, etc.

市場上可得到許多不同種類的非揮發性記憶體，例如快閃記憶體、電子抹除式可複寫唯讀記憶體(electrically erasable programmable read-only memory，EEPROM)和多次寫 入(multi-time programmable，MTP)非揮發性記憶體。然而，嵌入式(embedded)快閃記憶體，特別是嵌入式分離閘極(split-gate)快閃記憶體，相較於其他的非揮發性記憶體的技術具有較大的優勢。 Many different types of non-volatile memory are available on the market, such as flash memory, electrically erasable programmable read-only memory (EEPROM), and multiple writes. Multi-time programmable (MTP) non-volatile memory. However, embedded flash memory, especially embedded split-gate flash memory, has significant advantages over other non-volatile memory technologies.

雖然現存的快閃記憶體及其製造方法已足夠應付它們原先預定的用途，但它們仍未在各個方面皆徹底的符合要求，因此快閃記憶體的技術目前仍有需克服的問題。 Although the existing flash memory and its manufacturing method are sufficient for their intended use, they have not been fully met in all respects, so the flash memory technology still has problems to overcome.

本發明提供了快閃記憶體的實施例及其製造方法的實施例，特別是嵌入式分離閘極快閃記憶體。在本發明的一些實施例中，在開口的側壁上形成間隙物。然後，在實施氧化製程的期間，將間隙物的一部分氧化以在開口內形成氧化物結構。在實施氧化製程之後，間隙物的剩餘部分具有朝向其上方之氧化物結構的凹面，以及在接續的蝕刻製程之後，形成具有垂直尖端之完整的浮置閘極。 The present invention provides embodiments of flash memory embodiments and methods of fabricating the same, particularly embedded split gate flash memory. In some embodiments of the invention, a spacer is formed on the sidewall of the opening. Then, during the oxidation process, a portion of the spacer is oxidized to form an oxide structure within the opening. After the oxidation process is performed, the remaining portion of the spacer has a concave surface toward the oxide structure thereabove, and after the subsequent etching process, a complete floating gate having a vertical tip is formed.

在前述之方法中，間隙物係用以形成浮置閘極的尖端，且裝置的抹除(erase)效率係取決於尖端的尖銳程度。因此，在確保尖端具有足夠之尖銳程度的前提下，間隙物的存在可縮短氧化製程的實施期間，使得位於氧化物結構下之浮置閘極的厚度不會太薄。結果，藉由前述方法形成之具有尖端之浮置閘極的快閃記憶體可產生例如改善裝置的抹除效率、增加裝置的整體效能和易於任何快閃記憶體之製程中製造的優勢。 In the foregoing method, the interstitial is used to form the tip of the floating gate, and the erase efficiency of the device depends on the sharpness of the tip. Therefore, under the premise of ensuring that the tip has sufficient sharpness, the presence of the spacer can shorten the implementation period of the oxidation process so that the thickness of the floating gate under the oxide structure is not too thin. As a result, the flash memory having the tipped floating gate formed by the foregoing method can produce, for example, an improvement in the erasing efficiency of the device, an increase in the overall performance of the device, and an advantage in manufacturing in any process of flash memory.

此外，在本發明的一些實施例中，在形成完整的浮置閘極之前，氧化物結構已先形成，故在形成漂浮閘極的蝕 刻製程期間，氧化物結構可作為遮罩使用，因此，無需使用額外的遮罩以產生尖端，且可降低製程成本。 Moreover, in some embodiments of the invention, the oxide structure is formed prior to forming a complete floating gate, so that the etch is formed in the floating gate The oxide structure can be used as a mask during the engraving process, so that no additional mask is needed to create the tip and the process cost can be reduced.

根據一些實施例，提供快閃記憶體的製造方法。方法包含在半導體基底上形成第一導電層，且在第一導電層上形成圖案化遮罩層，其中圖案化遮罩層之開口暴露出第一導電層。方法也包含在圖案化遮罩層上形成第二導電層，其中第二導電層延伸進入開口。方法更包含對第二導電層實施第一蝕刻製程，以在開口之側壁上形成間隙物，以及實施氧化製程以在開口內形成氧化物結構。此外，方法包含以氧化物結構作為遮罩，實施第二蝕刻製程以形成浮置閘極，以及在半導體基底內形成源極區和汲極區。 According to some embodiments, a method of fabricating a flash memory is provided. The method includes forming a first conductive layer on a semiconductor substrate and forming a patterned mask layer on the first conductive layer, wherein the opening of the patterned mask layer exposes the first conductive layer. The method also includes forming a second conductive layer on the patterned mask layer, wherein the second conductive layer extends into the opening. The method further includes performing a first etching process on the second conductive layer to form a spacer on the sidewall of the opening, and performing an oxidation process to form an oxide structure in the opening. Additionally, the method includes performing a second etch process to form a floating gate with an oxide structure as a mask, and forming a source region and a drain region within the semiconductor substrate.

根據一些實施例，提供快閃記憶體。快閃記憶體包含設置於半導體基底上的浮置閘極，其中浮置閘極的第一邊緣為第一尖端，且浮置閘極的第二邊緣為第二尖端。快閃記憶體也包含設置於浮置閘極上的氧化物結構，其中氧化物結構的第一突出部分係位於第一尖端的正上方，且氧化物結構的第二突出部分係位於第二尖端的正上方。快閃記憶體更包含設置於半導體基底內的源極區和汲極區，且浮置閘極係位於源極區與汲極區之間。 According to some embodiments, a flash memory is provided. The flash memory includes a floating gate disposed on the semiconductor substrate, wherein the first edge of the floating gate is a first tip and the second edge of the floating gate is a second tip. The flash memory also includes an oxide structure disposed on the floating gate, wherein the first protruding portion of the oxide structure is located directly above the first tip, and the second protruding portion of the oxide structure is located at the second tip Directly above. The flash memory further includes a source region and a drain region disposed in the semiconductor substrate, and the floating gate is located between the source region and the drain region.

以下的實施例與所附的參考圖式將提供詳細的描述。 The following examples and the accompanying reference drawings will provide a detailed description.

100‧‧‧快閃記憶體 100‧‧‧flash memory

101‧‧‧半導體基底 101‧‧‧Semiconductor substrate

103‧‧‧介電層 103‧‧‧ dielectric layer

103’‧‧‧介電結構 103'‧‧‧ dielectric structure

105‧‧‧第一導電層 105‧‧‧First conductive layer

105’‧‧‧第一導電層的剩餘部分 105’‧‧‧The remainder of the first conductive layer

107‧‧‧圖案化遮罩層 107‧‧‧ patterned mask layer

108‧‧‧開口 108‧‧‧ openings

109‧‧‧第二導電層 109‧‧‧Second conductive layer

109a‧‧‧第一間隙物 109a‧‧‧First spacer

109b‧‧‧第二間隙物 109b‧‧‧Second spacer

109a’‧‧‧第一間隙物的剩餘部分 109a’‧‧‧The remainder of the first spacer

109b’‧‧‧第二間隙物的剩餘部分 109b’‧‧‧The remainder of the second spacer

110‧‧‧凹陷 110‧‧‧ dent

111‧‧‧氧化物結構 111‧‧‧Oxide structure

111a‧‧‧第一突出部分 111a‧‧‧first highlight

111b‧‧‧第二突出部分 111b‧‧‧second highlight

113‧‧‧浮置閘極 113‧‧‧Floating gate

115‧‧‧控制閘極 115‧‧‧Control gate

117‧‧‧源極區 117‧‧‧ source area

119‧‧‧汲極區 119‧‧ ‧ bungee area

藉由以下的詳述配合所附圖式，我們能更加理解本發明實施例的觀點。值得注意的是，根據工業上的標準慣 例，一些部件(feature)可能沒有按照比例繪製。事實上，為了能清楚地討論，不同部件的尺寸可能被增加或減少。 The views of the embodiments of the present invention can be further understood by the following detailed description in conjunction with the accompanying drawings. It is worth noting that according to industry standard For example, some features may not be drawn to scale. In fact, the dimensions of the different components may be increased or decreased for clarity of discussion.

第1-8圖是根據本發明的一些實施例，顯示形成第8圖之快閃記憶體之各個中間階段的剖面示意圖。 1-8 are schematic cross-sectional views showing respective intermediate stages of forming the flash memory of Fig. 8 in accordance with some embodiments of the present invention.

以下揭露提供了很多不同的實施例或範例，用於實施所提供的半導體裝置之不同元件。各元件和其配置的具體範例描述如下，以簡化本發明實施例。當然，這些僅僅是範例，並非用以限定本發明。舉例而言，敘述中若提及第一元件形成在第二元件之上，可能包含第一和第二元件直接接觸的實施例，也可能包含額外的元件形成在第一和第二元件之間，使得它們不直接接觸的實施例。此外，本發明實施例可能在不同的範例中重複參考數字及/或字母。如此重複是為了簡明和清楚，而非用以表示所討論的不同實施例及/或形態之間的關係。 The following disclosure provides many different embodiments or examples for implementing the various components of the semiconductor device provided. Specific examples of the components and their configurations are described below to simplify embodiments of the present invention. Of course, these are merely examples and are not intended to limit the invention. For example, reference to a first element formed above a second element in the description may include embodiments in which the first and second elements are in direct contact, and may also include additional elements formed between the first and second elements. Embodiments that make them in direct contact. Furthermore, embodiments of the invention may repeat reference numerals and/or letters in different examples. This repetition is for the purpose of clarity and clarity, and is not intended to represent the relationship of the various embodiments and/

以下描述實施例的一些變化。在不同圖式和說明的實施例中，相似的參考數字被用來標明相似的元件。可以理解的是，在方法的前、中、後可以提供額外的操作，且一些敘述的操作可為了該方法的其他實施例被取代或刪除。 Some variations of the embodiments are described below. In the various figures and illustrated embodiments, like reference numerals are used to design It will be appreciated that additional operations may be provided before, during, and after the method, and that some of the recited operations may be substituted or deleted for other embodiments of the method.

第1-8圖是根據本發明的一些實施例，顯示形成第8圖之快閃記憶體100之各個中間階段的剖面示意圖。 1-8 are cross-sectional views showing various intermediate stages of forming the flash memory 100 of Fig. 8, in accordance with some embodiments of the present invention.

根據一些實施例，如第1圖所示，提供半導體基底101。一些實施例中，半導體基底101可由矽或其他半導體材料製成，或者，半導體基底101可包含其他元素半導體材料，例如鍺(Ge)。一些實施例中，半導體基底101由化合物半導體 製成，例如碳化矽、氮化鎵、砷化鎵、砷化銦或磷化銦。一些實施例中，半導體基底101由合金半導體製成，例如矽鍺、碳化矽鍺、磷化砷鎵或磷化銦鎵。一些實施例中，半導體基底101包含絕緣層上覆矽(silicon-on-insulator，SOI)基底。 According to some embodiments, as shown in FIG. 1, a semiconductor substrate 101 is provided. In some embodiments, the semiconductor substrate 101 can be made of germanium or other semiconductor material, or the semiconductor substrate 101 can comprise other elemental semiconductor materials, such as germanium (Ge). In some embodiments, the semiconductor substrate 101 is composed of a compound semiconductor It is made, for example, of tantalum carbide, gallium nitride, gallium arsenide, indium arsenide or indium phosphide. In some embodiments, the semiconductor substrate 101 is made of an alloy semiconductor such as germanium, tantalum carbide, gallium arsenide or indium gallium phosphide. In some embodiments, the semiconductor substrate 101 comprises a silicon-on-insulator (SOI) substrate.

一些實施例中，半導體基底101具有第一導電類型，例如本實施例之半導體基底101為輕摻雜之P型基底，然而在其他實施例中，半導體基底101可為輕摻雜之N型基底。 In some embodiments, the semiconductor substrate 101 has a first conductivity type, for example, the semiconductor substrate 101 of the present embodiment is a lightly doped P-type substrate, while in other embodiments, the semiconductor substrate 101 can be a lightly doped N-type substrate. .

接續前述，根據一些實施例，如第2圖所示，在半導體基底101上形成介電層103。一些實施例中，介電層103可由氧化矽、氮化矽、氮氧化矽或其他合適的介電材料製成。再者，介電層103可藉由熱氧化製程、化學氣相沉積(chemical vapor deposition，CVD)製程或前述之組合以形成。 Following the foregoing, according to some embodiments, as shown in FIG. 2, a dielectric layer 103 is formed over the semiconductor substrate 101. In some embodiments, the dielectric layer 103 can be made of tantalum oxide, tantalum nitride, hafnium oxynitride, or other suitable dielectric material. Furthermore, the dielectric layer 103 can be formed by a thermal oxidation process, a chemical vapor deposition (CVD) process, or a combination thereof.

然後，在介電層103上形成第一導電層105。一些實施例中，第一導電層105可由多晶矽製成。然而，在其他實施例中，第一導電層105可由其他合適的導電材料，例如金屬材料製成。第一導電層105可藉由沉積製程以形成，例如化學氣相沉積(CVD)製程、物理氣相沉積(physical vapor deposition，PVD)製程、原子層沉積(atomic layer deposition，ALD)製程、低壓化學氣相沉積(low pressure CVD，LPCVD)製程、高密度電漿化學氣相沉積(high density plasma CVD，HDPCVD)製程、金屬有機化學氣相沉積(metal organic CVD，MOCVD)製程、電漿增強化學氣相沉積(plasma-enhanced CVD，PECVD)製程或前述之組合。 Then, a first conductive layer 105 is formed on the dielectric layer 103. In some embodiments, the first conductive layer 105 can be made of polysilicon. However, in other embodiments, the first conductive layer 105 can be made of other suitable electrically conductive materials, such as metallic materials. The first conductive layer 105 can be formed by a deposition process such as a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, and a low pressure chemistry. Low pressure CVD (LPCVD) process, high density plasma chemical vapor deposition (HDPCVD) process, metal organic CVD (MOCVD) process, plasma enhanced chemical gas A plasma-enhanced CVD (PECVD) process or a combination of the foregoing.

再參見第2圖，在形成第一導電層105之後，於 第一導電層105上形成遮罩層(未繪示)。隨後，藉由實施圖案化製程將遮罩層圖案化，以形成具有開口108於其中的圖案化遮罩層107。圖案化製程包含微影製程和蝕刻製程。微影製程包含光阻塗佈(例如旋轉塗佈)、軟烤、遮罩對準、曝光、曝光後烘烤、光阻顯影、洗滌和烘乾(例如硬烤)。蝕刻製程包含乾式蝕刻或濕式蝕刻。 Referring again to FIG. 2, after forming the first conductive layer 105, A mask layer (not shown) is formed on the first conductive layer 105. Subsequently, the mask layer is patterned by performing a patterning process to form a patterned mask layer 107 having openings 108 therein. The patterning process includes a lithography process and an etch process. The lithography process includes photoresist coating (eg, spin coating), soft baking, mask alignment, exposure, post-exposure bake, photoresist development, washing and drying (eg, hard bake). The etching process includes dry etching or wet etching.

一些實施例中，圖案化遮罩層107可由氮化物，例如氮化矽或其他合適的材料製成。值得注意的是，圖案化遮罩層107的開口108暴露出第一導電層105的一部分，且開口108的形成係用以定義出隨後將形成之浮置閘極的位置。 In some embodiments, the patterned mask layer 107 can be made of a nitride such as tantalum nitride or other suitable material. Notably, the opening 108 of the patterned mask layer 107 exposes a portion of the first conductive layer 105, and the opening 108 is formed to define the location of the floating gate that will be subsequently formed.

接著，根據一些實施例，如第3圖所示，在圖案化遮罩層107上形成第二導電層109。此外，第二導電層109延伸進入圖案化遮罩層107的開口108中。換言之，形成第二導電層109覆蓋於圖案化遮罩層107和第一導電層105由開口108所暴露之部分上。 Next, according to some embodiments, as shown in FIG. 3, a second conductive layer 109 is formed on the patterned mask layer 107. Additionally, the second conductive layer 109 extends into the opening 108 of the patterned mask layer 107. In other words, the second conductive layer 109 is formed to cover the portion of the patterned mask layer 107 and the first conductive layer 105 that is exposed by the opening 108.

一些實施例中，第一導電層105由開口108所暴露之部分係完全由第二導電層109所覆蓋，且第二導電層109在開口108之位置的正上方處具有凹陷110。更明確而言，凹陷110位於開口108的範圍內。 In some embodiments, the portion of the first conductive layer 105 that is exposed by the opening 108 is completely covered by the second conductive layer 109, and the second conductive layer 109 has the recess 110 directly above the location of the opening 108. More specifically, the recess 110 is located within the range of the opening 108.

用來形成第二導電層109的一些製程和材料相似或相同於用來形成第一導電層105的製程和材料，在此便不重複敘述。一些實施例中，第一導電層105和第二導電層109由相同的材料製成，例如多晶矽。 Some of the processes and materials used to form the second conductive layer 109 are similar or identical to the processes and materials used to form the first conductive layer 105, and are not repeated herein. In some embodiments, the first conductive layer 105 and the second conductive layer 109 are made of the same material, such as polysilicon.

如第4圖所示，對第二導電層109實施第一蝕刻 製程，以移除覆蓋於圖案化遮罩層107之上的第二導電層109。此外，填入開口108之第二導電層109的一部分也藉由第一蝕刻製程移除，留下在開口108相對之側壁上的第一間隙物109a和第二間隙物109b。換言之，第一間隙物109a和第二間隙物109b係由第二導電層109所形成。 As shown in FIG. 4, the first etching is performed on the second conductive layer 109. A process is performed to remove the second conductive layer 109 overlying the patterned mask layer 107. In addition, a portion of the second conductive layer 109 that fills the opening 108 is also removed by a first etch process, leaving a first spacer 109a and a second spacer 109b on opposite sidewalls of the opening 108. In other words, the first spacer 109a and the second spacer 109b are formed by the second conductive layer 109.

一些實施例中，第一間隙物109a和第二間隙物109b可具有與圖案化遮罩層107相同的高度。在其他實施例中，第一間隙物109a和第二間隙物109b的高度可小於圖案化遮罩層107的高度。 In some embodiments, the first spacers 109a and the second spacers 109b may have the same height as the patterned mask layer 107. In other embodiments, the height of the first spacer 109a and the second spacer 109b may be less than the height of the patterned mask layer 107.

一些實施例中，第一蝕刻製程包含乾式蝕刻製程或濕式蝕刻製程。結果，在實施第一蝕刻製程之後，第一導電層105之頂面的一部分由開口108再一次地暴露出來。此外，如第4圖所示，第一間隙物109a和第二間隙物109b具有朝向開口108之中心的凸面。 In some embodiments, the first etch process comprises a dry etch process or a wet etch process. As a result, a portion of the top surface of the first conductive layer 105 is again exposed by the opening 108 after the first etching process is performed. Further, as shown in FIG. 4, the first spacer 109a and the second spacer 109b have a convex surface toward the center of the opening 108.

根據一些實施例，如第5圖所示，實施氧化製程以在開口108內形成氧化物結構111。在實施氧化製程的期間，將第一間隙物109a的一部分、第二間隙物109b的一部分和在開口108下方之第一導電層105的一部分氧化並轉換形成氧化物結構111。結果，氧化物結構111的底面低於圖案化遮罩層107的底面，且第一間隙物的剩餘部分109a’(又稱為第一尖端)和第二間隙物的剩餘部分109b’(又稱為第二尖端)具有朝向氧化物結構111的凹面。 According to some embodiments, as shown in FIG. 5, an oxidation process is performed to form an oxide structure 111 within the opening 108. During the oxidation process, a portion of the first spacer 109a, a portion of the second spacer 109b, and a portion of the first conductive layer 105 under the opening 108 are oxidized and converted to form the oxide structure 111. As a result, the bottom surface of the oxide structure 111 is lower than the bottom surface of the patterned mask layer 107, and the remaining portion 109a' (also referred to as the first tip) of the first spacer and the remaining portion 109b' of the second spacer (also referred to as It is a second tip) having a concave surface facing the oxide structure 111.

第一間隙物的剩餘部分109a’和第二間隙物的剩餘部分109b’為浮置閘極113的尖端(如第6圖所示)。值得注 意的是，在第5圖所示的階段中，浮置閘極113仍未完全形成。 由於第一間隙物109a和第二間隙物109b能提供第一尖端109a’和第二尖端109b’的高度，可縮短氧化製程的實施期間，使得位於氧化物結構111下的第一導電層105的厚度不會太薄。 The remaining portion 109a' of the first spacer and the remaining portion 109b' of the second spacer are the tips of the floating gate 113 (as shown in Fig. 6). Worth note It is intended that the floating gate 113 is still not fully formed in the stage shown in FIG. Since the first spacer 109a and the second spacer 109b can provide the heights of the first tip 109a' and the second tip 109b', the implementation of the oxidation process can be shortened so that the first conductive layer 105 under the oxide structure 111 The thickness is not too thin.

換言之，氧化物結構111和介電層103之間可維持足夠的最短距離D，且第一尖端109a’和第二尖端109b’可具有足夠的尖銳程度。結果，可改善裝置的抹除效率。 In other words, a sufficiently shortest distance D can be maintained between the oxide structure 111 and the dielectric layer 103, and the first tip 109a' and the second tip 109b' can have sufficient sharpness. As a result, the erasing efficiency of the device can be improved.

再者，參見第5圖，氧化物結構111包含自圖案化遮罩層107的頂面突出的第一突出部分111a和第二突出部分111b。值得注意的是，第一突出部分111a位於第一尖端109a’的正上方，且第二突出部分111b位於第二尖端109b’的正上方。第一突出部分111a和第二突出部分111b位於氧化物結構111的相對兩側邊緣。 Furthermore, referring to FIG. 5, the oxide structure 111 includes a first protruding portion 111a and a second protruding portion 111b that protrude from the top surface of the patterned mask layer 107. It is to be noted that the first projecting portion 111a is located directly above the first tip end 109a' and the second projecting portion 111b is located directly above the second tip end 109b'. The first protruding portion 111a and the second protruding portion 111b are located at opposite side edges of the oxide structure 111.

明確而言，第一突出部分111a和第二突出部分111b具有圓弧的頂面。一些實施例中，第一突出部分111a和第二突出部分111b的頂面可為半圓形或半橢圓形。 Specifically, the first protruding portion 111a and the second protruding portion 111b have a top surface of a circular arc. In some embodiments, the top surfaces of the first protruding portion 111a and the second protruding portion 111b may be semi-circular or semi-elliptical.

另外，在本實施例中，氧化物結構111也可包含在第一突出部分111a與第二突出部分111b之間的平坦的頂面，且此平坦的頂面低於第一突出部分111a和第二突出部分111b的頂面。 In addition, in the present embodiment, the oxide structure 111 may also include a flat top surface between the first protruding portion 111a and the second protruding portion 111b, and the flat top surface is lower than the first protruding portion 111a and the first The top surface of the second protruding portion 111b.

接著，如第6圖所示，使用氧化物結構111做為遮罩實施第二蝕刻製程，以形成完整的浮置閘極113。一些實施例中，第二蝕刻製程可包含乾式蝕刻製程或濕式蝕刻製程。 在第二蝕刻製程之後，移除圖案化遮罩層107和第一導電層105在圖案化遮罩層107下方的部分。 Next, as shown in FIG. 6, a second etching process is performed using the oxide structure 111 as a mask to form a complete floating gate 113. In some embodiments, the second etch process can include a dry etch process or a wet etch process. After the second etch process, portions of the patterned mask layer 107 and the first conductive layer 105 under the patterned mask layer 107 are removed.

更明確而言，蝕刻移除圖案化遮罩層107和第一導電層105未被氧化物結構111所覆蓋的部分，且第一導電層的剩餘部分105’、第一尖端109a’和第二尖端109b’組成浮置閘極113。一旦結束第二蝕刻製程後，即完成浮置閘極113，且第一尖端109a’和第二尖端109b’係位於浮置閘極113的相對兩側邊緣。 More specifically, the portion of the patterned mask layer 107 and the first conductive layer 105 that is not covered by the oxide structure 111 is removed by etching, and the remaining portion 105' of the first conductive layer, the first tip 109a', and the second The tip 109b' constitutes a floating gate 113. Once the second etching process is completed, the floating gate 113 is completed, and the first tip 109a' and the second tip 109b' are located at opposite side edges of the floating gate 113.

再參見第6圖，在第二蝕刻製程之後，形成另一介電層以覆蓋浮置閘極113的側壁。在浮置閘極113之側壁上的介電層和先前形成的介電層103可結合形成介電結構103’。在本實施例中，浮置閘極113完全由介電結構103’和氧化物結構111所環繞。 Referring again to FIG. 6, after the second etching process, another dielectric layer is formed to cover the sidewalls of the floating gate 113. A dielectric layer on the sidewalls of the floating gate 113 and the previously formed dielectric layer 103 may be combined to form a dielectric structure 103'. In the present embodiment, the floating gate 113 is completely surrounded by the dielectric structure 103' and the oxide structure 111.

根據一些實施例，如第7圖所示，在介電結構103’上形成控制閘極115。一些實施例中，控制閘極115延伸至氧化物結構111上。更明確而言，控制閘極115覆蓋氧化物結構111的第一突出部分111a，且控制閘極115未覆蓋氧化物結構111的第二突出部分111b。值得注意的是，控制閘極115藉由介電結構103’和氧化物結構111與浮置閘極113隔開。 According to some embodiments, as shown in Fig. 7, a control gate 115 is formed over the dielectric structure 103'. In some embodiments, the control gate 115 extends over the oxide structure 111. More specifically, the control gate 115 covers the first protruding portion 111a of the oxide structure 111, and the control gate 115 does not cover the second protruding portion 111b of the oxide structure 111. It is noted that the control gate 115 is separated from the floating gate 113 by the dielectric structure 103' and the oxide structure 111.

一些實施例中，形成第三導電層(未繪示)覆蓋於介電結構103’和氧化物結構111之上。然後，將第三導電層圖案化以形成控制閘極115。第三導電層的圖案化製程可相似或相同於用來形成圖案化遮罩層107的製程，在此便不重複敘述。在本實施例中，控制閘極115的厚度大於浮置閘極113的厚 度，且控制閘極115的長度大於浮置閘極113的長度。 In some embodiments, a third conductive layer (not shown) is formed overlying the dielectric structure 103' and the oxide structure 111. The third conductive layer is then patterned to form a control gate 115. The patterning process of the third conductive layer may be similar or identical to the process used to form the patterned mask layer 107, and the description thereof will not be repeated here. In this embodiment, the thickness of the control gate 115 is greater than the thickness of the floating gate 113. And the length of the control gate 115 is greater than the length of the floating gate 113.

用來形成第三導電層的一些材料和製程可相似或相同於用來形成第一導電層105和第二導電層109的材料和製程，在此便不重複敘述。一些實施例中，第一導電層105、第二導電層109和第三導電層由相同的材料製成，例如多晶矽。 Some of the materials and processes used to form the third conductive layer may be similar or identical to the materials and processes used to form the first conductive layer 105 and the second conductive layer 109, and the description thereof will not be repeated. In some embodiments, the first conductive layer 105, the second conductive layer 109, and the third conductive layer are made of the same material, such as polysilicon.

接著，根據一些實施例，如第8圖所示，藉由將離子佈植於半導體基底101內以形成源極區117和汲極區119。浮置閘極113和控制閘極115位於源極區117和汲極區119之間。 Next, according to some embodiments, as shown in FIG. 8, the source region 117 and the drain region 119 are formed by implanting ions in the semiconductor substrate 101. The floating gate 113 and the control gate 115 are located between the source region 117 and the drain region 119.

在本實施例中，半導體基底101為P型基底，且源極區117和汲極區119係藉由在半導體基底101內佈植N型摻雜物以形成，例如磷(P)或砷(As)。在其他實施例中，半導體基底101為N型基底，且源極區117和汲極區119係藉由在半導體基底101內佈植P型摻雜物以形成，例如硼(B)。半導體基底101的導電類型相反於源極區117和汲極區119的導電類型。一旦形成源極區117和汲極區119之後，即完成快閃記憶體100。 In the present embodiment, the semiconductor substrate 101 is a P-type substrate, and the source region 117 and the drain region 119 are formed by implanting an N-type dopant in the semiconductor substrate 101, such as phosphorus (P) or arsenic ( As). In other embodiments, the semiconductor substrate 101 is an N-type substrate, and the source region 117 and the drain region 119 are formed by implanting a P-type dopant in the semiconductor substrate 101, such as boron (B). The conductivity type of the semiconductor substrate 101 is opposite to the conductivity type of the source region 117 and the drain region 119. Once the source region 117 and the drain region 119 are formed, the flash memory 100 is completed.

在本發明的一些實施例中，在開口的側壁上形成間隙物。然後，在實施氧化製程的期間，將間隙物的一部分氧化以在開口內形成氧化物結構。在實施氧化製程之後，間隙物的剩餘部分具有朝向其上方之氧化物結構的凹面，以及在接續的蝕刻製程之後，形成具有垂直尖端之完整的浮置閘極。 In some embodiments of the invention, a spacer is formed on the sidewall of the opening. Then, during the oxidation process, a portion of the spacer is oxidized to form an oxide structure within the opening. After the oxidation process is performed, the remaining portion of the spacer has a concave surface toward the oxide structure thereabove, and after the subsequent etching process, a complete floating gate having a vertical tip is formed.

在前述之方法中，間隙物係用以形成浮置閘極的尖端，且裝置的抹除效率係取決於尖端的尖銳程度。因此，在 確保尖端具有足夠之尖銳程度的前提下，間隙物的存在可縮短氧化製程的實施期間，使得位於氧化物結構下之浮置閘極的厚度不會太薄。結果，藉由前述方法形成之具有尖端之浮置閘極的快閃記憶體可產生例如改善裝置的抹除效率、增加裝置的整體效能和易於任何快閃記憶體之製程中製造的優勢。 In the foregoing method, the spacer is used to form the tip of the floating gate, and the erasing efficiency of the device depends on the sharpness of the tip. Thus, in Providing that the tip has sufficient sharpness, the presence of the spacer shortens the implementation of the oxidation process so that the thickness of the floating gate under the oxide structure is not too thin. As a result, the flash memory having the tipped floating gate formed by the foregoing method can produce, for example, an improvement in the erasing efficiency of the device, an increase in the overall performance of the device, and an advantage in manufacturing in any process of flash memory.

此外，在本發明的一些實施例中，在形成完整的浮置閘極之前，氧化物結構已先形成，故在形成浮置閘極的蝕刻製程期間，氧化物結構可作為遮罩使用，因此，無需使用額外的遮罩以產生尖端，且可降低製程成本。 In addition, in some embodiments of the present invention, the oxide structure is formed before the formation of the complete floating gate, so that the oxide structure can be used as a mask during the etching process for forming the floating gate. There is no need to use additional masks to create the tip and reduce process costs.

以上概述數個實施例，以便在本發明所屬技術領域中具有通常知識者可以更理解本發明實施例的觀點。在本發明所屬技術領域中具有通常知識者應該理解，他們能以本發明實施例為基礎，設計或修改其他製程和結構，以達到與在此介紹的實施例相同之目的及/或優勢。在本發明所屬技術領域中具有通常知識者也應該理解到，此類等效的製程和結構並無悖離本發明的精神與範圍，且他們能在不違背本發明之精神和範圍之下，做各式各樣的改變、取代和替換。 The embodiments are summarized above in order to provide a further understanding of the embodiments of the present invention. It is to be understood by those of ordinary skill in the art that the present invention may be practiced or modified by the embodiments of the present invention in order to achieve the same objects and/or advantages as the embodiments described herein. It is also to be understood by those skilled in the art that the present invention is not limited to the spirit and scope of the invention. Do all kinds of changes, substitutions and substitutions.