TWI656425B - Semiconductor structures for enhanced transient response in low dropout (ldo) voltage regulators - Google Patents

本發明公開用於低壓降(LDO)穩壓器中的增強型暫態響應的系統、半導體結構、電子電路和方法。舉例來說，本發明公開用於LDO穩壓器中的增強型暫態響應的半導體結構，所述半導體結構包括第一電流鏡電路，其耦合到所述LDO穩壓器的輸入連接件和輸出連接件；第二電流鏡電路，其耦合到所述LDO穩壓器的所述輸入連接件。第一放大器電路的第一輸入耦合到所述第二電流鏡電路，所述第一放大器電路的第二輸入耦合到所述LDO穩壓器的所述輸出連接件，且所述第一放大器電路的第三輸入耦合到參考電壓。第二放大器電路的輸入耦合到所述第一放大器電路的輸出，所述第二放大器電路的輸出耦合到所述第一電流鏡電路，第三放大器電路的輸入耦合到所述第一放大器電路的所述輸出，且所述第三放大器電路的輸出耦合到所述第二電流鏡電路。在一些實施方式中，所述半導體結構是形成於半導體IC、晶圓、晶片或晶粒上的電源管理積體電路(PMIC)中或電源中的自我調整偏置LDO穩壓器。 Systems, semiconductor structures, electronic circuits, and methods for enhanced transient response in low dropout (LDO) voltage regulators are disclosed. For example, the present invention discloses an enhanced transient response semiconductor structure for use in an LDO regulator, the semiconductor structure including a first current mirror circuit coupled to an input connector and an output of the LDO regulator a connector; a second current mirror circuit coupled to the input connector of the LDO regulator. a first input of the first amplifier circuit is coupled to the second current mirror circuit, a second input of the first amplifier circuit is coupled to the output connector of the LDO regulator, and the first amplifier circuit The third input is coupled to a reference voltage. An input of a second amplifier circuit coupled to an output of the first amplifier circuit, an output of the second amplifier circuit coupled to the first current mirror circuit, an input of a third amplifier circuit coupled to the first amplifier circuit The output, and an output of the third amplifier circuit is coupled to the second current mirror circuit. In some embodiments, the semiconductor structure is a self-regulating bias LDO regulator formed in a power management integrated circuit (PMIC) on a semiconductor IC, wafer, wafer or die or in a power supply.

用於低壓降穩壓器中增強型暫態響應的半導體結構 Semiconductor structure for enhanced transient response in low dropout regulators

本發明大體上涉及低壓降(LDO)穩壓器，並且具體來說涉及利用半導體積體電路、晶圓、晶片或晶粒中的增強型暫態響應的自我調整偏置LDO穩壓器。 The present invention relates generally to low dropout (LDO) voltage regulators and, in particular, to self-regulating bias LDO regulators utilizing enhanced transient response in semiconductor integrated circuits, wafers, wafers or dies.

相關申請的交叉引用 Cross-reference to related applications

本申請涉及2014年2月5日提交的標題為“用於低壓降(LDO)穩壓器中增強型暫態響應的半導體結構(SEMICONDUCTOR STRUCTURES FOR ENHANCED TRANSIENT RESPONSE IN LOW DROPOUT(LDO)VOLTAGE REGULATORS)”並以引用的方式併入本文的美國臨時專利申請序號61/936,111。本申請還涉及2014年2月28日提交的標題為“用於低壓降(LDO)穩壓器中增強型暫態響應的半導體結構(SEMICONDUCTOR STRUCTURES FOR ENHANCED TRANSIENT RESPONSE IN LOW DROPOUT(LDO)VOLTAGE REGULATORS)”並以引用的方式併入本文的美國臨時專利申請序號61/946,268。本申請在此要求美國臨時專利申請序號61/936,111和61/946,268的權益。 This application relates to a semiconductor structure (SEMICONDUCTOR STRUCTURES FOR ENHANCED TRANSIENT RESPONSE IN LOW DROPOUT (LDO) VOLTAGE REGULATORS), entitled "Enhanced Transient Response for Low Dropout (LDO) Regulators," filed on February 5, 2014. U.S. Provisional Patent Application Serial No. 61/936,111, which is incorporated herein by reference. This application also relates to a semiconductor structure (SEMICONDUCTOR STRUCTURES FOR ENHANCED TRANSIENT RESPONSE IN LOW DROPOUT (LDO) VOLTAGE REGULATORS) entitled "Enhanced Transient Response for Low Dropout (LDO) Regulators, submitted on February 28, 2014. U.S. Provisional Patent Application Serial No. 61/946,268, which is incorporated herein by reference. This application claims the benefit of U.S. Provisional Patent Application Serial Nos. 61/936,111 and 61/946,268.

在使用“超級電流鏡”設計的常規LDO穩壓器中，調節器 對暫態的響應速度受它們的自我調整偏置回路上升到適當的操作點所花費的時間限制。然而，這些LDO穩壓器採用來自它們的導通電晶體的閘極的自我調整偏置回饋，並且因此它們的自我調整偏置回饋回路的頻寬受它們的導通裝置的大閘極電容限制。因此，這些LDO穩壓器的暫態誘發的輸出電壓跌落相當大。 In a conventional LDO regulator designed with a "super current mirror", the regulator The response speed to transients is limited by the time it takes for their self-adjusting bias loop to rise to the appropriate operating point. However, these LDO regulators use self-tuning bias feedback from the gates of their conducting crystals, and thus the bandwidth of their self-adjusting bias feedback loops is limited by the large gate capacitance of their conducting devices. Therefore, the transient induced output voltage drop of these LDO regulators is quite large.

一個實施方案是針對一種用於LDO穩壓器中增強型暫態響應的半導體結構。所述半導體結構是包括形成於半導體積體電路、晶圓、晶片或晶粒上的自我調整偏置輸入級的LDO穩壓器。自我調整偏置信號是從輸入級(例如，第一增益級)的輸出耦合到所述級的輸入的回饋信號。因此，所得自我調整偏置回饋回路的暫態響應明顯快於LDO穩壓器的主回饋回路的暫態響應。更確切地說，到LDO穩壓器的輸出級的驅動電流以明顯高於輸出電流的速率增加，以便給導通電晶體裝置的閘極電容充電。因此，自我調整偏置LDO穩壓器的負載暫態誘發的輸出電壓跌落明顯小於常規LDO穩壓器的輸出電壓跌落(例如，如果使用相對較小的輸出電容器)。 One embodiment is directed to a semiconductor structure for enhanced transient response in an LDO regulator. The semiconductor structure is an LDO regulator comprising a self-regulating bias input stage formed on a semiconductor integrated circuit, wafer, wafer or die. The self-adjusting bias signal is a feedback signal coupled from the output of the input stage (eg, the first gain stage) to the input of the stage. Therefore, the transient response of the resulting self-tuning bias feedback loop is significantly faster than the transient response of the LDO regulator's main feedback loop. More specifically, the drive current to the output stage of the LDO regulator is increased at a rate significantly higher than the output current to charge the gate capacitance of the conducting crystal device. Therefore, the load transient induced output voltage drop of the self-tuning bias LDO regulator is significantly less than the output voltage drop of a conventional LDO regulator (eg, if a relatively small output capacitor is used).

100‧‧‧電子電路 100‧‧‧Electronic circuit

102‧‧‧第一放大器 102‧‧‧First amplifier

104‧‧‧非反相輸入 104‧‧‧Non-inverting input

106‧‧‧節點 106‧‧‧ nodes

108‧‧‧電阻器R1 108‧‧‧Resistor R1

110‧‧‧電阻器R2 110‧‧‧Resistor R2

112‧‧‧反相輸入 112‧‧‧Inverting input

114‧‧‧輸出 114‧‧‧ Output

116‧‧‧偏置電流控制輸入 116‧‧‧Off current control input

118‧‧‧輸入 118‧‧‧Enter

120‧‧‧第二放大器 120‧‧‧second amplifier

122‧‧‧電流鏡 122‧‧‧current mirror

124‧‧‧輸出 124‧‧‧ Output

126‧‧‧第一電晶體裝置 126‧‧‧First transistor device

128‧‧‧第二電晶體裝置 128‧‧‧Second transistor device

130‧‧‧輸入端子 130‧‧‧Input terminal

132‧‧‧輸出端子 132‧‧‧Output terminal

134‧‧‧電容器C1 134‧‧‧Capacitor C1

136‧‧‧接地端子 136‧‧‧ Grounding terminal

200‧‧‧電子電路 200‧‧‧Electronic circuit

201‧‧‧輸入 201‧‧‧ Input

202‧‧‧第一放大器 202‧‧‧First amplifier

203‧‧‧緩衝放大器 203‧‧‧Buffer amplifier

204‧‧‧非反相輸入 204‧‧‧Non-inverting input

205‧‧‧輸出 205‧‧‧ output

206‧‧‧節點 206‧‧‧ nodes

208‧‧‧電阻器R1 208‧‧‧Resistor R1

210‧‧‧電阻器R2 210‧‧‧Resistor R2

212‧‧‧反相輸入 212‧‧‧Inverting input

214‧‧‧輸出 214‧‧‧ output

216‧‧‧偏置電流控制輸入 216‧‧‧ bias current control input

218‧‧‧輸入 218‧‧‧ Input

220‧‧‧第二放大器 220‧‧‧second amplifier

222‧‧‧電流鏡 222‧‧‧current mirror

224‧‧‧輸出 224‧‧‧ output

226‧‧‧第一電晶體裝置 226‧‧‧First transistor device

228‧‧‧第二電晶體裝置 228‧‧‧Second transistor device

230‧‧‧輸入端子 230‧‧‧Input terminal

232‧‧‧輸出端子 232‧‧‧Output terminal

234‧‧‧電容器C1 234‧‧‧Capacitor C1

236‧‧‧接地端子 236‧‧‧ Grounding terminal

300‧‧‧電子電路 300‧‧‧Electronic circuits

302‧‧‧第一放大器 302‧‧‧First amplifier

304‧‧‧非反相輸入 304‧‧‧Non-inverting input

305‧‧‧第三放大器 305‧‧‧3rd amplifier

306‧‧‧節點 306‧‧‧ nodes

307‧‧‧第三電晶體裝置 307‧‧‧The third transistor device

308‧‧‧電阻器R1 308‧‧‧Resistor R1

309‧‧‧第四電晶體裝置 309‧‧‧4th crystal device

310‧‧‧電阻器R2 310‧‧‧Resistor R2

312‧‧‧反相輸入 312‧‧‧Inverting input

316‧‧‧偏置電流輸入 316‧‧‧ bias current input

318‧‧‧輸入 318‧‧‧ Input

319‧‧‧輸入 319‧‧‧Enter

320‧‧‧第二放大器 320‧‧‧second amplifier

322‧‧‧第一電流鏡 322‧‧‧First current mirror

324‧‧‧輸出 324‧‧‧ Output

325‧‧‧輸出 325‧‧‧ output

326‧‧‧第一電晶體裝置 326‧‧‧First transistor device

328‧‧‧第二電晶體裝置 328‧‧‧Second transistor device

330‧‧‧輸入端子 330‧‧‧Input terminal

332‧‧‧輸出端子 332‧‧‧Output terminal

334‧‧‧電容器C1 334‧‧‧Capacitor C1

336‧‧‧接地端子 336‧‧‧ Grounding terminal

338‧‧‧第二電流鏡 338‧‧‧second current mirror

400‧‧‧電子電路 400‧‧‧Electronic circuits

401‧‧‧輸入 401‧‧‧ input

402‧‧‧第一放大器 402‧‧‧First amplifier

403‧‧‧緩衝放大器 403‧‧‧Buffer amplifier

404‧‧‧非反相輸入 404‧‧‧Non-inverting input

405‧‧‧第三放大器 405‧‧‧3rd amplifier

406‧‧‧節點 406‧‧‧ nodes

407‧‧‧第三電晶體裝置 407‧‧‧The third transistor device

408‧‧‧電阻器R1 408‧‧‧Resistor R1

409‧‧‧第四電晶體裝置 409‧‧‧4th transistor device

410‧‧‧電阻器R2 410‧‧‧Resistor R2

412‧‧‧反相輸入 412‧‧‧Inverting input

416‧‧‧偏置電流輸入 416‧‧‧ Bias current input

418‧‧‧輸入 418‧‧‧Enter

419‧‧‧輸入 419‧‧‧Enter

420‧‧‧第二放大器 420‧‧‧second amplifier

422‧‧‧第一電流鏡 422‧‧‧First current mirror

424‧‧‧輸出 424‧‧‧ Output

425‧‧‧輸出 425‧‧‧ output

426‧‧‧第一電晶體裝置 426‧‧‧First transistor device

428‧‧‧第二電晶體裝置 428‧‧‧Second transistor device

430‧‧‧輸入端子 430‧‧‧Input terminal

432‧‧‧輸出端子 432‧‧‧Output terminal

434‧‧‧電容器C1 434‧‧‧Capacitor C1

436‧‧‧接地端子 436‧‧‧ Grounding terminal

438‧‧‧第二電流鏡 438‧‧‧second current mirror

500‧‧‧半導體結構 500‧‧‧Semiconductor structure

501‧‧‧電晶體M8 501‧‧‧Transistor M8

502‧‧‧第一放大器 502‧‧‧First amplifier

503‧‧‧緩衝放大器 503‧‧‧Buffer amplifier

504‧‧‧非反相輸入 504‧‧‧Non-inverting input

505‧‧‧第三放大器 505‧‧‧3rd amplifier

506‧‧‧節點 506‧‧‧ nodes

507‧‧‧第三電晶體裝置 507‧‧‧The third transistor device

508‧‧‧電阻器R1 508‧‧‧Resistor R1

509‧‧‧第四電晶體裝置 509‧‧‧4th crystal device

510‧‧‧電阻器R2 510‧‧‧Resistor R2

512‧‧‧反相輸入 512‧‧‧Inverting input

514‧‧‧輸出 514‧‧‧ Output

515‧‧‧輸出 515‧‧‧ output

520‧‧‧第二放大器 520‧‧‧second amplifier

522‧‧‧第一電流鏡 522‧‧‧First current mirror

526‧‧‧第一電晶體裝置 526‧‧‧First transistor device

528‧‧‧第二電晶體裝置 528‧‧‧Second transistor device

530‧‧‧輸入端子 530‧‧‧Input terminal

532‧‧‧輸出端子 532‧‧‧Output terminal

534‧‧‧電容器C1 534‧‧‧Capacitor C1

536‧‧‧接地端子 536‧‧‧ Grounding terminal

538‧‧‧第二電流鏡 538‧‧‧second current mirror

600‧‧‧半導體結構 600‧‧‧Semiconductor structure

601‧‧‧電晶體M8 601‧‧•Transistor M8

602‧‧‧第一放大器 602‧‧‧First amplifier

604‧‧‧非反相輸入 604‧‧‧Non-inverting input

605‧‧‧第三放大器 605‧‧‧3rd amplifier

606‧‧‧節點 606‧‧‧ nodes

607‧‧‧第三電晶體裝置 607‧‧‧The third transistor device

608‧‧‧電阻器R1 608‧‧‧Resistor R1

609‧‧‧第四電晶體裝置 609‧‧‧4th transistor device

610‧‧‧電阻器R2 610‧‧‧Resistor R2

612‧‧‧反相輸入 612‧‧‧Inverting input

614‧‧‧輸出 614‧‧‧ output

620‧‧‧第二放大器 620‧‧‧second amplifier

622‧‧‧第一電流鏡 622‧‧‧First current mirror

626‧‧‧第一電晶體裝置 626‧‧‧First transistor device

628‧‧‧第二電晶體裝置 628‧‧‧Second transistor device

630‧‧‧輸入端子 630‧‧‧Input terminal

632‧‧‧輸出端子 632‧‧‧Output terminal

634‧‧‧電容器C1 634‧‧‧Capacitor C1

636‧‧‧接地端子 636‧‧‧ Grounding terminal

638‧‧‧第二電流鏡 638‧‧‧second current mirror

700a‧‧‧曲線圖 700a‧‧‧Curve

700b‧‧‧曲線圖 700b‧‧‧Curve

800‧‧‧曲線圖 800‧‧‧Chart

802‧‧‧2.176V 802‧‧‧2.176V

900‧‧‧曲線圖 900‧‧‧Curve

902a‧‧‧性能曲線 902a‧‧‧ performance curve

902b‧‧‧性能曲線 902b‧‧‧ performance curve

904a‧‧‧性能曲線 904a‧‧‧ performance curve

904b‧‧‧性能曲線 904b‧‧‧ performance curve

906a‧‧‧性能曲線 906a‧‧‧ performance curve

906b‧‧‧性能曲線 906b‧‧‧ performance curve

908a‧‧‧性能曲線 908a‧‧‧ performance curve

908b‧‧‧性能曲線 908b‧‧‧ performance curve

1000‧‧‧系統 1000‧‧‧ system

1002‧‧‧自我調整偏置LDO穩壓器 1002‧‧‧ Self-adjusting bias LDO regulator

1004‧‧‧VLOGIC通道輸出連接件 1004‧‧‧VLOGIC channel output connector

1006‧‧‧定序器 1006‧‧‧Sequencer

1008‧‧‧AVDD增壓控制器 1008‧‧‧AVDD boost controller

1010‧‧‧閘控脈衝調製器 1010‧‧‧Gate Control Pulse Modulator

1012‧‧‧電壓檢測器 1012‧‧‧Voltage detector

1014‧‧‧數位控制電位計 1014‧‧‧Digital Control Potentiometer

1030‧‧‧輸入端子 1030‧‧‧Input terminal

1032‧‧‧輸出端子 1032‧‧‧Output terminal

1100‧‧‧系統 1100‧‧‧ system

1102‧‧‧自我調整偏置LDO穩壓器 1102‧‧‧ Self-adjusting bias LDO regulator

1130‧‧‧電壓輸入 1130‧‧‧Voltage input

1132‧‧‧電壓輸出 1132‧‧‧Voltage output

1136‧‧‧接地端子 1136‧‧‧ Grounding terminal

1200‧‧‧流程圖 1200‧‧‧ Flowchart

應理解，附圖僅描繪示例性實施方案且因而在範圍上不視為具有限定性，通過使用附圖，將另外以額外的專一性和細節對所述示例性實施方案進行描述。 It is to be understood that the appended drawings are not intended to

圖1是電子電路的示意性方塊圖，所述電子電路可用於實施 本發明的一個示例性實施方案。 1 is a schematic block diagram of an electronic circuit that can be used to implement An exemplary embodiment of the invention.

圖2是第二電子電路的示意性方塊圖，所述第二電子電路可用於實施本發明的第二示例性實施方案。 2 is a schematic block diagram of a second electronic circuit that can be used to implement a second exemplary embodiment of the present invention.

圖3是第三電子電路的示意性方塊圖，所述第三電子電路可用於實施本發明的第三示例性實施方案。 3 is a schematic block diagram of a third electronic circuit that can be used to implement a third exemplary embodiment of the present invention.

圖4是第四電子電路的示意性方塊圖，所述第四電子電路可用於實施本發明的第四示例性實施方案。 4 is a schematic block diagram of a fourth electronic circuit that can be used to implement a fourth exemplary embodiment of the present invention.

圖5是示例性半導體結構的示意性電路圖，所述半導體結構可用於實施圖2中描繪的電子電路或圖4中描繪的電子電路。 5 is a schematic circuit diagram of an exemplary semiconductor structure that can be used to implement the electronic circuit depicted in FIG. 2 or the electronic circuit depicted in FIG.

圖6是示例性半導體結構的示意性電路圖，所述半導體結構可用於實施圖1中描繪的電子電路或圖3中描繪的電子電路。 6 is a schematic circuit diagram of an exemplary semiconductor structure that can be used to implement the electronic circuit depicted in FIG. 1 or the electronic circuit depicted in FIG.

圖7A和圖7B是展示根據本發明的實施方案結構化的LDO穩壓器的類比相位邊限性能曲線和增益邊限性能曲線的相關曲線圖。 7A and 7B are graphs showing correlation curves of analog phase margin performance curves and gain margin performance curves for a structured LDO regulator in accordance with an embodiment of the present invention.

圖8是展示根據本發明的實施方案結構化的自我調整偏置LDO穩壓器的類比暫態負載響應的曲線圖。 8 is a graph showing the analog transient load response of a structured self-adjusting bias LDO regulator in accordance with an embodiment of the present invention.

圖9是描繪根據本發明的實施方案在LDO穩壓器的類比操作條件下的性能模式的曲線圖。 9 is a graph depicting performance patterns under analog operating conditions of an LDO regulator, in accordance with an embodiment of the present invention.

圖10是配置為電源管理積體電路(PMIC)的示例性系統的示意性方塊圖，所述電源管理積體電路可用於實施根據本發明的一個或多個實施方案的用於增強型暫態響應的半導體結構。 10 is a schematic block diagram of an exemplary system configured as a power management integrated circuit (PMIC) that can be used to implement enhanced transients in accordance with one or more embodiments of the present invention. Responsive semiconductor structure.

圖11是配置為PMIC的示例性系統的示意性方塊圖，所述PMIC可用於實施根據本發明的一個或多個實施方案的用於增強型暫態響 應的半導體結構。 11 is a schematic block diagram of an exemplary system configured as a PMIC that can be used to implement an enhanced transient response in accordance with one or more embodiments of the present invention. The semiconductor structure should be.

圖12是描繪根據本發明的一個或多個實施方案的自我調整偏置LDO穩壓器的示例性操作方法的流程圖。 12 is a flow chart depicting an exemplary method of operation of a self-adjusting bias LDO regulator in accordance with one or more embodiments of the present invention.

在以下詳細描述中，參考形成本發明一部分的附圖，且其中借助於特定說明性實施方案來展示。然而，將理解，可利用其它實施方案，且可進行邏輯、機械和電氣方面的改變。另外，附圖與說明書中呈現的方法不應被理解為限定可執行個別動作的順序。因此，不應在限制意義上解釋以下詳細描述。在整個附圖中，盡可能使用相同或相似參考符號來指代相同或相似結構元件或零件。 In the following detailed description, reference is made to the accompanying drawings in drawing However, it will be understood that other embodiments may be utilized and that logical, mechanical, and electrical changes may be made. In addition, the figures and the methods presented in the specification are not to be construed as limiting the order in which the individual acts can be performed. Therefore, the following detailed description should not be construed in a limiting sense. Throughout the drawings, the same or similar reference numerals are used to refer to the same or similar structural elements or parts.

本文所述的實施方案提供用於低壓降(LDO)穩壓器中的增強型暫態響應的半導體結構。對於一個示例性實施方案來說，半導體結構包括具有自我調整偏置輸入級的LDO穩壓器。自我調整偏置信號是從輸入級(例如，第一增益級)的輸出耦合到所述級的輸入的回饋信號。因此，所得自我調整偏置回饋回路的暫態響應明顯快於LDO穩壓器的主回饋回路的暫態響應。更確切地說，到LDO穩壓器的輸出級的驅動電流以明顯高於輸出電流的速率的速率增加，以便對導通電晶體裝置的閘極電容充電。因此，自我調整偏置LDO穩壓器的負載暫態誘發的輸出電壓跌落明顯小於常規LDO穩壓器的輸出電壓跌落(例如，如果使用相對較小的輸出電容器)。 Embodiments described herein provide a semiconductor structure for enhanced transient response in a low dropout (LDO) voltage regulator. For an exemplary embodiment, the semiconductor structure includes an LDO regulator with a self-adjusting bias input stage. The self-adjusting bias signal is a feedback signal coupled from the output of the input stage (eg, the first gain stage) to the input of the stage. Therefore, the transient response of the resulting self-tuning bias feedback loop is significantly faster than the transient response of the LDO regulator's main feedback loop. More specifically, the drive current to the output stage of the LDO regulator is increased at a rate significantly higher than the rate of the output current to charge the gate capacitance of the conducting crystal device. Therefore, the load transient induced output voltage drop of the self-tuning bias LDO regulator is significantly less than the output voltage drop of a conventional LDO regulator (eg, if a relatively small output capacitor is used).

可在例如半導體積體電路(IC)、晶圓、晶片或晶粒中形成用於增強型暫態響應的本發明半導體結構的實施方案。因此，例如，所述半導體結構可用作IC電源或電源管理IC(PMIC)中的LDO穩壓器或與其結合 使用。舉例來說，可在需要高值、低等效串聯電阻(ESR)電容性負載和增強的電源抑制比(PSRR)性能的產品中使用此類IC電源或PMIC。如此，例如，用於增強型暫態響應的本發明半導體結構可用於智慧型電話或類似產品的IC電源或PMIC中，所述產品使用相對較大(μF範圍)、低ESR陶瓷電容器以用於電源去耦合。另外，某些產品可能要求此類半導體IC實施為對相對較低的輸出電容具有合適暫態響應的LDO穩壓器，因為供應數位電路的此類LDO調節器常常經歷負載電流的突然增加。因此，應當使LDO穩壓器的所得輸出電壓跌落最小化(例如，10mV到30mV)，以便保持LDO穩壓器在低電壓下的合適電路性能。如此，用於增強型暫態響應的本發明半導體結構由於從LDO穩壓器中的第一增益級的輸出取得自我調整偏置回饋而容易滿足此類性能要求，使得自我調整偏置回饋回路的頻寬不受導通電晶體裝置的大閘極電容限制，而在常規LDO穩壓器中頻寬是受限的。 Embodiments of the semiconductor structures of the present invention for enhanced transient response can be formed, for example, in semiconductor integrated circuits (ICs), wafers, wafers, or dies. Thus, for example, the semiconductor structure can be used as an LDO regulator in an IC power supply or power management IC (PMIC) or combined therewith. use. For example, such IC power supplies or PMICs can be used in products that require high value, low equivalent series resistance (ESR) capacitive loading, and enhanced power supply rejection ratio (PSRR) performance. Thus, for example, the inventive semiconductor structure for enhanced transient response can be used in IC power supplies or PMICs for smart phones or similar products that use relatively large (μF range), low ESR ceramic capacitors for The power supply is decoupled. In addition, some products may require such semiconductor ICs to be implemented as LDO regulators with suitable transient response to relatively low output capacitance, as such LDO regulators that supply digital circuits often experience a sudden increase in load current. Therefore, the resulting output voltage drop of the LDO regulator should be minimized (eg, 10mV to 30mV) in order to maintain proper circuit performance of the LDO regulator at low voltages. As such, the semiconductor structure of the present invention for enhanced transient response easily meets such performance requirements by self-adjusting bias feedback from the output of the first gain stage in the LDO regulator, such that the self-adjusting bias feedback loop The bandwidth is not limited by the large gate capacitance of the conducting crystal device, which is limited in conventional LDO regulators.

圖1是電子電路100的示意性方塊圖，所述電子電路可用於實施本發明的一個示例性實施方案。舉例來說，電子電路100可用於實施用於半導體結構中的增強型暫態響應的自我調整偏置LDO穩壓器，例如半導體積體電路(IC)、晶圓、晶片或晶粒。 1 is a schematic block diagram of an electronic circuit 100 that can be used to implement an exemplary embodiment of the present invention. For example, electronic circuit 100 can be used to implement a self-regulating bias LDO regulator for enhanced transient response in a semiconductor structure, such as a semiconductor integrated circuit (IC), wafer, wafer, or die.

參考圖1中所示的示例性實施方案，電子電路100(例如，LDO穩壓器)包括第一放大器102，所述第一放大器是也充當電路100中的誤差放大器的輸入級。在此示例性實施方案中，第一放大器102是電壓增益放大器，其電流偏置位準受其輸出電壓控制(例如，自偏置放大器)。第一輸入電壓(例如，參考電壓或Vref)耦合到第一放大器102的非反相輸入104。在一些實施方案中，第一輸入電壓是電子電路100內產生的固定參考電壓。在 其它實施方案中，第一輸入電壓是可變的參考電壓(例如，由數位/類比轉換器改變)。在一些實施方案中，第一輸入電壓在電子電路100外部產生，並通過例如半導體IC或晶片的針腳連接到輸入104。第二輸入電壓(例如，回饋電壓或Vfb)從連接到第一電阻器108和第二電阻器110的節點106(例如，電阻性分壓器)連接到第一放大器102的反相輸入112，且第一放大器102的輸出電壓從第一放大器102的輸出114耦合回第一放大器102的偏置電流控制輸入116(即，自偏置)，且還耦合到第二放大器120的輸入118。在此示例性實施方案中，第二放大器120是反相跨導放大器，所述第二放大器形成用於電流鏡輸出級122的驅動電流。更確切地說，第二放大器120的輸出124耦合到電流鏡輸出級122的第一電晶體裝置126的閘極端子和汲極端子，且還耦合到電流鏡輸出級122的第二電晶體裝置128的閘極端子。第一電晶體裝置126和第二電晶體裝置128的源極端子耦合到電子電路100的輸入端子130(例如，VIN)。第二電晶體裝置128的汲極端子耦合到第一電阻器108的一側(例如，與節點106的一側相對)以及電子電路100的輸出端子132(例如，VOUT)。電容器134(例如，輸出電容器)的一側耦合到輸出端子132，且電容器134的相對側耦合到電子電路100的接地端子136(例如，GND或電路接地)。第二電阻器110的第二側(例如，與節點106的一側相對)也耦合到接地端子136。 Referring to the exemplary embodiment shown in FIG. 1, electronic circuit 100 (eg, an LDO regulator) includes a first amplifier 102 that is also an input stage that also functions as an error amplifier in circuit 100. In this exemplary embodiment, the first amplifier 102 is a voltage gain amplifier whose current bias level is controlled by its output voltage (eg, a self-biased amplifier). A first input voltage (eg, a reference voltage or Vref) is coupled to the non-inverting input 104 of the first amplifier 102. In some embodiments, the first input voltage is a fixed reference voltage generated within electronic circuit 100. in In other embodiments, the first input voltage is a variable reference voltage (eg, changed by a digital/analog converter). In some embodiments, the first input voltage is generated external to electronic circuit 100 and is coupled to input 104 by, for example, a pin of a semiconductor IC or wafer. A second input voltage (eg, a feedback voltage or Vfb) is coupled to an inverting input 112 of the first amplifier 102 from a node 106 (eg, a resistive voltage divider) coupled to the first resistor 108 and the second resistor 110, And the output voltage of the first amplifier 102 is coupled back from the output 114 of the first amplifier 102 back to the bias current control input 116 of the first amplifier 102 (ie, self-biased) and also to the input 118 of the second amplifier 120. In this exemplary embodiment, the second amplifier 120 is an inverting transconductance amplifier that forms a drive current for the current mirror output stage 122. More specifically, the output 124 of the second amplifier 120 is coupled to the gate and drain terminals of the first transistor device 126 of the current mirror output stage 122, and is also coupled to the second transistor device of the current mirror output stage 122. The gate terminal of 128. The source terminals of the first transistor device 126 and the second transistor device 128 are coupled to an input terminal 130 (eg, VIN) of the electronic circuit 100. The 汲 terminal of the second transistor device 128 is coupled to one side of the first resistor 108 (eg, opposite one side of the node 106) and the output terminal 132 (eg, VOUT) of the electronic circuit 100. One side of capacitor 134 (eg, an output capacitor) is coupled to output terminal 132, and the opposite side of capacitor 134 is coupled to ground terminal 136 (eg, GND or circuit ground) of electronic circuit 100. The second side of the second resistor 110 (eg, opposite one side of the node 106) is also coupled to the ground terminal 136.

在此示例性實施方案中，電子電路100的輸出電流由第二(鏡)電晶體裝置128產生，所述第二(鏡)電晶體裝置通常是具有比第一(鏡)電晶體裝置126的總閘極面積或寬度大了大約50到500倍的總閘極面積或寬度的大導通電晶體裝置。換句話說，由第一電晶體裝置126和第二電晶體裝 置128形成的電流鏡122與其它常規電流鏡級相比，可具有相對較高的導通比。電子電路100的頻率補償由輸出電容器134提供，所述輸出電容器在電子電路100中產生支配頻率極點。由第二(鏡)電晶體裝置128的閘極電容產生的極點頻率由第一鏡電晶體裝置126增加。注意，由於輸出114處的電容，第一放大器102的輸出114處也產生頻率極點。然而，第一放大器102的輸出阻抗(且因此為電壓增益)依據設計選擇而適當減小，從而使此極點為非支配的。另外，此時注意以下內容是有用的：例如，取決於設計或製造偏好，可利用p通道金屬氧化物半導體(PMOS)或n通道MOS(NMOS)電晶體裝置來實施本文所述的所有電晶體裝置。應注意，在一些實施方案中，不使用第一(鏡)電晶體裝置126，因此不使用輸出電流鏡(122)，且輸出級大致上由輸出電晶體128組成。 In this exemplary embodiment, the output current of the electronic circuit 100 is generated by a second (mirror) transistor device 128, which typically has a ratio of the first (mirror) transistor device 126. A large-conducting electrified crystal device having a total gate area or width that is about 50 to 500 times larger than the total gate area or width. In other words, mounted by the first transistor device 126 and the second transistor The current mirror 122 formed by the 128 can have a relatively high turn-on ratio compared to other conventional current mirror stages. The frequency compensation of the electronic circuit 100 is provided by an output capacitor 134 that produces a dominant frequency pole in the electronic circuit 100. The pole frequency generated by the gate capacitance of the second (mirror) transistor device 128 is increased by the first mirror transistor device 126. Note that due to the capacitance at the output 114, a frequency pole is also produced at the output 114 of the first amplifier 102. However, the output impedance of the first amplifier 102 (and therefore the voltage gain) is suitably reduced depending on design choices, making this pole non-dominated. Additionally, it is useful to note at this point that, for example, depending on design or manufacturing preferences, all of the transistors described herein can be implemented using p-channel metal oxide semiconductor (PMOS) or n-channel MOS (NMOS) transistor devices. Device. It should be noted that in some embodiments, the first (mirror) transistor device 126 is not used, so the output current mirror (122) is not used and the output stage is substantially comprised of the output transistor 128.

圖2是第二電子電路200的示意性方塊圖，所述第二電子電路可用於實施本發明的第二示例性實施方案。舉例來說，電子電路200可用於實施用於半導體結構中的增強型暫態響應的第二自我調整偏置LDO穩壓器，例如半導體IC、晶圓、晶片或晶粒。 2 is a schematic block diagram of a second electronic circuit 200 that can be used to implement a second exemplary embodiment of the present invention. For example, electronic circuit 200 can be used to implement a second self-adjusting bias LDO regulator, such as a semiconductor IC, wafer, wafer, or die, for enhanced transient response in a semiconductor structure.

參考圖2中所示的示例性實施方案，電子電路200(例如，LDO穩壓器)包括第一放大器202，所述第一放大器是也充當電路200中的誤差放大器的輸入級。在此示例性實施方案中，第一放大器202是電壓增益放大器，其電流偏置位準受其輸出電壓控制(例如，自偏置放大器)。第一輸入電壓(例如，參考電壓或Vref)耦合到第一放大器202的非反相輸入204。在一些實施方案中，第一輸入電壓是電子電路200內產生的固定參考電壓。在其它實施方案中，第一輸入電壓是可變的參考電壓(例如，由數位/類比轉換 器改變)。在一些實施方案中，第一輸入電壓在電子電路200外部產生，並通過例如半導體IC或晶片的針腳耦合到輸入204。第二輸入電壓(例如，回饋電壓或Vfb)從連接到第一電阻器208和第二電阻器210的節點206(例如，電阻性分壓器)耦合到第一放大器202的反相輸入212，且第一放大器202的輸出電壓從第一放大器202的輸出214耦合回第一放大器202的偏置電流控制輸入216(即，自偏置)，且還連接到第二放大器220的輸入218。在此示例性實施方案中，第二放大器220是反相跨導放大器，所述第二放大器形成用於電流鏡輸出級222的驅動電流。更確切地說，第二放大器220的輸出224耦合到電流鏡輸出級222的第一電晶體裝置226的汲極端子，且還耦合到第三(例如，緩衝)放大器203的輸入201。第三放大器203的輸出205耦合到第一電晶體裝置226的閘極端子，且還耦合到電流鏡輸出級222的第二電晶體裝置228的閘極端子。 Referring to the exemplary embodiment shown in FIG. 2, electronic circuit 200 (eg, an LDO regulator) includes a first amplifier 202, which is an input stage that also functions as an error amplifier in circuit 200. In this exemplary embodiment, the first amplifier 202 is a voltage gain amplifier whose current bias level is controlled by its output voltage (eg, a self-biased amplifier). A first input voltage (eg, a reference voltage or Vref) is coupled to the non-inverting input 204 of the first amplifier 202. In some embodiments, the first input voltage is a fixed reference voltage generated within electronic circuit 200. In other embodiments, the first input voltage is a variable reference voltage (eg, converted by digital/analog Change). In some embodiments, the first input voltage is generated external to electronic circuit 200 and coupled to input 204 by, for example, a pin of a semiconductor IC or wafer. A second input voltage (eg, a feedback voltage or Vfb) is coupled from a node 206 (eg, a resistive voltage divider) coupled to the first resistor 208 and the second resistor 210 to an inverting input 212 of the first amplifier 202, And the output voltage of the first amplifier 202 is coupled back from the output 214 of the first amplifier 202 back to the bias current control input 216 of the first amplifier 202 (ie, self-biased) and also to the input 218 of the second amplifier 220. In this exemplary embodiment, the second amplifier 220 is an inverting transconductance amplifier that forms a drive current for the current mirror output stage 222. More specifically, the output 224 of the second amplifier 220 is coupled to the first terminal of the first transistor device 226 of the current mirror output stage 222 and also to the input 201 of the third (eg, buffer) amplifier 203. The output 205 of the third amplifier 203 is coupled to the gate terminal of the first transistor device 226 and also to the gate terminal of the second transistor device 228 of the current mirror output stage 222.

在此示例性實施方案中，電子電路200的輸出電流由電流鏡輸出級222的第二(鏡)電晶體裝置228產生。第二電晶體裝置228通常是具有比第一(鏡)電晶體裝置226的總閘極面積或寬度大了大約50到500倍的總閘極面積或寬度的大導通電晶體裝置。注意，在所示的示例性實施方案中，耦合在第二放大器220的輸出224與第一電晶體裝置226和第二電晶體裝置228的閘極端子之間的第三放大器203的組合形成經緩衝電流鏡輸出級222。換句話說，例如，第三放大器203充當緩衝放大器或電壓跟隨器，以驅動電流鏡輸出級222的第二電晶體裝置228的相對較大的閘極電容。因此，第三放大器203可用於增加電流鏡輸出級222的總頻寬，從而超過電子電路100的電流鏡輸出級122的總頻寬。然而，因為使用額外的電路元件， 所以此增強可被電子電路200中略高於電子電路100的電流消耗略微抵消。 In this exemplary embodiment, the output current of electronic circuit 200 is generated by a second (mirror) transistor device 228 of current mirror output stage 222. The second transistor device 228 is typically a large conducting crystal device having a total gate area or width that is about 50 to 500 times greater than the total gate area or width of the first (mirror) transistor device 226. Note that in the illustrated exemplary embodiment, the combination of the third amplifier 203 coupled between the output 224 of the second amplifier 220 and the gate terminals of the first transistor device 226 and the second transistor device 228 forms a The current mirror output stage 222 is buffered. In other words, for example, the third amplifier 203 acts as a buffer amplifier or voltage follower to drive the relatively large gate capacitance of the second transistor device 228 of the current mirror output stage 222. Accordingly, the third amplifier 203 can be used to increase the total bandwidth of the current mirror output stage 222 beyond the total bandwidth of the current mirror output stage 122 of the electronic circuit 100. However, because of the use of additional circuit components, Therefore, this enhancement can be slightly offset by the current consumption in the electronic circuit 200 that is slightly higher than the electronic circuit 100.

第一電晶體裝置226和第二電晶體裝置228的源極端子耦合到電子電路200的輸入端子230(例如，V_IN)。第二電晶體裝置228的汲極端子耦合到第一電阻器208的一側(例如，與節點206的一側相對)以及電子電路200的輸出端子232(例如，V_OUT)。電容器234(例如，輸出電容器)的一側耦合到輸出端子232，且電容器234的相對側耦合到電子電路200的接地端子236(例如，GND或電路接地)。第二電阻器210的第二側(例如，與節點206的一側相對)也耦合到接地端子236。 The source terminals of the first transistor device 226 and the second transistor device 228 are coupled to an input terminal 230 (eg, V _IN ) of the electronic circuit 200. The drain terminal of the second transistor device 228 is coupled to one side of the first resistor 208 (e.g., opposite one side of the node 206) and an output terminal 232 (e.g., V _OUT ) of the electronic circuit 200. One side of capacitor 234 (eg, an output capacitor) is coupled to output terminal 232, and the opposite side of capacitor 234 is coupled to ground terminal 236 of electronic circuit 200 (eg, GND or circuit ground). The second side of the second resistor 210 (eg, opposite one side of the node 206) is also coupled to the ground terminal 236.

圖3是第三電子電路300的示意性方塊圖，所述第三電子電路可用於實施本發明的第三示例性實施方案。舉例來說，電子電路300可用於實施用於半導體結構中的增強型暫態響應的第三自我調整偏置LDO穩壓器，例如半導體IC、晶圓、晶片或晶粒。 3 is a schematic block diagram of a third electronic circuit 300 that can be used to implement a third exemplary embodiment of the present invention. For example, electronic circuit 300 can be used to implement a third self-adjusting bias LDO regulator, such as a semiconductor IC, wafer, wafer, or die, for enhanced transient response in a semiconductor structure.

參考圖3中所示的示例性實施方案，電子電路300(例如，LDO穩壓器)包括第一放大器302，所述第一放大器是也充當電路300中的誤差放大器的輸入級。在此示例性實施方案中，第一放大器302是電壓增益放大器，其電流偏置位準受其輸出電壓控制(例如，自偏置放大器)。第一輸入電壓(例如，參考電壓或Vref)耦合到第一放大器302的非反相輸入304。在一些實施方案中，第一輸入電壓是電子電路300內產生的固定參考電壓。在其它實施方案中，第一輸入電壓是可變的參考電壓(例如，由數位/類比轉換器改變)。在一些實施方案中，第一輸入電壓在電子電路300外部產生，並通過例如半導體IC或晶片的針腳耦合到輸入304。第二輸入電壓(例如，回饋電壓或Vfb)從連接到第一電阻器308和第二電阻器310的節點306(例如， 電阻性分壓器)耦合到第一放大器302的反相輸入312，且第一放大器302的輸出電壓從第一放大器302的輸出314耦合到第二放大器320的輸入318，且還耦合到第三放大器305的輸入319。在此示例性實施方案中，第二放大器320是反相跨導放大器，所述第二放大器形成用於第一電流鏡輸出級322的驅動電流。更確切地說，第二放大器320的輸出324耦合到第一電流鏡輸出級322的第一電晶體裝置326的閘極端子和汲極端子，且還耦合到第一電流鏡輸出級322的第二電晶體裝置328的閘極端子。第一電晶體裝置326和第二電晶體裝置328的源極端子耦合到電子電路300的輸入端子330(例如，V_IN)。第二電晶體裝置328的汲極端子耦合到第一電阻器308的一側(例如，與節點306的一側相對)以及電子電路300的輸出端子332(例如，V_OUT)。電容器334(例如，輸出電容器)的一側耦合到輸出端子332，且電容器334的相對側耦合到電子電路300的接地端子336(例如，GND或電路接地)。第二電阻器310的第二側(例如，與節點306的一側相對)也耦合到接地端子336。 Referring to the exemplary embodiment shown in FIG. 3, electronic circuit 300 (eg, an LDO regulator) includes a first amplifier 302 that is also an input stage that also acts as an error amplifier in circuit 300. In this exemplary embodiment, the first amplifier 302 is a voltage gain amplifier whose current bias level is controlled by its output voltage (eg, a self-biased amplifier). A first input voltage (eg, a reference voltage or Vref) is coupled to the non-inverting input 304 of the first amplifier 302. In some embodiments, the first input voltage is a fixed reference voltage generated within electronic circuit 300. In other embodiments, the first input voltage is a variable reference voltage (eg, changed by a digital/analog converter). In some embodiments, the first input voltage is generated external to electronic circuit 300 and coupled to input 304 by, for example, the pins of a semiconductor IC or wafer. A second input voltage (eg, a feedback voltage or Vfb) is coupled from a node 306 (eg, a resistive voltage divider) coupled to the first resistor 308 and the second resistor 310 to the inverting input 312 of the first amplifier 302, And the output voltage of the first amplifier 302 is coupled from the output 314 of the first amplifier 302 to the input 318 of the second amplifier 320 and also to the input 319 of the third amplifier 305. In this exemplary embodiment, the second amplifier 320 is an inverting transconductance amplifier that forms a drive current for the first current mirror output stage 322. More specifically, the output 324 of the second amplifier 320 is coupled to the gate and drain terminals of the first transistor device 326 of the first current mirror output stage 322, and is also coupled to the first current mirror output stage 322. The gate terminal of the second transistor device 328. The source terminals of the first transistor device 326 and the second transistor device 328 are coupled to an input terminal 330 (eg, V _IN ) of the electronic circuit 300. The drain terminal of second transistor device 328 is coupled to one side of first resistor 308 (e.g., opposite one side of node 306) and to output terminal 332 (e.g., V _OUT ) of electronic circuit 300. One side of capacitor 334 (eg, an output capacitor) is coupled to output terminal 332, and the opposite side of capacitor 334 is coupled to ground terminal 336 of electronic circuit 300 (eg, GND or circuit ground). The second side of the second resistor 310 (eg, opposite one side of the node 306) is also coupled to the ground terminal 336.

在此示例性實施方案中，電子電路300的輸出電流由第二電晶體裝置328產生，所述第二電晶體裝置通常是具有比第一電晶體裝置326的總閘極面積或寬度大了大約50到500倍的總閘極面積或寬度的大導通電晶體裝置。換句話說，由第一電晶體裝置326和第二電晶體裝置328形成的第一電流鏡322與其它常規電流鏡級相比具有相對較高的導通比。 In this exemplary embodiment, the output current of electronic circuit 300 is generated by second transistor device 328, which typically has a larger total gate area or width than first transistor device 326. 50 to 500 times the total gate area or width of the large conducting crystal device. In other words, the first current mirror 322 formed by the first transistor device 326 and the second transistor device 328 has a relatively high turn-on ratio compared to other conventional current mirror stages.

在此示例性實施方案中，第三放大器305也是反相跨導級，所述反相跨導級與第二放大器320的反相跨導級類似地起作用。第三放大器305的輸出325耦合到第二電流鏡級338的第三電晶體裝置307的閘極端 子，且還耦合到第二電流鏡級338的第四電晶體裝置309的閘極端子和汲極端子。第三電晶體裝置307的汲極端子耦合到第一放大器302的偏置電流輸入316。因此，第三放大器305通過第二電流鏡級338的第三電晶體裝置307和第四電晶體裝置309將偏置電流提供到第一放大器302的偏置電流輸入316，且所述偏置電流與由第二放大器320供應到第一電流鏡輸出級322的第一電晶體裝置326和第二電晶體裝置328的電流成比例。比例值是可通過調整第二放大器320的跨導值以及第二電流鏡級338的第三電晶體裝置307與第四電晶體裝置309之間的鏡比來設置的設計參數。應注意，跨導放大器320和305的跨導值可以是不同的，且第二電流鏡級338的電晶體的尺寸可比第一電流鏡級322的電晶體的尺寸小得多。 In this exemplary embodiment, the third amplifier 305 is also an inverting transconductance stage that functions similarly to the inverting transconductance stage of the second amplifier 320. The output 325 of the third amplifier 305 is coupled to the gate terminal of the third transistor device 307 of the second current mirror stage 338. And also coupled to the gate terminal and the NMOS terminal of the fourth transistor device 309 of the second current mirror stage 338. The 汲 terminal of the third transistor device 307 is coupled to the bias current input 316 of the first amplifier 302. Accordingly, the third amplifier 305 provides a bias current to the bias current input 316 of the first amplifier 302 through the third transistor device 307 and the fourth transistor device 309 of the second current mirror stage 338, and the bias current The current is proportional to the current supplied by the second amplifier 320 to the first transistor device 326 and the second transistor device 328 of the first current mirror output stage 322. The scale value is a design parameter that can be set by adjusting the transconductance value of the second amplifier 320 and the mirror ratio between the third transistor device 307 of the second current mirror stage 338 and the fourth transistor device 309. It should be noted that the transconductance values of transconductance amplifiers 320 and 305 can be different, and the size of the transistors of second current mirror stage 338 can be much smaller than the size of the transistors of first current mirror stage 322.

圖4是第四電子電路400的示意性方塊圖，所述第四電子電路可用於實施本發明的第四示例性實施方案。舉例來說，電子電路400可用於實施用於半導體結構中的增強型暫態響應的第四自我調整偏置LDO穩壓器，例如半導體IC、晶圓、晶片或晶粒。 4 is a schematic block diagram of a fourth electronic circuit 400 that can be used to implement a fourth exemplary embodiment of the present invention. For example, electronic circuit 400 can be used to implement a fourth self-adjusting bias LDO regulator, such as a semiconductor IC, wafer, wafer, or die, for enhanced transient response in a semiconductor structure.

參考圖4中所示的示例性實施方案，電子電路400(例如，LDO穩壓器)包括第一放大器402，所述第一放大器是也充當電路400中的誤差放大器的輸入級。在此示例性實施方案中，第一放大器402是電壓增益放大器，其電流偏置位準受其輸出電壓控制(例如，自偏置放大器)。第一輸入電壓(例如，參考電壓或Vref)耦合到第一放大器402的非反相輸入404。在一些實施方案中，第一輸入電壓是電子電路400內產生的固定參考電壓。在其它實施方案中，第一輸入電壓是可變的參考電壓(例如，由數位/類比轉換器改變)。在一些實施方案中，第一輸入電壓在電子電路400外部產生，通 過例如半導體IC或晶片的針腳耦合到輸入404。第二輸入電壓(例如，回饋電壓或Vfb)從連接到第一電阻器408和第二電阻器410的節點406(例如，電阻性分壓器)耦合到第一放大器402的反相輸入412，且第一放大器402的輸出電壓從第一放大器402的輸出414耦合到第二放大器420的輸入418，且還耦合到第三放大器405的輸入419。在此示例性實施方案中，第二放大器420是反相跨導放大器，所述第二放大器形成用於第一電流鏡輸出級422的驅動電流。更確切地說，第二放大器420的輸出424耦合到第一電晶體裝置426的汲極端子，且還耦合到緩衝放大器403的輸入401。緩衝放大器403的輸出405耦合到第一電晶體裝置426的閘極端子，且還連接到第一電流鏡輸出級422的第二電晶體裝置428的閘極端子。第一電晶體裝置426和第二電晶體裝置428的源極端子耦合到電子電路400的輸入端子430(例如，V_IN)。第二電晶體裝置428的汲極端子耦合到第一電阻器408的一側(例如，與節點406的一側相對)以及電子電路400的輸出端子432(例如，V_OUT)。電容器434(例如，輸出電容器)的一側耦合到輸出端子432，且電容器434的相對側耦合到電子電路400的接地端子436(例如，GND或電路接地)。第二電阻器410的第二側(例如，與節點406的一側相對)也耦合到接地端子436。 Referring to the exemplary embodiment shown in FIG. 4, electronic circuit 400 (eg, an LDO regulator) includes a first amplifier 402 that is also an input stage that also acts as an error amplifier in circuit 400. In this exemplary embodiment, the first amplifier 402 is a voltage gain amplifier whose current bias level is controlled by its output voltage (eg, a self-biased amplifier). A first input voltage (eg, a reference voltage or Vref) is coupled to the non-inverting input 404 of the first amplifier 402. In some embodiments, the first input voltage is a fixed reference voltage generated within electronic circuit 400. In other embodiments, the first input voltage is a variable reference voltage (eg, changed by a digital/analog converter). In some embodiments, the first input voltage is generated external to electronic circuit 400 and coupled to input 404 by, for example, a pin of a semiconductor IC or wafer. A second input voltage (eg, a feedback voltage or Vfb) is coupled to an inverting input 412 of the first amplifier 402 from a node 406 (eg, a resistive voltage divider) coupled to the first resistor 408 and the second resistor 410, And the output voltage of the first amplifier 402 is coupled from the output 414 of the first amplifier 402 to the input 418 of the second amplifier 420 and also to the input 419 of the third amplifier 405. In this exemplary embodiment, the second amplifier 420 is an inverting transconductance amplifier that forms a drive current for the first current mirror output stage 422. More specifically, the output 424 of the second amplifier 420 is coupled to the delta terminal of the first transistor device 426 and is also coupled to the input 401 of the buffer amplifier 403. The output 405 of the buffer amplifier 403 is coupled to the gate terminal of the first transistor device 426 and is also coupled to the gate terminal of the second transistor device 428 of the first current mirror output stage 422. The source terminals of the first transistor device 426 and the second transistor device 428 are coupled to an input terminal 430 (eg, V _IN ) of the electronic circuit 400. The 汲 terminal of the second transistor device 428 is coupled to one side of the first resistor 408 (eg, opposite one side of the node 406) and the output terminal 432 (eg, V _OUT ) of the electronic circuit 400. One side of capacitor 434 (eg, an output capacitor) is coupled to output terminal 432, and the opposite side of capacitor 434 is coupled to ground terminal 436 (eg, GND or circuit ground) of electronic circuit 400. The second side of the second resistor 410 (eg, opposite one side of the node 406) is also coupled to the ground terminal 436.

在此示例性實施方案中，電子電路400的輸出電流由第一電流鏡輸出級422的第二電晶體裝置428產生。第二電晶體裝置428通常是具有比第一電晶體裝置426的總閘極面積或寬度大了大約50到500倍的總閘極面積或寬度的大導通電晶體裝置。換句話說，由第一電晶體裝置426和第二電晶體裝置428形成的第一電流鏡422與其它常規電流鏡級相比，可具有相對較高的導通比。 In this exemplary embodiment, the output current of electronic circuit 400 is generated by second transistor device 428 of first current mirror output stage 422. The second transistor device 428 is typically a large conductive crystal device having a total gate area or width that is about 50 to 500 times greater than the total gate area or width of the first transistor device 426. In other words, the first current mirror 422 formed by the first transistor device 426 and the second transistor device 428 can have a relatively high conduction ratio compared to other conventional current mirror stages.

在這個示例性實施方案中，第三放大器405也是反相跨導級，所述反相跨導級與第二放大器420的反相跨導級類似地起作用。第三放大器405的輸出425耦合到第二電流鏡級438的第三電晶體裝置407的閘極端子，且還耦合到第二電流鏡級438的第四電晶體裝置409的閘極端子和源極端子。第三電晶體裝置407的汲極端子耦合到第一放大器402的偏置電流輸入416。因此，第三放大器405通過第二電流鏡級438的第三電晶體裝置407和第四電晶體裝置409將偏置電流提供到第一放大器402的偏置電流輸入416，且所述偏置電流與由第二放大器420供應到第一電流鏡輸出級422的第一電晶體裝置426和第二電晶體裝置428的電流成比例。比例值是可通過調整第二放大器420的跨導值以及第二電流鏡級438的第三電晶體裝置407與第四電晶體裝置409之間的鏡比來設置的設計參數。 In this exemplary embodiment, the third amplifier 405 is also an inverting transconductance stage that functions similarly to the inverting transconductance stage of the second amplifier 420. The output 425 of the third amplifier 405 is coupled to the gate terminal of the third transistor device 407 of the second current mirror stage 438 and also to the gate terminal and source of the fourth transistor device 409 of the second current mirror stage 438. Extreme. The drain terminal of the third transistor device 407 is coupled to the bias current input 416 of the first amplifier 402. Accordingly, the third amplifier 405 provides a bias current to the bias current input 416 of the first amplifier 402 through the third transistor device 407 and the fourth transistor device 409 of the second current mirror stage 438, and the bias current The current is proportional to the current supplied by the second amplifier 420 to the first transistor device 426 and the second transistor device 428 of the first current mirror output stage 422. The scale value is a design parameter that can be set by adjusting the transconductance value of the second amplifier 420 and the mirror ratio between the third transistor device 407 of the second current mirror stage 438 and the fourth transistor device 409.

注意，在所示的示例性實施方案中，耦合在第二放大器420的輸出424與第一電晶體裝置426和第二電晶體裝置428的閘極端子之間的緩衝放大器403的組合用於形成經緩衝電流鏡輸出級422。換句話說，例如，緩衝放大器403充當緩衝放大器或電壓跟隨器以驅動第一電流鏡級422的第二電晶體裝置428的相對較大的閘極電容。因此，緩衝放大器403用於增加電流鏡輸出級422的總頻寬，從而超過電子電路300的電流鏡輸出級322的總頻寬。應注意，跨導放大器420和405的跨導值可以是不同的，且第二電流鏡級438的電晶體的尺寸可比第一電流鏡級422的電晶體的尺寸小得多。 Note that in the illustrated exemplary embodiment, a combination of buffer amplifiers 403 coupled between the output 424 of the second amplifier 420 and the gate terminals of the first transistor device 426 and the second transistor device 428 is used to form The current mirror stage 422 is buffered. In other words, for example, the buffer amplifier 403 acts as a buffer amplifier or voltage follower to drive a relatively large gate capacitance of the second transistor device 428 of the first current mirror stage 422. Therefore, the buffer amplifier 403 is used to increase the total bandwidth of the current mirror output stage 422, thereby exceeding the total bandwidth of the current mirror output stage 322 of the electronic circuit 300. It should be noted that the transconductance values of transconductance amplifiers 420 and 405 can be different, and the size of the transistors of second current mirror stage 438 can be much smaller than the size of the transistors of first current mirror stage 422.

圖5是示例性半導體結構500的示意性電路圖，所述半導體結構包括可用於實施電子電路200或電子電路400的電子電路(例如，用於增強型暫態響應的自我調整偏置LDO穩壓器)。舉例來說，半導體結構500 可為半導體IC、晶圓、晶片或晶粒。在此實施方案中，緩衝放大器包括在電路500中，以例如產生經緩衝電流鏡輸出級，如圖2和圖4中所示的經緩衝電流鏡輸出級222、422。 5 is a schematic circuit diagram of an exemplary semiconductor structure 500 including electronic circuitry that can be used to implement electronic circuit 200 or electronic circuit 400 (eg, a self-regulating bias LDO regulator for enhanced transient response) ). For example, semiconductor structure 500 It can be a semiconductor IC, wafer, wafer or die. In this embodiment, a buffer amplifier is included in circuit 500 to, for example, generate a buffered current mirror output stage, such as buffered current mirror output stages 222, 422 as shown in FIGS. 2 and 4.

參考圖5中所示的示例性實施方案(並且例如，將圖5中的結構與圖2和圖4中所示的結構進行比較)，半導體結構500包括第一放大器502(例如，由包括電晶體M1到M4的虛線指示)，所述第一放大器是也充當誤差放大器的輸入級。在此示例性實施方案中，第一放大器502是電壓增益放大器，其電流偏置位準受其輸出電壓控制(例如，自偏置放大器)。電晶體501耦合到第一放大器502，且響應耦合到電晶體501的閘極端子的輸入電壓(例如，BIAS)，電晶體501產生固定偏置電流，且因此在例如輕負載處為第一放大器502提供基準偏置電流。在一些實施方案中，輸入電壓(BIAS)是半導體結構500內產生的固定電壓。在其它實施方案中，輸入電壓(BIAS)是可變的參考電壓(例如，由數位/類比轉換器改變)。在一些實施方案中，輸入電壓(BIAS)在半導體結構500外部產生，並通過例如半導體IC或晶片的針腳耦合到電晶體501的閘極端子。 Referring to the exemplary embodiment shown in FIG. 5 (and, for example, comparing the structure in FIG. 5 with the structure shown in FIGS. 2 and 4), the semiconductor structure 500 includes a first amplifier 502 (eg, including The dashed lines of crystals M1 through M4 indicate) that the first amplifier is also an input stage that also acts as an error amplifier. In this exemplary embodiment, the first amplifier 502 is a voltage gain amplifier whose current bias level is controlled by its output voltage (eg, a self-biased amplifier). The transistor 501 is coupled to the first amplifier 502, and in response to an input voltage (e.g., BIAS) coupled to the gate terminal of the transistor 501, the transistor 501 generates a fixed bias current, and thus is, for example, a first amplifier at a light load. The 502 provides a reference bias current. In some embodiments, the input voltage (BIAS) is a fixed voltage generated within the semiconductor structure 500. In other embodiments, the input voltage (BIAS) is a variable reference voltage (eg, changed by a digital/analog converter). In some embodiments, an input voltage (BIAS) is generated external to the semiconductor structure 500 and coupled to the gate terminal of the transistor 501 by, for example, a pin of a semiconductor IC or wafer.

第一輸入電壓(例如，參考電壓或Vref)耦合到第一放大器502的非反相輸入504(電晶體M1的閘極)。在一些實施方案中，第一輸入電壓是半導體結構500內產生的固定參考電壓。在其它實施方案中，第一輸入電壓在半導體結構500外部產生，並通過例如半導體IC或晶片的針腳耦合到輸入504。第二輸入電壓(例如，回饋電壓或Vfb)從連接到第一電阻器508和第二電阻器510的節點506(例如，電阻性分壓器)耦合到第一放大器502的反相輸入512(例如，電晶體M2的閘極)。第一放大器502的輸出電壓從 第一放大器的輸出514耦合到第二放大器520(電晶體M9)的閘極端子(輸入)，且還耦合到第三放大器505(電晶體M5)的閘極端子(輸入)。 A first input voltage (eg, a reference voltage or Vref) is coupled to the non-inverting input 504 of the first amplifier 502 (the gate of the transistor M1). In some implementations, the first input voltage is a fixed reference voltage generated within the semiconductor structure 500. In other embodiments, the first input voltage is generated external to the semiconductor structure 500 and coupled to the input 504 by, for example, a pin of a semiconductor IC or wafer. A second input voltage (eg, a feedback voltage or Vfb) is coupled from a node 506 (eg, a resistive voltage divider) coupled to the first resistor 508 and the second resistor 510 to an inverting input 512 of the first amplifier 502 ( For example, the gate of transistor M2). The output voltage of the first amplifier 502 is from The output 514 of the first amplifier is coupled to the gate terminal (input) of the second amplifier 520 (transistor M9) and is also coupled to the gate terminal (input) of the third amplifier 505 (transistor M5).

在此示例性實施方案中，第二放大器520是反相跨導放大器，所述第二放大器形成用於第一電流鏡輸出級522的驅動電流。更確切地說，第二放大器520的輸出(汲極端子)耦合到緩衝放大器503(例如，由包括電晶體M10到M13的虛線指示)的輸入，且還耦合到第一電晶體裝置526的汲極端子(經由連接有二極體的電晶體M10、M12)。緩衝放大器503的輸出515耦合到第一電晶體裝置526的閘極端子，且還連接到第一電流鏡輸出級522的第二電晶體裝置528的閘極端子。第一電晶體裝置526和第二電晶體裝置528的源極端子耦合到半導體結構500的輸入端子530(例如，V_IN)。第二電晶體裝置528的汲極端子耦合到第一電阻器508的一側(例如，與節點506的一側相對)以及半導體結構500的輸出端子532(例如，V_OUT)。電容器534(例如，輸出電容器)的一側耦合到輸出端子532，且電容器534的相對側耦合到半導體結構500的接地端子536(例如，GND或電路接地)。第二電阻器510的第二側(例如，與節點506的一側相對)也耦合到接地端子536。 In this exemplary embodiment, the second amplifier 520 is an inverting transconductance amplifier that forms a drive current for the first current mirror output stage 522. More specifically, the output of the second amplifier 520 (汲 terminal) is coupled to the input of the buffer amplifier 503 (eg, indicated by the dashed lines including transistors M10 through M13) and is also coupled to the first transistor device 526. An extreme (via a transistor M10, M12 to which a diode is connected). The output 515 of the buffer amplifier 503 is coupled to the gate terminal of the first transistor device 526 and also to the gate terminal of the second transistor device 528 of the first current mirror output stage 522. The source terminals of the first transistor device 526 and the second transistor device 528 are coupled to an input terminal 530 (eg, V _IN ) of the semiconductor structure 500. The drain terminal of the second transistor device 528 is coupled to one side of the first resistor 508 (e.g., opposite one side of the node 506) and the output terminal 532 (e.g., V _OUT ) of the semiconductor structure 500. One side of capacitor 534 (eg, an output capacitor) is coupled to output terminal 532, and the opposite side of capacitor 534 is coupled to ground terminal 536 of semiconductor structure 500 (eg, GND or circuit ground). The second side of the second resistor 510 (eg, opposite one side of the node 506) is also coupled to the ground terminal 536.

在此示例性實施方案中，半導體結構500的輸出電流由第一電流鏡輸出級522的第二電晶體裝置528產生。第二電晶體裝置528通常是具有可能比第一電晶體裝置526的總閘極面積或寬度大了大約50到500倍的總閘極面積或寬度的大導通電晶體裝置。換句話說，由第一電晶體裝置526和第二電晶體裝置528形成的第一電流鏡522與其它常規電流鏡級相比，可具有相對較高的導通比。 In this exemplary embodiment, the output current of the semiconductor structure 500 is generated by the second transistor device 528 of the first current mirror output stage 522. The second transistor device 528 is typically a large conductive crystal device having a total gate area or width that may be about 50 to 500 times greater than the total gate area or width of the first transistor device 526. In other words, the first current mirror 522 formed by the first transistor device 526 and the second transistor device 528 can have a relatively high turn-on ratio as compared to other conventional current mirror stages.

在此示例性實施方案中，第三放大器505也是反相跨導級， 所述反相跨導級與第二放大器520的反相跨導級類似地起作用。第三放大器505的輸出(汲極端子)耦合到第二電流鏡級538(例如，由包括電晶體M5到M7的虛線指示)的第三電晶體裝置507的閘極端子，且還耦合到第二電流鏡級538的第四電晶體裝置509的閘極端子和汲極端子。第三電晶體裝置507的汲極端子耦合到第一放大器502的偏置電流輸入(M1、M2的源極)。因此，第三放大器505通過第二電流鏡級538的第三電晶體裝置507和第四電晶體裝置509將偏置電流提供到第一放大器502的偏置電流輸入(M1、M2的源極)，且所述偏置電流與由第二放大器520供應到第一電流鏡輸出級522的第一電晶體裝置526和第二電晶體裝置528的電流成比例。比例值是可通過調整第二放大器520的跨導值(例如，通過調整電晶體M5相對於電晶體M9的尺寸)以及第二電流鏡級538的第三電晶體裝置507與第四電晶體裝置509之間的鏡比來設置的設計參數。應注意，跨導放大器520和505的跨導值可以是不同的，且第二電流鏡級538的電晶體的尺寸可比第一電流鏡級522的電晶體的尺寸小得多。 In this exemplary embodiment, the third amplifier 505 is also an inverting transconductance stage, The inverting transconductance stage functions similarly to the inverting transconductance stage of the second amplifier 520. The output of the third amplifier 505 (汲 terminal) is coupled to the second current mirror stage 538 (eg, indicated by the dashed line including transistors M5 through M7) and is also coupled to the gate terminal of the third transistor device 507. The gate terminal and the 汲 terminal of the fourth transistor device 509 of the second current mirror stage 538. The 汲 terminal of the third transistor device 507 is coupled to the bias current input of the first amplifier 502 (the source of M1, M2). Therefore, the third amplifier 505 supplies the bias current to the bias current input of the first amplifier 502 through the third transistor device 507 and the fourth transistor device 509 of the second current mirror stage 538 (sources of M1, M2) And the bias current is proportional to the current supplied by the second amplifier 520 to the first transistor device 526 and the second transistor device 528 of the first current mirror output stage 522. The scale value is a third transistor device 507 and a fourth transistor device that can be adjusted by adjusting the transconductance value of the second amplifier 520 (eg, by adjusting the size of the transistor M5 relative to the transistor M9) and the second current mirror stage 538. Between the 509 mirror to set the design parameters. It should be noted that the transconductance values of transconductance amplifiers 520 and 505 can be different, and the size of the transistors of second current mirror stage 538 can be much smaller than the size of the transistors of first current mirror stage 522.

注意，在所示的示例性實施方案中，耦合在第二放大器520的輸出(汲極端子)與第一電晶體526和第二電晶體528的閘極端子之間的緩衝放大器503的組合用於形成經緩衝電流鏡輸出級522。換句話說，例如，緩衝放大器503充當緩衝放大器或電壓跟隨器，以驅動第一電流鏡輸出級522的第二電晶體裝置528的相對較大的閘極電容。因此，緩衝放大器503用於增加電流鏡輸出級522的總頻寬，從而超過其它未經緩衝電流鏡輸出級(例如，圖3中所示的電流鏡輸出級322)的總頻寬。 Note that in the illustrated exemplary embodiment, the combination of the buffer amplifier 503 coupled between the output of the second amplifier 520 (the 汲 terminal) and the gate terminal of the first transistor 526 and the second transistor 528 is used. A buffered current mirror output stage 522 is formed. In other words, for example, the buffer amplifier 503 acts as a buffer amplifier or voltage follower to drive the relatively large gate capacitance of the second transistor device 528 of the first current mirror output stage 522. Thus, buffer amplifier 503 is used to increase the total bandwidth of current mirror output stage 522 beyond the total bandwidth of other unbuffered current mirror output stages (e.g., current mirror output stage 322 shown in FIG. 3).

在操作中，參考圖5，當半導體結構500被例如實施為LDO 穩壓器時，考慮以下兩種輸出條件或狀態：1)通過輸出端子532(V_OUT)的負載電流是穩定的(DC)；以及2)通過輸出端子532(V_OUT)的負載電流突然增加。舉例來說，在穩態操作中，半導體結構500基本上利用三個電流鏡級運行：1)由電晶體526和528形成的電流鏡對；2)由電晶體520和505形成的電流鏡對(即，M9和M5)；以及3)由電晶體509和507形成的電流鏡對。這三個電流鏡級產生尾電流並(通過電晶體507)將尾電流耦合到差分電晶體對M1和M2的源極端子(例如，第一放大器502的偏置電流輸入)。此尾電流的值通常被設計成通過第一電流鏡輸出級522的電晶體528的輸出電流的一小部分(因此第二電流鏡級538的電晶體的尺寸通常是第一電流鏡級522的電晶體的尺寸的一小部分)。在穩態操作中，半導體結構500的整體回饋回路處於平衡狀態，且節點506處的回饋電壓Vfb大致上等於參考電壓Vref。如此，當輸出電流的值相對較小時(例如，穩態)，電晶體501響應於施加到電晶體501的閘極的電壓(BIAS)的值而產生第一放大器502的靜態偏置電流，並且由電晶體507產生的偏置電流可能很小，甚至是可忽略的。 In operation, referring to FIG. 5, when the semiconductor structure 500 is implemented, for example, as an LDO regulator, consider the following two output conditions or states: 1) The load current through the output terminal 532 (V _OUT ) is stable (DC) And 2) the load current through the output terminal 532 (V _OUT ) suddenly increases. For example, in steady state operation, semiconductor structure 500 operates substantially with three current mirror stages: 1) a current mirror pair formed by transistors 526 and 528; 2) a current mirror pair formed by transistors 520 and 505 (ie, M9 and M5); and 3) current mirror pairs formed by transistors 509 and 507. The three current mirror stages produce a tail current and (via transistor 507) couple the tail current to the source terminals of the differential transistor pair M1 and M2 (eg, the bias current input of the first amplifier 502). The value of this tail current is typically designed to pass a fraction of the output current of the transistor 528 of the first current mirror output stage 522 (so the size of the transistor of the second current mirror stage 538 is typically the first current mirror stage 522 A small part of the size of the transistor). In steady state operation, the overall feedback loop of semiconductor structure 500 is in an equilibrium state, and the feedback voltage Vfb at node 506 is substantially equal to reference voltage Vref. As such, when the value of the output current is relatively small (eg, steady state), the transistor 501 generates a static bias current of the first amplifier 502 in response to the value of the voltage (BIAS) applied to the gate of the transistor 501, And the bias current generated by the transistor 507 may be small or even negligible.

在第二操作狀態中，通過輸出端子532(V_OUT)的負載電流突然增加。在半導體結構500的整體回饋回路可對此狀態改變作出反應之前，額外的負載電流使輸出電容器534放電，且進而降低輸出電壓V_OUT的值。輸出電壓的此降低減小了節點506處的回饋電壓Vfb的值，所述回饋電壓是施加到第一放大器502的電晶體M2的閘極端子的電壓。電晶體M2的閘極電壓的所得降低使到差分對電晶體M1和M2的輸入電壓不平衡，從而增加通過電晶體M2的電流，且進而增加施加到電晶體505和520的閘極的電壓。電晶體505的所得的增加的漏電流通過電流鏡電晶體對509和507回饋回第 一放大器502的偏置電流輸入，從而又增加了正產生的尾電流的值。尾電流的此增加增大可通過電晶體M2的電流，且進而以正(增加的)速率增加電晶體505和520的閘極端子處的電壓。同時，通過電晶體520的增加的電流給輸出電晶體528的大閘極電容充電(例如，通過緩衝放大器503)，直到電晶體528的汲極電流足夠供應負載電流為止。這時，輸出電壓V_OUT的量級返回到所增加的電流給輸出電容器534充電時的穩態。如此，第一放大器502的自我調整偏置配置(輸入級)使第一級的電流位準增加到整體回饋回路的平衡位準之上，以便更快地給輸出電晶體528的閘極電容充電。因此，達到新的穩態條件，自我調整偏置電流達到新的平衡值，所述平衡值由電晶體對528和526、520和505、以及509和507的閘極面積(或寬度)比明確定義。 In the second operational state, the load current through the output terminal 532 (V _OUT ) suddenly increases. The additional load current discharges the output capacitor 534 and further reduces the value of the output voltage _VOUT before the overall feedback loop of the semiconductor structure 500 can react to this state change. This decrease in output voltage reduces the value of the feedback voltage Vfb at node 506, which is the voltage applied to the gate terminal of transistor M2 of first amplifier 502. The resulting decrease in the gate voltage of transistor M2 unbalances the input voltages to differential pair transistors M1 and M2, thereby increasing the current through transistor M2 and, in turn, increasing the voltage applied to the gates of transistors 505 and 520. The resulting increased leakage current of transistor 505 is fed back to the bias current input of first amplifier 502 by current mirror transistor pairs 509 and 507, which in turn increases the value of the tail current being generated. This increase in tail current increases the current through the transistor M2 and, in turn, increases the voltage at the gate terminals of the transistors 505 and 520 at a positive (increased) rate. At the same time, the large gate capacitance of output transistor 528 is charged through the increased current of transistor 520 (e.g., through buffer amplifier 503) until the gate current of transistor 528 is sufficient to supply the load current. At this time, the magnitude of the output voltage V _OUT returns to the steady state when the increased current charges the output capacitor 534. As such, the self-adjusting bias configuration (input stage) of the first amplifier 502 increases the current level of the first stage above the equilibrium level of the overall feedback loop to more quickly charge the gate capacitance of the output transistor 528. . Thus, reaching a new steady state condition, the self-adjusting bias current reaches a new equilibrium value that is clear by the gate area (or width) ratio of transistor pairs 528 and 526, 520 and 505, and 509 and 507. definition.

總之，根據本申請的教示，導通電晶體528的相對較大閘極電容在自我調整偏置回路外部。自我調整偏置回路通過增加自我調整偏置電流的值來響應所增加的負載電流，以便更快地給導通電晶體528的閘極電容充電。因為導通電晶體528的閘極電容在自我調整偏置回路的外部，所以自我調整偏置回路的響應時間明顯快於常規LDO穩壓器中的常規偏置回路的響應時間，且利用半導體結構500實施的LDO穩壓器的所得的輸出電壓跌落明顯小於常規LDO穩壓器的輸出電壓跌落。 In summary, in accordance with the teachings of the present application, the relatively large gate capacitance of the conductive crystal 528 is external to the self-adjusting bias loop. The self-adjusting bias loop responds to the increased load current by increasing the value of the self-adjusting bias current to more quickly charge the gate capacitance of the conductive crystal 528. Because the gate capacitance of the conductive crystal 528 is external to the self-adjusting bias loop, the response time of the self-regulating bias loop is significantly faster than the response time of a conventional bias loop in a conventional LDO regulator, and the semiconductor structure 500 is utilized. The resulting output voltage drop of the implemented LDO regulator is significantly less than the output voltage drop of a conventional LDO regulator.

注意，半導體結構500的示例性實施方案中使用正回饋。因此，偏置電流中所得的增加在第一放大器502的操作點中發生改變，從而又增加了所產生的自我調整偏置電流。在由半導體結構500描繪的示例性實施方案中，正回路回饋增益被設計成小於1，以確保自我調整偏置回路的 穩定性。舉例來說，選擇電晶體尺寸設計以使得自我調整回饋電晶體505以是電晶體M3和M4的電流密度的兩倍的電流密度操作。因此，由於跨導/汲極電流比(GM/Id)隨著電流密度而減小，小於1的回路增益得以確保。 Note that positive feedback is used in an exemplary embodiment of semiconductor structure 500. Thus, the resulting increase in bias current changes in the operating point of the first amplifier 502, which in turn increases the resulting self-regulating bias current. In an exemplary embodiment depicted by semiconductor structure 500, the positive loop feedback gain is designed to be less than one to ensure self-adjusting bias loop stability. For example, the transistor size design is chosen such that the self-adjusting feedback transistor 505 operates at a current density that is twice the current density of the transistors M3 and M4. Therefore, since the transconductance/drain current ratio (GM/Id) decreases with current density, a loop gain of less than 1 is ensured.

圖6是示例性半導體結構600的示意性電路圖，所述半導體結構包括可用於實施圖1和圖3中所示的電子電路100或電子電路300的電子電路(例如，作為用於增強型暫態響應的自我調整偏置LDO穩壓器)。舉例來說，半導體結構600可以是半導體IC、晶圓、晶片或晶粒。注意，半導體結構600的結構和操作大致上類似於圖5中所示的半導體結構500的結構和操作，但緩衝放大器級(例如，圖5中的503)不包括在半導體結構600中。 6 is a schematic circuit diagram of an exemplary semiconductor structure 600 including electronic circuitry that can be used to implement the electronic circuit 100 or electronic circuit 300 shown in FIGS. 1 and 3 (eg, as an enhanced transient) Responsive self-adjusting bias LDO regulator). For example, semiconductor structure 600 can be a semiconductor IC, wafer, wafer, or die. Note that the structure and operation of the semiconductor structure 600 is substantially similar to the structure and operation of the semiconductor structure 500 shown in FIG. 5, but a buffer amplifier stage (eg, 503 in FIG. 5) is not included in the semiconductor structure 600.

參考圖6中所示的示例性實施方案(且例如，將圖6中的結構與圖1和圖3中所示的結構進行比較)，半導體結構600包括第一放大器602(例如，由包括電晶體M1到M4的虛線指示)，所述第一放大器是也充當誤差放大器的輸入級。在此示例性實施方案中，第一放大器602是電壓增益放大器，其電流偏置位準受其輸出電壓控制(例如，自偏置放大器)。電晶體601耦合到第一放大器602，且響應耦合到電晶體601的閘極端子的輸入電壓(例如，BIAS)，電晶體601產生固定偏置電流，且因此在例如輕負載處為第一放大器602提供基準偏置電流。在一些實施方案中，輸入電壓(BIAS)是半導體結構600內產生的固定電壓。在其它實施方案中，輸入電壓(BIAS)是可變的參考電壓(例如，由數位/類比轉換器改變)。在一些實施方案中，輸入電壓(BIAS)在半導體結構600外部產生，並通過例如半導體IC或晶片的針腳耦合到電晶體601的閘極端子。 Referring to the exemplary embodiment shown in FIG. 6 (and, for example, comparing the structure in FIG. 6 with the structure shown in FIGS. 1 and 3), the semiconductor structure 600 includes a first amplifier 602 (eg, including The dashed lines of crystals M1 through M4 indicate) that the first amplifier is also an input stage that also acts as an error amplifier. In this exemplary embodiment, the first amplifier 602 is a voltage gain amplifier whose current bias level is controlled by its output voltage (eg, a self-biased amplifier). The transistor 601 is coupled to the first amplifier 602 and, in response to an input voltage (e.g., BIAS) coupled to the gate terminal of the transistor 601, the transistor 601 generates a fixed bias current, and thus is, for example, a first amplifier at a light load 602 provides a reference bias current. In some embodiments, the input voltage (BIAS) is a fixed voltage generated within the semiconductor structure 600. In other embodiments, the input voltage (BIAS) is a variable reference voltage (eg, changed by a digital/analog converter). In some embodiments, an input voltage (BIAS) is generated external to semiconductor structure 600 and coupled to a gate terminal of transistor 601 by, for example, a pin of a semiconductor IC or wafer.

第一輸入電壓(例如，參考電壓或Vref)耦合到第一放大器602的非反相輸入604(電晶體M1的閘極)。在一些實施方案中，第一輸入電壓是半導體結構600內產生的固定參考電壓。在其它實施方案中，第一輸入電壓在半導體結構600外部產生，並通過例如半導體IC或晶片的針腳耦合到輸入604。第二輸入電壓(例如，回饋電壓或Vfb)從連接到第一電阻器608和第二電阻器610的節點606(例如，電阻性分壓器)耦合到第一放大器602的反相輸入612(電晶體M2的閘極)。第一放大器602的輸出電壓從第一放大器602的輸出614耦合到第二放大器620(電晶體M9)的閘極端子(輸入)，且還耦合到第三放大器605(電晶體M5)的閘極端子(輸入)。 A first input voltage (eg, a reference voltage or Vref) is coupled to the non-inverting input 604 of the first amplifier 602 (the gate of the transistor M1). In some implementations, the first input voltage is a fixed reference voltage generated within the semiconductor structure 600. In other embodiments, the first input voltage is generated external to the semiconductor structure 600 and coupled to the input 604 by, for example, a pin of a semiconductor IC or wafer. A second input voltage (eg, a feedback voltage or Vfb) is coupled from a node 606 (eg, a resistive voltage divider) coupled to the first resistor 608 and the second resistor 610 to an inverting input 612 of the first amplifier 602 ( Gate of transistor M2). The output voltage of the first amplifier 602 is coupled from the output 614 of the first amplifier 602 to the gate terminal (input) of the second amplifier 620 (the transistor M9) and also to the gate terminal of the third amplifier 605 (the transistor M5). Child (input).

在此示例性實施方案中，第二放大器620是反相跨導放大器，所述第二放大器形成用於第一電流鏡輸出級622的驅動電流。更確切地說，第二放大器620的輸出(汲極端子)耦合到第一電晶體裝置626的汲極端子，且還耦合到第一電流鏡輸出級622的第一電晶體裝置626和第二電晶體裝置628的閘極端子。第一電晶體裝置626和第二電晶體裝置628的源極端子耦合到半導體結構600的輸入端子630(例如，V_IN)。第二電晶體裝置628的汲極端子耦合到第一電阻器608的一側(例如，與節點606的一側相對)以及半導體結構600的輸出端子632(例如，V_OUT)。電容器634(例如，輸出電容器)的一側耦合到輸出端子632，且電容器634的相對側耦合到半導體結構600的接地端子636(例如，GND或電路接地)。第二電阻器610的第二側(例如，與節點606的一側相對)也耦合到接地端子636。 In this exemplary embodiment, the second amplifier 620 is an inverting transconductance amplifier that forms a drive current for the first current mirror output stage 622. More specifically, the output of the second amplifier 620 (the 汲 terminal) is coupled to the 汲 terminal of the first transistor device 626 and is also coupled to the first transistor device 626 and the second of the first current mirror output stage 622. The gate terminal of the transistor device 628. The source terminals of the first transistor device 626 and the second transistor device 628 are coupled to an input terminal 630 (eg, V _IN ) of the semiconductor structure 600. The drain terminal of the second transistor device 628 is coupled to one side of the first resistor 608 (e.g., opposite one side of the node 606) and to the output terminal 632 (e.g., V _OUT ) of the semiconductor structure 600. One side of capacitor 634 (eg, an output capacitor) is coupled to output terminal 632, and the opposite side of capacitor 634 is coupled to ground terminal 636 (eg, GND or circuit ground) of semiconductor structure 600. The second side of the second resistor 610 (eg, opposite one side of the node 606) is also coupled to the ground terminal 636.

在此示例性實施方案中，半導體結構600的輸出電流由第一電流鏡輸出級622的第二電晶體裝置628產生。第二電晶體裝置628通常是 具有可能比第一電晶體裝置626的總閘極面積或寬度大了大約50到500倍的總閘極面積或寬度的大導通電晶體裝置。換句話說，由第一電晶體裝置626和第二電晶體裝置628形成的第一電流鏡輸出級622與其它常規電流鏡級相比，可具有相對較高的導通比。 In this exemplary embodiment, the output current of the semiconductor structure 600 is generated by the second transistor device 628 of the first current mirror output stage 622. The second transistor device 628 is typically A large conducting crystal device having a total gate area or width that may be about 50 to 500 times larger than the total gate area or width of the first transistor device 626. In other words, the first current mirror output stage 622 formed by the first transistor device 626 and the second transistor device 628 can have a relatively high turn-on ratio as compared to other conventional current mirror stages.

在此示例性實施方案中，第三放大器605也是反相跨導級，所述反相跨導級與第二放大器620的反相跨導級類似地起作用。第三放大器605的輸出(汲極端子)耦合到第二電流鏡級638(例如，由包括電晶體M5到M7的虛線指示)的第三電晶體裝置607的閘極端子，且還耦合到第二電流鏡級638的第四電晶體裝置609的閘極端子和汲極端子。第三電晶體裝置607的汲極端子耦合到第一放大器602的偏置電流輸入(M1、M2的源極)。因此，第三放大器605通過第二電流鏡級638的第三電晶體裝置607和第四電晶體裝置609將偏置電流提供到第一放大器602的偏置電流輸入(M1、M2的源極)，且所述偏置電流與由第二放大器620供應到第一電流鏡輸出級622的第一電晶體裝置626和第二電晶體裝置628的電流成比例。比例值是可通過調整第二放大器620的跨導值以及第二電流鏡級638的第三電晶體裝置607與第四電晶體裝置609之間的鏡比來設置的設計參數。 In this exemplary embodiment, the third amplifier 605 is also an inverting transconductance stage that functions similarly to the inverting transconductance stage of the second amplifier 620. The output of the third amplifier 605 (汲 terminal) is coupled to the second current mirror stage 638 (eg, indicated by the dashed line including transistors M5 through M7) and is also coupled to the gate terminal of the third transistor device 607. The gate terminal and the 汲 terminal of the fourth transistor device 609 of the second current mirror stage 638. The 汲 terminal of the third transistor device 607 is coupled to the bias current input of the first amplifier 602 (the source of M1, M2). Therefore, the third amplifier 605 supplies the bias current to the bias current input of the first amplifier 602 through the third transistor device 607 and the fourth transistor device 609 of the second current mirror stage 638 (the source of the M1, M2) And the bias current is proportional to the current supplied by the second amplifier 620 to the first transistor device 626 and the second transistor device 628 of the first current mirror output stage 622. The scale value is a design parameter that can be set by adjusting the transconductance value of the second amplifier 620 and the mirror ratio between the third transistor device 607 of the second current mirror stage 638 and the fourth transistor device 609.

在操作中，參考圖6，當將半導體結構600實施為例如LDO穩壓器時，考慮以下兩種輸出條件或狀態：1)通過輸出端子632(V_OUT)的負載電流是穩定的(DC)；以及2)通過輸出端子632(V_OUT)的負載電流突然增加。舉例來說，在穩態操作中，半導體結構600基本上利用三個電流鏡級運行：1)由電晶體626和628形成的電流鏡對；2)由電晶體620和605形成的電流鏡對(M9和M5)；以及3)由電晶體609和607形成的電流鏡對。這三個電流 鏡級產生尾電流，並(通過電晶體607)將尾電流耦合到差分電晶體對M1和M2(例如，第一放大器602的偏置電流輸入)。將此尾電流的值設計成通過第一電流鏡輸出級622的電晶體628的輸出電流的一小部分。在穩態操作中，半導體結構600的整體回饋回路處於平衡狀態，且節點606處的回饋電壓Vfb大致上等於參考電壓Vref。如此，當輸出電流的值相對較小時(例如，穩態)，電晶體601響應於施加到電晶體601的閘極的電壓(BIAS)的值而產生第一放大器602的靜態偏置電流，且由電晶體607產生的偏置電流可能很小，甚至是可忽略的。 In operation, referring to FIG. 6, when the semiconductor structure 600 is implemented as, for example, an LDO regulator, the following two output conditions or states are considered: 1) The load current through the output terminal 632 (V _OUT ) is stable (DC) And 2) the load current through the output terminal 632 (V _OUT ) suddenly increases. For example, in steady state operation, semiconductor structure 600 operates substantially with three current mirror stages: 1) a current mirror pair formed by transistors 626 and 628; 2) a current mirror pair formed by transistors 620 and 605 (M9 and M5); and 3) current mirror pairs formed by transistors 609 and 607. The three current mirror stages produce a tail current and couple (via transistor 607) the tail current to the differential transistor pair M1 and M2 (eg, the bias current input of the first amplifier 602). The value of this tail current is designed to pass a fraction of the output current of the transistor 628 of the first current mirror output stage 622. In steady state operation, the overall feedback loop of semiconductor structure 600 is in an equilibrium state, and the feedback voltage Vfb at node 606 is substantially equal to the reference voltage Vref. As such, when the value of the output current is relatively small (eg, steady state), the transistor 601 generates a static bias current of the first amplifier 602 in response to the value of the voltage (BIAS) applied to the gate of the transistor 601, And the bias current generated by transistor 607 may be small or even negligible.

在第二操作狀態中，通過輸出端子632(V_OUT)的負載電流突然增加。在半導體結構600的整體回饋回路可對此狀態改變作出反應之前，額外的負載電流使輸出電容器634放電，且進而降低輸出電壓V_OUT的值。輸出電壓的此降低減小了節點606處的回饋電壓值Vfb的值，所述回饋電壓是施加到第一放大器602的電晶體M2的閘極端子的電壓。電晶體M2的閘極電壓的所得降低使到差分對電晶體M1和M2的輸入電壓不平衡，從而增加通過電晶體M2的電流，且進而增加施加到電晶體605和620的閘極的電壓。電晶體605的所得的增加的漏電流通過電流鏡電晶體對609和607回饋回第一放大器602的偏置電流輸入，從而又增加了正產生的尾電流的值。尾電流的此增加增大可通過電晶體M2的電流，且進而以正(增加的)速率增加電晶體605和620的閘極端子處的電壓。同時，通過電晶體620的增加的電流更快地給輸出電晶體628的大閘極電容充電，直到電晶體628的汲極電流足夠供應負載電流為止。這時，輸出電壓V_OUT的量級返回到所增加的電流給輸出電容器634充電時的穩態。如此，第一放大器602的自我調整偏置 配置(輸入級)使第一級的電流位準增加到整體回饋回路的平衡位準之上，以便給輸出電晶體628的閘極電容充電。因此，達到新的穩態條件，自我調整偏置電流達到新的平衡值，所述平衡值由電晶體對628和626、620和605、以及609和607的閘極面積比明確定義。 In the second operational state, the load current through the output terminal 632 (V _OUT ) suddenly increases. The additional load current discharges the output capacitor 634 and further reduces the value of the output voltage _VOUT before the overall feedback loop of the semiconductor structure 600 can react to this state change. This decrease in output voltage reduces the value of the feedback voltage value Vfb at node 606, which is the voltage applied to the gate terminal of transistor M2 of first amplifier 602. The resulting decrease in the gate voltage of transistor M2 unbalances the input voltages to differential pair transistors M1 and M2, thereby increasing the current through transistor M2 and, in turn, increasing the voltage applied to the gates of transistors 605 and 620. The resulting increased leakage current of transistor 605 is fed back to the bias current input of first amplifier 602 by current mirror transistor pairs 609 and 607, which in turn increases the value of the tail current being generated. This increase in tail current increases the current through the transistor M2 and, in turn, increases the voltage at the gate terminals of the transistors 605 and 620 at a positive (increased) rate. At the same time, the increased current through transistor 620 charges the large gate capacitance of output transistor 628 more quickly until the gate current of transistor 628 is sufficient to supply the load current. At this time, the magnitude of the output voltage V _OUT returns to the steady state when the increased current charges the output capacitor 634. As such, the self-adjusting bias configuration (input stage) of the first amplifier 602 increases the current level of the first stage above the equilibrium level of the overall feedback loop to charge the gate capacitance of the output transistor 628. Thus, reaching a new steady state condition, the self-adjusting bias current reaches a new equilibrium value that is clearly defined by the gate area ratio of transistor pairs 628 and 626, 620 and 605, and 609 and 607.

總之，根據本申請的教示，導通電晶體628的相對較大的閘極電容在自我調整偏置回路外部。自我調整偏置回路通過增加自我調整偏置電流的值來響應增加的負載電流，以便更快地給導通電晶體628的閘極電容充電。因為導通電晶體628的閘極電容在自我調整偏置回路的外部，所以自我調整偏置回路的響應時間明顯快於常規LDO穩壓器中的常規偏置回路的響應時間，且利用半導體結構600實施的LDO穩壓器的所得的輸出電壓跌落明顯小於常規LDO穩壓器的輸出電壓跌落。 In summary, in accordance with the teachings of the present application, the relatively large gate capacitance of the conductive crystal 628 is external to the self-adjusting bias loop. The self-adjusting bias loop responds to the increased load current by increasing the value of the self-adjusting bias current to more quickly charge the gate capacitance of the conductive crystal 628. Because the gate capacitance of the conductive crystal 628 is external to the self-adjusting bias loop, the response time of the self-regulating bias loop is significantly faster than the response time of a conventional bias loop in a conventional LDO regulator, and the semiconductor structure 600 is utilized. The resulting output voltage drop of the implemented LDO regulator is significantly less than the output voltage drop of a conventional LDO regulator.

注意，半導體結構600的示例性實施方案中使用正回饋。因此，偏置電流中所得的增加在第一放大器602的操作點中發生改變，從而又增加了所產生的自我調整偏置電流。在由半導體結構600描繪的示例性實施方案中，將正回饋回路增益設計成小於1，以確保自我調整偏置回路的穩定性。舉例來說，選擇電晶體尺寸設計以使得自我調整回饋電晶體605以是電晶體M3和M4的電流密度的兩倍的電流密度操作。因此，由於跨導/汲極電流比(GM/Id)隨著電流密度的減小，小於1的回路增益得以確保。 Note that positive feedback is used in an exemplary embodiment of semiconductor structure 600. Thus, the resulting increase in bias current changes in the operating point of the first amplifier 602, which in turn increases the resulting self-regulating bias current. In an exemplary embodiment depicted by semiconductor structure 600, the positive feedback loop gain is designed to be less than one to ensure the stability of the self-adjusting bias loop. For example, the transistor size design is chosen such that the self-adjusting feedback transistor 605 operates at a current density that is twice the current density of the transistors M3 and M4. Therefore, the loop gain of less than 1 is ensured as the transconductance/drain current ratio (GM/Id) decreases with current density.

圖7A和圖7B是描繪根據本發明的上述實施方案中的一個或多個而結構化的自我調整偏置LDO穩壓器的類比相位邊限性能曲線和增益邊限性能曲線的相關曲線圖。這些曲線圖描繪被施加不同電源電壓、溫度和製程邊界角的自我調整偏置LDO穩壓器的類比性能曲線。位準(X)軸指 示所施加的負載電流，且垂直(Y)軸指示針對所涉及的LDO穩壓器模擬的不同操作條件和不同輸出電流位準的相位邊限值或增益邊限值。 7A and 7B are correlation graphs depicting an analog phase margin performance curve and a gain margin performance curve for a structured self-adjusting bias LDO regulator in accordance with one or more of the above-described embodiments of the present invention. These graphs depict the analog performance curves of self-tuning bias LDO regulators that are applied with different supply voltages, temperatures, and process boundary angles. Level (X) axis The applied load current is shown, and the vertical (Y) axis indicates the phase margin or gain margin for different operating conditions and different output current levels simulated for the LDO regulator involved.

注意，如曲線圖700a和700b指示，對電路穩定性的可接受位準的提供給予相當大的設計關注，所述可接受位準在所有可能遭遇的潛在操作條件和輸出電流位準之上。然而，此穩定性位準通常涉及對靜態電流位準的顯著權衡。然而，如圖7A和圖7B中所示的LDO調節器性能特性所指示，這些模擬結果證實了本發明的上述實施方案可用於實施LDO穩壓器，所述LDO穩壓器實現用於小信號和大信號兩者的電路穩定性的可接受位準。換句話說，如曲線圖700a和700b所示，對於所有不同操作條件(例如，電源電壓、溫度、製程邊界角)以及所施加的輸出電流位準來說，所涉及的LDO穩壓器的整體性能大致上是類似的。 Note that as the graphs 700a and 700b indicate, there is considerable design attention to the provision of acceptable levels of circuit stability above all potential operating conditions and output current levels that may be encountered. However, this level of stability typically involves a significant trade-off between quiescent current levels. However, as indicated by the LDO regulator performance characteristics shown in Figures 7A and 7B, these simulation results demonstrate that the above-described embodiments of the present invention can be used to implement an LDO regulator that is implemented for small signals. Acceptable levels of circuit stability for both large and large signals. In other words, as shown in graphs 700a and 700b, the overall LDO regulator involved for all different operating conditions (eg, supply voltage, temperature, process boundary angle) and applied output current levels The performance is roughly similar.

圖8是描繪根據本申請的上述教示而結構化的自我調整偏置LDO穩壓器的類比暫態負載響應的曲線圖。對於所示的模擬來說，在500μs處將300mA負載電流步長施加到自我調整偏置LDO穩壓器。注意，圖8展示超過常規LDO穩壓器暫態電壓跌落性能的暫態電壓跌落性能的改進主要由超過常規LDO穩壓器的響應速度的增加的響應速度產生。舉例來說，圖8中所示，模擬LDO穩壓器的輸出電壓在約500.45μs處“跌落”到大約2.176V(802)。在顯著對比中，常規LDO穩壓器的輸出電壓將在500.5μs處或在稍後時間跌落到至少2.142V。如此，與常規LDO穩壓器相比，自我調整偏置LDO穩壓器的增強型暫態響應主要如下實施。有點類似於常規LDO穩壓器，自我調整偏置LDO穩壓器的輸出電壓在所增加的負載用於給輸出電容器放電時降低。然而，自我調整偏置LDO穩壓器增加其偏置電流， 以便能夠更快地給導通電晶體裝置的閘極電容充電。自我調整偏置回饋回路的暫態響應時間比LDO穩壓器的整體回饋回路的暫態響應時間短得多，且因此，自我調整偏置LDO穩壓器比不具有自我調整偏置回饋回路的常規LDO穩壓器更快速地響應負載暫態，以及比具有自我調整偏置回饋的常規LDO穩壓器(其中所述自我調整偏置回饋回路包括通常較大的輸出裝置的輸入電容)更快速地響應負載暫態。另外，自我調整偏置LDO穩壓器所經歷的暫態跌落明顯小於常規LDO穩壓器所經歷的暫態跌落。 8 is a graph depicting an analog transient load response of a structured self-adjusting bias LDO regulator in accordance with the above teachings of the present application. For the simulation shown, a 300 mA load current step is applied to the self-adjusting bias LDO regulator at 500 μs. Note that Figure 8 shows that the improvement in transient voltage drop performance over conventional LDO regulator transient voltage drop performance is primarily due to the increased response speed over the response speed of conventional LDO regulators. For example, as shown in Figure 8, the output voltage of the analog LDO regulator "drops" to approximately 2.176V (802) at approximately 500.45 [mu]s. In a significant comparison, the output voltage of a conventional LDO regulator will drop to at least 2.142V at 500.5 μs or at a later time. As such, the enhanced transient response of the self-regulating bias LDO regulator is primarily implemented as compared to conventional LDO regulators. Similar to a conventional LDO regulator, the output voltage of a self-tuning bias LDO regulator is reduced when the increased load is used to discharge the output capacitor. However, a self-tuning bias LDO regulator increases its bias current, In order to be able to charge the gate capacitance of the conducting crystal device more quickly. The transient response time of the self-adjusting bias feedback loop is much shorter than the transient response time of the LDO regulator's overall feedback loop, and therefore, the self-tuning bias LDO regulator is less than the self-adjusting bias feedback loop. Conventional LDO regulators respond more quickly to load transients and faster than conventional LDO regulators with self-tuning bias feedback, where the self-tuning bias feedback loop includes the input capacitance of a normally larger output device Ground response to load transients. In addition, the transient drop experienced by the self-tuning bias LDO regulator is significantly less than the transient drop experienced by conventional LDO regulators.

圖9是描繪自我調整偏置LDO穩壓器在高操作溫度(125℃)、2.5V輸入電壓(例如，V_IN)和2.2V額定輸出電壓(例如，V_OUT)的模擬操作條件下的類比性能模式的曲線圖。如圖9所示，儘管模擬在多種不同製程、溫度和輸入電壓條件下進行，但自我調整偏置LDO穩壓器的性能模式大致上得以保持。換句話說，圖9中所描繪的曲線圖展示製造變化(m)對自我調整偏置LDO穩壓器的性能具有怎樣小的影響。如此，圖9中所描繪的性能變化主要從操作溫度的改變產生。舉例來說，圖9中所示的上部曲線902a到908a描繪自我調整偏置LDO穩壓器的最大電壓誤差或暫態過衝，且下部曲線902b到908b描繪所涉及的自我調整偏置LDO穩壓器的最小電壓或暫態跌落。位準(X)軸指示用於針對以下五種製造情況的此類比的製程邊界角：情況0指示用於典型n通道金屬氧化物半導體(NMOS)和p通道(PMOS)電晶體的製程邊界角；情況1指示用於慢NMOS和PMOS電晶體的製程邊界角；情況2指示用於快NMOS和PMOS電晶體的製程邊界角；情況3指示用於慢NMOS電晶體和快PMOS電晶體的製程邊界角；以及情況4指示用於快NMOS電晶體和慢PMOS電晶體的製程邊界角。在此示例性 類比中，性能曲線902a和902b指示針對2.5V輸入電壓和125℃操作溫度的電路性能；曲線904a和904b指示針對5.5V輸入電壓和125℃操作溫度的電路性能；曲線906a和906b指示針對5.5V輸入電壓和-20C操作溫度的電路性能；以及曲線908a和908b指示針對2.5V輸入電壓和-20C操作溫度的電路性能。2.2V輸出電壓(額定)用於所有模擬。注意，圖9中所示的模擬指示上述自我調整偏置LDO穩壓器的增強型暫態過衝和跌落性能優於常規LDO穩壓器的暫態過衝和跌落性能。 Figure 9 is a graph depicting the analogy of a self-tuning bias LDO regulator under high operating temperature (125 ° C), 2.5 V input voltage (eg, V _IN ), and 2.2 V rated output voltage (eg, V _OUT ). A graph of the performance mode. As shown in Figure 9, although the simulation is performed under a variety of different process, temperature, and input voltage conditions, the performance mode of the self-tuning bias LDO regulator is substantially maintained. In other words, the graph depicted in Figure 9 shows how the manufacturing variation (m) has little effect on the performance of the self-adjusting bias LDO regulator. As such, the performance changes depicted in Figure 9 are primarily due to changes in operating temperature. For example, the upper curves 902a through 908a shown in Figure 9 depict the maximum voltage error or transient overshoot of the self-adjusting bias LDO regulator, and the lower curves 902b through 908b depict the self-adjusting bias LDO involved. The minimum voltage or transient drop of the press. The level (X) axis indicates the process boundary angle for such ratios for the following five manufacturing cases: Case 0 indicates the process boundary angle for typical n-channel metal oxide semiconductor (NMOS) and p-channel (PMOS) transistors. Case 1 indicates the process boundary angle for slow NMOS and PMOS transistors; Case 2 indicates the process boundary angle for fast NMOS and PMOS transistors; Case 3 indicates the process boundary for slow NMOS transistors and fast PMOS transistors Angle; and Case 4 indicates the process boundary angle for the fast NMOS transistor and the slow PMOS transistor. In this exemplary analogy, performance curves 902a and 902b indicate circuit performance for 2.5V input voltage and 125°C operating temperature; curves 904a and 904b indicate circuit performance for 5.5V input voltage and 125°C operating temperature; curves 906a and 906b Circuit performance for 5.5V input voltage and -20C operating temperature is indicated; and curves 908a and 908b indicate circuit performance for 2.5V input voltage and -20C operating temperature. The 2.2V output voltage (rated) is used for all simulations. Note that the simulation shown in Figure 9 indicates that the enhanced transient overshoot and drop performance of the self-tuning bias LDO regulator described above is superior to the transient overshoot and drop performance of conventional LDO regulators.

圖10描繪配置為PMIC的示例性系統1000的示意性方塊圖，所述PMIC可用於實施根據本發明的一個或多個實施方案的用於增強型暫態響應的半導體結構。在一些實施方案中，系統1000可在半導體IC、晶圓、晶片或晶粒上實施。在所示的示例性實施方案中，系統1000可被實施為集成PMIC，以便例如為筆記本電腦、平板式個人電腦(PC)、監視器中的薄膜電晶體液晶顯示器(TFT-LCD)提供電力，且還為小尺寸顯示器(如智慧型電話顯示器)的TFT-LCD提供電力。參考圖10，對於一個示例性實施方案來說，系統1000包括根據圖1到6中所描繪的上述實施方案中的一個或多個而配置的自我調整偏置LDO穩壓器1002。自我調整偏置LDO穩壓器1002耦合到電壓輸入連接件1030以接收輸入電壓(V_IN)，且耦合到電壓輸出連接件1032以將經調節電壓(V_OUT)輸出到VLOGIC通道輸出連接件1004。來自自我調整偏置LDO穩壓器1002的經調節輸出電壓是用於驅動耦合到VLOGIC通道輸出1004的外部數位電路的相對較低電壓。LDO調節器1002還用於將經調節電壓提供到定序器1006、類比Vdd或電源電壓(AVDD)增壓控制器1008、閘控脈衝調製器(GPM)1010、電壓檢測器1012以及用作校準器以調整 所使用的LCD的V_COM電壓的數位控制電位計(DCP)1014。在這個示例性系統中，LDO穩壓器1002是外部可調整部件(例如，經由半導體IC或晶片的接觸針腳)，且暴露為“獨立”功能。在其它示例性系統中，LDO穩壓器1002不是外部可調整的。如此，根據本發明的上述教示，自我調整偏置LDO穩壓器1002提供系統1000中優於常規LDO穩壓器的暫態響應的增強型(例如，大致上更快的)暫態響應。 10 depicts a schematic block diagram of an exemplary system 1000 configured as a PMIC that can be used to implement a semiconductor structure for enhanced transient response in accordance with one or more embodiments of the present invention. In some embodiments, system 1000 can be implemented on a semiconductor IC, wafer, wafer, or die. In the exemplary embodiment shown, system 1000 can be implemented as an integrated PMIC to provide power, for example, to a thin film transistor liquid crystal display (TFT-LCD) in a notebook computer, a tablet personal computer (PC), a monitor, It also supplies power to the TFT-LCD of a small-sized display such as a smart phone display. Referring to Figure 10, for an exemplary embodiment, system 1000 includes a self-adjusting bias LDO regulator 1002 configured in accordance with one or more of the above-described embodiments depicted in Figures 1 through 6. A self-adjusting bias LDO regulator 1002 is coupled to the voltage input connector 1030 to receive the input voltage (V _IN ) and coupled to the voltage output connector 1032 to output the regulated voltage (V _OUT ) to the VLOGIC channel output connector 1004 . The regulated output voltage from the self-adjusting bias LDO regulator 1002 is a relatively low voltage used to drive an external digital circuit coupled to the VLOGIC channel output 1004. LDO regulator 1002 is also used to provide regulated voltage to sequencer 1006, analog Vdd or supply voltage (AVDD) boost controller 1008, gated pulse modulator (GPM) 1010, voltage detector 1012, and for calibration A digitally controlled potentiometer (DCP) 1014 that adjusts the V _COM voltage of the LCD used. In this exemplary system, LDO regulator 1002 is an externally adjustable component (eg, via a contact pin of a semiconductor IC or wafer) and exposed as a "stand-alone" function. In other exemplary systems, LDO regulator 1002 is not externally adjustable. Thus, in accordance with the above teachings of the present invention, the self-adjusting bias LDO regulator 1002 provides an enhanced (e.g., substantially faster) transient response in system 1000 that is superior to the transient response of a conventional LDO regulator.

圖11描繪配置為PMIC的第二示例性系統1100的示意性方塊圖，所述PMIC可用於實施根據本發明的一個或多個實施方案的用於增強型暫態響應的半導體結構。在一些實施方案中，系統1100可在半導體IC、晶圓、晶片或晶粒上實施。在所示的示例性實施方案中，將系統1100實施為用於小尺寸、掌上型顯示器(例如智慧型電話TFT-LCD)的高效率電源。參考圖11，對於一個示例性實施方案來說，系統1100包括根據圖1到6中所描繪的上述實施方案的一個或多個而配置的自我調整偏置LDO穩壓器1102。自我調整偏置LDO穩壓器1102耦合在系統1100的電流接地1136與眾多其它電路元件之間，以便為系統1100中的電源電路提供合適的去耦合。如此，在一些示例性實施方案中，自我調整偏置LDO穩壓器1102與“晶片上”電壓調整集成，以便實現自我調整偏置LDO穩壓器1102的後續製造電壓調整。基本上，在操作中，自我調整偏置LDO穩壓器1102的輸入1130(V_IN)處的電壓是從增壓轉換器1101提供，所述增壓轉換器適配於追蹤自我調整偏置LDO穩壓器1102的輸出1132(V_OUT)處的電壓，以便提供剛好足夠的電壓降以供自我調整偏置LDO穩壓器1102如所需運行。如此，根據本發明的教示，自我調整偏置LDO穩壓器1102提供系統1100中優於常規LDO穩壓 器的暫態響應的增強型(例如，更快的)暫態響應。 11 depicts a schematic block diagram of a second exemplary system 1100 configured as a PMIC that can be used to implement a semiconductor structure for enhanced transient response in accordance with one or more embodiments of the present invention. In some implementations, system 1100 can be implemented on a semiconductor IC, wafer, wafer, or die. In the exemplary embodiment shown, system 1100 is implemented as a high efficiency power supply for small size, palm-sized displays, such as smart phone TFT-LCDs. Referring to Figure 11, for an exemplary embodiment, system 1100 includes a self-adjusting bias LDO regulator 1102 configured in accordance with one or more of the above-described embodiments depicted in Figures 1 through 6. A self-adjusting bias LDO regulator 1102 is coupled between current ground 1136 of system 1100 and numerous other circuit components to provide suitable decoupling for the power supply circuitry in system 1100. As such, in some exemplary embodiments, the self-adjusting bias LDO regulator 1102 is integrated with "on-wafer" voltage regulation to achieve subsequent fabrication voltage adjustment of the self-adjusting bias LDO regulator 1102. Basically, in operation, the voltage at the input 1130 (V _IN ) of the self-adjusting bias LDO regulator 1102 is provided from a boost converter 1101 that is adapted to track the self-adjusting bias LDO. The voltage at the output 1132 (V _OUT ) of the voltage regulator 1102 is provided to provide just enough voltage drop for self-tuning to bias the LDO regulator 1102 as desired. As such, in accordance with the teachings of the present invention, the self-adjusting bias LDO regulator 1102 provides an enhanced (eg, faster) transient response in the system 1100 that is superior to the transient response of a conventional LDO regulator.

圖12是描繪根據本發明的一個或多個實施方案的自我調整偏置LDO穩壓器的示例性操作方法1200的流程圖。舉例來說，方法1200可用於描述圖1到圖6中所描繪的示例性實施方案中的一個或多個的操作。參考圖12，對於一個示例性實施方案來說，第一放大器(例如，誤差放大器)輸出合適的電壓(1202)，所述電壓轉換(例如，通過跨導放大器)成用於控制自我調整偏置LDO穩壓器的輸出裝置(例如，導通電晶體)的負載電流。第一放大器還接收代表自我調整偏置LDO穩壓器的輸出電壓的回饋電壓(1204)。如果由第一放大器接收的回饋電壓發生跌落(例如，與負載電流的暫態相關聯的輸出電壓降低)(1206)，那麼響應於輸出電壓跌落，第一放大器使用正回饋回路來增加其自身的偏置電流(1208)。注意，正回饋回路不包括與輸出裝置的控制端子相關聯的電容(例如，導通或輸出電晶體的閘極電容)。響應於偏置電流的增加，第一放大器增加其輸出電壓且(例如，經由跨導放大器)，進而增加去往輸出裝置的負載電流(1210)。然而，如果(1206)回饋電壓沒有發生跌落，那麼流程返回到監視輸出電壓(1204)。 12 is a flow diagram depicting an exemplary method of operation 1200 of a self-adjusting bias LDO regulator in accordance with one or more embodiments of the present invention. For example, method 1200 can be used to describe the operation of one or more of the exemplary embodiments depicted in FIGS. 1 through 6. Referring to Figure 12, for an exemplary embodiment, a first amplifier (e.g., an error amplifier) outputs a suitable voltage (1202) that is converted (e.g., by a transconductance amplifier) for controlling self-adjusting bias The load current of the output device of the LDO regulator (for example, a conducting crystal). The first amplifier also receives a feedback voltage (1204) representative of the output voltage of the self-adjusting bias LDO regulator. If the feedback voltage received by the first amplifier drops (eg, the output voltage associated with the transient of the load current decreases) (1206), then in response to the output voltage drop, the first amplifier uses a positive feedback loop to increase its own Bias current (1208). Note that the positive feedback loop does not include the capacitance associated with the control terminal of the output device (eg, turning on or outputting the gate capacitance of the transistor). In response to an increase in the bias current, the first amplifier increases its output voltage and (eg, via a transconductance amplifier), thereby increasing the load current to the output device (1210). However, if (126) the feedback voltage does not drop, the flow returns to the monitor output voltage (1204).

在本文的論述和申請專利範圍中，相對於兩種材料使用的術語“在......上”、一個在另一個“上”意味著這些材料之間至少有一些接觸，而“在......上方”意味著這些材料是接近，但可能具有一個或多個附加的插入層，因此接觸是可能的而不是必須的。如本文所使用的“在......上(on)”或“在......上方(over)”均不暗示任何方向性。術語“約”指示所列出值可以有所更改，只要所述改變不對所說明實施方案的過程或結構造成不一致即可。 In the context of the discussion and patent application, the terms "on" and "on" the use of the two materials mean that there is at least some contact between the materials, and "Upper" means that the materials are close, but may have one or more additional intervening layers, so contact is possible rather than necessary. As used herein, "on" or "over" does not imply any directionality. The term "about" indicates that the listed values may be modified as long as the changes do not cause inconsistencies in the process or structure of the illustrated embodiment.

本申請中使用的相對位置的術語是基於與晶圓或基板的常規平面或工作表面平行的平面來定義的，而不考慮晶片或基板的定向。如本申請中使用的術語“位準”、“橫向”定義為與晶片或基板的常規平面或工作表面平行的平面，而不考慮晶片或基板的定向。術語“垂直”指的是與位準垂直的方向。諸如“在……上”、“側”(如在“側壁”中的側)、“較高”、“較低”、“在……之上”、“頂部”、以及“在……之下”是相對於位於晶片或基板頂部表面上的常規平面或工作表面來定義，而不考慮晶片或基板的定向。 The term relative position as used in this application is defined based on a plane parallel to the normal plane or working surface of the wafer or substrate, regardless of the orientation of the wafer or substrate. The terms "level" and "lateral" as used in this application are defined as planes that are parallel to a conventional planar or working surface of a wafer or substrate, regardless of the orientation of the wafer or substrate. The term "vertical" refers to the direction perpendicular to the level. Such as "on", "side" (as in the "side" side), "higher", "lower", "above", "top", and "in" The "lower" is defined relative to a conventional planar or working surface located on the top surface of the wafer or substrate, regardless of the orientation of the wafer or substrate.

儘管本文已說明和描述了具體的實施方案，但本領域技術人員應瞭解，計畫來實現相同目的的任何配置可代替所展示的具體實施方案。因此，顯然希望僅僅由所附申請專利範圍及其均等物來限制本發明。 Although specific embodiments have been illustrated and described herein, it will be understood by those skilled in the art Therefore, it is apparent that the invention is limited only by the scope of the appended claims and their equivalents.