patents.google.com

TWI673695B - Display panel - Google Patents

  • ️Tue Oct 01 2019

TWI673695B - Display panel - Google Patents

Display panel Download PDF

Info

Publication number
TWI673695B
TWI673695B TW107124248A TW107124248A TWI673695B TW I673695 B TWI673695 B TW I673695B TW 107124248 A TW107124248 A TW 107124248A TW 107124248 A TW107124248 A TW 107124248A TW I673695 B TWI673695 B TW I673695B Authority
TW
Taiwan
Prior art keywords
switch
sub
pixel
period
turned
Prior art date
2018-07-13
Application number
TW107124248A
Other languages
Chinese (zh)
Other versions
TW202006691A (en
Inventor
鄭貿薰
洪嘉澤
黃正翰
陳勇志
鄭景升
Original Assignee
友達光電股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
2018-07-13
Filing date
2018-07-13
Publication date
2019-10-01
2018-07-13 Application filed by 友達光電股份有限公司 filed Critical 友達光電股份有限公司
2018-07-13 Priority to TW107124248A priority Critical patent/TWI673695B/en
2018-09-30 Priority to CN201811154428.6A priority patent/CN109166524B/en
2019-10-01 Application granted granted Critical
2019-10-01 Publication of TWI673695B publication Critical patent/TWI673695B/en
2020-02-01 Publication of TW202006691A publication Critical patent/TW202006691A/en

Links

Classifications

    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Control Of El Displays (AREA)

Abstract

本發明實施例提供一種顯示面板。所述顯示面板具有週邊區及顯示區。其中,包含多個子畫素的畫素串設置於顯示區,且每一子畫素皆電連接於資料線,資料線與資料驅動器間具有第一開關。外部臨界電壓補償電路則設置於週邊區,並且通過經由第二開關電連接於資料線,以用來依序對於這些子畫素中的一者進行補償。於第二開關導通的第一期間及第三期間,外部臨界電壓補償電路透過資料線提供第一參考電壓或第二參考電壓至此子畫素。於第二開關導通的第二期間及第四期間,外部臨界電壓補償電路透過資料線偵測流經此子畫素之驅動電晶體的第一感測電流或第二感測電流,並產生第一積分值或第二積分值。An embodiment of the present invention provides a display panel. The display panel has a peripheral area and a display area. A pixel string including a plurality of sub-pixels is disposed in the display area, and each sub-pixel is electrically connected to a data line, and a first switch is provided between the data line and the data driver. The external critical voltage compensation circuit is disposed in the peripheral area and is electrically connected to the data line through the second switch, so as to sequentially compensate one of these sub-pixels. During the first period and the third period when the second switch is turned on, the external threshold voltage compensation circuit provides the first reference voltage or the second reference voltage to the sub-pixel through the data line. During the second period and the fourth period when the second switch is turned on, the external threshold voltage compensation circuit detects the first sensing current or the second sensing current of the driving transistor through the data line through the data line, and generates a first sensing current An integral value or a second integral value.

Description

顯示面板Display panel

本發明是有關於一種顯示面板,且特別是一種具有外部臨界電壓補償電路(threshold voltage compensation circuit)的顯示面板。 The present invention relates to a display panel, and particularly to a display panel having an external threshold voltage compensation circuit.

在顯示器的運作過程中,薄膜電晶體(Thin-Film Transistor,TFT)可能會因製程影響或其他操作條件改變,而造成其臨界電壓變異,導致顯示畫面亮度不均,並且連帶降低顯示品質。一般來說,現有技術是會藉由臨界電壓補償電路來補償薄膜電晶體的臨界電壓變異,而常見的臨界電壓補償電路是由設置於畫素內的數個薄膜電晶體及儲存電容所構成,亦即稱其作為內部臨界電壓補償電路。 During the operation of the display, Thin-Film Transistors (TFTs) may be subject to process influence or other operating conditions that may cause their threshold voltages to vary, resulting in uneven brightness on the display screen and a reduction in display quality. Generally, in the prior art, the threshold voltage variation of a thin film transistor is compensated by a threshold voltage compensation circuit, and a common threshold voltage compensation circuit is composed of several thin film transistors and storage capacitors arranged in a pixel. Also known as its internal critical voltage compensation circuit.

然而,在現今解析度需求越高的趨勢下,顯示面板上就需要設置越多的畫素。由於面板上的空間有限,因此往往也就必須對畫素內的內部臨界電壓補償電路而有所取捨。除此之外,畫素內的內部臨界電壓補償電路所能用到的補償時間,卻又與資料寫入畫素的時間有關。因此,當解析度變高時,畫素內的內部臨界電壓補償電路所能用到的補償時間也就相對變少。 However, in the current trend of higher resolution requirements, more pixels need to be set on the display panel. Because the space on the panel is limited, it is often necessary to choose between the internal threshold voltage compensation circuit in the pixel. In addition, the compensation time that can be used by the internal critical voltage compensation circuit in the pixel is related to the time that the data is written into the pixel. Therefore, when the resolution becomes higher, the compensation time that can be used by the internal threshold voltage compensation circuit in the pixel becomes relatively less.

有鑑於此,本發明之目的在於提供一種設置於畫素外的外部臨界電壓補償電路。為達上述目的,本發明實施例提供一種顯示面板,所述顯示面板具有週邊區(peripheral area)及顯示區(display area)。其中,包含多個子畫素的畫素串設置於顯示區,且每一子畫素皆電連接於資料線,資料線與資料驅動器間具有第一開關。外部臨界電壓補償電路則設置於週邊區,並且通過經由第二開關電連接於資料線,以用來依序對於這些子畫素中的一者進行補償。於第二開關導通的第一期間,外部臨界電壓補償電路透過資料線提供第一參考電壓至此子畫素。於第二開關導通的第二期間,外部臨界電壓補償電路透過資料線偵測流經此子畫素之驅動電晶體的第一感測電流,並產生第一積分值。於第二開關導通的第三期間,外部臨界電壓補償電路透過資料線提供第二參考電壓至此子畫素,其中第一參考電壓及第二參考電壓係皆小於等於電連接至此子畫素之發光二極體的第一供應電壓與發光二極體的導通電壓(turn-on voltage)之總和,且第二參考電壓不等於第一參考電壓。於第二開關導通的第四期間,外部臨界電壓補償電路透過資料線偵測流經此子畫素之驅動電晶體的第二感測電流,並產生第二積分值。 In view of this, an object of the present invention is to provide an external threshold voltage compensation circuit provided outside a pixel. To achieve the above object, an embodiment of the present invention provides a display panel. The display panel has a peripheral area and a display area. A pixel string including a plurality of sub-pixels is disposed in the display area, and each sub-pixel is electrically connected to a data line, and a first switch is provided between the data line and the data driver. The external critical voltage compensation circuit is disposed in the peripheral area and is electrically connected to the data line through the second switch, so as to sequentially compensate one of these sub-pixels. During the first period when the second switch is turned on, the external threshold voltage compensation circuit provides the first reference voltage to the sub-pixel through the data line. During the second period when the second switch is turned on, the external threshold voltage compensation circuit detects the first sensing current flowing through the driving transistor of the sub-pixel through the data line, and generates a first integrated value. During the third period when the second switch is turned on, the external critical voltage compensation circuit provides a second reference voltage to the sub-pixel through the data line, wherein the first reference voltage and the second reference voltage are both less than or equal to the light emission electrically connected to the sub-pixel. The sum of the first supply voltage of the diode and the turn-on voltage of the light emitting diode, and the second reference voltage is not equal to the first reference voltage. During the fourth period when the second switch is turned on, the external threshold voltage compensation circuit detects the second sensing current flowing through the driving transistor of the sub-pixel through the data line, and generates a second integrated value.

為使能更進一步瞭解本發明之特徵及技術內容,請參閱以下有關本發明之詳細說明與附圖,但是此等說明與所附圖式僅係用來說明本發明,而非對本發明的權利範圍作任何的限制。 In order to further understand the features and technical contents of the present invention, please refer to the following detailed description and accompanying drawings of the present invention, but these descriptions and attached drawings are only used to illustrate the present invention, not the right to the present invention. No limitation on scope.

1‧‧‧顯示面板 1‧‧‧display panel

10‧‧‧週邊區 10‧‧‧Peripheral area

20‧‧‧顯示區 20‧‧‧display area

11‧‧‧資料驅動器 11‧‧‧Data Drive

12‧‧‧掃描驅動器 12‧‧‧ scan driver

13‧‧‧感測驅動器 13‧‧‧Sense driver

14‧‧‧時序控制器 14‧‧‧Sequence Controller

15[0]~15[m]‧‧‧外部臨界電壓補償電路 15 [0] ~ 15 [m] ‧‧‧External critical voltage compensation circuit

151‧‧‧運算放大器 151‧‧‧ Operational Amplifier

153‧‧‧回授單元 153‧‧‧Feedback Unit

155‧‧‧類比數位轉換器 155‧‧‧ Analog Digital Converter

157‧‧‧儲存器 157‧‧‧Storage

159‧‧‧資料更新單元 159‧‧‧Data Update Unit

DATA、DATAc‧‧‧顯示資料 DATA, DATAc‧‧‧ Display data

CINT‧‧‧電容 C INT ‧‧‧Capacitance

SW1[0]~SW1[m]‧‧‧第一開關 SW1 [0] ~ SW1 [m] ‧‧‧First switch

SW2[0]~SW1[m]‧‧‧第二開關 SW2 [0] ~ SW1 [m] ‧‧‧Second switch

SW3‧‧‧第三開關 SW3‧‧‧Third switch

SW4‧‧‧第四開關 SW4‧‧‧Fourth switch

SW5‧‧‧第五開關 SW5‧‧‧Fifth switch

VREF1‧‧‧第一參考電壓 V REF1 ‧‧‧ first reference voltage

VREF2‧‧‧第二參考電壓 V REF2 ‧‧‧ second reference voltage

I1‧‧‧第一感測電流 I1‧‧‧First sensing current

I2‧‧‧第二感測電流 I2‧‧‧Second sensing current

△O1‧‧‧第一積分值 △ O1‧‧‧First integral value

△O2‧‧‧第二積分值 △ O2‧‧‧Second integral value

21[0]~21[m]‧‧‧畫素串 21 [0] ~ 21 [m] ‧‧‧pixel string

22[0]~22[n]‧‧‧子畫素 22 [0] ~ 22 [n] ‧‧‧ sub pixels

DL[0]~DL[m]‧‧‧資料線 DL [0] ~ DL [m] ‧‧‧Data line

OLED‧‧‧發光二極體 OLED‧‧‧light-emitting diode

TD‧‧‧驅動電晶體 TD‧‧‧Drive Transistor

CST、CST’‧‧‧儲存電容 C ST , C ST '‧‧‧ storage capacitor

T1~T3、T1’~T2’‧‧‧開關電晶體 T1 ~ T3, T1 ’~ T2’‧‧‧Switching transistor

OVDD、OVSS‧‧‧供應電壓 OVDD, OVSS‧‧‧ supply voltage

P1、P2、P3‧‧‧節點 P1, P2, P3‧‧‧ nodes

EM[0]~EM[n]‧‧‧發光控制訊號 EM [0] ~ EM [n] ‧‧‧Light control signal

S[0]~S[n]‧‧‧掃描訊號 S [0] ~ S [n] ‧‧‧Scan signal

R[0]~R[n]‧‧‧感測訊號 R [0] ~ R [n] ‧‧‧Sensing signal

圖1是本發明實施例所提供的顯示面板的功能方塊示意圖。 FIG. 1 is a functional block diagram of a display panel according to an embodiment of the present invention.

圖2是圖1的顯示面板中的外部臨界電壓補償電路的電路示意圖。 FIG. 2 is a circuit diagram of an external critical voltage compensation circuit in the display panel of FIG. 1.

圖3A~圖3E是圖2的外部臨界電壓補償電路所對於子畫素進行補償時的運作示意圖。 FIG. 3A to FIG. 3E are operation schematic diagrams of subpixels compensated by the external threshold voltage compensation circuit of FIG. 2.

圖4是圖2的外部臨界電壓補償電路所對於子畫素進行補償時的時序示意圖。 FIG. 4 is a timing diagram of the sub-pixel compensation performed by the external threshold voltage compensation circuit of FIG. 2.

圖5是圖2的外部臨界電壓補償電路於另一實施例的示意圖。 FIG. 5 is a schematic diagram of the external critical voltage compensation circuit of FIG. 2 in another embodiment.

圖6A~圖6C是圖1的顯示面板中的子畫素於顯示期間的運作示意圖。 FIG. 6A to FIG. 6C are operation schematic diagrams of the sub-pixels in the display panel of FIG. 1 during a display period.

圖7是圖1的顯示面板中的子畫素於顯示期間的時序示意圖。 FIG. 7 is a timing diagram of a sub-pixel in the display panel of FIG. 1 during a display period.

圖8是圖1的顯示面板中的子畫素於另一實施例的電路示意圖。 FIG. 8 is a schematic circuit diagram of a sub-pixel in the display panel of FIG. 1 according to another embodiment.

在下文中,將藉由圖式說明本發明之各種實施例來詳細描述本發明。然而,本發明概念可能以許多不同形式來體現,且不應解釋為限於本文中所闡述之例示性實施例。此外,在圖式中相同參考數字可用以表示類似的元件。 Hereinafter, the present invention will be described in detail by explaining various embodiments of the present invention with drawings. However, the inventive concept may be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Moreover, the same reference numbers may be used in the drawings to indicate similar elements.

具體而言,本發明實施例所提供的顯示面板,可以指的是任何類型的顯示面板。換言之,本發明並不限制顯示面板的具體實現方式,本技術領域中具有通常知識者應可依據實際需求或應用來進行相關設計。但為了方便以下說明,本實施例將是以主動矩陣有機發光二極體(AMOLED)顯示面板來作說明。舉例來說,請參閱圖1,圖1是本發明實施例所提供的顯示面板的功能方塊示意圖。 Specifically, the display panel provided in the embodiment of the present invention may refer to any type of display panel. In other words, the present invention does not limit the specific implementation of the display panel. Those with ordinary knowledge in the technical field should be able to make related designs based on actual needs or applications. However, in order to facilitate the following description, this embodiment will be described by using an active matrix organic light emitting diode (AMOLED) display panel. For example, please refer to FIG. 1, which is a functional block diagram of a display panel according to an embodiment of the present invention.

如圖1所示,顯示面板1具有週邊區10及顯示區20。而根據現有技術可知,週邊區10通常包括資料驅動器11、掃描驅動器12、感測驅動器13及時序控制器14。另外,顯示區20上則設置有複數個畫素串,例如畫素串21[0]到畫素串21[m],且每一畫素串包含多個子畫素,例如子畫素22[0]到 子畫素22[n]。在本實施例中,m及n即可分別為大於1的任意正整數。總而言之,由於本發明並不限制顯示面板1的解析度,因此本技術領域中具有通常知識者應可依據實際需求或應用來進行m及n的設計。 As shown in FIG. 1, the display panel 1 includes a peripheral area 10 and a display area 20. According to the prior art, the peripheral area 10 generally includes a data driver 11, a scan driver 12, a sensing driver 13, and a timing controller 14. In addition, the display area 20 is provided with a plurality of pixel strings, for example, a pixel string 21 [0] to a pixel string 21 [m], and each pixel string includes multiple sub pixels, such as a sub pixel 22 [ 0] to Sub-pixel 22 [n]. In this embodiment, m and n may each be any positive integer greater than 1. In a word, since the present invention does not limit the resolution of the display panel 1, those with ordinary knowledge in the technical field should be able to design m and n according to actual needs or applications.

然而,為了方便以下說明,本實施例將是僅先以探討單一個畫素串,例如畫素串21[0]的例子來進行說明。應當理解的是,畫素串21[0]的每一子畫素22[0]~22[n]皆電連接於資料線DL[0],並且經由資料線DL[0]接收來自資料驅動器11所提供的顯示資料(未繪示)。而在本實施例中,資料線DL[0]與資料驅動器11間係具有第一開關SW1[0]。另外,一個外部臨界電壓補償電路15[0]則設置於週邊區10,並且通過經由第二開關SW2[0]電連接於資料線DL[0],以用來依序對於這些子畫素22[0]~22[n]中的一者進行補償。 However, in order to facilitate the following description, this embodiment will be described by taking only an example of discussing a single pixel string, for example, a pixel string 21 [0]. It should be understood that each sub-pixel 22 [0] ~ 22 [n] of the pixel string 21 [0] is electrically connected to the data line DL [0], and receives data from the data driver via the data line DL [0]. Display information provided (not shown). In this embodiment, the data line DL [0] and the data driver 11 have a first switch SW1 [0]. In addition, an external critical voltage compensation circuit 15 [0] is disposed in the peripheral area 10, and is electrically connected to the data line DL [0] through the second switch SW2 [0], for sequentially ordering these sub-pixels 22 One of [0] to 22 [n] is compensated.

根據以上內容的教示,本技術領域中具有通常知識者應可以理解到,習知技術設計是讓每一子畫素22[0]~22[n]都個別具有內部臨界電壓補償電路,但本實施例的顯示面板1設計可以是讓同一行(column)內的多個子畫素,即畫素串21[0]的子畫素22[0]~22[n]皆共用同一外部臨界電壓補償電路15[0],且此外部臨界電壓補償電路15[0]設置於週邊區10內,亦即顯示區20與資料驅動器11之間的走線區,因此,本實施例能夠大幅簡化每一子畫素22[0]~22[n]所需的電晶體元件個數,以進而提升顯示區20的佈局(layout)彈性,並且有助於實現更高需求的解析度。 According to the teachings of the above content, those with ordinary knowledge in the technical field should understand that the conventional technology design is to allow each sub-pixel 22 [0] ~ 22 [n] to have an internal threshold voltage compensation circuit individually. The design of the display panel 1 of the embodiment may be such that multiple sub pixels in the same column (column), that is, the sub pixels 22 [0] to 22 [n] of the pixel string 21 [0] all share the same external critical voltage compensation. Circuit 15 [0], and the external critical voltage compensation circuit 15 [0] is disposed in the peripheral area 10, that is, the routing area between the display area 20 and the data driver 11, so this embodiment can greatly simplify each The number of transistor elements required for the sub-pixels 22 [0] to 22 [n] is to further improve the layout flexibility of the display area 20 and help achieve a higher required resolution.

另一方面,需要說明的是,本實施例的第一開關SW1[0]與第二開關SW2[0]係為不同時導通。也就是說,本實施例的外部臨界電壓補償電路15[0]所使用到的補償時間,不與資料寫入子畫素22[0]~22[n]的時間有關。因此,即使當顯示面板1的解析度增加時,例如增加顯示面板1的資料線與掃描線,外部臨界電壓補償電路15[0]所能分配的補償時間不會因解析度增 加而相較於設置於子畫素內的內部臨界電壓補償電路的補償時間變少。舉例來說,本發明所揭露之一實施例的使用情況可以是在顯示面板1每次剛開機還未顯示正常畫面前的黑屏期間,控制截止第一開關SW1[0],並且控制導通第二開關SW2[0],以讓外部臨界電壓補償電路15[0]來依序對於這些子畫素22[0]~22[n]的每一者進行補償,但本發明亦不以為限制。另外,外部臨界電壓補償電路15[0]亦可以在顯示面板1未與顯示裝置或行動裝置整合時,預先進行臨界電壓補償設定。 On the other hand, it should be noted that the first switch SW1 [0] and the second switch SW2 [0] in this embodiment are not turned on at the same time. That is to say, the compensation time used by the external critical voltage compensation circuit 15 [0] of this embodiment is not related to the time when the data is written into the sub-pixels 22 [0] to 22 [n]. Therefore, even when the resolution of the display panel 1 is increased, for example, the data lines and scan lines of the display panel 1 are increased, the compensation time that can be allocated by the external critical voltage compensation circuit 15 [0] does not increase due to the resolution. In addition, the compensation time is shorter than the internal threshold voltage compensation circuit provided in the sub-pixel. For example, the use case of an embodiment disclosed in the present invention may be to control the first switch SW1 [0] to be turned off, and to control the second switch to be turned on during the black screen before the display panel 1 is turned on before the normal screen is displayed. The switch SW2 [0] enables the external threshold voltage compensation circuit 15 [0] to sequentially compensate each of these sub-pixels 22 [0] to 22 [n], but the present invention is not limited thereto. In addition, the external threshold voltage compensation circuit 15 [0] may also perform a threshold voltage compensation setting in advance when the display panel 1 is not integrated with a display device or a mobile device.

接著,同樣為了方便以下說明,本實施例將是僅先以探討外部臨界電壓補償電路15[0]所對於子畫素22[0]進行補償的例子來進行說明。請一併參閱圖2,圖2是圖1的顯示面板中的外部臨界電壓補償電路的電路示意圖。其中,圖2中部分與圖1相同之元件以相同之圖號標示,故於此不再多加詳述其細節。在本實施例中,外部臨界電壓補償電路15[0]即可包括運算放大器151及回授單元153。運算放大器151的反相輸入端(inverting input)電連接於第二開關SW2[0],運算放大器151的非反相輸入端(non-inverting input)則選擇性地接收第一參考電壓VREF1或第二參考電壓VREF2,且運算放大器151的輸出端則輸出第一積分值△O1或第二積分值△O2(請參閱圖3B及圖3D)。 Next, for the convenience of the following description, this embodiment will be described by taking only an example in which the sub-pixel 22 [0] is compensated by the external critical voltage compensation circuit 15 [0]. Please refer to FIG. 2 together. FIG. 2 is a circuit diagram of an external critical voltage compensation circuit in the display panel of FIG. 1. Among them, some components in FIG. 2 that are the same as those in FIG. 1 are marked with the same drawing numbers, and therefore no further details are given here. In this embodiment, the external critical voltage compensation circuit 15 [0] may include an operational amplifier 151 and a feedback unit 153. The inverting input of the operational amplifier 151 is electrically connected to the second switch SW2 [0], and the non-inverting input of the operational amplifier 151 selectively receives the first reference voltage V REF1 or The second reference voltage V REF2 , and the output terminal of the operational amplifier 151 outputs the first integrated value ΔO1 or the second integrated value ΔO2 (see FIG. 3B and FIG. 3D).

回授單元153電連接於運算放大器151的反相輸入端及輸出端間,且其係經由相互並聯的被動元件(passive component)及第三開關SW3所組成。在本實施例中,所述被動元件即可例如為電容CINT,但本發明卻不以此為限制。舉例來說,在其他實施例中,所述被動元件也可例如為電阻RFB(未繪示)。總而言之,本發明並不限制所述被動元件的具體實現方式,本技術領域中具有通常知識者應可依據實際需求或應用來進行相關設計。然而,為了讓運算放大器151的非反相輸入端可選擇性地接收第一參考電壓 VREF1或第二參考電壓VREF2,因此,實作上,外部臨界電壓補償電路15[0]更可包括第四開關SW4及第五開關SW5。 The feedback unit 153 is electrically connected between the inverting input terminal and the output terminal of the operational amplifier 151, and is composed of a passive component and a third switch SW3 connected in parallel with each other. In this embodiment, the passive component may be, for example, the capacitor C INT , but the invention is not limited thereto. For example, in other embodiments, the passive element may also be, for example, a resistor R FB (not shown). All in all, the present invention does not limit the specific implementation of the passive component, and those with ordinary knowledge in the technical field should be able to make related designs based on actual needs or applications. However, in order for the non-inverting input terminal of the operational amplifier 151 to selectively receive the first reference voltage V REF1 or the second reference voltage V REF2 , in practice, the external threshold voltage compensation circuit 15 [0] may further include The fourth switch SW4 and the fifth switch SW5.

如圖2所示,第四開關SW4係電連接於運算放大器151的非反相輸入端及第一參考電壓VREF1間,而第五開關SW5則電連接於運算放大器151的非反相輸入端及第二參考電壓VREF2間。另外,在本實施例,子畫素22[0]即可例如包括發光二極體OLED、驅動電晶體TD、儲存電容CST及開關電晶體T1~T3。子畫素22[0]的驅動電晶體TD係具有第一端接收供應電壓OVDD、第二端通過經由節點P2耦接至發光二極體OLED的陽極,以及閘極端通過經由節點P3耦接至資料線DL[0]。開關電晶體T1則串聯於節點P3至資料線DL[0]之間,且其具有閘極端接收掃描訊號S[0]、第一端電連接於節點P3,以及第二端電連接於資料線DL[0],並且根據掃描訊號S[0]而導通或截止。 As shown in FIG. 2, the fourth switch SW4 is electrically connected between the non-inverting input terminal of the operational amplifier 151 and the first reference voltage V REF1 , and the fifth switch SW5 is electrically connected to the non-inverting input terminal of the operational amplifier 151. And the second reference voltage V REF2 . In addition, in this embodiment, the sub-pixel 22 [0] may include, for example, a light emitting diode OLED, a driving transistor TD, a storage capacitor C ST, and switching transistors T1 to T3. The driving transistor TD of the sub-pixel 22 [0] has a first terminal receiving a supply voltage OVDD, a second terminal coupled to the anode of the light emitting diode OLED through a node P2, and a gate terminal coupled to the anode through a node P3 Data line DL [0]. The switching transistor T1 is connected in series between the node P3 and the data line DL [0], and has a gate terminal receiving the scanning signal S [0], the first terminal is electrically connected to the node P3, and the second terminal is electrically connected to the data line. DL [0], and is turned on or off according to the scanning signal S [0].

開關電晶體T2具有閘極端接收感測訊號R[0]、第一端電連接於資料線DL[0],以及第二端電連接於節點P2,並且根據感測訊號R[0]而導通或截止。開關電晶體T3則串聯於驅動電晶體TD的第二端至節點P2之間,且其具有閘極端接收發光控制訊號EM[0]、第一端電連接於驅動電晶體TD的第二端,以及第二端電連接於節點P2,並且根據發光控制訊號EM[0]而導通或截止。儲存電容CST則電連接於節點P3及驅動電晶體TD的第一端之間。 The switching transistor T2 has a gate terminal for receiving a sensing signal R [0], a first terminal is electrically connected to the data line DL [0], and a second terminal is electrically connected to the node P2, and is turned on according to the sensing signal R [0]. Or deadline. The switching transistor T3 is connected in series between the second terminal of the driving transistor TD and the node P2, and has a gate terminal for receiving the light-emitting control signal EM [0], and the first terminal is electrically connected to the second terminal of the driving transistor TD. And the second terminal is electrically connected to the node P2, and is turned on or off according to the light emission control signal EM [0]. The storage capacitor C ST is electrically connected between the node P3 and the first terminal of the driving transistor TD.

在本實施例中,上述驅動電晶體TD及開關電晶體T1~T3即可皆例如為P型低溫多晶矽薄膜電晶體(P-type LTPS TFT),但本發明卻不以此為限制。總而言之,由於子畫素22[0]的運作原理已為本技術領域中具有通常知識者所習知,因此有關上述細部內容於此亦就不再多加贅述。接著,請一併參閱圖3A~圖3D及圖4,圖3A~圖3D是圖2的外部臨界電壓補償電路所對於子畫素進行補償時的運作示意圖,而圖4則是圖2的外部臨界電壓 補償電路所對於子畫素進行補償時的時序示意圖。其中,圖3A~圖3D中部分與圖2相同之元件以相同之圖號標示,故於此不再多加詳述其細節。 In this embodiment, the driving transistors TD and the switching transistors T1 to T3 may be, for example, P-type low-temperature polycrystalline silicon thin-film transistors (P-type LTPS TFTs), but the present invention is not limited thereto. In a word, since the operation principle of the sub-pixel 22 [0] is already known to those having ordinary knowledge in the technical field, the details of the above-mentioned details will not be repeated here. Next, please refer to FIG. 3A to FIG. 3D and FIG. 4 together. FIG. 3A to FIG. 3D are schematic diagrams of operations performed by the external critical voltage compensation circuit of FIG. 2 when subpixels are compensated, and FIG. 4 is an external view of FIG. 2. Critical voltage Timing diagram when the compensation circuit compensates the sub-pixels. Among them, in FIG. 3A to FIG. 3D, some components that are the same as those in FIG. 2 are marked with the same drawing numbers, so details are not described in detail here.

首先,如圖3A及圖4所示,於第二開關SW2[0]導通的第一期間(1),外部臨界電壓補償電路15[0]係透過資料線DL[0]提供第一參考電壓VREF1至子畫素22[0]。其次,如圖3B及圖4所示,於第二開關SW2[0]導通的第二期間(2),外部臨界電壓補償電路15[0]則透過資料線DL[0]偵測流經子畫素22[0]之驅動電晶體TD的第一感測電流I1,並產生第一積分值△O1。 First, as shown in FIGS. 3A and 4, during the first period (1) when the second switch SW2 [0] is turned on, the external threshold voltage compensation circuit 15 [0] provides a first reference voltage through the data line DL [0]. V REF1 to sub-pixel 22 [0]. Secondly, as shown in FIG. 3B and FIG. 4, during the second period (2) when the second switch SW2 [0] is turned on, the external critical voltage compensation circuit 15 [0] detects the flow through sub-line through the data line DL [0]. The first sensing current I1 of the driving transistor TD of the pixel 22 [0] generates a first integrated value ΔO1.

顯然地,根據以上內容的教示,本技術領域中具有通常知識者應可以理解到,外部臨界電壓補償電路15[0]即為一積分器(integrator)。因此,於第二開關SW2[0]導通的第一期間(1),即該積分器的第一重置(first reset)期間,本實施例則控制導通第三開關SW3及第四開關SW4,並且截止第五開關SW5,然後藉由發光控制訊號EM[0]控制截止子畫素22[0]的開關電晶體T3,並且藉由掃描訊號S[0]及感測訊號R[0]分別控制導通子畫素22[0]的開關電晶體T1及開關電晶體T2,使得節點P1、P2及P3上能夠共同具有第一參考電壓VREF1的電壓。 Obviously, according to the teachings of the above content, those with ordinary knowledge in the technical field should understand that the external critical voltage compensation circuit 15 [0] is an integrator. Therefore, during the first period (1) where the second switch SW2 [0] is turned on, that is, the first reset period of the integrator, this embodiment controls the third switch SW3 and the fourth switch SW4 to be turned on. And the fifth switch SW5 is turned off, and then the switching transistor T3 that turns off the sub-pixel 22 [0] is controlled by the light emission control signal EM [0], and the scanning signal S [0] and the sensing signal R [0] are respectively The switching transistor T1 and the switching transistor T2 of the conductive sub-pixel 22 [0] are controlled, so that the nodes P1, P2, and P3 can have the voltage of the first reference voltage V REF1 in common.

相對地,於第二開關SW2[0]導通的第二期間(2),即該積分器的第一讀取(first readout)期間,本實施例則控制持續導通第四開關SW4,並且截止第三開關SW3,然後藉由發光控制訊號EM[0]及感測訊號R[0]分別控制導通子畫素22[0]的開關電晶體T3及開關電晶體T2,並且藉由掃描訊號S[0]控制截止子畫素22[0]的開關電晶體T1,使得外部臨界電壓補償電路15[0]能夠回應流經自驅動電晶體TD的第一感測電流I1而產生第一積分值△O1。 In contrast, during the second period (2) where the second switch SW2 [0] is turned on, that is, the first readout period of the integrator, this embodiment controls the fourth switch SW4 to be continuously turned on, and the first switch SW4 is turned off. Three switches SW3, and then control the switching transistor T3 and the switching transistor T2 of the sub-pixel 22 [0] by the light-emitting control signal EM [0] and the sensing signal R [0], respectively, and by scanning the signal S [ 0] Control the switching transistor T1 of the sub-pixel 22 [0], so that the external critical voltage compensation circuit 15 [0] can generate a first integrated value △ in response to the first sensing current I1 flowing through the self-driving transistor TD O1.

一般來說,因為這時驅動電晶體TD的驅動電壓,亦即供應電壓OVDD與節點P3的電壓差值是固定的,所以第一感測電流I1也是固定的, 且其通過經由驅動電晶體TD、開關電晶體T3、節點P2、開關電晶體T2、節點P1及第二開關SW2[0]而流回運算放大器151的反相輸入端。然後,本實施例藉由控制感測電流的流出時間△tRD,外部臨界電壓補償電路15[0],即積分器所能產生的第一積分值△O1便可表示成△O1=(-I1*△tRD)/CST。應當理解的是,所述△tRD也就泛指為積分時間,但本發明並不限制其數值的具體實現方式,本技術領域中具有通常知識者應可依據實際需求或應用來進行相關設計。由於積分器的運作原理已為本技術領域中具有通常知識者所習知,因此有關上述細部內容於此亦就不再多加贅述。 Generally, because the driving voltage of the driving transistor TD at this time, that is, the voltage difference between the supply voltage OVDD and the node P3 is fixed, the first sensing current I1 is also fixed, and it passes through the driving transistor TD, The switching transistor T3, the node P2, the switching transistor T2, the node P1, and the second switch SW2 [0] flow back to the inverting input terminal of the operational amplifier 151. Then, in this embodiment, by controlling the outflow time Δt RD of the sensing current, the external critical voltage compensation circuit 15 [0], that is, the first integrated value ΔO1 that can be generated by the integrator can be expressed as ΔO1 = (- I1 * △ t RD ) / C ST . It should be understood that the Δt RD is generally referred to as the integration time, but the present invention does not limit the specific implementation of its value. Those with ordinary knowledge in the technical field should be able to make related designs based on actual needs or applications. . Since the operation principle of the integrator is already known to those with ordinary knowledge in the technical field, the details of the above-mentioned details will not be repeated here.

接著,如圖3C及圖4所示,於第二開關SW2[0]導通的第三期間(3),外部臨界電壓補償電路15[0]係透過資料線DL[0]提供第二參考電壓VREF2至子畫素22[0]。需要說明的是,如同前面內容所述,由於這時的補償機制是在顯示面板1剛開機而未顯示正常畫面前的黑屏期間作動,因此,為了確保不讓子畫素22[0]的發光二極體OLED發亮,所以本實施例的第一參考電壓VREF1及第二參考電壓VREF2係皆小於等於電連接至子畫素22[0]之發光二極體OLED的供應電壓OVSS與發光二極體OLED的導通電壓之總和,且第二參考電壓VREF2不等於第一參考電壓VREF1。再者,如圖3D及圖4所示,於第二開關SW2[0]導通的第四期間(4),外部臨界電壓補償電路15[0]則透過資料線DL[0]偵測流經子畫素22[0]之驅動電晶體TD的第二感測電流I2,並產生第二積分值△O2。 Next, as shown in FIG. 3C and FIG. 4, during the third period (3) when the second switch SW2 [0] is turned on, the external threshold voltage compensation circuit 15 [0] provides a second reference voltage through the data line DL [0]. V REF2 to sub-pixel 22 [0]. It should be noted that, as described in the foregoing, the compensation mechanism at this time operates during the black screen just before the display panel 1 is turned on but the normal screen is not displayed. Therefore, in order to ensure that the sub-pixel 22 [0] does not emit light, The polar OLED is illuminated, so the first reference voltage V REF1 and the second reference voltage V REF2 in this embodiment are both less than or equal to the supply voltage OVSS and light emission of the light-emitting diode OLED electrically connected to the sub-pixel 22 [0]. The sum of the on-voltages of the diode OLED, and the second reference voltage V REF2 is not equal to the first reference voltage V REF1 . Furthermore, as shown in FIG. 3D and FIG. 4, during the fourth period (4) when the second switch SW2 [0] is turned on, the external threshold voltage compensation circuit 15 [0] detects the flow through the data line DL [0]. The second sensing current I2 of the driving transistor TD of the sub-pixel 22 [0] generates a second integrated value ΔO2.

也就是說,於第二開關SW2[0]導通的第三期間(3),即該積分器的第二重置期間,本實施例則控制導通第三開關SW3及第五開關SW5,並且截止第四開關SW4,然後藉由發光控制訊號EM[0]控制截止子畫素22[0]的開關電晶體T3,並且藉由掃描訊號S[0]及感測訊號R[0]分別控制導通子畫素 22[0]的開關電晶體T1及開關電晶體T2,使得節點P1、P2及P3上能夠共同具有第二參考電壓VREF2的電壓。 That is, during the third period (3) where the second switch SW2 [0] is turned on, that is, the second reset period of the integrator, this embodiment controls the third switch SW3 and the fifth switch SW5 to be turned on and turned off. The fourth switch SW4 then controls the switching transistor T3 of the sub-pixel 22 [0] by the light-emitting control signal EM [0], and controls the conduction by the scanning signal S [0] and the sensing signal R [0], respectively. The switching transistor T1 and the switching transistor T2 of the sub-pixel 22 [0] enable the nodes P1, P2, and P3 to have the voltage of the second reference voltage V REF2 in common.

相對地,於第二開關SW2[0]導通的第四期間(4),即該積分器的第二讀取期間,本實施例則控制持續導通五開關SW5,並且截止第三開關SW3,然後藉由發光控制訊號EM[0]及感測訊號R[0]分別控制導通子畫素22[0]的開關電晶體T3及開關電晶體T2,並且藉由掃描訊號S[0]控制截止子畫素22[0]的開關電晶體T1,使得外部臨界電壓補償電路15[0]能夠回應流經自驅動電晶體TD的第二感測電流I2而產生第二積分值△O2。 In contrast, during the fourth period (4) where the second switch SW2 [0] is turned on, that is, the second read period of the integrator, this embodiment controls the five switches SW5 to be continuously turned on, and the third switch SW3 to be turned off, and then The light-emitting control signal EM [0] and the sensing signal R [0] respectively control the switching transistor T3 and the switching transistor T2 of the sub-pixel 22 [0], and control the cut-off element by the scanning signal S [0] The switching transistor T1 of the pixel 22 [0] enables the external threshold voltage compensation circuit 15 [0] to generate a second integrated value ΔO2 in response to the second sensing current I2 flowing through the self-driving transistor TD.

類似地,外部臨界電壓補償電路15[0],即積分器所能產生的第二積分值△O2便可表示成△O2=(-I2*△tRD)/CST。然後,為了讓外部臨界電壓補償電路15[0]能再緊接著對於子畫素22[1]~22[n]的每一者進行補償,因此,當已取得到與子畫素22[0]有關的第一積分值△O1及第二積分值△O2後,本實施例則藉由發光控制訊號EM[0]、掃描訊號S[0]及感測訊號R[0]分別控制截止子畫素22[0]的開關電晶體T3、開關電晶體T1及開關電晶體T2,如圖3E所示。也就是說,如圖4所示,對於與子畫素22[0]同行的下一子畫素22[1]而言,外部臨界電壓補償電路15[0]則將再用來重新進行上述操作,藉此取得到有關下一子畫素22[1]的第一積分值△O1及第二積分值△O2,以此類推,而有關外部臨界電壓補償電路15[0]所再接續對於子畫素22[1]~22[n]的每一者進行補償時的詳盡細節亦如同前述實施例所述,故於此就不再多加贅述。 Similarly, the external critical voltage compensation circuit 15 [0], that is, the second integrated value ΔO2 generated by the integrator can be expressed as ΔO2 = (-I2 * Δt RD ) / C ST . Then, in order to allow the external threshold voltage compensation circuit 15 [0] to compensate for each of the sub-pixels 22 [1] to 22 [n] again, when the sub-pixels 22 [0] have been obtained, ] After the relevant first integrated value △ O1 and the second integrated value △ O2, in this embodiment, the cut-off is controlled by the light emitting control signal EM [0], the scanning signal S [0], and the sensing signal R [0], respectively. The switching transistor T3, the switching transistor T1, and the switching transistor T2 of the pixel 22 [0] are shown in FIG. 3E. In other words, as shown in FIG. 4, for the next sub-pixel 22 [1] that is accompanying the sub-pixel 22 [0], the external threshold voltage compensation circuit 15 [0] will be used to perform the above-mentioned process again. Operation to obtain the first integrated value ΔO1 and the second integrated value ΔO2 of the next sub-pixel 22 [1], and so on, and the external critical voltage compensation circuit 15 [0] is further connected to the The detailed details of each of the sub-pixels 22 [1] to 22 [n] when performing compensation are also described in the foregoing embodiment, so they will not be repeated here.

每一子畫素22[0]~22[n]的第一積分值△O1及第二積分值△O2的相除結果,即能為每一子畫素22[0]~22[n]的第一感測電流I1及第二感測電流I2的相除結果。因此,對於每一子畫素22[0]~22[n]而言,其臨界電壓值Vth便可表示成如下方程式(1)所示。其中,K代表製程係數,但本發明並不 限制其數值的具體實現方式,本技術領域中具有通常知識者應可依據實際需求或應用來進行相關設計。 The division result of the first integrated value △ O1 and the second integrated value △ O2 of each sub-pixel 22 [0] ~ 22 [n] can be 22 [0] ~ 22 [n] for each sub-pixel A division result of the first sensing current I1 and the second sensing current I2. Therefore, for each sub-pixel 22 [0] ~ 22 [n], its threshold voltage value Vth can be expressed as shown in the following equation (1). Among them, K represents a process coefficient, but the present invention does not Specific implementations whose values are limited, those with ordinary knowledge in the technical field should be able to make related designs based on actual needs or applications.

總而言之,從上述內容可知,本實施例的外部臨界電壓補償電路15[0]便能夠取得到有關每一子畫素22[0]~22[n]的臨界電壓值Vth。最後,為了更進一步說明關於外部臨界電壓補償電路15[0]進行補償時的實現細節,本發明進一步提供其外部臨界電壓補償電路15[0]的一種實施方式。請參閱圖5,圖5是圖2的外部臨界電壓補償電路於另一實施例的示意圖。其中,圖5中部分與圖2相同之元件以相同之圖號標示,故於此不再多加詳述其細節。 In a word, it can be known from the foregoing that the external threshold voltage compensation circuit 15 [0] of this embodiment can obtain the threshold voltage value Vth of each sub-pixel 22 [0] ~ 22 [n]. Finally, in order to further explain the implementation details when the external critical voltage compensation circuit 15 [0] performs compensation, the present invention further provides an implementation manner of the external critical voltage compensation circuit 15 [0]. Please refer to FIG. 5, which is a schematic diagram of the external critical voltage compensation circuit of FIG. 2 in another embodiment. Among them, the parts in FIG. 5 that are the same as those in FIG. 2 are marked with the same drawing numbers, so the details are not described in detail here.

如圖5所示,外部臨界電壓補償電路15[0]更可包括類比數位轉換器155、儲存器157及資料更新單元159。其中,上述各元件可以是透過硬件電路來實現,或者是透過硬件電路搭配固件或軟件來實現,但本發明並不以此為限制。除此之外,上述各元件可以是整合或是分開設置,且本發明亦不以此為限制。 As shown in FIG. 5, the external critical voltage compensation circuit 15 [0] may further include an analog-to-digital converter 155, a storage 157, and a data update unit 159. Wherein, the foregoing components may be implemented through hardware circuits, or may be implemented through hardware circuits combined with firmware or software, but the present invention is not limited thereto. In addition, the above components may be integrated or separately provided, and the present invention is not limited thereto.

在本實施例中,類比數位轉換器155係電連接於運算放大器151,並且針對進行補償的子畫素,例如子畫素22[0]而言,類比數位轉換器155則用來分別將其第一積分值△O1及第二積分值△O2,轉換成為第一數位補償值及第二數位補償值(未繪示)。儲存器157電連接於類比數位轉換器 155,並且針對進行補償的子畫素22[0]而言,儲存器157則用來儲存其第一及第二數位補償值。資料更新單元159電連接於儲存器157及資料驅動器11間,並且針對進行補償的子畫素22[0]而言,資料更新單元159則用來接收顯示資料DATA,以及根據前述第一數位補償值及第二數位補償值,產生相應於子畫素22[0]的補償訊號,並且在子畫素22[0]的顯示期間,根據補償訊號及顯示資料DATA提供更新後的顯示資料DATAc至子畫素22[0]。值得一提的是,所述資料更新單元159可以是如圖5所示獨立設置,或者資料更新單元159可以為整合於資料驅動器11或時序控制器(未繪示)內之邏輯電路,亦即資料更新單元159可以加法器等邏輯電路實現,但本發明亦不以此為限制。 In this embodiment, the analog-to-digital converter 155 is electrically connected to the operational amplifier 151, and for the sub-pixels to be compensated, such as the sub-pixel 22 [0], the analog-to-digital converter 155 is used to separately The first integrated value ΔO1 and the second integrated value ΔO2 are converted into a first digital compensation value and a second digital compensation value (not shown). The memory 157 is electrically connected to the analog-to-digital converter 155, and for the compensated sub-pixel 22 [0], the storage 157 is used to store its first and second digital compensation values. The data update unit 159 is electrically connected between the storage 157 and the data driver 11, and for the compensated sub-pixel 22 [0], the data update unit 159 is used to receive the display data DATA, and to compensate according to the aforementioned first digital digit Value and the second digital compensation value to generate a compensation signal corresponding to sub-pixel 22 [0], and during the display period of sub-pixel 22 [0], the updated display data DATAc is provided according to the compensation signal and the display data DATA to Subpixel 22 [0]. It is worth mentioning that the data update unit 159 may be provided independently as shown in FIG. 5, or the data update unit 159 may be a logic circuit integrated in the data driver 11 or a timing controller (not shown), that is, The data updating unit 159 may be implemented by a logic circuit such as an adder, but the present invention is not limited thereto.

應當理解的是,本文所述之「子畫素22[0]的補償訊號」即能指的就是子畫素22[0]的臨界電壓值Vth,但本發明亦不以此為限制,子畫素22[0]的補償訊號還可以根據使用者需求有不同設計。另外,本文所述之「子畫素22[0]的顯示期間」也就能指的是第一開關SW1[0]導通而第二開關SW2[0]截止的期間。換句話說,本發明實施例所提供的外部臨界電壓補償電路15[0]將能藉由在資料寫入至子畫素22[0]的期間,即子畫素22[0]的顯示期間,使得資料驅動器11能夠根據子畫素22[0]的臨界電壓值Vth來調整顯示資料DATA,從而讓子畫素22[0]的驅動電晶體TD在使發光二極體OLED發光時所輸出的驅動電流IOLED而不受到其臨界電壓值Vth變異所影響,並藉此解決前述亮度不均或顯示品質不良的習知問題。 It should be understood that the “compensation signal for the sub-pixel 22 [0]” referred to herein can refer to the threshold voltage value Vth of the sub-pixel 22 [0], but the present invention is not limited to this. The compensation signal of pixel 22 [0] can also be designed differently according to user needs. In addition, the “display period of the sub-pixel 22 [0]” described herein can also refer to a period in which the first switch SW1 [0] is turned on and the second switch SW2 [0] is turned off. In other words, the external critical voltage compensation circuit 15 [0] provided by the embodiment of the present invention will be able to write data to the period of the sub-pixel 22 [0], that is, the display period of the sub-pixel 22 [0]. , So that the data driver 11 can adjust the display data DATA according to the threshold voltage value Vth of the sub-pixel 22 [0], so that the driving transistor TD of the sub-pixel 22 [0] outputs when the light-emitting diode OLED emits light The driving current I OLED is not affected by the variation of its threshold voltage Vth, and thereby solves the aforementioned conventional problems of uneven brightness or poor display quality.

舉例來說,若同樣是以子畫素22[0]的例子來作說明的話,請一併參閱圖6A~圖6C及圖7,圖6A~圖6C是圖1的顯示面板中的子畫素於顯示期間的運作示意圖,而圖7則是圖1的顯示面板中的子畫素於顯示期間的時 序示意圖。其中,圖6A~圖6C中部分與圖2相同之元件以相同之圖號標示,故於此不再多加詳述其細節。 For example, if the description is also based on the example of the sub-pixel 22 [0], please refer to FIGS. 6A to 6C and FIG. 7 together. FIGS. 6A to 6C are sub-pictures in the display panel of FIG. 1. The schematic diagram of the operation during the display period, and FIG. 7 is the time during which the sub-pixels in the display panel of FIG. 1 are displayed. Sequence diagram. Among them, some of the same components in FIG. 6A to FIG. 6C as those in FIG. 2 are marked with the same reference numerals, so the details are not described in detail here.

如圖6A及圖7所示,於第一開關SW1[0]導通的第一期間(1’),即子畫素22[0]的重置期間,本實施例則藉由發光控制訊號EM[0]控制截止子畫素22[0]的開關電晶體T3,並且藉由掃描訊號S[0]及感測訊號R[0]分別控制導通子畫素22[0]的開關電晶體T1及開關電晶體T2,使得節點P1、P2及P3上能夠共同具有電壓VINT(未繪示)的電壓。相對地,如圖6B及圖7所示,於第一開關SW1[0]導通的第二期間(2’),即子畫素22[0]的資料寫入期間,本實施例則藉由發光控制訊號EM[0]及感測訊號R[0]分別控制截止子畫素22[0]的開關電晶體T3及開關電晶體T2,並且藉由掃描訊號S[0]控制導通子畫素22[0]的開關電晶體T1,使得節點P2上仍具有電壓VINT的電壓,但節點P1及P3則接收到子畫素22[0]的顯示資料DATAc[0]。 As shown in FIG. 6A and FIG. 7, during the first period (1 ′) where the first switch SW1 [0] is turned on, that is, the reset period of the sub-pixel 22 [0], the light control signal EM is used in this embodiment. [0] Control the switching transistor T3 of the sub-pixel 22 [0], and control the switching transistor T1 of the sub-pixel 22 [0] by scanning the signal S [0] and the sensing signal R [0], respectively. And the switching transistor T2, so that the nodes P1, P2, and P3 can have a voltage of a voltage V INT (not shown) in common. In contrast, as shown in FIG. 6B and FIG. 7, during the second period (2 ′) where the first switch SW1 [0] is turned on, that is, the data writing period of the sub-pixel 22 [0], this embodiment uses The light-emitting control signal EM [0] and the sensing signal R [0] control the switching transistor T3 and the switching transistor T2 of the sub-pixel 22 [0], respectively, and control the sub-pixel by the scanning signal S [0] The switching transistor T1 of 22 [0] makes the node P2 still have the voltage V INT , but the nodes P1 and P3 receive the display data DATAc [0] of the sub-pixel 22 [0].

最後,如圖6C及圖7所示,第一開關SW1[0]導通的第三期間(3’),即子畫素22[0]之發光二極體OLED的發光期間,本實施例則藉由發光控制訊號EM[0]控制導通子畫素22[0]的開關電晶體T3,並且藉由掃描訊號S[0]及感測訊號R[0]分別控制截止子畫素22[0]的開關電晶體T1及開關電晶體T2,使得驅動電晶體TD輸出驅動電流IOLED來讓發光二極體OLED發光。顯然地,子畫素22[0]的驅動電晶體TD在使發光二極體OLED發光時所輸出的驅動電流IOLED便可簡化表示成如下方程式(2)所示。然而,由於子畫素22[0]的顯示原理已為本技術領域中具有通常知識者所習知,因此有關上述細部內容於此亦就不再多加贅述。 Finally, as shown in FIG. 6C and FIG. 7, the third period (3 ′) during which the first switch SW1 [0] is turned on, that is, the light-emitting period of the light-emitting diode OLED of the sub-pixel 22 [0]. The switching transistor T3 that turns on the sub-pixel 22 [0] is controlled by the light emission control signal EM [0], and the cut-off sub-pixel 22 [0] is controlled by the scanning signal S [0] and the sensing signal R [0], respectively. ] The switching transistor T1 and the switching transistor T2 enable the driving transistor TD to output a driving current I OLED to cause the light emitting diode OLED to emit light. Obviously, the driving current I OLED output by the driving transistor TD of the sub-pixel 22 [0] when the light-emitting diode OLED emits light can be simplified and expressed as shown in the following equation (2). However, since the display principle of the sub-pixel 22 [0] is already known to those having ordinary knowledge in the technical field, the details of the above-mentioned details will not be repeated here.

另一方面,若同樣是以子畫素22[0]的例子來作說明的話,請參閱圖8,圖8則是圖1的顯示面板中的子畫素於另一實施例的電路示意圖。其中,圖8中部分與圖2相同之元件以相同之圖號標示,故於此不再多加詳述其細節。如圖8所示,子畫素22[0]也可例如包括發光二極體OLED、驅動電晶體TD、儲存電容CST’及開關電晶體T1’~T2’。需要說明的是,圖8的驅動電晶體TD可以是根據發光控制訊號EM[0]而導通或截止。開關電晶體T1’則具有閘極端接收掃描訊號S[0]、第一端電連接於節點P3以及第二端電連接於資料線DL[0],並且根據掃描訊號S[0]而導通或截止。 On the other hand, if the description is also based on the example of the sub-pixel 22 [0], please refer to FIG. 8, which is a schematic circuit diagram of the sub-pixel in the display panel of FIG. 1 according to another embodiment. Among them, some components in FIG. 8 that are the same as those in FIG. 2 are marked with the same drawing numbers, so the details are not described in detail here. As shown in FIG. 8, the sub-pixel 22 [0] may also include, for example, a light emitting diode OLED, a driving transistor TD, a storage capacitor C ST ′, and switching transistors T1 ′ to T2 ′. It should be noted that the driving transistor TD in FIG. 8 may be turned on or off according to the light emission control signal EM [0]. The switching transistor T1 'has a gate terminal to receive the scanning signal S [0], the first terminal is electrically connected to the node P3, and the second terminal is electrically connected to the data line DL [0], and is turned on according to the scanning signal S [0] or cutoff.

開關電晶體T2’具有閘極端接收感測訊號R[0]、第一端電連接於DL[0],以及第二端電連接於節點P2,並且根據感測訊號R[0]而導通或截止。儲存電容CST’則電連接於節點P3及驅動電晶體TD的第一端之間。在本實施例中,上述開關電晶體T1’及T2’亦可皆例如為P型低溫多晶矽薄膜電晶體,但本發明卻不以此為限制。相較於圖2的子畫素22[0]而言,圖8的子畫素22[0]通過減少一個薄膜電晶體,以減低佈局面積。由於圖8的子畫素22[0]其餘操作細節大致上與前述實施例所述操作相似,故此處不另贅述。 The switching transistor T2 'has a gate terminal for receiving a sensing signal R [0], a first terminal is electrically connected to DL [0], and a second terminal is electrically connected to the node P2, and is turned on according to the sensing signal R [0] or cutoff. The storage capacitor C ST ′ is electrically connected between the node P3 and the first terminal of the driving transistor TD. In this embodiment, the above-mentioned switching transistors T1 ′ and T2 ′ may both be P-type low-temperature polycrystalline silicon thin-film transistors, but the present invention is not limited thereto. Compared with the sub-pixel 22 [0] of FIG. 2, the sub-pixel 22 [0] of FIG. 8 reduces the layout area by reducing a thin film transistor. Since the remaining operation details of the sub-pixel 22 [0] of FIG. 8 are substantially similar to the operations described in the foregoing embodiment, no further details are provided here.

綜上所述,本發明實施例所提供的顯示面板,可以是讓同一行內的多個子畫素皆共用同一外部臨界電壓補償電路,且此外部臨界電壓補償電路設置於顯示面板的週邊區內,而非設置於顯示面板的顯示區內,因此,本發明實施例將能夠簡化每一子畫素所需的元件個數,以進而提升顯示區的佈局彈性,並且有助於實現更高需求的解析度,而且即使當顯示面板的解析度變高時,本實施例的外部臨界電壓補償電路所能用到的補償時間也不會相對變少。此外,本實施例的外部臨界電壓補償電路將藉由在資料寫入至子畫素的期間,使得資料驅動器能夠根據子畫素的臨界電壓來調整顯示資料,從而讓子畫素的驅動電晶體在使發光二極體發光時所輸出的驅動 電流而不受到其臨界電壓變異所影響,並藉此解決前述亮度不均或顯示品質不良的習知問題。 In summary, the display panel provided by the embodiment of the present invention may allow multiple sub-pixels in the same row to share the same external critical voltage compensation circuit, and the external critical voltage compensation circuit is disposed in the peripheral area of the display panel. Instead of being located in the display area of the display panel, the embodiments of the present invention will be able to simplify the number of elements required for each sub-pixel, thereby improving the layout flexibility of the display area and helping to achieve higher demand And even when the resolution of the display panel becomes high, the compensation time that can be used by the external threshold voltage compensation circuit of this embodiment will not be relatively reduced. In addition, the external threshold voltage compensation circuit of this embodiment will enable the data driver to adjust the display data according to the threshold voltage of the subpixel by writing data to the subpixel, thereby allowing the subpixel to drive the transistor. Driving output when the light emitting diode is made to emit light The current is not affected by the variation of its threshold voltage, thereby solving the aforementioned conventional problems of uneven brightness or poor display quality.

以上所述僅為本發明之實施例,其並非用以侷限本發明之專利範圍。 The above description is only an embodiment of the present invention, and is not intended to limit the patent scope of the present invention.

Claims (9)

一種顯示面板,具有一週邊區及一顯示區,其中一畫素串設置於該顯示區,該畫素串包含多個子畫素,且每一該些子畫素皆電連接於一資料線,該資料線與一資料驅動器間具有一第一開關,一外部臨界電壓補償電路設置於該週邊區,並且通過經由一第二開關電連接於該資料線,以用來依序對於該些子畫素中的一者進行補償,其中: 於該第二開關導通的一第一期間,該外部臨界電壓補償電路透過該資料線提供一第一參考電壓至該子畫素; 於該第二開關導通的一第二期間,該外部臨界電壓補償電路透過該資料線偵測流經該子畫素之一驅動電晶體的一第一感測電流,並產生一第一積分值; 於該第二開關導通的一第三期間,該外部臨界電壓補償電路透過該資料線提供一第二參考電壓至該子畫素,該第一參考電壓及該第二參考電壓係皆小於等於電連接至該子畫素之一發光二極體的一第一供應電壓與該發光二極體的一導通電壓之總和,且該第二參考電壓不等於該第一參考電壓; 於該第二開關導通的一第四期間,該外部臨界電壓補償電路透過該資料線偵測流經該子畫素之該驅動電晶體的一第二感測電流,並產生一第二積分值;以及 於一顯示期間,該第一開關導通。A display panel has a peripheral area and a display area, wherein a pixel string is disposed in the display area, the pixel string includes a plurality of sub pixels, and each of the sub pixels is electrically connected to a data line. There is a first switch between the data line and a data driver, and an external critical voltage compensation circuit is disposed in the peripheral area, and is electrically connected to the data line through a second switch for sequentially ordering the sub-pictures. One of the pixels is compensated, wherein: during a first period when the second switch is turned on, the external threshold voltage compensation circuit provides a first reference voltage to the sub-pixel through the data line; when the second switch is turned on During a second period, the external critical voltage compensation circuit detects a first sensing current flowing through a driving transistor of one of the sub-pixels through the data line, and generates a first integrated value; at the second switch During a third period of conduction, the external critical voltage compensation circuit provides a second reference voltage to the sub-pixel through the data line, and the first reference voltage and the second reference voltage are both less than or equal to electrically connected to the The sum of a first supply voltage of a light-emitting diode and a turn-on voltage of the light-emitting diode, and the second reference voltage is not equal to the first reference voltage; During the four periods, the external critical voltage compensation circuit detects a second sensing current flowing through the driving transistor of the sub-pixel through the data line, and generates a second integrated value; and during a display period, the first A switch is turned on. 如請求項第1項所述的顯示面板,其中該第一開關與該第二開關不同時導通。The display panel according to claim 1, wherein the first switch and the second switch are not turned on at the same time. 如請求項第1項所述的顯示面板,其中該外部臨界電壓補償電路包括: 一運算放大器,具有一反相輸入端電連接於該第二開關、一非反相輸入端選擇性地接收該第一或該第二參考電壓,以及一輸出端輸出該第一或該第二積分值;以及 一回授單元,電連接於該運算放大器的該反相輸入端及該輸出端間,其中該回授單元係經由相互並聯的一被動元件及一第三開關所組成,並且於該第二開關導通的該第一期間及該第三期間而導通該第三開關,於該第二開關導通的該第二期間及該第四期間而截止該第三開關。The display panel according to claim 1, wherein the external critical voltage compensation circuit includes: an operational amplifier having an inverting input terminal electrically connected to the second switch, and a non-inverting input terminal selectively receiving the A first or the second reference voltage, and an output terminal outputting the first or the second integral value; and a feedback unit electrically connected between the inverting input terminal and the output terminal of the operational amplifier, wherein the The feedback unit is composed of a passive element and a third switch connected in parallel with each other, and the third switch is turned on during the first period and the third period when the second switch is turned on. The third switch is turned off in the second period and the fourth period. 如請求項第3項所述的顯示面板,其中該外部臨界電壓補償電路更包括: 一第四開關,電連接於該運算放大器的該非反相輸入端及該第一參考電壓間,並且於該第二開關導通的該第一期間及該第二期間而導通該第四開關,於該第二開關導通的該第三期間及該第四期間而截止該第四開關;以及 一第五開關,電連接於該運算放大器的該非反相輸入端及該第二參考電壓間,並且於該第二開關導通的該第一期間及該第二期間而截止該第五開關,於該第二開關導通的該第三期間及該第四期間而導通該第五開關。The display panel according to claim 3, wherein the external critical voltage compensation circuit further includes: a fourth switch electrically connected between the non-inverting input terminal of the operational amplifier and the first reference voltage, and The fourth switch is turned on for the first period and the second period to turn on the fourth switch, and the fourth switch is turned off for the third period and the fourth period when the second switch is turned on; and a fifth switch, Is electrically connected between the non-inverting input terminal of the operational amplifier and the second reference voltage, and turns off the fifth switch during the first period and the second period when the second switch is turned on, and turns on the second switch The fifth period is turned on in the third period and the fourth period. 如請求項第4項所述的顯示面板,其中該子畫素的該驅動電晶體係具有一第一端接收一第二供應電壓、一第二端通過經由一第一節點耦接至該發光二極體的一陽極,以及一閘極端通過經由一第二節點耦接至該資料線。The display panel according to claim 4, wherein the driving transistor system of the sub-pixel has a first terminal receiving a second supply voltage, and a second terminal coupled to the light-emitting device through a first node. An anode and a gate terminal of the diode are coupled to the data line through a second node. 如請求項第5項所述的顯示面板,其中該子畫素更包括: 一第一開關電晶體,串聯於該第二節點至該資料線之間,具有一閘極端接收一掃描訊號、一第一端電連接於該第二節點,以及一第二端電連接於該資料線,並且根據該掃描訊號而導通或截止; 一第二開關電晶體,具有一閘極端接收一感測訊號、一第一端電連接於該資料線,以及一第二端電連接於該第一節點,並且根據該感測訊號而導通或截止; 一第三開關電晶體,串聯於該驅動電晶體的該第二端至該第一節點之間,具有一閘極端接收一發光控制訊號、一第一端電連接於該驅動電晶體的該第二端,以及一第二端電連接於該第一節點,並且根據該發光控制訊號而導通或截止;以及 一儲存電容,電連接於該第二節點及該驅動電晶體的該第一端之間。The display panel according to claim 5, wherein the sub-pixel further includes: a first switching transistor connected in series between the second node and the data line, and having a gate terminal for receiving a scanning signal, a The first terminal is electrically connected to the second node, and a second terminal is electrically connected to the data line, and is turned on or off according to the scanning signal; a second switching transistor has a gate terminal to receive a sensing signal, A first terminal is electrically connected to the data line, and a second terminal is electrically connected to the first node, and is turned on or off according to the sensing signal; a third switching transistor is connected in series with the driving transistor. Between the second end and the first node, a gate terminal receives a light-emitting control signal, a first end is electrically connected to the second end of the driving transistor, and a second end is electrically connected to the first node. And is turned on or off according to the light emitting control signal; and a storage capacitor is electrically connected between the second node and the first terminal of the driving transistor. 如請求項第6項所述的顯示面板,其中於該第二開關導通的該第一期間及該第三期間,該發光控制訊號係用以截止該子畫素的該第三開關電晶體,該掃描訊號及該感測訊號則分別導通該子畫素的該第一開關電晶體及該第二開關電晶體,使得該第一節點及該第二節點上則能共同具有該第一參考電壓或該第二參考電壓的電壓,並且於該第二開關導通的該第二期間及該第四期間,該發光控制訊號及該感測訊號係分別導通該子畫素的該第三開關電晶體及該第二開關電晶體,該掃描訊號則用以截止該子畫素的該第一開關電晶體,使得該外部臨界電壓補償電路能夠回應流經自該驅動電晶體的該第一感測電流或該第二感測電流而產生該第一積分值或該第二積分值。The display panel according to claim 6, wherein during the first period and the third period when the second switch is turned on, the light-emitting control signal is used to turn off the third switching transistor of the sub-pixel, The scanning signal and the sensing signal respectively turn on the first switching transistor and the second switching transistor of the sub-pixel, so that the first node and the second node can have the first reference voltage in common. Or the voltage of the second reference voltage, and during the second period and the fourth period when the second switch is turned on, the light-emitting control signal and the sensing signal are respectively turned on by the third switching transistor of the sub-pixel. And the second switching transistor, the scanning signal is used to cut off the first switching transistor of the sub-pixel, so that the external critical voltage compensation circuit can respond to the first sensing current flowing through the driving transistor Or the second sensing current generates the first integrated value or the second integrated value. 如請求項第5項所述的顯示面板,其中該子畫素的該驅動電晶體係根據該發光控制訊號而導通或截止,且該子畫素更包括: 一第一開關電晶體,串聯於該第二節點至該資料線之間,具有一閘極端接收一掃描訊號、一第一端電連接於該第二節點,以及一第二端電連接於該資料線,並且根據該掃描訊號而導通或截止; 一第二開關電晶體,具有一閘極端接收一感測訊號、一第一端電連接於該資料線,以及一第二端電連接於該第一節點,並且根據該感測訊號而導通或截止;以及 一儲存電容,電連接於該第二節點及該驅動電晶體的該第一端之間。The display panel according to claim 5, wherein the driving transistor system of the sub-pixel is turned on or off according to the light emission control signal, and the sub-pixel further includes: a first switching transistor connected in series with Between the second node and the data line, a gate terminal receives a scanning signal, a first terminal is electrically connected to the second node, and a second terminal is electrically connected to the data line, and according to the scanning signal, On or off; a second switching transistor with a gate terminal receiving a sensing signal, a first terminal electrically connected to the data line, and a second terminal electrically connected to the first node, and according to the sensing The signal is turned on or off; and a storage capacitor is electrically connected between the second node and the first terminal of the driving transistor. 如請求項第3項所述的顯示面板,其中該外部臨界電壓補償電路更包括: 一類比數位轉換器,電連接於該運算放大器,該類比數位轉換器則用來分別將該第一積分值及該第二積分值,轉換成為一第一數位補償值及一第二數位補償值; 一儲存器,電連接於該類比數位轉換器,該儲存器則用來儲存該第一數位補償值及該第二數位補償值;以及 一資料更新單元,電連接於該儲存器及該資料驅動器間,該資料更新單元則用來接收一顯示資料,以及根據該第一數位補償值及該第二數位補償值,產生相應於該子畫素的一補償訊號,並且於該顯示期間,根據該補償訊號及該顯示資料提供一更新後的顯示資料至該子畫素。The display panel according to item 3 of the claim, wherein the external critical voltage compensation circuit further comprises: an analog digital converter electrically connected to the operational amplifier, and the analog digital converter is respectively used for the first integration value And the second integrated value are converted into a first digital compensation value and a second digital compensation value; a memory electrically connected to the analog digital converter, and the memory is used to store the first digital compensation value and The second digital compensation value; and a data update unit electrically connected between the storage and the data driver, the data update unit is used to receive a display data, and according to the first digital compensation value and the second digital The compensation value generates a compensation signal corresponding to the sub-pixel, and during the display period, an updated display data is provided to the sub-pixel according to the compensation signal and the display data.

TW107124248A 2018-07-13 2018-07-13 Display panel TWI673695B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW107124248A TWI673695B (en) 2018-07-13 2018-07-13 Display panel
CN201811154428.6A CN109166524B (en) 2018-07-13 2018-09-30 Display panel

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW107124248A TWI673695B (en) 2018-07-13 2018-07-13 Display panel

Publications (2)

Publication Number Publication Date
TWI673695B true TWI673695B (en) 2019-10-01
TW202006691A TW202006691A (en) 2020-02-01

Family

ID=64877361

Family Applications (1)

Application Number Title Priority Date Filing Date
TW107124248A TWI673695B (en) 2018-07-13 2018-07-13 Display panel

Country Status (2)

Country Link
CN (1) CN109166524B (en)
TW (1) TWI673695B (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20220149244A (en) * 2021-04-30 2022-11-08 엘지디스플레이 주식회사 Light Emitting Display Device and Driving Method of the same
CN114267298A (en) * 2021-12-16 2022-04-01 Tcl华星光电技术有限公司 Pixel driving circuit and display panel
TWI810935B (en) * 2022-05-13 2023-08-01 友達光電股份有限公司 Display device
CN117693786A (en) * 2022-06-14 2024-03-12 京东方科技集团股份有限公司 Display panel and display device
CN115985237B (en) * 2023-03-17 2023-07-21 合肥集创微电子科技有限公司 Driving circuit, chip, display device and electronic device

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104036726A (en) * 2014-05-30 2014-09-10 京东方科技集团股份有限公司 Pixel circuit and driving method, organic light-emitting diode (OLED) display panel and device thereof
TW201445541A (en) * 2013-05-24 2014-12-01 Samsung Display Co Ltd Compensation unit and organic light emitting display including the same
TW201525967A (en) * 2013-11-14 2015-07-01 Samsung Display Co Ltd Organic light emitting display
TW201624452A (en) * 2014-12-26 2016-07-01 樂金顯示科技股份有限公司 Sensing circuit and organic light emitting diode display device having the same
US20170018229A1 (en) * 2015-07-17 2017-01-19 Boe Technology Group Co., Ltd. Pixel driving circuit, driving method thereof, and display device

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101976546B (en) * 2010-10-19 2012-08-22 友达光电股份有限公司 Pixel circuit and light-emitting panel with power supply voltage drop compensation function
CN103137072B (en) * 2013-03-14 2015-05-20 京东方科技集团股份有限公司 External compensation induction circuit, induction method of external compensation induction circuit and display device
KR102060311B1 (en) * 2013-12-27 2020-02-11 엘지디스플레이 주식회사 Organic light emitting diode display and method for driving the same
CN106409225B (en) * 2016-12-09 2019-03-01 上海天马有机发光显示技术有限公司 Organic light emissive pixels compensation circuit, organic light emitting display panel and driving method

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201445541A (en) * 2013-05-24 2014-12-01 Samsung Display Co Ltd Compensation unit and organic light emitting display including the same
TW201525967A (en) * 2013-11-14 2015-07-01 Samsung Display Co Ltd Organic light emitting display
CN104036726A (en) * 2014-05-30 2014-09-10 京东方科技集团股份有限公司 Pixel circuit and driving method, organic light-emitting diode (OLED) display panel and device thereof
TW201624452A (en) * 2014-12-26 2016-07-01 樂金顯示科技股份有限公司 Sensing circuit and organic light emitting diode display device having the same
US20170018229A1 (en) * 2015-07-17 2017-01-19 Boe Technology Group Co., Ltd. Pixel driving circuit, driving method thereof, and display device

Also Published As

Publication number Publication date
CN109166524A (en) 2019-01-08
CN109166524B (en) 2020-03-20
TW202006691A (en) 2020-02-01

Similar Documents

Publication Publication Date Title
TWI673695B (en) 2019-10-01 Display panel
KR102212927B1 (en) 2021-02-05 Organic light emitting diode display with external compensation and anode reset
JP6128738B2 (en) 2017-05-17 Pixel circuit and driving method thereof
JP4589614B2 (en) 2010-12-01 Image display device
KR102697930B1 (en) 2024-08-26 Display device
US11410605B2 (en) 2022-08-09 Organic light emitting display device having improved pixel structure configuration
US9881551B2 (en) 2018-01-30 Drive circuit, display device, and drive method
US10504422B2 (en) 2019-12-10 Compensation circuit and display panel
WO2018219066A1 (en) 2018-12-06 Pixel circuit, driving method, display panel, and display device
JP4979772B2 (en) 2012-07-18 Current-driven display device
WO2017113679A1 (en) 2017-07-06 Display driver circuit, array substrate, circuit driving method, and display device
KR102686300B1 (en) 2024-07-22 Method for compensating degradation of display device
WO2016155161A1 (en) 2016-10-06 Oeld pixel circuit, display device and control method
KR102715269B1 (en) 2024-10-10 Gate driver, organic light emitting display apparatus and driving method thereof
JP6288710B2 (en) 2018-03-07 Display device driving method and display device
KR102244932B1 (en) 2021-04-27 Organic light emitting display device and method for driving thereof
WO2019064523A1 (en) 2019-04-04 Display device and pixel circuit
JP6196809B2 (en) 2017-09-13 Pixel circuit and driving method thereof
KR20180025512A (en) 2018-03-09 Sensing Circuit And Organic Light Emitting Display Including The Same, And Sensing Method Of Organic Light Emitting Display
CN114446228A (en) 2022-05-06 Display panel and display device using the same
US10210783B2 (en) 2019-02-19 Apparatus and method for sensing display panel
CN108154850B (en) 2020-03-17 Pixel circuit
KR20230103568A (en) 2023-07-07 Organic light emitting display device and sensing method for elecric characteristics of the same
CN112117991B (en) 2023-06-20 Circuit comprising a trigger and a control element
KR102733849B1 (en) 2024-11-22 Display apparatus