TWI697750B - Voltage regulator device and control method for voltage regulator device - Google Patents

A voltage regulator device and a control method thereof are provided. The voltage regulator device includes a regulator and a path switch. The regulator includes an output node and a voltage divider circuit. The output node generates a control voltage. The voltage divider circuit generates a overshoot reference voltage according to an input voltage. A first node of the path switch is coupled to the output node, a second node of the path switch is coupled to a reference voltage node, and a control node of the path switch receives the overshoot reference voltage. When the control voltage is greater than the sum of the overshoot reference voltage and a threshold voltage of the path switch, the path switch is turned on to direct the charge at the output to the reference voltage node.

穩壓裝置及穩壓裝置的控制方法Voltage stabilizing device and control method of stabilizing device

本發明是有關於一種穩壓器技術，且特別是有關於一種可適用於快取記憶體的穩壓裝置及穩壓裝置的控制方法。The present invention relates to a voltage stabilizer technology, and particularly relates to a voltage stabilizer device suitable for cache memory and a control method of the voltage stabilizer device.

在反或閘（NOR）快取記憶體技術中，穩壓器（regulator）主要是對高於工作電壓的抽取電壓（pumping voltage）進行穩壓而產生控制電壓，從而順利地讓快取記憶體進行相應操作，如，讀取/寫入/設定/程式化/抹除操作等。因此，穩壓器皆希望能夠以迅速提升控制電壓且維持此控制電壓的穩定為設計方向。In the NOR cache technology, the regulator mainly regulates the pumping voltage higher than the working voltage to generate a control voltage, so as to smoothly fetch the memory Perform corresponding operations, such as read/write/set/program/erase operations, etc. Therefore, voltage regulators are expected to be able to rapidly increase the control voltage and maintain the stability of the control voltage as the design direction.

然則，由於習知穩壓器的輸出端難以釋放電荷，在快取記憶體的部分操作下將可能造成誤判。例如，在後段程式化（Post-Program；Post-PGM）操作中，穩壓器所產生的控制電壓將會影響到記憶胞的驗證結果而導致誤操作。However, since it is difficult for the output terminal of the conventional voltage regulator to discharge electric charge, it may cause misjudgment under the partial operation of the cache memory. For example, in the post-program (Post-PGM) operation, the control voltage generated by the voltage regulator will affect the verification result of the memory cell and cause misoperation.

本發明提供一種可應用於快取記憶體的穩壓裝置及其控制方法，從而使穩壓裝置的輸出端在特定情形下具備較佳的電荷釋放效率。The invention provides a voltage stabilizing device that can be applied to a cache memory and a control method thereof, so that the output end of the voltage stabilizing device has a better charge release efficiency under a specific situation.

本發明實施例的穩壓裝置包括穩壓器及路徑開關。穩壓器包括輸出端以及分壓電路。輸出端用以產生控制電壓。分壓電路依據輸入電壓產生過衝參考電壓。路徑開關的第一端耦接輸出端，路徑開關的第二端耦接參考電壓端，路徑開關的控制端接收過衝參考電壓。當控制電壓大於過衝參考電壓與路徑開關的臨界電壓的加總時，路徑開關導通以將輸出端的電荷導引至參考電壓端。The voltage stabilizing device of the embodiment of the present invention includes a voltage regulator and a path switch. The regulator includes an output terminal and a voltage divider circuit. The output terminal is used to generate a control voltage. The voltage divider circuit generates an overshoot reference voltage based on the input voltage. The first terminal of the path switch is coupled to the output terminal, the second terminal of the path switch is coupled to the reference voltage terminal, and the control terminal of the path switch receives the overshoot reference voltage. When the control voltage is greater than the sum of the overshoot reference voltage and the threshold voltage of the path switch, the path switch is turned on to guide the charge at the output terminal to the reference voltage terminal.

本發明實施例的穩壓裝置的控制方法包括下列步驟。設置路徑開關，其中路徑開關的第一端耦接所述輸出端，路徑開關的第二端耦接參考電壓端。透過分壓電路產生過衝參考電壓，其中路徑開關的控制端接收過衝參考電壓。判斷控制電壓是否大於過衝參考電壓與路徑開關的臨界電壓的加總。以及，當控制電壓大於過衝參考電壓與路徑開關的臨界電壓的加總時，導通路徑開關以將輸出端的電荷導引至參考電壓端。The control method of the voltage stabilizing device of the embodiment of the present invention includes the following steps. A path switch is provided, wherein the first terminal of the path switch is coupled to the output terminal, and the second terminal of the path switch is coupled to the reference voltage terminal. The overshoot reference voltage is generated through the voltage divider circuit, and the control terminal of the path switch receives the overshoot reference voltage. Determine whether the control voltage is greater than the sum of the overshoot reference voltage and the threshold voltage of the path switch. And, when the control voltage is greater than the sum of the overshoot reference voltage and the threshold voltage of the path switch, the path switch is turned on to guide the charge at the output terminal to the reference voltage terminal.

基於上述，本發明實施例所述的穩壓裝置及其控制方法在穩壓裝置的輸出端設置路徑開關，利用穩壓裝置中的分壓電路產生過衝參考電壓，並利用路徑開關的物理特性以比較過衝參考電壓以及輸出端上的控制電壓。當控制電壓大於過衝參考電壓與路徑開關的臨界電壓的加總時，表示位於快取記憶體的後段程式化操作中且快取記憶體的記憶胞有發生過衝現象，此時路徑開關便會導通以將輸出端的電荷導引至參考電壓端，從而使穩壓裝置的輸出端具備較佳的電荷釋放效率。相對地，控制電壓不大於過衝參考電壓與路徑開關的臨界電壓的加總時，路徑開關便會截止以維持輸出端的電荷。藉此，穩壓裝置在特定情形下可使其輸出端具備較佳的電荷釋放效率。Based on the above, the voltage stabilizing device and its control method described in the embodiments of the present invention set a path switch at the output end of the voltage stabilizing device, use the voltage divider circuit in the voltage stabilizing device to generate an overshoot reference voltage, and use the physical properties of the path switch Features to compare the overshoot reference voltage and the control voltage on the output. When the control voltage is greater than the sum of the overshoot reference voltage and the threshold voltage of the path switch, it means that it is in the post-programming operation of the cache memory and the memory cell of the cache memory has overshoot. At this time, the path switch is It is turned on to guide the charge at the output terminal to the reference voltage terminal, so that the output terminal of the voltage stabilizing device has better charge release efficiency. In contrast, when the control voltage is not greater than the sum of the overshoot reference voltage and the threshold voltage of the path switch, the path switch is turned off to maintain the charge at the output terminal. Thereby, the voltage stabilizing device can make its output end have better charge release efficiency under certain circumstances.

為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

圖1是依照本發明一實施例的一種穩壓裝置100的示意圖。穩壓裝置100可應用於快取記憶體的控制裝置。快取記憶體可以是邏輯反或（NOR）型快取記憶體或是邏輯反及（NAND）型快取記憶體。穩壓裝置100主要是對高於工作電壓的抽取電壓進行穩壓而產生控制電壓VCNT，從而順利地讓快取記憶體進行相應操作。應用本實施例者亦可依其需求而將本發明實施例所述的穩壓裝置應用在其他技術中，例如應用在其他類型的記憶體元件（如，電阻型隨機存取記憶體（RRAM）、鐵電隨機存取記憶體（FeRAM）、磁阻型隨機存取記憶體（MRAM））的控制裝置中。FIG. 1 is a schematic diagram of a voltage stabilizing device 100 according to an embodiment of the invention. The voltage stabilizing device 100 can be applied to a control device of a cache memory. The cache memory can be a NOR type cache or a NAND type cache. The voltage stabilizing device 100 mainly stabilizes the extraction voltage higher than the working voltage to generate the control voltage VCNT, so as to smoothly allow the cache memory to perform corresponding operations. Those applying this embodiment can also apply the voltage stabilizing device described in the embodiment of the invention to other technologies according to their needs, for example, to other types of memory devices (eg, resistive random access memory (RRAM)) , Ferroelectric random access memory (FeRAM), magnetoresistive random access memory (MRAM)) control devices.

本實施例的穩壓裝置100包括穩壓器110以及路徑開關130。穩壓器110依據參考電壓VREF產生控制電壓VCNT。穩壓器110主要包括輸出端NOUT以及分壓電路120。輸出端NOUT用以產生控制電壓VCNT。分壓電路120依據輸入電壓產生過衝參考電壓VREFOS。應用本實施例者可依據需求調整過衝參考電壓VREFOS的電壓值，例如，本實施例是基於快取記憶體的後段程式化操作下對於記憶胞的過衝情形來設計過衝參考電壓VREFOS的電壓值，藉以利用過衝參考電壓VREFOS判斷記憶胞是否發生過衝情形。The voltage stabilizing device 100 of this embodiment includes a voltage regulator 110 and a path switch 130. The voltage regulator 110 generates the control voltage VCNT according to the reference voltage VREF. The voltage regulator 110 mainly includes an output terminal NOUT and a voltage divider circuit 120. The output terminal NOUT is used to generate the control voltage VCNT. The voltage divider circuit 120 generates an overshoot reference voltage VREFOS according to the input voltage. Those applying this embodiment can adjust the voltage value of the overshoot reference voltage VREFOS according to requirements. For example, this embodiment designs the overshoot reference voltage VREFOS based on the overshoot of the memory cell under the programming operation of the cache memory. The voltage value is used to determine whether the memory cell has an overshoot condition by using the overshoot reference voltage VREFOS.

路徑開關130的第一端N1耦接輸出端NOUT，路徑開關130的第二端N2耦接參考電壓端（本實施例以接地電壓端GND作為舉例）。路徑開關130的控制端NC接收過衝參考電壓VREFOS。路徑開關130可利用金氧半場效電晶體（Metal-Oxide-Semiconductor Field-Effect Transistor；MOS）來實現，本實施例主要是以P型MOS實現。以P型MOS實現的路徑開關130具備臨界電壓Vth。如此一來，在快取記憶體的後段程式化操作時，當控制電壓VCNT大於過衝參考電壓VREFOS與路徑開關130的臨界電壓Vth的加總時，路徑開關130將導通以將輸出端NOUT的電荷導引至參考電壓端（接地電壓端GND）。相對地，當控制電壓VCNT不大於過衝參考電壓VREFOS與臨界電壓Vth的加總時，路徑開關130將截止，以維持輸出端NOUT的電荷。The first terminal N1 of the path switch 130 is coupled to the output terminal NOUT, and the second terminal N2 of the path switch 130 is coupled to the reference voltage terminal (this embodiment takes the ground voltage terminal GND as an example). The control terminal NC of the path switch 130 receives the overshoot reference voltage VREFOS. The path switch 130 can be implemented by using a metal-oxide-semiconductor field-effect transistor (MOS), and this embodiment is mainly implemented by a P-type MOS. The path switch 130 implemented by P-type MOS has a threshold voltage Vth. In this way, when the control voltage VCNT is greater than the sum of the overshoot reference voltage VREFOS and the threshold voltage Vth of the path switch 130 during the later programming operation of the cache memory, the path switch 130 will be turned on to turn on the output terminal NOUT. The charge is guided to the reference voltage terminal (ground voltage terminal GND). In contrast, when the control voltage VCNT is not greater than the sum of the overshoot reference voltage VREFOS and the threshold voltage Vth, the path switch 130 will be turned off to maintain the charge at the output terminal NOUT.

圖2是依照本發明一實施例的一種穩壓裝置100的方塊圖。圖2主要說明穩壓器110中的各個元件。穩壓器110除了分壓電路120以外，還主要地包括誤差放大器230、訊號轉換電路235、電壓準位位移電路240及輸出級電路250。穩壓器110還可包括頻率補償電路260、修剪（trimming）電路270及偏壓電路280。FIG. 2 is a block diagram of a voltage stabilizing device 100 according to an embodiment of the invention. FIG. 2 mainly illustrates the various components in the regulator 110. In addition to the voltage divider circuit 120, the voltage stabilizer 110 mainly includes an error amplifier 230, a signal conversion circuit 235, a voltage level shift circuit 240, and an output stage circuit 250. The voltage stabilizer 110 may further include a frequency compensation circuit 260, a trimming circuit 270, and a bias circuit 280.

分壓電路120還包括回授端NFB。誤差放大器230的反相接收端耦接參考電壓VREF，誤差放大器230的非反相接收端耦接回授端NFB。訊號轉換電路235的輸入端耦接誤差放大器230的比較輸出端NCOM。輸出級電路250可透過電壓準位位移電路240耦接至訊號轉換電路235，輸出級電路250另由其輸出端耦接穩壓器110的輸出端NOUT。輸出級電路250還耦接偏壓電路280。The voltage divider circuit 120 also includes a feedback terminal NFB. The inverting receiving terminal of the error amplifier 230 is coupled to the reference voltage VREF, and the non-inverting receiving terminal of the error amplifier 230 is coupled to the feedback terminal NFB. The input terminal of the signal conversion circuit 235 is coupled to the comparison output terminal NCOM of the error amplifier 230. The output stage circuit 250 can be coupled to the signal conversion circuit 235 through the voltage level shift circuit 240, and the output stage circuit 250 is further coupled to the output terminal NOUT of the regulator 110 through its output terminal. The output stage circuit 250 is also coupled to the bias circuit 280.

在各元件的操作方面，誤差放大器230比較參考電壓VREF以及回授端NFB的電壓，以在比較輸出端NCOM產生比較電壓VG。訊號轉換電路235透過電流鏡結構以將電壓訊號轉換為電流訊號，例如，將比較電壓VG轉換為流經訊號轉換電路235、電壓準位位移電路240以及分壓電路120的電流I。分壓電路120、電壓準位位移電路240以及訊號轉換電路235依據比較電壓VG而在電壓準位位移電路240的第一端N2401產生第一控制電壓VCNT1，且在電壓準位位移電路240的第二端N2402產生第二控制電壓VCNT2。電壓準位位移電路240用以對第一控制電壓VCNT1進行電壓準位的位移，藉此使電壓準位位移電路240及輸出級電路250可消除控制電壓VCNT因製程上的差異所產生的偏移，並於下列實施例詳述之。輸出級電路250依據第二控制電壓VCNT2以及偏壓電路280而產生控制電壓VCNT。Regarding the operation of each element, the error amplifier 230 compares the reference voltage VREF and the voltage of the feedback terminal NFB to generate a comparison voltage VG at the comparison output terminal NCOM. The signal conversion circuit 235 converts the voltage signal into a current signal through a current mirror structure, for example, converts the comparison voltage VG into a current I flowing through the signal conversion circuit 235, the voltage level shift circuit 240, and the voltage divider circuit 120. The voltage divider circuit 120, the voltage level shift circuit 240, and the signal conversion circuit 235 generate the first control voltage VCNT1 at the first terminal N2401 of the voltage level shift circuit 240 according to the comparison voltage VG, and the voltage level shift circuit 240 The second terminal N2402 generates the second control voltage VCNT2. The voltage level shift circuit 240 is used to shift the voltage level of the first control voltage VCNT1, so that the voltage level shift circuit 240 and the output stage circuit 250 can eliminate the shift of the control voltage VCNT due to the difference in the process , And detailed in the following examples. The output stage circuit 250 generates the control voltage VCNT according to the second control voltage VCNT2 and the bias circuit 280.

頻率補償電路260耦接於誤差放大器230的比較輸出端NCOM及分壓電路120之間，用以補償因回授端NFB而產生的雜訊。修剪電路270耦接分壓電路120。修剪電路270用以依據數位修剪碼DTCODE來調整分壓電路120所產生的第一控制電壓VCNT1與過衝參考電壓VREFOS的電壓值。修剪電路270的詳細電路圖請見圖3及相應描述。The frequency compensation circuit 260 is coupled between the comparison output terminal NCOM of the error amplifier 230 and the voltage divider circuit 120 to compensate for the noise generated by the feedback terminal NFB. The trimming circuit 270 is coupled to the voltage divider circuit 120. The trimming circuit 270 is used for adjusting the voltage values of the first control voltage VCNT1 and the overshoot reference voltage VREFOS generated by the voltage divider circuit 120 according to the digital trimming code DTCODE. The detailed circuit diagram of the trimming circuit 270 is shown in Fig. 3 and the corresponding description.

圖3是依照本發明一實施例的一種穩壓裝置100的電路圖。圖1及圖2的相關元件皆繪示於圖3中，且利用金氧半場效電晶體（MOS）、電阻、電容、放大器等基礎電路元件來實現。例如，分壓電路120可由多個電阻R1~R6相互串連而形成的電阻串來實現；路徑開關130可由P型MOS MP1實現；訊號轉換電路235及偏壓電路280可由多個N型MOS及P型MOS實現；輸出級電路250可由N型MOS MN1所形成的源極隨耦器實現；頻率補償電路260可由相互串聯的補償電阻Rm及補償電容Cm實現；電壓準位位移電路240可由N型MOS MN2實現，MOS MN2的源極端作為電壓準位位移電路240的第一端N2401，MOS MN2的汲極端與其閘極端相耦接而作為電壓準位位移電路240的第二端N2402。Vin為穩壓裝置100的輸入電壓，VDD為穩壓裝置100的工作電壓。FIG. 3 is a circuit diagram of a voltage stabilizing device 100 according to an embodiment of the invention. The related components of FIG. 1 and FIG. 2 are all shown in FIG. 3, and are implemented by basic circuit components such as MOS, resistors, capacitors, and amplifiers. For example, the voltage divider circuit 120 can be implemented by a resistor string formed by connecting multiple resistors R1 to R6 in series; the path switch 130 can be implemented by P-type MOS MP1; the signal conversion circuit 235 and the bias circuit 280 can be implemented by multiple N-type MOS and P-type MOS implementation; the output stage circuit 250 can be implemented by a source follower formed by an N-type MOS MN1; the frequency compensation circuit 260 can be implemented by a compensation resistor Rm and a compensation capacitor Cm connected in series; the voltage level shift circuit 240 can be implemented by The N-type MOS MN2 is implemented. The source terminal of the MOS MN2 serves as the first terminal N2401 of the voltage level shift circuit 240, and the drain terminal of the MOS MN2 is coupled to its gate terminal and serves as the second terminal N2402 of the voltage level shift circuit 240. Vin is the input voltage of the voltage stabilizing device 100, and VDD is the operating voltage of the voltage stabilizing device 100.

穩壓裝置100還包括啟用開關MEN。路徑開關130的第二端N2透過啟用開關MEN耦接參考電壓端（如，接地電壓端GND）。啟用開關MEN的控制端接收啟用電壓EN。藉此，在穩壓裝置100為啟用時，啟用開關MEN將被導通，從而避免穩壓裝置100在啟用時的雜訊干擾。The voltage stabilizing device 100 further includes an enable switch MEN. The second terminal N2 of the path switch 130 is coupled to the reference voltage terminal (eg, the ground voltage terminal GND) through the enable switch MEN. The control terminal of the enable switch MEN receives the enable voltage EN. Thereby, when the voltage stabilizing device 100 is activated, the enable switch MEN will be turned on, thereby avoiding noise interference when the voltage stabilizing device 100 is activated.

在此詳加說明電壓準位位移電路240及輸出級電路250如何消除控制電壓VCNT因製程上的差異所產生的偏移。請參見圖3，第二控制電壓VCNT2的電壓值係等於第一控制電壓VCNT1加上電壓準位位移電路240中N型MOS MN2的臨界電壓Vth2後的電壓值，並且，控制電壓VCNT的電壓值係等於第二控制電壓VCNT2減去輸出級電路250中N型MOS MN1的臨界電壓Vth1後的電壓值。N型MOS MN1及MN2的臨界電壓Vth1、Vth2皆與製程上的差異所產生的偏移有關，因此在相同製程下，MOS MN1的臨界電壓Vth1將相等於MOS MN2的臨界電壓Vth2，從而消除製程上偏移（process variation）。Here is a detailed description of how the voltage level shift circuit 240 and the output stage circuit 250 eliminate the deviation of the control voltage VCNT caused by the difference in the manufacturing process. Referring to FIG. 3, the voltage value of the second control voltage VCNT2 is equal to the voltage value of the first control voltage VCNT1 plus the threshold voltage Vth2 of the N-type MOS MN2 in the voltage level shift circuit 240, and the voltage value of the control voltage VCNT It is equal to the second control voltage VCNT2 minus the threshold voltage Vth1 of the N-type MOS MN1 in the output stage circuit 250. The threshold voltages Vth1 and Vth2 of N-type MOS MN1 and MN2 are all related to the offset caused by the difference in the process. Therefore, under the same process, the threshold voltage Vth1 of MOS MN1 will be equal to the threshold voltage Vth2 of MOS MN2, thereby eliminating the process Process variation.

在此詳加說明修剪電路270。修剪電路270由多個作為開關的N型MOS（如，圖3中的MOS MS1~MS3）以及將數位修剪碼DTCODE轉換為類比電壓的多個電壓轉換器（level shifter）310實現。電壓轉換器310將數位修剪碼DTCODE轉換為類比電壓，並利用這些類比電壓來控制N型MOS MS1~MS3是否導通，從而調整電阻串R1~R6被電流通過的數量，並以此來調整第一控制電壓CVNT1與過衝參考電壓VREFOS的電壓值。例如，當N型MOS MS1導通且N型MOS MS2及MS3截止時，會使電阻R1、R2及R6讓電流流過，其餘電阻（如，電阻R3-R5）並不會讓電流流過。因此，基於電壓分壓效應，過衝參考電壓VREFOS將成為以下電壓值：

；當N型MOS MS1~MS3皆為截止時，會使電阻R1~R6皆讓電流流過，因此，基於電壓分壓效應，過衝參考電壓VREFOS將成為以下電壓值：

。 The trimming circuit 270 is explained in detail here. The trimming circuit 270 is implemented by a plurality of N-type MOS (for example, MOS MS1 to MS3 in FIG. 3) as switches and a plurality of level shifters 310 that convert the digital trim code DTCODE into analog voltage. The voltage converter 310 converts the digital trim code DTCODE into an analog voltage, and uses these analog voltages to control whether the N-type MOS MS1~MS3 are turned on, so as to adjust the number of resistor strings R1~R6 passed by current, and adjust the first The voltage values of the control voltage CVNT1 and the overshoot reference voltage VREFOS. For example, when the N-type MOS MS1 is turned on and the N-type MOS MS2 and MS3 are turned off, the resistors R1, R2, and R6 will allow current to flow, and the remaining resistors (eg, resistors R3-R5) will not allow current to flow. Therefore, based on the voltage divider effect, the overshoot reference voltage VREFOS will become the following voltage value:

; When the N-type MOS MS1~MS3 are all off, the resistors R1~R6 will let current flow. Therefore, based on the voltage divider effect, the overshoot reference voltage VREFOS will become the following voltage value:

.

為了有效地維持控制電壓VCNT以及第一控制電壓VCNT1的電荷，控制電壓VCNT所在的輸出端NOUT可設置有第一維持電容CT1，第一控制電壓VCNT1所在的端點可設置有第二維持電容CT2。In order to effectively maintain the charge of the control voltage VCNT and the first control voltage VCNT1, the output terminal NOUT where the control voltage VCNT is located can be provided with a first sustain capacitor CT1, and the end point where the first control voltage VCNT1 is located can be provided with a second sustain capacitor CT2 .

圖4是依照本發明一實施例的一種穩壓裝置100的控制方法的流程圖。此控制方法所適用的穩壓裝置100如同上述圖1至圖3所述。請同時參照圖1及圖4，於步驟S410中，設置路徑開關130，其中此路徑開關130的第一端N1耦接穩壓裝置100的輸出端NOUT，且路徑開關130的第二端N2耦接參考電壓端（接地電壓端GND）。於步驟S420中，透過穩壓裝置100的分壓電路120產生過衝參考電壓VREFOS，且路徑開關130的控制端NC接收過衝參考電壓VREFOS。於步驟S430中，透過路徑開關130判斷輸出端NOUT上的控制電壓VCNT是否大於過衝參考電壓VREFOS與路徑開關130的臨界電壓的加總。FIG. 4 is a flowchart of a control method of the voltage stabilizing device 100 according to an embodiment of the present invention. The voltage stabilizing device 100 to which this control method is applied is the same as that described in FIGS. 1 to 3 above. 1 and 4, in step S410, a path switch 130 is set, wherein the first terminal N1 of the path switch 130 is coupled to the output terminal NOUT of the voltage stabilizing device 100, and the second terminal N2 of the path switch 130 is coupled Connect to the reference voltage terminal (ground voltage terminal GND). In step S420, an overshoot reference voltage VREFOS is generated through the voltage divider 120 of the voltage stabilizing device 100, and the control terminal NC of the path switch 130 receives the overshoot reference voltage VREFOS. In step S430, it is determined through the path switch 130 whether the control voltage VCNT on the output terminal NOUT is greater than the sum of the overshoot reference voltage VREFOS and the threshold voltage of the path switch 130.

當控制電壓VCNT大於過衝參考電壓VREFOS與路徑開關130的臨界電壓的加總時，便從步驟S430進入步驟S440，導通路徑開關130以將輸出端NOUT的電荷導引至參考電壓端（接地電壓端GND）。相對地，當控制電壓VCNT不大於過衝參考電壓VREFOS與路徑開關130的臨界電壓的加總時，便從步驟S430進入步驟S450，截止路徑開關130以維持輸出端的電荷。操作方法的詳細步驟流程亦可參考圖1至圖3的實施例及相應描述。When the control voltage VCNT is greater than the sum of the overshoot reference voltage VREFOS and the threshold voltage of the path switch 130, the process proceeds from step S430 to step S440, and the path switch 130 is turned on to guide the charge at the output terminal NOUT to the reference voltage terminal (ground voltage Terminal GND). In contrast, when the control voltage VCNT is not greater than the sum of the overshoot reference voltage VREFOS and the threshold voltage of the path switch 130, the process proceeds from step S430 to step S450, and the path switch 130 is turned off to maintain the charge at the output terminal. For the detailed step flow of the operation method, reference may also be made to the embodiments and corresponding descriptions in FIGS. 1 to 3.

綜上所述，本發明實施例所述的穩壓裝置及其控制方法在穩壓裝置的輸出端設置路徑開關，利用穩壓裝置中的分壓電路產生過衝參考電壓，並利用路徑開關的物理特性以比較過衝參考電壓以及輸出端上的控制電壓。當控制電壓大於過衝參考電壓與路徑開關的臨界電壓的加總時，表示位於快取記憶體的後段程式化操作中且快取記憶體的記憶胞有發生過衝現象，此時路徑開關便會導通以將輸出端的電荷導引至參考電壓端，從而使穩壓裝置的輸出端具備較佳的電荷釋放效率。相對地，控制電壓不大於過衝參考電壓與路徑開關的臨界電壓的加總時，路徑開關便會截止以維持輸出端的電荷。藉此，穩壓裝置在特定情形下可使其輸出端具備較佳的電荷釋放效率。In summary, the voltage stabilizing device and its control method according to the embodiments of the present invention set a path switch at the output end of the voltage stabilizing device, use the voltage divider circuit in the voltage stabilizing device to generate an overshoot reference voltage, and use the path switch To compare the overshoot reference voltage and the control voltage on the output terminal. When the control voltage is greater than the sum of the overshoot reference voltage and the threshold voltage of the path switch, it means that it is in the post-programming operation of the cache memory and the memory cell of the cache memory has overshoot. At this time, the path switch is It is turned on to guide the charge at the output terminal to the reference voltage terminal, so that the output terminal of the voltage stabilizing device has better charge release efficiency. In contrast, when the control voltage is not greater than the sum of the overshoot reference voltage and the threshold voltage of the path switch, the path switch is turned off to maintain the charge at the output terminal. Thereby, the voltage stabilizing device can make its output end have better charge release efficiency under certain circumstances.

雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make slight changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be subject to those defined by the attached patent scope.

100:穩壓裝置 110:穩壓器 120:分壓電路 130:路徑開關 230:誤差放大器 235:訊號轉換電路 240:電壓準位位移電路 250:輸出級電路 260:頻率補償電路 270:修剪電路 280:偏壓電路 310:電壓轉換器 DTCODE:數位修剪碼 VREF:參考電壓 VREFOS:過衝參考電壓 VCNT:控制電壓 Vth1、Vth2:臨界電壓 VCNT1:第一控制電壓 VG:比較電壓 N1:路徑開關的第一端 N2:路徑開關的第二端 N2401:電壓準位位移電路的第一端 N2402:電壓準位位移電路的第二端 NC:路徑開關的控制端 NOUT:輸出端 NFB:回授端 NCOM:比較輸出端 Rm:補償電阻 Cm:補償電容 CT1:第一維持電容 CT2:第二維持電容 VDD:工作電壓 Vin:輸入電壓 R1~R6:電阻 MS1~MS3、MN1、MN2:N型MOS MP1:P型MOS GND:接地電壓端 MEN:啟用開關 EN:啟用電壓 I:電流 100: voltage regulator 110: voltage regulator 120: Voltage divider circuit 130: Path switch 230: error amplifier 235: signal conversion circuit 240: Voltage level shift circuit 250: output stage circuit 260: frequency compensation circuit 270: Trim the circuit 280: Bias circuit 310: Voltage converter DTCODE: digital trim code VREF: Reference voltage VREFOS: Overshoot reference voltage VCNT: control voltage Vth1, Vth2: critical voltage VCNT1: first control voltage VG: Comparison voltage N1: The first end of the path switch N2: The second end of the path switch N2401: The first terminal of the voltage level shift circuit N2402: The second end of the voltage level shift circuit NC: Control terminal of path switch NOUT: output terminal NFB: feedback terminal NCOM: Comparison output Rm: Compensation resistance Cm: compensation capacitor CT1: first sustain capacitor CT2: second sustain capacitor VDD: working voltage Vin: input voltage R1~R6: resistance MS1~MS3, MN1, MN2: N-type MOS MP1: P-type MOS GND: Ground voltage terminal MEN: Enable switch EN: enable voltage I: current

圖1是依照本發明一實施例的一種穩壓裝置的示意圖。 圖2是依照本發明一實施例的一種穩壓裝置的方塊圖。 圖3是依照本發明一實施例的一種穩壓裝置的電路圖。 圖4是依照本發明一實施例的一種穩壓裝置的控制方法的流程圖。 FIG. 1 is a schematic diagram of a voltage stabilizing device according to an embodiment of the invention. FIG. 2 is a block diagram of a voltage stabilizing device according to an embodiment of the invention. Fig. 3 is a circuit diagram of a voltage stabilizing device according to an embodiment of the present invention. Fig. 4 is a flowchart of a control method of a voltage stabilizing device according to an embodiment of the present invention.

100:穩壓裝置 100: voltage regulator

110:穩壓器 110: voltage regulator

120:分壓電路 120: Voltage divider circuit

130:路徑開關 130: Path switch

VREF:參考電壓 VREF: Reference voltage

VREFOS:過衝參考電壓 VREFOS: Overshoot reference voltage

VCNT:控制電壓 VCNT: control voltage

N1:路徑開關的第一端 N1: The first end of the path switch

N2:路徑開關的第二端 N2: The second end of the path switch

NC:路徑開關的控制端 NC: Control terminal of path switch

NOUT:輸出端 NOUT: output terminal

GND:接地電壓端 GND: Ground voltage terminal