TWI720791B - Global clock synchronization transmission method - Google Patents

一種全域時鐘同步傳輸方法，其中，全域時鐘同步傳輸方法應用於一數位硬體系統中，數位硬體系統包含有一主設備及至少一從設備，實施時，主設備將一時鐘計數封包傳送給各個從設備，所述的時鐘計數封包只帶有一高位計數數據，各個從設備可基於高位計數數據自行計算出一低位計數數據，使各從設備儲存全部(高位和低位)計數數據後開始計數作業，當各從設備再次收到時鐘計數封包後，從設備即可比對全部(高位和低位)計數數據，判斷從設備是否與主設備達到時鐘同步，據此，主設備僅需傳送高位計數數據給從設備，以大幅減少數據的發送量。A global clock synchronization transmission method, wherein the global clock synchronization transmission method is applied to a digital hardware system. The digital hardware system includes a master device and at least one slave device. When implemented, the master device transmits a clock count packet to each The slave device, the clock counting packet only contains a high-order count data, and each slave device can calculate a low-order count data by itself based on the high-order count data, so that each slave device stores all (high-order and low-order) count data and then starts the counting operation. When each slave device receives the clock count packet again, the slave device can compare all (high and low) count data to determine whether the slave device has reached clock synchronization with the master device. According to this, the master device only needs to transmit the high count data to the slave Equipment to greatly reduce the amount of data sent.

全域時鐘同步傳輸方法Global clock synchronization transmission method

本發明涉及一種全域時鐘同步傳輸方法，所述的全域時鐘同步傳輸方法主要是透過主設備只發送高位計數數據，使從設備可基於高位計數數據計算出低位計數數據，據此判斷是否達成時鐘同步。 The invention relates to a global clock synchronization transmission method. The global clock synchronization transmission method mainly transmits only high count data through a master device, so that the slave device can calculate low count data based on the high count data, and judge whether clock synchronization is achieved based on this .

全域時鐘應用領域繁多，全域時鐘可確保系統中各硬體設備(晶片模組或電路板)之間有完全相同的時間基準，當多個硬體設備協同工作時，設備之間的資料通訊需要透過發送和接收資料封包來完成。 There are many applications of the global clock. The global clock can ensure that the hardware devices (chip modules or circuit boards) in the system have exactly the same time reference. When multiple hardware devices work together, data communication between the devices is required This is done by sending and receiving data packets.

為了方便同步不同類型資料封包和分辨同類型資料封包的先後順序，資料封包發送設備通常會將資料封包打上時間戳記。 In order to facilitate the synchronization of different types of data packets and distinguish the sequence of the same type of data packets, the data packet sending device usually timestamps the data packets.

每個資料發送設備都要有個別的計數器，當多個設備協同工作時，通常每個設備需要同時發送資料包及接收資料包。 Each data sending device must have an individual counter. When multiple devices work together, usually each device needs to send and receive data packets at the same time.

由於每個設備使用自己專屬的計數器，使得每個設備發送資料封包的時間戳記和接收到的資料封包時間戳記沒有關聯性，同時每個設備收到不同發送端發送的資料封包時間戳記也沒有關聯性，很容易造成資料封包發送和接收的混亂。 Since each device uses its own counter, there is no correlation between the time stamp of the data packet sent by each device and the time stamp of the received data packet, and the time stamp of the data packet sent by each device from a different sender is also not related. It is easy to cause confusion in the sending and receiving of data packets.

在實際應用中，通常透過時鐘同步演算法同步各協同工作設備的計數器，使得各設備計數時鐘在同一時間相同，或者時鐘計數誤差在一個可以接受的範圍內，所述的時鐘同步演算法實施時，時鐘同步演算法主要透過主設備統一發送資料封包給各個從設備，使各個從設備所收到的時間戳記可達到一致，藉此達到時鐘同步目的。 In practical applications, the counters of each cooperative device are usually synchronized through a clock synchronization algorithm, so that the count clock of each device is the same at the same time, or the clock counting error is within an acceptable range. , The clock synchronization algorithm mainly uses the master device to uniformly send data packets to each slave device, so that the time stamps received by each slave device can be consistent, so as to achieve the purpose of clock synchronization.

以目前時鐘同步演算法為例，主設備每隔一段間隔時間發佈資料封包，所述的資料封包包含有主設備計數器所產生的時鐘計數數據，從設備擷取資料封包中時鐘計數數據，判斷是否達到時鐘同步，然而，資料封包係夾帶整個時鐘計數數據，主設備與從設備之間需耗費較多的資料發送量，且數據通訊功耗亦會隨之增加。 Taking the current clock synchronization algorithm as an example, the master device publishes data packets at regular intervals. The data packets contain clock count data generated by the master device counter. The slave device retrieves the clock count data in the data packet to determine whether To achieve clock synchronization, however, the data packet contains the entire clock count data, which requires a lot of data transmission between the master device and the slave device, and the data communication power consumption will also increase.

目前電子產品設計上皆以節省功耗做為設計重點，有些做法是減少資料發送次數，但這將會延長從設備確認時鐘同步之時機，可能造成主設備與從設備誤差更嚴重， 這絕非設計者所樂見的狀況，是以，如何以較小的資料發送量達成時鐘同步，此乃待需解決之問題。 At present, the design of electronic products is focused on saving power consumption. Some methods are to reduce the number of data transmissions, but this will extend the time for the slave device to confirm the clock synchronization, which may cause more serious errors between the master device and the slave device. This is by no means a situation that designers would like to see. Therefore, how to achieve clock synchronization with a small amount of data transmission is a problem to be solved.

有鑑於上述的問題，本發明人依據多年來從事相關行業的經驗，針對全域時鐘同步傳輸方法進行研究及改進，本發明之主要目的在於提供一種主設備僅需發送部分時鐘計數數據至從設備，達成全域時鐘同步傳輸。 In view of the above-mentioned problems, the inventor of the present invention has conducted research and improvement on the global clock synchronization transmission method based on years of experience in related industries. The main purpose of the present invention is to provide a master device that only needs to send part of the clock count data to the slave device. Achieve global clock synchronization transmission.

為達上述的目的，本發明之全域時鐘同步傳輸方法，其應用於一數位硬體系統，所述的數位硬體系統包含有一主設備及至少一從設備，實施時，主設備將一時鐘計數封包傳送給各個從設備，所述的時鐘計數封包只帶有一高位計數數據，各個從設備可基於高位計數數據自行計算出一低位計數數據，使各從設備儲存全部(高位和低位)計數數據後開始計數作業，當各從設備再次收到時鐘計數封包後，從設備即可比對全部(高位和低位)計數數據，判斷從設備是否與主設備達到時鐘同步，據此，主設備僅需傳送高位計數數據給從設備，以大幅減少數據的發送量及減少數據通訊功耗。 To achieve the above objective, the global clock synchronization transmission method of the present invention is applied to a digital hardware system. The digital hardware system includes a master device and at least one slave device. When implemented, the master device counts a clock The packet is transmitted to each slave device. The clock counting packet only has a high-order count data. Each slave device can calculate a low-order count data based on the high-order count data by itself, so that each slave device stores all (high-order and low-order) count data. Start the counting operation. When each slave device receives the clock counting packet again, the slave device can compare all (high and low) count data to determine whether the slave device has reached clock synchronization with the master device. According to this, the master device only needs to transmit the high bit Count data to the slave device to greatly reduce the amount of data sent and reduce the power consumption of data communication.

為使 貴審查委員得以清楚了解本發明之目的、技術特徵及其實施後之功效，茲以下列說明搭配圖示進行說明，敬請參閱。 In order to enable your reviewer to have a clear understanding of the purpose, technical features and effects of the present invention after implementation, the following descriptions and illustrations are used for explanation, please refer to them.

10:數位硬體系統 10: Digital hardware system

101:主設備 101: master device

102:從設備 102: Slave device

102’:從設備 102’: Slave device

102”:從設備 102": Slave device

D:時鐘計數封包 D: Clock counting packet

D’:時鐘計數封包 D’: Clock counting packet

S:硬體全域時鐘同步傳輸方法 S: Hardware global clock synchronization transmission method

S1:主設備發送第一筆時鐘計數封包 S1: The master device sends the first clock count packet

S2:從設備接收時鐘計數封包後開始計數時鐘 S2: The slave device starts counting the clock after receiving the clock counting packet

S3:主設備更新時鐘計數封包 S3: Master device update clock count packet

S4:從設備比對主設備時鐘計數封包 S4: The slave device compares the master device clock count packet

S5:從設備將時鐘計數調整至同步 S5: Slave device adjusts clock count to synchronization

第1圖，為本發明之硬體系統架構圖。 Figure 1 is a diagram of the hardware system architecture of the present invention.

第2圖，為本發明之實施流程圖。 Figure 2 is a flow chart of the implementation of the present invention.

第3圖，為本發明時鐘計數封包結構之實施例(一)。 Figure 3 is an embodiment (1) of the clock counting packet structure of the present invention.

第4圖，為本發明時鐘計數封包結構之實施例(二)。 Figure 4 is an embodiment (2) of the clock counting packet structure of the present invention.

第5圖，為本發明封包間隔周期設定之實施例(一)。 Figure 5 is an embodiment (1) of setting the packet interval period of the present invention.

第6圖，為本發明封包間隔周期設定之實施例(二)。 Figure 6 is an embodiment (2) of setting the packet interval period of the present invention.

請參閱「第1圖」，圖中所示為本發明之硬體系統架構圖，如圖，本發明之數位硬體系統10，其主要具有一主設備101及至少一從設備(102、102’、102”)，其中，主設備101及各從設備(102、102’、102”)分別具有一計數器，所述的計數器可供執行計數任務及比對計數數據，主設備和從設備可為同一電路板上的晶片，或以數據線連接安裝有晶片的不同電路板。 Please refer to "Figure 1". The figure shows the hardware system architecture diagram of the present invention. As shown in the figure, the digital hardware system 10 of the present invention mainly has a master device 101 and at least one slave device (102, 102). ', 102”), where the master device 101 and each slave device (102, 102', 102”) respectively have a counter, and the counter can be used to perform counting tasks and compare counting data. The master device and the slave device can It is a chip on the same circuit board, or a data line is used to connect different circuit boards on which the chip is mounted.

主設備101和各從設備(102、102’、102”)之間透過一資料線完成資訊連接，所述的資料線可為差分線或單端線，主設備101透過資料線定時將主設備的一時鐘計數封包發送給所有從設備(102、102’、102”)。 The master device 101 and each slave device (102, 102', 102") complete the information connection through a data line. The data line can be a differential line or a single-ended line. The master device 101 periodically connects the master device through the data line. The one-clock count packet is sent to all slave devices (102, 102', 102").

各從設備(102、102’、102”)接收主設備101的時鐘計數封包後，各個從設備(102、102’、102”)可觸發計數器進行計數、以及各從設備(102、102’、102”)比對時鐘計數封包之數據調整從設備計數器之計數數據，使各從設備(102、102’、102”)的時鐘計數數據與主設備101的時鐘計數數據誤差在一個極小的誤差範圍內，即各從設備(102、102’、102”)的計數器鎖定主設備101的時鐘計數器，從設備(102、102’、102”)可以將這個鎖定資訊，透過發送計數時鐘的資料線傳送，亦可以建立專屬的一鎖定資料線發送給主設備101，或者，從設備(102、102’、102”)可以不發送鎖定資訊給主設備101以簡化全域時鐘同步程序。 After each slave device (102, 102', 102") receives the clock counting packet of the master device 101, each slave device (102, 102', 102") can trigger a counter to count, and each slave device (102, 102', 102”) Compare the data in the clock count packet and adjust the count data of the slave device counter so that the clock count data of each slave device (102, 102', 102”) and the clock count data of the master device 101 have a very small error range Inside, that is, the counter of each slave device (102, 102', 102") locks the clock counter of the master device 101, and the slave device (102, 102', 102”) can send this lock information through the data line that sends the count clock. It is also possible to create a dedicated lock data line and send it to the master device 101, or the slave devices (102, 102', 102") may not send lock information to the master device 101 to simplify the global clock synchronization procedure.

在全域時鐘同步傳輸過程中，主設備101需要定時將完整的時鐘計數數據通過資料線以資料封包的形式發送給從設備(102、102’、102”)，資料線可以是專門用於全域時鐘同步的專用資料線，也可以是設備間通訊的通用資料線，本發明之資料線使用專門用於全域時鐘同步的專用資料線，使主設備101與從設備(102、102’、102”)之間傳輸其它資料時，不會因為傳輸其它資料而影響到主設備101精準發送時鐘計數數據的時間。 In the process of global clock synchronization transmission, the master device 101 needs to periodically send the complete clock count data to the slave devices (102, 102', 102") through the data line in the form of data packets. The data line can be dedicated to the global clock The dedicated data line for synchronization can also be a general data line for communication between devices. The data line of the present invention uses a dedicated data line specifically for global clock synchronization, so that the master device 101 and the slave device (102, 102', 102") When other data is transferred between, the time for the master device 101 to accurately send the clock count data will not be affected by the transmission of other data.

請參閱「第2圖」，圖中所示為本發明之實施流程圖，如圖本發明之硬體全域時鐘同步傳輸方法S，其包含： (1)主設備發送第一筆時鐘計數封包S1：設備初始化後，主設備的計數器基於一時鐘計數週期進行計數，歷經一個時鐘計數週期後，主設備計數器將一時鐘計數封包透過資料線發佈到至少一從設備；所述的時鐘計數週期是介於2的16次方奈秒(ns)~2的32次方奈秒，最佳為2的24次方奈秒，時鐘計數週期可以依據需求設定，選擇以低位為零的數值作為時鐘計數週期，例如65,536奈秒(即2的16次方奈秒)，時鐘計數週期的設定以節省功耗作為考量，時鐘同步傳輸中，如果時鐘計數週期很短，從設備可以經常接收到主設備的時鐘計數封包調整從設備的時鐘計數數據，可以確保從設備的時鐘計數數據與主設備的時鐘計數數據同步或接近於同步，然而主設備通訊功耗亦相對提高，如果時鐘計數週期很長，主設備需等待很長一段時間才能發送一次時鐘計數封包給從設備，如此，主設備可以節省通訊功耗，但從設備接收封包的間隔時間較長，可能會造成較大的同步誤差；(2)據此，本實施例中以16,777,216奈秒(約16ms)為最佳實施例，可滿足多數應用在100奈秒左右的主設備與從設備計數誤差要求，所述的時鐘計數封包包含有一封包標頭、一高位計數數據和一封包標尾，其中，高位計數數據可以依據需求設定，其可以選用8位元(bit，亦可稱比特)、24位元或40位元等，另外，主計數器進一步對低位計數數據補0，例如，當主設備計數到16, 777,216奈秒時，主設備的計數十六進制表示為0x1000000，即高位為0x1、低位為0x0，如果主設備時鐘計數器設定為32位元時，主設備發給從設備的高位計數數據應為8位元(8’b00000001)，低位部分全部為0(24’b000000000000000000000000(24’h0))(主設備僅發送高位計數數據)；(3)從設備接收時鐘計數封包後開始計數時鐘S2：在從設備初始化完成，各個從設備收到主設備發來的時鐘計數封包後，各從設備可分別取出封包中的高位計數數據，且各個從設備計數器可進一步基於封包中的高位計數數據，經補零計算出低位計數數據，儲存全部數據(即高位計數數據和低位計數數據)並開始計數作業；(4)主設備更新時鐘計數封包S3：主設備計數器再次計數至指定的時鐘計數週期(例如16,777,216奈秒)時，主設備計數器更新時鐘計數封包中高位計數數據，並且將更新後的時鐘計數封包再次發佈至各個從設備，例如，主設備計數器計數到33,554,432奈秒(即下一次16,777,216奈秒)時，主設備計數器以十六進制表示為”0x2000000”，即高位為”0x2”、低位為”0x0”，如果主設備為32位元計數，主設備發給從設備的計數應為高位為8位元，即為8’b00000010，低位全部為0，即為24’b000000000000000000000000(24’h0)(主設備僅發送高位計數數據)；(5)從設備比對主設備時鐘計數封包S4：從設備再次收到 主設備的時鐘計數封包後，從設備以封包中高位計數數據，經過低位補零的計數出低位計數數據，以高位計數數據和低位計數數據，比對從設備計數器的時鐘計數數據，若主設備的時鐘計數數據和從設備的時鐘計數數據之間誤差在一誤差容許範圍，從設備即可判斷從設備的時鐘計數數據與主設備的時鐘計數數據達到同步，並等待主設備下一筆發送的時鐘計數封包進行下一次比對，若主設備的時鐘計數數據與從設備的時鐘計數數據未在誤差容許範圍內(即誤差過大)，則進行下一步驟，所述的誤差容許範圍可依據主設備與從設備之應用進行設定，例如，影片電子標準協會(VESA)制定的數位式視訊介面標準(DisplayPort)中，全域時間碼(Global Time Code,GTC)用於Video和Audio之間的同步，標準要求，在GTC保持階段(maintenance phase)，GTC master和GTC slave的時鐘計數數據誤差在平均+-50奈秒，最大誤差不能超過+-100奈秒；(6)從設備將時鐘計數調整至同步S5：若主設備的時鐘計數數據與從設備的時鐘計數數據之間差值未在誤差容許範圍內，則從設備調整從設備計數時鐘的頻率或調整從設備每個時鐘週期的計數增加值，然後重覆上述步驟「主設備更新時鐘計數封包S3」和「從設備比對主設備時鐘計數封包S4」，直到從設備的時鐘計數數據值再次與主設備的時鐘計數數據值同步，即主設備 的時鐘計數數據和從設備的時鐘計數數據誤差維持在誤差容許範圍內。 Please refer to "Figure 2", which shows an implementation flowchart of the present invention, as shown in the hardware global clock synchronization transmission method S of the present invention, which includes: (1) The master device sends the first clock count packet S1: After the device is initialized, the counter of the master device counts based on a clock count period. After a clock count period, the master device counter sends a clock count packet to the data line. At least one slave device; the clock counting period is between 2 to the 16th power of nanoseconds (ns) to 2 to the 32th power of nanoseconds, preferably 2 to the 24th power of nanoseconds, the clock counting period can be based on requirements Setting, select the value with the low bit as zero as the clock counting period, such as 65,536 nanoseconds (that is, 2 to the 16th power of nanoseconds). The clock counting period is set to save power consumption as a consideration. During clock synchronization transmission, if the clock counting period is Very short, the slave device can often receive the clock count packet of the master device to adjust the clock count data of the slave device, which can ensure that the clock count data of the slave device is synchronized or close to the clock count data of the master device. However, the communication power consumption of the master device It is also relatively improved. If the clock counting period is very long, the master device will have to wait a long time before sending a clock counting packet to the slave device. In this way, the master device can save communication power consumption, but the slave device has a longer interval for receiving packets. It may cause a large synchronization error; (2) According to this, 16,777,216 nanoseconds (about 16ms) is the best embodiment in this embodiment, which can meet the count error of the master device and the slave device in most applications of about 100 nanoseconds. It is required that the clock counting packet includes a packet header, a high-order count data, and a packet trailer. The high-order count data can be set according to requirements, and it can be selected as 8-bit (bit, also called bit), 24 Bit or 40 bit, etc. In addition, the main counter further adds 0 to the lower count data. For example, when the main device counts to 16, At 777,216 nanoseconds, the hexadecimal representation of the master device is 0x1000000, that is, the high bit is 0x1, and the low bit is 0x0. If the clock counter of the master device is set to 32 bits, the high bit count data sent by the master device to the slave device should be It is 8 bits (8'b00000001), the low part is all 0 (24'b000000000000000000000000(24'h0)) (the master device only sends the high count data); (3) The slave device starts counting clock S2 after receiving the clock counting packet: After the slave device is initialized and each slave device receives the clock count packet from the master device, each slave device can take out the high count data in the packet, and each slave device counter can be further based on the high count data in the packet. Add zero to calculate the low count data, store all the data (that is, the high count data and the low count data) and start the counting operation; (4) The master device updates the clock count packet S3: The master device counter counts again to the specified clock count period (for example 16,777,216 nanoseconds), the master device counter updates the high count data in the clock count packet, and re-publishes the updated clock count packet to each slave device. For example, the master device counter counts to 33,554,432 nanoseconds (that is, the next 16,777,216 nanoseconds ), the counter of the master device is expressed in hexadecimal as "0x2000000", that is, the high bit is "0x2" and the low bit is "0x0". If the master device is a 32-bit count, the count sent by the master device to the slave device should be the high bit It is 8 bits, which is 8'b00000010, and the low bits are all 0s, which is 24'b000000000000000000000000 (24'h0) (the master only sends high count data); (5) The slave device compares the master clock count packet S4: Received again from the device After the master's clock counts the packet, the slave uses the high-order count data in the packet to count the low-order count data after zero-filling the low-order, and compares the high-order count data with the low-order count data to compare the clock count data of the slave counter. If the master device The error between the clock count data and the clock count data of the slave device is within an error tolerance range, and the slave device can determine that the clock count data of the slave device and the clock count data of the master device are synchronized, and wait for the next clock sent by the master device The counting packet is compared for the next time. If the clock count data of the master device and the clock count data of the slave device are not within the error tolerance range (that is, the error is too large), then proceed to the next step. The error tolerance range can be based on the master device Set up with the application of the slave device. For example, in the Digital Video Interface Standard (DisplayPort) formulated by the Video Electronics Standards Association (VESA), the Global Time Code (GTC) is used for synchronization between Video and Audio. It is required that in the GTC maintenance phase, the clock count data error of the GTC master and GTC slave is on average +-50 nanoseconds, and the maximum error cannot exceed +-100 nanoseconds; (6) The slave device adjusts the clock count to be synchronized S5: If the difference between the clock count data of the master device and the clock count data of the slave device is not within the error tolerance, the slave device adjusts the frequency of the slave device count clock or adjusts the count increase value of each clock cycle of the slave device, Then repeat the above steps "Master device update clock count packet S3" and "Slave device compare master device clock count packet S4" until the clock count data value of the slave device is again synchronized with the clock count data value of the master device, that is, the master device The error between the clock count data and the clock count data of the slave device is maintained within the error tolerance range.

承上，主設備每個時鐘週期計數器增加2的整數次冪，例如主設備時鐘使用125MHz，每個時鐘週期計數器計數增加為8，每個時鐘週期為8奈秒，如果主設備時鐘使用62.5MHz，則每個時鐘週期計數器計數增加為16，代表每個時鐘週期為16奈秒，為了儘量減少主設備發給從設備的計數數據量(bit，位元/比特)，同時維持主設備與從設備之間封包發送時間在合適區間內，主設備優選以16,777,216奈秒作為封包發送時間的間隔週期，但不以此為限，其中，16,777,216為2的24次方，所以每次主設備為從設備發送時鐘計數數據時，主設備只需發送時鐘計數數據中高位計數數據(數據不為0的部分)至從設備，而不發送低位(24位元)數據，進而減少主設備的數據發送量。 Continuing from the above, the counter of the master device is increased by an integer power of 2 for each clock cycle. For example, the master device clock uses 125MHz, and the counter count per clock cycle is increased to 8, and each clock cycle is 8 nanoseconds. If the master device clock uses 62.5MHz , The counter count of each clock cycle is increased to 16, which means that each clock cycle is 16 nanoseconds. In order to minimize the amount of count data (bit, bit/bit) sent by the master device to the slave device, while maintaining the master device and the slave device The packet sending time between devices is within a suitable interval. The master device preferably uses 16,777,216 nanoseconds as the interval period of the packet sending time, but it is not limited to this. Among them, 16,777,216 is 2 to the 24th power, so every time the master device is the slave When the device sends clock count data, the master device only needs to send the high-order count data (the part of the data that is not 0) in the clock count data to the slave device, and does not send the low-order (24-bit) data, thereby reducing the amount of data sent by the master device .

請參閱「第3圖」，圖中所示為本發明時鐘計數封包結構之實施例(一)，如圖，實施例(一)中，主設備計數器以24位元作為低位計數數據，當主設備時鐘計數器採用32位元計數規格時，每次只需發送高位計數數據給從設備102，即，主設備時鐘計數數據擷取高位計數數據之部分，即32位元-24位元=8位元。 Please refer to "Figure 3". The figure shows the embodiment (1) of the clock counting packet structure of the present invention. In the figure, in the embodiment (1), the master device counter uses 24 bits as the low count data. When the device clock counter adopts the 32-bit counting specification, only the high-order count data needs to be sent to the slave device 102 each time, that is, the part of the high-order count data captured by the master device clock count data, that is, 32 bits-24 bits = 8 bits yuan.

請參閱「第4圖」，圖中所示為本發明時鐘計數封 包結構之實施例(二)，如圖，主設備計數器以24位元作為低位計數數據，當主設備時鐘計數器採用64位元計數規格時，每次只需發送高位計數數據給從設備102，即，主設備時鐘計數數據擷取高位計數數據之部分，即64位元-24位元=40位元。 Please refer to "Figure 4", the figure shows the clock counting envelope of the present invention Example (2) of the packet structure, as shown in the figure, the master device counter uses 24 bits as the low count data. When the master device clock counter adopts the 64-bit count specification, only the high count data needs to be sent to the slave device 102 each time. That is, the master device clock count data captures the part of the higher count data, that is, 64 bits-24 bits=40 bits.

請參閱「第5圖」，圖中所示為本發明封包間隔周期設定之實施例(一)，圖中所示為主設備發送時鐘計數封包D及下一筆時鐘計數封包D’的間隔時間，當主設備計數器使用16,777,216奈秒作為時鐘計數週期，且主設備時鐘採用125MHz，計數時，每個主時鐘週期時鐘計數增加8，則主設備時鐘計數封包(D、D’)發送的間隔周期，即為16,777,216÷8=2,097,152個主設備時鐘計數周期。 Please refer to "Figure 5". The figure shows an embodiment (1) of the packet interval period setting of the present invention. The figure shows the interval time between the master device sending a clock counting packet D and the next clock counting packet D'. When the master device counter uses 16,777,216 nanoseconds as the clock count period, and the master device clock uses 125MHz, when counting, the clock count of each master clock cycle increases by 8, then the master device clock counts the interval period of packet (D, D') sending, That is 16,777,216÷8=2,097,152 master clock count cycles.

請參閱「第6圖」，圖中所示為本發明封包間隔周期設定之實施例(二)，圖中所示為主設備發送時鐘計數封包D及下一筆時鐘計數封包D’的間隔時間，當主設備計數器使用了16,777,216奈秒作為時鐘計數週期，且主設備時鐘採用62.5MHz，計數時，每個主時鐘週期時鐘計數增加16，則主設備封包發送的間隔周期為16777216÷16=1,048,576個主設備時鐘計數周期。 Please refer to "Figure 6". The figure shows the embodiment (2) of the packet interval period setting of the present invention. The figure shows the interval time between the master device sending a clock counting packet D and the next clock counting packet D'. When the master device counter uses 16,777,216 nanoseconds as the clock counting period, and the master device clock uses 62.5MHz, when counting, the clock count of each master clock cycle increases by 16, then the interval period of the master device packet transmission is 16777216÷16=1,048,576 The master clock count period.

綜上可知，本發明之用於數位硬體系統之全域時鐘同步傳輸方法，本發明主要透過主設備向多個從設備發 送一時鐘計數封包，使從設備接收到封包後可開始計數或確認是否達到時鐘同步，其中，主設備所發送的時鐘計數封包中只保留高位計數數據，當從設備收到時鐘計數封包後，從設備可基於高位計數數據，經補零計算出低位計數數據，使從設備計數器可以比對全部計數數據(即高位計數數據和低位計數數據)，進而確認從設備計數器是否與主設備計數器形成同步，並進行修正至同步。 In summary, in the global clock synchronization transmission method for digital hardware systems of the present invention, the present invention mainly transmits data to multiple slave devices through the master device. Send a clock counting packet so that the slave device can start counting or confirm whether it has reached clock synchronization after receiving the packet. Among them, the clock counting packet sent by the master device only retains the high count data. When the slave device receives the clock counting packet, The slave device can calculate the low count data based on the high count data and zero-filled, so that the slave counter can compare all the count data (that is, the high count data and the low count data), and then confirm whether the slave counter is synchronized with the master counter , And make corrections to sync.

本發明其據以實施後，確實可達到提供一種主設備僅需發送部分時鐘計數數據至從設備，達成全域時鐘同步傳輸之目的。 According to the implementation of the present invention, it can indeed achieve the purpose of providing a master device that only needs to send part of the clock count data to the slave device to achieve the goal of synchronous transmission of the global clock.

以上所述者，僅為本發明之較佳之實施例而已，並非用以限定本發明實施之範圍；任何熟習此技藝者，在不脫離本發明之精神與範圍下所作之均等變化與修飾，皆應涵蓋於本發明之專利範圍內。 The above are only preferred embodiments of the present invention, and are not intended to limit the scope of implementation of the present invention; anyone who is familiar with this technique can make equal changes and modifications without departing from the spirit and scope of the present invention. It should be covered in the scope of the patent of the present invention.

綜上所述，本發明具有「產業利用性」、「新穎性」與「進步性」等專利要件；申請人爰依專利法之規定，向 鈞局提起發明專利之申請。 In summary, the present invention has patent requirements such as "industrial applicability", "novelty" and "advancedness"; the applicant filed an application for a patent for invention with the Bureau in accordance with the provisions of the Patent Law.

S:硬體全域時鐘同步傳輸方法 S: Hardware global clock synchronization transmission method

S1:主設備發送第一筆時鐘計數封包 S1: The master device sends the first clock count packet

S2:從設備接收時鐘計數封包後開始計數時鐘 S2: The slave device starts counting the clock after receiving the clock counting packet

S3:主設備更新時鐘計數封包 S3: Master device update clock count packet

S4:從設備比對主設備時鐘計數封包 S4: The slave device compares the master device clock count packet

S5:從設備將時鐘計數調整至同步 S5: Slave device adjusts clock count to synchronization