TWI766765B - Clock generator device and clock generation method - Google Patents
- ️Wed Jun 01 2022
TWI766765B - Clock generator device and clock generation method - Google Patents
Clock generator device and clock generation method Download PDFInfo
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- TWI766765B TWI766765B TW110126666A TW110126666A TWI766765B TW I766765 B TWI766765 B TW I766765B TW 110126666 A TW110126666 A TW 110126666A TW 110126666 A TW110126666 A TW 110126666A TW I766765 B TWI766765 B TW I766765B Authority
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Abstract
A clock generator device includes a first clock generator circuit, a second clock generator circuit, a detector circuit, and a selection circuit. The first clock generator circuit has a first starting voltage and generates a first clock signal in response to a supply voltage. The second clock generator circuit has a second starting voltage, and generates a second clock signal in response to the supply voltage. The detector circuit detects the second clock signal to generate a valid signal. The selection circuit selectively outputs one of the first clock signal and the second clock signal according to the valid signal. The first starting voltage is lower than the second starting voltage.
Description
本案是關於時脈產生裝置,尤其是關於可縮短系統開機時間的時脈產生裝置與時脈產生方法。 This case is about a clock generation device, especially a clock generation device and a clock generation method that can shorten the system startup time.
在一些需要即時時鐘(real time clock,RTC)的應用中,當系統開機後,系統中的數位電路需要穩定的時脈訊號才可以開始進行運作。然而,一般振盪器電路的工作電壓較高。當供應電壓未達到振盪器電路的最低工作電壓前,振盪器電路無法提供合適的時脈訊號。因此,在供應電壓之位準升高至最低工作電壓後,數位電路才能獲得合適的時脈訊號。如此一來,數位電路在系統開機後需等候一段時間才能開始運作,無法滿足需快速啟動系統的應用場景。 In some applications requiring a real time clock (RTC), after the system is powered on, the digital circuits in the system need a stable clock signal to start to operate. However, the operating voltage of the general oscillator circuit is relatively high. When the supply voltage does not reach the minimum operating voltage of the oscillator circuit, the oscillator circuit cannot provide a suitable clock signal. Therefore, after the level of the supply voltage is raised to the minimum operating voltage, the digital circuit can obtain a proper clock signal. As a result, the digital circuit needs to wait for a period of time to start to operate after the system is turned on, which cannot meet the application scenarios that need to quickly start the system.
於一些實施態樣中,時脈產生裝置包含第一時脈產生電路、第二時脈產生電路、第一偵測電路以及選擇電路。第一時脈產生電路具有一第一啟動電壓,並響應一供應電壓產生一第一時脈訊號。第二時脈產生電路具有一 第二啟動電壓,並響應該供應電壓產生一第二時脈訊號。第一偵測電路偵測該第二時脈訊號,以產生一生效訊號。選擇電路根據該生效訊號選擇輸出該第一時脈訊號與該第二時脈訊號中之一者。該第一啟動電壓低於該第二啟動電壓。 In some implementations, the clock generation device includes a first clock generation circuit, a second clock generation circuit, a first detection circuit, and a selection circuit. The first clock generating circuit has a first start-up voltage and generates a first clock signal in response to a supply voltage. The second clock generating circuit has a The second startup voltage is used to generate a second clock signal in response to the supply voltage. The first detection circuit detects the second clock signal to generate a valid signal. The selection circuit selects and outputs one of the first clock signal and the second clock signal according to the valid signal. The first startup voltage is lower than the second startup voltage.
於一些實施態樣中,時脈產生方法包含下列操作:利用一第一時脈產生電路以響應一供應電壓產生一第一時脈訊號,其中該第一時脈產生電路具有第一啟動電壓;利用一第二時脈產生電路以響應該供應電壓產生一第二時脈訊號,其中該第二時脈產生電路具有第二啟動電壓,且該第一啟動電壓低於該第二啟動電壓;偵測該第二時脈訊號,以產生一生效訊號;以及根據該生效訊號選擇輸出該第一時脈訊號與該第二時脈訊號中之一者。 In some implementations, the clock generation method includes the following operations: using a first clock generation circuit to generate a first clock signal in response to a supply voltage, wherein the first clock generation circuit has a first start-up voltage; utilizing a second clock generating circuit to generate a second clock signal in response to the supply voltage, wherein the second clock generating circuit has a second start-up voltage, and the first start-up voltage is lower than the second start-up voltage; detecting measuring the second clock signal to generate a valid signal; and selecting and outputting one of the first clock signal and the second clock signal according to the valid signal.
於一些實施態樣中,時脈產生裝置包含第一時脈產生電路、第二時脈產生電路、第一偵測電路以及選擇電路。第一時脈產生電路在一供應電壓大於或等於一第一位準時產生一第一時脈訊號。第二時脈產生電路在供應電壓大於或等於一第二位準時產生一第二時脈訊號,其中該第一位準低於該第二位準。偵測電路偵測該第二時脈訊號,以產生一生效訊號。選擇電路根據該生效訊號選擇輸出該第一時脈訊號與該第二時脈訊號中之一者。 In some implementations, the clock generation device includes a first clock generation circuit, a second clock generation circuit, a first detection circuit, and a selection circuit. The first clock generating circuit generates a first clock signal when a supply voltage is greater than or equal to a first timing. The second clock generating circuit generates a second clock signal when the supply voltage is greater than or equal to a second level, wherein the first level is lower than the second level. The detection circuit detects the second clock signal to generate a valid signal. The selection circuit selects and outputs one of the first clock signal and the second clock signal according to the valid signal.
有關本案的特徵、實作與功效,茲配合圖式作較佳實施例詳細說明如下。 Regarding the features, implementation and effects of this case, a preferred embodiment is described in detail as follows in conjunction with the drawings.
100,100A:時脈產生裝置 100,100A: Clock generation device
110,120:時脈產生電路 110,120: Clock generation circuit
130,150:偵測電路 130,150: Detection circuit
140:選擇電路 140: Selection circuit
210:電流源 210: Current Source
220:開關 220: switch
230:電容 230: Capacitor
240:反相器 240: Inverter
250:計數器 250: Counter
260:比較器 260: Comparator
300,400:時脈產生裝置 300,400: Clock generator
310:邏輯閘電路 310: Logic gate circuit
410,420:延遲電路 410, 420: Delay Circuits
500:時脈產生方法 500: Clock generation method
CK1,CK2:時脈訊號 CK1, CK2: clock signal
CKF:最終時脈訊號 CKF: final clock signal
CT:計數值 CT: count value
GND:地電壓 GND: ground voltage
S1,S2:訊號 S1, S2: Signal
S510,S520,S530,S540:操作 S510, S520, S530, S540: Operation
SC1,SC2:控制訊號 SC1, SC2: Control signal
SD:偵測訊號 SD: detection signal
SV:生效訊號 SV: valid signal
T0~T3:時間 T0~T3: time
TH:臨界值 TH: Threshold value
TR:重置期間 TR: reset period
VDD:供應電壓 VDD: Supply voltage
〔圖1A〕為根據本案一些實施例繪製時脈產生裝置的示意圖;〔圖1B〕為根據本案一些實施例繪製時脈產生裝置之示意圖; 〔圖2A〕為根據本案一些實施例繪製圖1A或圖1B中的偵測電路之示意圖;〔圖2B〕為根據本案一些實施例繪製圖1A或圖1B中的偵測電路之示意圖;〔圖3〕為根據本案一些實施例繪製時脈產生裝置的示意圖;〔圖4A〕為根據本案一些實施例繪製時脈產生裝置的示意圖;〔圖4B〕為根據本案一些實施例繪製圖4A中的時脈產生裝置之時序示意圖;以及〔圖5〕為根據本案一些實施例繪製時脈產生方法的流程圖。 [FIG. 1A] is a schematic diagram of a clock generation device according to some embodiments of the present application; [FIG. 1B] is a schematic diagram of a clock generation device according to some embodiments of the present application; [FIG. 2A] is a schematic diagram of the detection circuit in FIG. 1A or FIG. 1B according to some embodiments of the present application; [FIG. 2B] is a schematic diagram of the detection circuit in FIG. 1A or FIG. 1B according to some embodiments of the present application; [FIG. 3] is a schematic diagram of a clock generation device according to some embodiments of the present application; [FIG. 4A] is a schematic diagram of a clock generation device according to some embodiments of the present application; [FIG. 4B] is a schematic diagram of the clock generation device in FIG. 4A according to some embodiments of this application A timing diagram of the pulse generating device; and [ FIG. 5 ] is a flowchart of a method for generating a clock according to some embodiments of the present application.
本文所使用的所有詞彙具有其通常的意涵。上述之詞彙在普遍常用之字典中之定義,在本案的內容中包含任一於此討論的詞彙之使用例子僅為示例,不應限制到本案之範圍與意涵。同樣地,本案亦不僅以於此說明書所示出的各種實施例為限。 All terms used herein have their ordinary meanings. The definitions of the above-mentioned terms in commonly used dictionaries, the use of any of the terms discussed in the content of this case is only an example, and should not be limited to the scope and meaning of this case. Likewise, the present application is not limited to the various embodiments shown in this specification.
關於本文中所使用之『耦接』或『連接』,均可指二或多個元件相互直接作實體或電性接觸,或是相互間接作實體或電性接觸,亦可指二或多個元件相互操作或動作。如本文所用,用語『電路』可為由至少一個電晶體與/或至少一個主被動元件按一定方式連接以處理訊號的裝置。 As used herein, "coupling" or "connection" may refer to two or more elements in direct physical or electrical contact with each other, or in indirect physical or electrical contact with each other, or two or more elements Elements interact or act on each other. As used herein, the term "circuit" can be a device that is connected in a manner to process signals by at least one transistor and/or at least one active and passive element.
圖1A為根據本案一些實施例繪製的一種時脈產生裝置100的示意圖。於一些實施例中,時脈產生裝置100可應用於影像處理晶片。例如,時脈產生裝置100可提供最終時脈訊號CKF給一安防晶片,以讓安防晶片具有較短的啟動時間來開始監控環境。 FIG. 1A is a schematic diagram of a clock generating apparatus 100 according to some embodiments of the present application. In some embodiments, the clock generation device 100 may be applied to an image processing wafer. For example, the clock generation device 100 can provide the final clock signal CKF to a security chip, so that the security chip has a shorter startup time to start monitoring the environment.
時脈產生裝置100包含時脈產生電路110、時脈產生電路120、偵測電路130以及選擇電路140。於一些實施例中,時脈產生電路110具有第一啟動電壓,時脈產生電路120具有第二啟動電壓,且第一啟動電壓低於第二啟動電壓。於一些實施例中,時脈產生電路120產生的時脈訊號CK2的精準度高於時脈產生電路110產生的時脈訊號CK1的精準度。於一些實施例中,時脈訊號CK1的頻率接近於(或相同於)時脈訊號CK2的頻率。 The clock generation device 100 includes a clock generation circuit 110 , a clock generation circuit 120 , a detection circuit 130 and a selection circuit 140 . In some embodiments, the clock generation circuit 110 has a first startup voltage, the clock generation circuit 120 has a second startup voltage, and the first startup voltage is lower than the second startup voltage. In some embodiments, the accuracy of the clock signal CK2 generated by the clock generation circuit 120 is higher than that of the clock signal CK1 generated by the clock generation circuit 110 . In some embodiments, the frequency of the clock signal CK1 is close to (or the same as) the frequency of the clock signal CK2.
例如,時脈產生電路110可為(但不限於)自由運行(free running)振盪器,其可響應供應電壓VDD產生時脈訊號CK1。時脈產生電路120可為(但不限於)石英振盪器,其可響應供應電壓VDD產生時脈訊號CK2。於一些實施例中,時脈產生電路110工作電壓的範圍約為0.5~3.3伏特,時脈產生電路120工作電壓的範圍約為0.9~3.3伏特,由此可知,時脈產生電路110的第一啟動電壓為0.5伏特,而時脈產生電路120的第二啟動電壓為0.9伏特。當供應電壓VDD大於或等於第一啟動電壓時,時脈產生電路110開始運作以產生時脈訊號CK1。當供應電壓VDD大於或等於第二啟動電壓時,時脈產生電路120開始運作以產生時脈訊號CK2。藉由上述設置方式,當時脈產生裝置100上電時,供應電壓VDD會由低電壓位準開始上升,由於第一啟動電壓低於第二啟動電壓,因此,時脈產生電路110產生時脈訊號CK1的時間會早於時脈產生電路120產生時脈訊號CK2的時間。 For example, the clock generation circuit 110 can be, but not limited to, a free running oscillator, which can generate the clock signal CK1 in response to the supply voltage VDD. The clock generating circuit 120 can be, but is not limited to, a quartz oscillator, which can generate the clock signal CK2 in response to the supply voltage VDD. In some embodiments, the operating voltage range of the clock generating circuit 110 is about 0.5~3.3 volts, and the operating voltage range of the clock generating circuit 120 is about 0.9~3.3 volts. It can be seen that the first voltage of the clock generating circuit 110 is The startup voltage is 0.5 volts, and the second startup voltage of the clock generation circuit 120 is 0.9 volts. When the supply voltage VDD is greater than or equal to the first startup voltage, the clock generating circuit 110 starts to operate to generate the clock signal CK1. When the supply voltage VDD is greater than or equal to the second startup voltage, the clock generating circuit 120 starts to operate to generate the clock signal CK2. With the above arrangement, when the clock generation device 100 is powered on, the supply voltage VDD will start to rise from a low voltage level. Since the first startup voltage is lower than the second startup voltage, the clock generation circuit 110 generates a clock signal. The time of CK1 is earlier than the time of the clock signal CK2 generated by the clock generation circuit 120 .
偵測電路130用以偵測時脈訊號CK2是否穩定並偵測時脈訊號CK2的特性(例如為頻率)是否合適,以產生生效訊號SV。於一些實施例中,如圖2A所示,偵測電路130可由類比電路實施。於一些實施例中,如圖2B所 示,偵測電路130可由數位電路實施。於另一些實施例中,偵測電路130可由混合訊號電路實施。 The detection circuit 130 is used for detecting whether the clock signal CK2 is stable and detecting whether the characteristic (eg, frequency) of the clock signal CK2 is suitable, so as to generate the valid signal SV. In some embodiments, as shown in FIG. 2A , the detection circuit 130 may be implemented by an analog circuit. In some embodiments, as shown in Figure 2B As shown, the detection circuit 130 may be implemented by a digital circuit. In other embodiments, the detection circuit 130 may be implemented by a mixed-signal circuit.
選擇電路140可根據生效訊號SV選擇輸出時脈訊號CK1與時脈訊號CK2中之一者為最終時脈訊號CKF。例如,當時脈產生裝置100上電時,供應電壓VDD開始升高。當供應電壓VDD大於或等於第一啟動電壓時,時脈產生電路110可開始運作以產生時脈訊號CK1,且時脈產生電路120尚未啟動。於此條件下,偵測電路130輸出具有第一邏輯值(例如為邏輯值0)的生效訊號SV。選擇電路140可根據此生效訊號SV選擇輸出時脈訊號CK1為最終時脈訊號CKF。當供應電壓VDD大於或等於第二啟動電壓時,時脈產生電路120開始運作以輸出時脈訊號CK2。於此條件下,偵測電路130輸出具有第二邏輯值(例如為邏輯值1)的生效訊號SV。選擇電路140可根據此生效訊號SV選擇輸出時脈訊號CK2為最終時脈訊號CKF。藉由上述設置方式,時脈產生裝置100可於開機過程中更快地提供最終時脈訊號CKF,以加快系統中其他電路的開始運作時間。於一些實施例中,選擇電路140可為多工器電路。 The selection circuit 140 can select and output one of the clock signal CK1 and the clock signal CK2 as the final clock signal CKF according to the valid signal SV. For example, when the clock generating apparatus 100 is powered on, the supply voltage VDD starts to increase. When the supply voltage VDD is greater than or equal to the first start-up voltage, the clock generating circuit 110 can start to operate to generate the clock signal CK1, and the clock generating circuit 120 has not been started. Under this condition, the detection circuit 130 outputs a valid signal SV having a first logic value (eg, logic value 0). The selection circuit 140 can select the output clock signal CK1 as the final clock signal CKF according to the valid signal SV. When the supply voltage VDD is greater than or equal to the second startup voltage, the clock generating circuit 120 starts to operate to output the clock signal CK2. Under this condition, the detection circuit 130 outputs the valid signal SV having the second logic value (eg, logic value 1). The selection circuit 140 can select the output clock signal CK2 as the final clock signal CKF according to the valid signal SV. With the above arrangement, the clock generation device 100 can provide the final clock signal CKF more quickly during the booting process, so as to speed up the start-up time of other circuits in the system. In some embodiments, the selection circuit 140 may be a multiplexer circuit.
圖1B為根據本案一些實施例繪製時脈產生裝置100A之示意圖。相較於圖1A,圖1B的時脈產生裝置100A更包含偵測電路150,其可用於確認時脈產生電路110是否開始輸出時脈訊號CK1,以產生控制訊號SC1。於一些實施例中,控制訊號SC1可用於致能系統中的周邊電路(未示出)。例如,當時脈產生電路110開始輸出時脈訊號CK1,控制訊號SC1由第一邏輯值切換至第二邏輯值。響應此控制訊號SC1,系統中的電源控制(power-on control)電路被致能以開始提供電源至周邊電路。如此,周邊電路可以更快地開始運作。 FIG. 1B is a schematic diagram of a clock generating apparatus 100A according to some embodiments of the present invention. Compared with FIG. 1A , the clock generating apparatus 100A of FIG. 1B further includes a detection circuit 150 , which can be used to confirm whether the clock generating circuit 110 starts to output the clock signal CK1 to generate the control signal SC1 . In some embodiments, the control signal SC1 may be used to enable peripheral circuits (not shown) in the system. For example, when the clock generation circuit 110 starts to output the clock signal CK1, the control signal SC1 is switched from the first logic value to the second logic value. In response to the control signal SC1, a power-on control circuit in the system is enabled to start supplying power to peripheral circuits. In this way, peripheral circuits can start operating faster.
圖2A為根據本案一些實施例繪製圖1A或圖1B中的偵測電路130之示意圖。偵測電路130包含電流源210、開關220、電容230以及反相器240。 FIG. 2A is a schematic diagram of the detection circuit 130 in FIG. 1A or FIG. 1B according to some embodiments of the present invention. The detection circuit 130 includes a current source 210 , a switch 220 , a capacitor 230 and an inverter 240 .
電流源210的第一端接收供應電壓VDD,且電流源210的第二端耦接至開關220的第一端。開關220的第二端接收地電壓GND,且開關220的控制端接收時脈訊號CK2。電容230的第一端耦接至電流源210的第二端,且電容230的第二端接收地電壓GND。反相器240的輸入端耦接至電容230的第一端,且反相器240的輸出端用以輸出生效訊號SV。電流源210用以提供電流訊號SI。開關220用以根據時脈訊號CK2選擇性導通。電容230用以經由電流訊號SI充電並經由開關220放電,以產生偵測訊號SD。反相器240用以根據偵測訊號SD輸出生效訊號SV。 The first end of the current source 210 receives the supply voltage VDD, and the second end of the current source 210 is coupled to the first end of the switch 220 . The second terminal of the switch 220 receives the ground voltage GND, and the control terminal of the switch 220 receives the clock signal CK2. The first terminal of the capacitor 230 is coupled to the second terminal of the current source 210, and the second terminal of the capacitor 230 receives the ground voltage GND. The input terminal of the inverter 240 is coupled to the first terminal of the capacitor 230, and the output terminal of the inverter 240 is used for outputting the valid signal SV. The current source 210 is used for providing the current signal SI. The switch 220 is selectively turned on according to the clock signal CK2. The capacitor 230 is charged through the current signal SI and discharged through the switch 220 to generate the detection signal SD. The inverter 240 is used for outputting the valid signal SV according to the detection signal SD.
詳細而言,在時脈產生電路120尚未產生時脈訊號CK2時,開關220不導通,且電容230經由電流訊號SI被充電,以產生具有高位準的偵測訊號SD。響應於此偵測訊號SD,反相器240輸出具有低位準(對應於邏輯值0)的生效訊號SV。或者,當時脈產生電路120開始產生合適的時脈訊號CK2時,代表時脈訊號CK2穩定地具有一定數量的脈波。開關220響應該些脈波依序被導通而使得電容230開始放電,以產生具有低位準的偵測訊號SD。響應於此偵測訊號SD,反相器240輸出具有高位準(對應於邏輯值1)的生效訊號SV。如此一來,生效訊號SV可用於指示時脈產生電路120是否有穩定地產生合適的時脈訊號CK2。 Specifically, when the clock signal CK2 is not yet generated by the clock generation circuit 120, the switch 220 is turned off, and the capacitor 230 is charged by the current signal SI to generate the detection signal SD with a high level. In response to the detection signal SD, the inverter 240 outputs a valid signal SV having a low level (corresponding to a logic value of 0). Alternatively, when the clock generation circuit 120 starts to generate a suitable clock signal CK2, it means that the clock signal CK2 has a certain number of pulses stably. In response to the pulses being turned on in sequence, the switch 220 makes the capacitor 230 begin to discharge, so as to generate the detection signal SD with a low level. In response to the detection signal SD, the inverter 240 outputs a valid signal SV having a high level (corresponding to a logic value of 1). In this way, the valid signal SV can be used to indicate whether the clock generation circuit 120 has stably generated the appropriate clock signal CK2.
於此例中,可利用電容230的容值C調整具有高位準的生效訊號SV之產生時間,進而設定自輸出時脈訊號CK1切換至輸出時脈訊號CK2的時間 (後稱切換時間T)。於一些實施例中,切換時間T可依據時脈訊號CK2的應用要求來決定。例如,切換時間T可依據時脈訊號CK2所需的頻率來決定。 In this example, the capacitance value C of the capacitor 230 can be used to adjust the generation time of the valid signal SV with a high level, thereby setting the switching time from the output clock signal CK1 to the output clock signal CK2 (hereinafter referred to as switching time T). In some embodiments, the switching time T may be determined according to the application requirements of the clock signal CK2. For example, the switching time T can be determined according to the required frequency of the clock signal CK2.
於一些實施例中,切換時間T與容值C符合下式:Q=C×VDD=I×T
其中,供應電壓VDD可為前述的第二啟動電壓所對應的電壓範圍,Q為電容230儲存的電荷量,I為電容230的放電電流,TCK2為時脈訊號CK2的週期,M為預定數值。上式表示電容230在預定期間(其對應於M個時脈訊號CK2的週期)放電使得電容230的第一端之位準為地電壓GND。根據上式,可藉由調整電容230的容值C或是電流訊號SI(影響電容230的放電電流I)來設定切換時間T。 In some embodiments, the switching time T and the capacitance C conform to the following formula: Q = C × VDD = I × T Wherein, the supply voltage VDD can be the voltage range corresponding to the aforementioned second startup voltage, Q is the amount of charge stored in the capacitor 230, I is the discharge current of the capacitor 230, T CK2 is the period of the clock signal CK2, and M is a predetermined value . The above equation indicates that the capacitor 230 is discharged during a predetermined period (corresponding to M cycles of the clock signal CK2 ) so that the level of the first terminal of the capacitor 230 is the ground voltage GND. According to the above formula, the switching time T can be set by adjusting the capacitance value C of the capacitor 230 or the current signal SI (which affects the discharge current I of the capacitor 230 ).圖2B為根據本案一些實施例繪製圖1A或圖1B中的偵測電路130之示意圖。偵測電路130包含計數器250以及比較器260。計數器250用以對時脈訊號CK2計數以產生計數值CT。於一些實施例中,計數器250可為上數計數器、下數計數器、漣波(ripple)計數器或其他類型的計數器。比較器260用以在計數值等於臨界值TH時輸出生效訊號SV。 FIG. 2B is a schematic diagram of the detection circuit 130 in FIG. 1A or FIG. 1B according to some embodiments of the present invention. The detection circuit 130 includes a counter 250 and a comparator 260 . The counter 250 is used for counting the clock signal CK2 to generate the count value CT. In some embodiments, the counter 250 may be an up counter, a down counter, a ripple counter, or other types of counters. The comparator 260 is used for outputting the valid signal SV when the count value is equal to the threshold value TH.
例如,計數器250為上數計數器,其用以響應時脈訊號CK2的一個脈波進行上數以產生計數值CT。當計數值CT增加至相同於臨界值TH時,代表時脈產生電路120可穩定地輸出時脈訊號CK2。於此條件下,比較器260輸出具有特定邏輯值的生效訊號SV。相較於圖2A,於此例中,可藉由調整臨界值TH來設定時脈訊號CK2的頻率及穩定度。 For example, the counter 250 is an up-counting counter, which is used for up-counting in response to a pulse of the clock signal CK2 to generate the count value CT. When the count value CT increases to be the same as the threshold value TH, the representative clock generation circuit 120 can stably output the clock signal CK2. Under this condition, the comparator 260 outputs the valid signal SV with a specific logic value. Compared with FIG. 2A , in this example, the frequency and stability of the clock signal CK2 can be set by adjusting the threshold TH.
於一些實施例中,偵測電路150與偵測電路130具有類似或相同電路設置方式。偵測電路150之設置方式可參照圖2A或圖2B,故不再重複贅 述。若是以圖2A的例子來實施偵測電路150,上式中的供應電壓VDD可為時脈產生電路110的工作電壓所對應的電壓範圍。或者,若是以圖2B的例子來實施偵測電路150,偵測電路150所使用的臨界值TH可不同於偵測電路130所使用的臨界值TH。 In some embodiments, the detection circuit 150 and the detection circuit 130 have similar or the same circuit configuration. The setting method of the detection circuit 150 can refer to FIG. 2A or FIG. 2B , so it is not repeated here. described. If the detection circuit 150 is implemented in the example of FIG. 2A , the supply voltage VDD in the above formula can be a voltage range corresponding to the operating voltage of the clock generating circuit 110 . Alternatively, if the detection circuit 150 is implemented with the example of FIG. 2B , the threshold TH used by the detection circuit 150 may be different from the threshold TH used by the detection circuit 130 .
圖3為根據本案一些實施例繪製時脈產生裝置300的示意圖。相較於圖1B,於此例中,生效訊號SV可用以控制時脈產生電路110。例如,時脈產生電路110為具有電源閘控(power gating)的環形振盪器電路,其可根據生效訊號SV致能或禁能。 FIG. 3 is a schematic diagram illustrating a clock generating apparatus 300 according to some embodiments of the present invention. Compared to FIG. 1B , in this example, the enable signal SV can be used to control the clock generating circuit 110 . For example, the clock generating circuit 110 is a ring oscillator circuit with power gating, which can be enabled or disabled according to the valid signal SV.
於一些實施例中,生效訊號SV的初始值為第一邏輯值。響應具有第一邏輯值的生效訊號SV,時脈產生電路110被致能,以根據供應電壓VDD開始產生時脈訊號CK1。當時脈產生裝置300上電時,供應電壓VDD由零位準開始爬升至一預定位準。當供應電壓VDD高於或等於該第一啟動電壓時,時脈產生電路110開始產生時脈訊號CK1。響應具有第一邏輯值的生效訊號SV,選擇電路140輸出時脈訊號CK1為最終時脈訊號CKF。當供應電壓VDD高於或等於第二啟動電壓時,時脈產生電路120開始產生時脈訊號CK2。偵測電路130確認時脈產生電路120可以穩定地產生合適的時脈訊號CK2,並產生具有第二邏輯值的生效訊號SV。響應具有第二邏輯值的生效訊號SV,選擇電路140切換為輸出時脈訊號CK2為最終時脈訊號CKF。另一方面,時脈產生電路110可響應具有第二邏輯值的生效訊號SV關閉,以節省系統功耗。當時脈產生電路110被關閉,時脈產生電路110停止輸出時脈訊號CK1。於此條件下,偵測電路150輸出具有第一邏輯值的控制訊號SC1。 In some embodiments, the initial value of the valid signal SV is the first logic value. In response to the valid signal SV having the first logic value, the clock generating circuit 110 is enabled to start generating the clock signal CK1 according to the supply voltage VDD. When the clock generating device 300 is powered on, the supply voltage VDD starts to climb from a zero level to a predetermined level. When the supply voltage VDD is higher than or equal to the first startup voltage, the clock generation circuit 110 starts to generate the clock signal CK1. In response to the valid signal SV having the first logic value, the selection circuit 140 outputs the clock signal CK1 as the final clock signal CKF. When the supply voltage VDD is higher than or equal to the second startup voltage, the clock generation circuit 120 starts to generate the clock signal CK2. The detection circuit 130 confirms that the clock generation circuit 120 can stably generate an appropriate clock signal CK2, and generates a valid signal SV having a second logic value. In response to the valid signal SV having the second logic value, the selection circuit 140 switches to output the clock signal CK2 as the final clock signal CKF. On the other hand, the clock generation circuit 110 can be turned off in response to the valid signal SV having the second logic value, so as to save system power consumption. When the clock generating circuit 110 is turned off, the clock generating circuit 110 stops outputting the clock signal CK1. Under this condition, the detection circuit 150 outputs the control signal SC1 having the first logic value.
再者,相較於圖1B,時脈產生裝置300更包含邏輯閘電路310。邏輯閘電路310用以根據生效訊號SV與控制訊號SC1產生控制訊號SC2。控制訊號SC2可用以控制系統中的數位電路,舉例來說,控制訊號SC2可用以控制電源控制電路,以決定是否對數位電路供電。 Furthermore, compared to FIG. 1B , the clock generating device 300 further includes a logic gate circuit 310 . The logic gate circuit 310 is used for generating the control signal SC2 according to the valid signal SV and the control signal SC1. The control signal SC2 can be used to control the digital circuit in the system. For example, the control signal SC2 can be used to control the power control circuit to determine whether to supply power to the digital circuit.
於一些實施例中,邏輯閘電路310可為(但不限於)互斥或(XOR)閘電路。當供應電壓VDD上電時,時脈產生電路110先輸出時脈訊號CK1(相較於時脈產生電路120)。於此條件下,控制訊號SC1具有第二邏輯值且生效訊號SV具有第一邏輯值。邏輯閘電路310響應此控制訊號SC1與生效訊號SV產生具有第二邏輯值的控制訊號SC2。電源控制電路可響應此控制訊號SC2提供電源給數位電路。當時脈產生電路120輸出合適的時脈訊號CK2時,偵測電路130輸出具有第二邏輯值的生效訊號SV。於此條件下,時脈產生電路110被關閉而停止輸出時脈訊號CK1,且偵測電路150據此輸出具有第一邏輯值的控制訊號SC1。響應此生效訊號SV與控制訊號SC1,邏輯閘電路310產生具有第二邏輯值的控制訊號SC2,電源控制電路可持續提供電源給數位電路。 In some embodiments, the logic gate circuit 310 may be, but is not limited to, an exclusive OR (XOR) gate circuit. When the supply voltage VDD is powered on, the clock generation circuit 110 first outputs the clock signal CK1 (compared to the clock generation circuit 120 ). Under this condition, the control signal SC1 has the second logic value and the valid signal SV has the first logic value. The logic gate circuit 310 generates a control signal SC2 having a second logic value in response to the control signal SC1 and the valid signal SV. The power control circuit can provide power to the digital circuit in response to the control signal SC2. When the clock generation circuit 120 outputs a suitable clock signal CK2, the detection circuit 130 outputs a valid signal SV having a second logic value. Under this condition, the clock generation circuit 110 is turned off to stop outputting the clock signal CK1, and the detection circuit 150 outputs the control signal SC1 having the first logic value accordingly. In response to the valid signal SV and the control signal SC1, the logic gate circuit 310 generates a control signal SC2 having a second logic value, and the power control circuit can continuously provide power to the digital circuit.
圖4A為根據本案一些實施例繪製時脈產生裝置400的示意圖。相較於圖3中的時脈產生裝置300,時脈產生裝置400更包含延遲電路410與延遲電路420。延遲電路410用以延遲生效訊號SV產生訊號S1。延遲電路420用以延遲控制訊號SC1產生訊號S2。邏輯閘電路310用以根據訊號S1與訊號S2產生控制訊號SC2。於一些實施例中,延遲電路420的延遲時間可小於延遲電路410的延遲時間。於此例中,控制訊號SC2可用於控制相關於即時時鐘(real time clock)應用的數位電路。例如,數位電路可包含具有重置功能的正反器電路,其可根據控制訊號SC2被重置,以重置數位電路的設定值或參數。 FIG. 4A is a schematic diagram illustrating a clock generating apparatus 400 according to some embodiments of the present invention. Compared with the clock generating apparatus 300 in FIG. 3 , the clock generating apparatus 400 further includes a delay circuit 410 and a delay circuit 420 . The delay circuit 410 is used for delaying the valid signal SV to generate the signal S1. The delay circuit 420 is used for delaying the control signal SC1 to generate the signal S2. The logic gate circuit 310 is used for generating the control signal SC2 according to the signal S1 and the signal S2. In some embodiments, the delay time of the delay circuit 420 may be smaller than the delay time of the delay circuit 410 . In this example, the control signal SC2 can be used to control digital circuits related to real time clock applications. For example, the digital circuit may include a flip-flop circuit with a reset function, which can be reset according to the control signal SC2 to reset the settings or parameters of the digital circuit.
為說明時脈產生裝置400的操作,參照圖4B,圖4B為根據本案一些實施例繪製圖4A中的時脈產生裝置400之時序示意圖。在時脈產生裝置400上電後,於時間T0,時脈產生電路110輸出時脈訊號CK1,且選擇電路140輸出時脈訊號CK1為最終時脈訊號CKF。於時間T1,偵測電路150判斷時脈產生電路110可穩定地輸出時脈訊號CK1,並輸出具有第二邏輯值(對應於高位準)的控制訊號SC1。於時間T2,時脈產生電路120輸出時脈訊號CK2。於時間T3,偵測電路130判斷時脈產生電路120可穩定地輸出合適的時脈訊號CK2,並輸出具有第二邏輯值(對應於高位準)的生效訊號SV。響應於此生效訊號SV,時脈產生電路110被關閉而停止輸出時脈訊號CK1。於此條件下,偵測電路150判斷時脈產生電路110未輸出時脈訊號CK1,並輸出具有第一邏輯值(對應於低位準)的控制訊號SC1。延遲電路410延遲生效訊號SV以輸出訊號S1。延遲電路420延遲控制訊號SC1以輸出訊號S2。邏輯閘電路310可根據訊號S1與訊號S2產生控制訊號SC2。藉由上述設置方式,如圖4B所示,控制訊號SC2具有重置期間TR。於重置期間TR,RTC電路的數位電路部分之操作將被重置。如此一來,可避免數位電路部分之操作受到時脈訊號的切換過程之影響(例如,突波(glitch)),進而提高整體系統的操作穩定度。 To illustrate the operation of the clock generating apparatus 400 , please refer to FIG. 4B , which is a timing diagram illustrating the clock generating apparatus 400 in FIG. 4A according to some embodiments of the present application. After the clock generating device 400 is powered on, at time T0, the clock generating circuit 110 outputs the clock signal CK1, and the selecting circuit 140 outputs the clock signal CK1 as the final clock signal CKF. At time T1, the detection circuit 150 determines that the clock generation circuit 110 can stably output the clock signal CK1, and outputs the control signal SC1 having the second logic value (corresponding to the high level). At time T2, the clock generating circuit 120 outputs the clock signal CK2. At time T3, the detection circuit 130 determines that the clock generation circuit 120 can stably output an appropriate clock signal CK2, and outputs a valid signal SV having a second logic value (corresponding to a high level). In response to the valid signal SV, the clock generation circuit 110 is turned off and stops outputting the clock signal CK1. Under this condition, the detection circuit 150 determines that the clock generation circuit 110 does not output the clock signal CK1, and outputs the control signal SC1 having the first logic value (corresponding to the low level). The delay circuit 410 delays the valid signal SV to output the signal S1. The delay circuit 420 delays the control signal SC1 to output the signal S2. The logic gate circuit 310 can generate the control signal SC2 according to the signal S1 and the signal S2. With the above arrangement, as shown in FIG. 4B , the control signal SC2 has a reset period TR. During the reset period TR, the operation of the digital circuit part of the RTC circuit will be reset. In this way, the operation of the digital circuit part can be prevented from being affected by the switching process of the clock signal (eg, glitch), thereby improving the operation stability of the overall system.
圖5為根據本案一些實施例繪製一種時脈產生方法500的流程圖。於一些實施例中,時脈產生方法500可由(但不限於)圖1A、圖1B、圖3或圖4中的時脈產生裝置執行。 FIG. 5 is a flowchart of a method 500 for generating a clock according to some embodiments of the present application. In some embodiments, the clock generation method 500 may be performed by, but not limited to, the clock generation device of FIG. 1A , FIG. 1B , FIG. 3 or FIG. 4 .
於操作S510,利用一第一時脈產生電路以響應供應電壓產生第一時脈訊號,其中該第一時脈產生電路具有第一啟動電壓。於操作S520,利用一第二時脈產生電路以響應該供應電壓產生第二時脈訊號,其中該第二時脈產 生電路具有第二啟動電壓,且該第一啟動電壓低於該第二啟動電壓。於操作S530,偵測該第二時脈訊號,以產生生效訊號。於操作S540,根據生效訊號選擇輸出第一時脈訊號與第二時脈訊號中之一者為最終時脈訊號。 In operation S510, a first clock generating circuit is used to generate a first clock signal in response to the supply voltage, wherein the first clock generating circuit has a first start-up voltage. In operation S520, a second clock generating circuit is used to generate a second clock signal in response to the supply voltage, wherein the second clock generates The generating circuit has a second startup voltage, and the first startup voltage is lower than the second startup voltage. In operation S530, the second clock signal is detected to generate a valid signal. In operation S540, one of the first clock signal and the second clock signal is selected and output as the final clock signal according to the valid signal.
上述操作S510至操作S540之說明可參照前述各個實施例,故不重複贅述。上述時脈產生方法500的多個操作僅為示例,並非限定需依照此示例中的順序執行。在不違背本案的各實施例的操作方式與範圍下,在時脈產生方法500下的各種操作當可適當地增加、替換、省略或以不同順序執行。或者,在時脈產生方法500下的一或多個操作可以是同時或部分同時執行。 For the description of the above operations S510 to S540, reference may be made to the foregoing embodiments, and thus will not be repeated. The operations of the above clock generation method 500 are only examples, and are not limited to be performed in the order in this example. Various operations under the clock generation method 500 may be appropriately added, replaced, omitted or performed in different orders without departing from the operation manner and scope of the embodiments of the present application. Alternatively, one or more operations under clock generation method 500 may be performed concurrently or partially concurrently.
綜上所述,本案一些實施例中的時脈產生裝置與時脈產生方法可以更快地輸出時脈訊號,以加快系統開始運作的時間。如此,可以降低RTC應用的相關電路或晶片的開始運作時間。 To sum up, the clock generation device and the clock generation method in some embodiments of the present application can output the clock signal faster, so as to speed up the time when the system starts to operate. In this way, the start-up time of the related circuits or chips of the RTC application can be reduced.
雖然本案之實施例如上所述,然而該些實施例並非用來限定本案,本技術領域具有通常知識者可依據本案之明示或隱含之內容對本案之技術特徵施以變化,凡此種種變化均可能屬於本案所尋求之專利保護範疇,換言之,本案之專利保護範圍須視本說明書之申請專利範圍所界定者為準。 Although the embodiments of the present case are as described above, these embodiments are not intended to limit the present case. Those with ordinary knowledge in the technical field can make changes to the technical features of the present case according to the explicit or implicit contents of the present case. All may belong to the scope of patent protection sought in this case. In other words, the scope of patent protection in this case must be determined by the scope of the patent application in this specification.
100:時脈產生裝置 100: Clock generator
110,120:時脈產生電路 110,120: Clock generation circuit
130:偵測電路 130: Detection circuit
140:選擇電路 140: Selection circuit
CK1,CK2:時脈訊號 CK1, CK2: clock signal
CKF:最終時脈訊號 CKF: final clock signal
SV:生效訊號 SV: valid signal
VDD:供應電壓 VDD: Supply voltage
Claims (11)
一種時脈產生裝置,包含: 一第一時脈產生電路,具有一第一啟動電壓,並響應一供應電壓產生一第一時脈訊號; 一第二時脈產生電路,具有一第二啟動電壓,並響應該供應電壓產生一第二時脈訊號; 一第一偵測電路,偵測該第二時脈訊號,以產生一生效訊號;以及 一選擇電路,根據該生效訊號選擇輸出該第一時脈訊號與該第二時脈訊號中之一者; 其中,該第一啟動電壓低於該第二啟動電壓。 A clock generating device, comprising: a first clock generating circuit having a first start-up voltage and generating a first clock signal in response to a supply voltage; a second clock generating circuit having a second start-up voltage and generating a second clock signal in response to the supply voltage; a first detection circuit for detecting the second clock signal to generate a valid signal; and a selection circuit for selecting and outputting one of the first clock signal and the second clock signal according to the valid signal; Wherein, the first startup voltage is lower than the second startup voltage. 如請求項1之時脈產生裝置,其中該生效訊號用以控制該第一時脈產生電路。The clock generating device of claim 1, wherein the valid signal is used to control the first clock generating circuit. 如請求項1之時脈產生裝置,更包含: 一第二偵測電路,偵測該第一時脈訊號,以產生一第一控制訊號。 Such as the clock generation device of claim 1, further comprising: A second detection circuit detects the first clock signal to generate a first control signal. 如請求項3之時脈產生裝置,更包含: 一邏輯閘電路,用以根據該生效訊號與該第一控制訊號產生一第二控制訊號,其中該第二控制訊號用以控制一數位電路。 Such as the clock generation device of claim 3, further comprising: A logic gate circuit is used for generating a second control signal according to the valid signal and the first control signal, wherein the second control signal is used for controlling a digital circuit. 如請求項3之時脈產生裝置,更包含: 一第一延遲電路,用以延遲該生效訊號,以產生一第一訊號; 一第二延遲電路,用以延遲該第一控制訊號,以產生一第二訊號;以及 一邏輯閘電路,用以根據該第一訊號與該第二訊號產生一第二控制訊號; 其中,該第一延遲電路之一延遲時間小於該第二延遲電路之一延遲時間。 Such as the clock generation device of claim 3, further comprising: a first delay circuit for delaying the valid signal to generate a first signal; a second delay circuit for delaying the first control signal to generate a second signal; and a logic gate circuit for generating a second control signal according to the first signal and the second signal; Wherein, a delay time of the first delay circuit is smaller than a delay time of the second delay circuit. 如請求項1之時脈產生裝置,其中當該供應電壓等於或大於該第一啟動電壓時,該第一時脈產生電路開始產生該第一時脈訊號,且當該供應電壓等於或大於該第二啟動電壓時,該第二時脈產生電路開始產生該第二時脈訊號。The clock generating device of claim 1, wherein when the supply voltage is equal to or greater than the first start-up voltage, the first clock generating circuit starts to generate the first clock signal, and when the supply voltage is equal to or greater than the first start-up voltage When the second starting voltage is used, the second clock generating circuit starts to generate the second clock signal. 如請求項1之時脈產生裝置,其中該第一偵測電路包含: 一電流源,用以提供一電流訊號; 一開關,用以根據該第二時脈訊號選擇性地導通; 一電容,用以經由該電流訊號充電並經由該開關放電,以產生一偵測訊號;以及 一反相器,用以根據該偵測訊號輸出該生效訊號。 The clock generating device of claim 1, wherein the first detection circuit comprises: a current source for providing a current signal; a switch for selectively turning on according to the second clock signal; a capacitor for charging through the current signal and discharging through the switch to generate a detection signal; and an inverter for outputting the valid signal according to the detection signal. 如請求項1之時脈產生裝置,其中該第一偵測電路包含: 一計數器,用以對該第二時脈訊號計數,以產生一計數值;以及 一比較器,用以在該計數值等於一臨界值時輸出該生效訊號。 The clock generating device of claim 1, wherein the first detection circuit comprises: a counter for counting the second clock signal to generate a count value; and a comparator for outputting the valid signal when the count value is equal to a threshold value. 如請求項1之時脈產生裝置,其中該第一時脈產生電路為一自由運行(free running)振盪器,且該第二時脈產生電路為一石英振盪器。The clock generating device of claim 1, wherein the first clock generating circuit is a free running oscillator, and the second clock generating circuit is a quartz oscillator. 一種時脈產生方法,包含: 利用一第一時脈產生電路以響應一供應電壓產生一第一時脈訊號,該第一時脈產生電路具有一第一啟動電壓; 利用一第二時脈產生電路以響應該供應電壓產生一第二時脈訊號,該第二時脈產生電路具有一第二啟動電壓; 偵測該第二時脈訊號,以產生一生效訊號;以及 根據該生效訊號選擇輸出該第一時脈訊號與該第二時脈訊號中之一者; 其中,該第一啟動電壓低於該第二啟動電壓。 A clock generation method, including: utilizing a first clock generating circuit to generate a first clock signal in response to a supply voltage, the first clock generating circuit having a first start-up voltage; utilizing a second clock generating circuit to generate a second clock signal in response to the supply voltage, the second clock generating circuit having a second start-up voltage; detecting the second clock signal to generate a valid signal; and Selecting and outputting one of the first clock signal and the second clock signal according to the valid signal; Wherein, the first startup voltage is lower than the second startup voltage. 一種時脈產生裝置,包含: 一第一時脈產生電路,在一供應電壓大於或等於一第一位準時產生一第一時脈訊號; 一第二時脈產生電路,在該供應電壓大於或等於一第二位準時產生一第二時脈訊號,其中該第一位準低於該第二位準; 一偵測電路,偵測該第二時脈訊號,以產生一生效訊號;以及 一選擇電路,根據該生效訊號選擇輸出該第一時脈訊號與該第二時脈訊號中之一者。 A clock generating device, comprising: a first clock generating circuit, which generates a first clock signal when a supply voltage is greater than or equal to a first bit timing; a second clock generating circuit for generating a second clock signal when the supply voltage is greater than or equal to a second level, wherein the first level is lower than the second level; a detection circuit for detecting the second clock signal to generate a valid signal; and A selection circuit selects and outputs one of the first clock signal and the second clock signal according to the valid signal.
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Citations (5)
* Cited by examiner, † Cited by third partyPublication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5550489A (en) * | 1995-09-29 | 1996-08-27 | Quantum Corporation | Secondary clock source for low power, fast response clocking |
TW200635234A (en) * | 2005-03-21 | 2006-10-01 | Mobius Microsystems Inc | Low-latency start-up for a monolithic clock generator and timing/frequency reference |
US20080100392A1 (en) * | 2004-03-22 | 2008-05-01 | Mobius Microsystems, Inc. | Low-Latency Start-Up for a Monolithic Clock Generator and Timing/Frequency Reference |
US20130265807A1 (en) * | 2012-04-06 | 2013-10-10 | Samsung Electronics Co., Ltd. | Clock-based soft-start circuit and power management integrated circuit device |
US20140118035A1 (en) * | 2012-10-31 | 2014-05-01 | Nec Corporation | Clock signal initialization circuit and its method |
-
2021
- 2021-07-20 TW TW110126666A patent/TWI766765B/en active
Patent Citations (5)
* Cited by examiner, † Cited by third partyPublication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5550489A (en) * | 1995-09-29 | 1996-08-27 | Quantum Corporation | Secondary clock source for low power, fast response clocking |
US20080100392A1 (en) * | 2004-03-22 | 2008-05-01 | Mobius Microsystems, Inc. | Low-Latency Start-Up for a Monolithic Clock Generator and Timing/Frequency Reference |
TW200635234A (en) * | 2005-03-21 | 2006-10-01 | Mobius Microsystems Inc | Low-latency start-up for a monolithic clock generator and timing/frequency reference |
US20130265807A1 (en) * | 2012-04-06 | 2013-10-10 | Samsung Electronics Co., Ltd. | Clock-based soft-start circuit and power management integrated circuit device |
US20140118035A1 (en) * | 2012-10-31 | 2014-05-01 | Nec Corporation | Clock signal initialization circuit and its method |
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