TWI824292B - Memory device and method of manufacturing the same - Google Patents

Provided is a memory device including a substrate, a plurality of word lines extending in a first direction, arranged in a second direction, disposed on the substrate; a dummy structure, adjacent to ends of the plurality of word lines, disposed on the substrate, wherein the dummy structure includes a body part that extends in the second direction; and a plurality of extension parts that extend in the first direction are connected to the body part, and are interposed between the body part and the plurality of word lines.

記憶元件及其製造方法Memory element and manufacturing method thereof

本發明是有關於一種半導體元件及其製造方法，且特別是有關於一種記憶元件及其製造方法。The present invention relates to a semiconductor element and a manufacturing method thereof, and in particular, to a memory element and a manufacturing method thereof.

隨著科技的進步，各類電子產品皆朝向輕薄短小的趨勢發展，記憶元件的關鍵尺寸亦逐漸縮小，進而使得微影製程愈來愈困難。在習知微影製程中，縮小關鍵尺寸的方法包括使用較大數值孔徑（numerical aperture，NA）的光學元件、較短的曝光波長（例如EUV）或是除了空氣以外的界面介質（例如水浸入）。隨著習知微影製程的解析度接近理論極限，製造商已開始轉向雙重圖案化（double-patterning，DP）方法來克服光學極限，進而提升記憶元件的積集度。With the advancement of technology, various electronic products are developing towards a trend of being light, thin and compact, and the key dimensions of memory components are gradually shrinking, making the lithography process increasingly difficult. In conventional lithography processes, methods to reduce critical dimensions include using optical elements with larger numerical aperture (NA), shorter exposure wavelengths (such as EUV), or interface media other than air (such as water immersion). ). As the resolution of conventional lithography processes approaches the theoretical limit, manufacturers have begun to turn to double-patterning (DP) methods to overcome optical limitations and thereby increase the density of memory devices.

然而，在目前的圖案化方法中，由於陣列區的中心與末端的圖案密度不同，使得蝕刻製程會面臨負載效應（loading effect），進而導致陣列區的中心與末端的記憶體單元的輪廓不一致，而產生電性上的問題。However, in the current patterning method, due to the different pattern densities at the center and end of the array area, the etching process will face a loading effect, which in turn causes the outlines of the memory cells at the center and end of the array area to be inconsistent. And cause electrical problems.

本發明提供一種記憶元件，包括：基底；多個字元線，在第一方向延伸，在第二方向排列，位於所述基底上；虛設結構，與所述多個字元線的末端相鄰，位於所述基底上，其中所述虛設結構包括：主體部，在所述第二方向延伸；以及多個延伸部，在所述第一方向延伸，且與所述主體部連接，且介於所述主體部與所述多個字元線之間。The invention provides a memory element, including: a substrate; a plurality of word lines extending in a first direction, arranged in a second direction, and located on the base; a dummy structure adjacent to the ends of the plurality of word lines , located on the substrate, wherein the dummy structure includes: a main body portion extending in the second direction; and a plurality of extension portions extending in the first direction and connected to the main body portion and between between the main body part and the plurality of character lines.

本發明提供一種記憶元件的製造方法，包括：提供基底；在所述基底上形成目標層與硬罩幕層；將所述硬罩幕層圖案化，以形成圖案化的硬罩幕層，所述圖案化的硬罩幕層包括：多個第一圖案、第二圖案與多個第三圖案，其中所述多個第一圖案，在第一方向延伸且在第二方向排列，所述第二圖案呈梳狀且位於所述多個第一圖案與所述第三圖案之間，所述多個第三圖案在所述第二方向延伸且在所述第一方向排列；以及以所述圖案化的硬罩幕層，將所述多個第一圖案、所述第二圖案以及所述多個第三圖案轉移至所述目標層，以形成多個字元線、梳狀虛設結構以及多個著陸墊。The invention provides a method for manufacturing a memory element, which includes: providing a substrate; forming a target layer and a hard mask layer on the substrate; and patterning the hard mask layer to form a patterned hard mask layer. The patterned hard mask layer includes: a plurality of first patterns, a second pattern and a plurality of third patterns, wherein the plurality of first patterns extend in a first direction and are arranged in a second direction, and the third pattern Two patterns are comb-shaped and are located between the plurality of first patterns and the third patterns, the plurality of third patterns extend in the second direction and are arranged in the first direction; and with the Patterning the hard mask layer, transferring the plurality of first patterns, the second patterns and the plurality of third patterns to the target layer to form a plurality of word lines, comb-shaped dummy structures and Multiple landing pads.

基於上述，本發明實施例在陣列區與繞線區增加虛設的圖案可在進行蝕刻製程時減少陣列區的末端與中心之間的負載效應。Based on the above, adding dummy patterns in the array area and the winding area in the embodiment of the present invention can reduce the load effect between the end and the center of the array area during the etching process.

請參照圖1A與1B，記憶元件100形成在基底10上。在方向D2上，基底10可以分為多個區塊A0、A1、A2、A3、…等。每一區塊，以區塊A1來說明，可以包括陣列區R1、過渡區R2與繞線區R3，過渡區R2位於陣列區R1與繞線區R3之間。Referring to FIGS. 1A and 1B , the memory element 100 is formed on the substrate 10 . In the direction D2, the substrate 10 can be divided into a plurality of blocks A0, A1, A2, A3, . . . and so on. Each block, illustrated as block A1, may include an array area R1, a transition area R2, and a winding area R3. The transition area R2 is located between the array area R1 and the winding area R3.

記憶元件100包括多個字元線WL以及多個選擇閘SG。各個字元線WL的一末端位於陣列區中，另一末端則會延伸至繞線區。在一些實施例中，多個字元線WL的一末端彼此切齊，而排列成“I”型；多個字元線WL的另一末端未切齊，而排列成橫置的“V”型。The memory device 100 includes a plurality of word lines WL and a plurality of selection gates SG. One end of each word line WL is located in the array area, and the other end extends to the winding area. In some embodiments, one ends of the plurality of word lines WL are aligned with each other and arranged in an "I" shape; the other ends of the plurality of word lines WL are not aligned and are arranged in a horizontal "V" shape. type.

舉例來說，多個字元線WL包括多個字元線WL ₀、WL ₁、WL ₂。多個字元線WL ₀/WL ₂設置在區塊A0/A2的陣列區R1中且其末端E ₀₀/E ₂₀還延伸到繞線區R3，且分別排列成橫置的“V”型。多個字元線WL ₀/WL ₂的另一其末端（未示出）則位於陣列區R1中，而未延伸到另一繞線區（未示出），且分別切齊而排列成“I”型。多個字元線WL ₁/WL ₃設置在區塊A1/A3的陣列區R1中且其末端E ₁₀/E ₃₀未延伸到繞線區R3，且分別切齊而排列成“I”型。多個字元線WL ₁/WL ₃的另一其末端（未示出）則位於陣列區R1中且延伸到另一繞線區（未示出），且分別排列成橫置的“V”型。 For example, the plurality of word lines WL include a plurality of word lines WL ₀ , WL ₁ , and WL ₂ . A plurality of word lines WL ₀ /WL ₂ are arranged in the array area R1 of the block A0/A2, and their ends E ₀₀ /E ₂₀ also extend to the winding area R3, and are respectively arranged in a horizontal "V" shape. The other ends (not shown) of the plurality of word lines WL ₀ /WL ₂ are located in the array area R1 and do not extend to another winding area (not shown), and are aligned and arranged in "I" type. A plurality of word lines WL ₁ /WL ₃ are arranged in the array area R1 of the block A1/A3, and their ends E ₁₀ /E ₃₀ do not extend to the winding area R3, and are aligned and arranged in an "I" shape. The other ends (not shown) of the plurality of word lines WL ₁ /WL ₃ are located in the array area R1 and extend to another winding area (not shown), and are respectively arranged in a horizontal "V" type.

記憶元件100還包括多個選擇閘SG，分別設置在多個字元線WL的兩側。多個選擇閘SG設置於陣列區R1中。The memory element 100 further includes a plurality of selection gates SG, which are respectively disposed on both sides of the plurality of word lines WL. A plurality of selection gates SG are provided in the array region R1.

多個選擇閘SG包括設置於多個字元線WL ₀兩側的選擇閘SG ₀₀（未示出）與SG ₀₁、設置於多個字元線WL ₁兩側的多個選擇閘SG ₁₀與SG ₁₁、設置於多個字元線WL ₂兩側的多個選擇閘SG ₂₀與SG ₂₁以及設置於多個字元線WL ₃兩側的多個選擇閘SG ₃₀與SG ₃₁（未示出）。 The plurality of selection gates SG include selection gates SG ₀₀ (not shown) and SG ₀₁ disposed on both sides of the plurality of word lines WL ₀ , and a plurality of selection gates SG 10 and SG ₁₀ disposed on both sides of the plurality of word lines WL ₁ SG ₁₁ , a plurality of selection gates SG ₂₀ and SG ₂₁ disposed on both sides of the plurality of word lines WL ₂ and a plurality of selection gates SG ₃₀ and SG ₃₁ disposed on both sides of the plurality of word lines WL ₃ (not shown). ).

記憶元件100還包括設置在繞線區R3的做為字元線WL的接點（pick up）的多個著陸墊LP。著陸墊LP包括著陸墊LP ₀₁、LP ₂₀、LP ₂₁（示於圖1A左側）。著陸墊LP ₀₁、LP ₂₀、LP ₂₁分別在方向D2上延伸且在方向D1排列。此外，著陸墊LP ₀₁、LP ₂₀、LP ₂₁彼此在方向D2上對齊排列。著陸墊LP ₀₁與LP ₂₀彼此分離，設置在多個字元線WL ₁的末端E ₁₀，且彼此沿著方向D2排列。著陸墊LP ₀₁從區塊A1延伸至區塊A0，而與部分的多個字元線WL ₀的末端E ₀₀連接。著陸墊LP ₂₀從區塊A1延伸至區塊A2，而與部分的多個字元線WL ₂的末端E ₂₀連接。著陸墊LP ₂₁設置在多個字元線WL ₃的末端E ₃₀，且從區塊A3延伸至區塊A2，而與另一部分的多個字元線WL ₂的末端E ₂₀連接。著陸墊LP還包括其他的著陸墊，分別設置在多個字元線WL ₀與WL ₂的相對於E ₀₀與E ₂₀的另一末端（圖1A右側，未示出），且與WL ₁以及WL ₃連接。 The memory device 100 also includes a plurality of landing pads LP disposed in the winding area R3 as pick-ups of the word lines WL. The landing pad LP includes landing pads LP ₀₁ , LP ₂₀ , and LP ₂₁ (shown on the left side of Figure 1A ). The landing pads LP ₀₁ , LP ₂₀ , and LP ₂₁ respectively extend in the direction D2 and are arranged in the direction D1. In addition, the landing pads LP ₀₁ , LP ₂₀ , and LP ₂₁ are aligned with each other in the direction D2. The landing pads LP ₀₁ and LP ₂₀ are separated from each other, are arranged at the ends E ₁₀ of the plurality of word lines WL ₁ , and are arranged along the direction D2 with each other. The landing pad LP ₀₁ extends from the block A1 to the block A0 and is connected to the end E ₀₀ of part of the plurality of word lines WL ₀ . The landing pad LP ₂₀ extends from the block A1 to the block A2 and is connected to the ends E ₂₀ of part of the plurality of word lines WL ₂ . The landing pad LP ₂₁ is disposed at the end E ₃₀ of the plurality of word lines WL ₃ , extends from the block A3 to the block A2, and is connected to the end E ₂₀ of another part of the plurality of word lines WL ₂ . The landing pad LP also includes other landing pads, which are respectively arranged at the other ends of the plurality of word lines WL ₀ and WL ₂ relative to E ₀₀ and E ₂₀ (right side of Figure 1A, not shown), and are connected to WL ₁ and WL ₃ connection.

在本發明的實施例中，記憶元件100還包括設置在繞線區R3與陣列區R1之間的虛設結構DS。虛設結構DS設置在末端排列成齊平的多個字元線WL旁。在圖1A中，虛設結構DS可以包括虛設結構DS ₁與DS ₃。虛設結構DS ₁設置於區塊A1中，位於多個字元線WL ₁的末端E ₁₀旁；虛設結構DS ₃設置於區塊A3中，位於多個字元線WL ₃的末端E ₃₀旁。虛設結構DS還可以包括其他的虛設結構，其分別設置於區塊A0與A2中，且位於多個字元線WL ₀以及WL ₂的另一末端（未示出）旁。虛設結構DS可以是浮置，而未連接到外部電路。 In the embodiment of the present invention, the memory element 100 further includes a dummy structure DS disposed between the winding area R3 and the array area R1. The dummy structure DS is arranged next to a plurality of word lines WL whose ends are arranged flush. In FIG. 1A , the dummy structure DS may include dummy structures DS ₁ and DS ₃ . The dummy structure DS ₁ is provided in the block A1 and is located next to the end E ₁₀ of the plurality of word lines WL ₁ ; the dummy structure DS ₃ is provided in the block A3 and is located next to the end E ₃₀ of the plurality of word lines WL ₃ . The dummy structure DS may also include other dummy structures, which are respectively provided in the blocks A0 and A2 and located next to the other ends (not shown) of the plurality of word lines WL ₀ and WL ₂ . The dummy structure DS can be floating without being connected to external circuitry.

虛設結構DS例如是呈梳狀。虛設結構DS包括主體部MP與多個延伸部EP。主體部MP位於過渡區R2中，且主體部MP以非零距離與著陸墊LP相鄰。主體部MP的形狀與設置方向比多個延伸部EP更相似於著陸墊LP的形狀與設置方向。主體部MP與著陸墊LP均為實心塊狀體。主體部MP的延伸方向與著陸墊LP的延伸方向相同，均為沿著方向D2延伸。The dummy structure DS is, for example, in the shape of a comb. The dummy structure DS includes a main body part MP and a plurality of extension parts EP. The main body MP is located in the transition region R2, and the main body MP is adjacent to the landing pad LP at a non-zero distance. The shape and arrangement direction of the main body part MP are more similar to the shape and arrangement direction of the landing pad LP than the plurality of extension parts EP. The main body MP and the landing pad LP are both solid blocks. The extension direction of the main body MP is the same as the extension direction of the landing pad LP, and both extend along the direction D2.

多個延伸部EP位於陣列區R1中。多個延伸部EP的形狀與設置方向比主體部MP更相似於字元線WL的形狀與設置方向。多個延伸部EP的延伸方向與字元線WL的延伸方向相同，均為沿著方向D1延伸。多個延伸部EP排列的方向也與字元線WL的排列方向相同，均為沿著方向D2排列。多個延伸部EP與主體部MP連接，且以非零距離與多個字元線WL相鄰。延伸部EP與多個字元線WL之間的距離d1小於114nm，例如是30nm至114nm之間。選擇閘SG ₁₀與SG ₁₁延伸突出於字元線WL ₁的末端，主體部MP的長度L小於字元線WL ₁兩側的選擇閘SG ₁₀與SG ₁₁之間的距離d3。 A plurality of extension parts EP are located in the array region R1. The shape and arrangement direction of the plurality of extension portions EP are more similar to the shape and arrangement direction of the word line WL than the main body portion MP. The extension direction of the plurality of extension portions EP is the same as the extension direction of the word line WL, and both extend along the direction D1. The arrangement direction of the plurality of extending portions EP is also the same as the arrangement direction of the word lines WL, and they are all arranged along the direction D2. The plurality of extension parts EP are connected to the main body part MP, and are adjacent to the plurality of word lines WL at a non-zero distance. The distance d1 between the extension part EP and the plurality of word lines WL is less than 114 nm, for example, between 30 nm and 114 nm. The selection gates SG ₁₀ and SG ₁₁ extend and protrude from the ends of the word line WL ₁ , and the length L of the main body MP is smaller than the distance d3 between the selection gates SG ₁₀ and SG ₁₁ on both sides of the word line WL ₁ .

延伸部EP的寬度W ₂大於2倍的多個字元線WL的寬度W ₁，例如是多個字元線WL的寬度W ₁的2.5倍至3.5倍。主體部MP的寬度W ₃大於延伸部EP的寬度W ₂，例如是多個字元線WL的寬度W ₁的6倍至9倍。 The width W ₂ of the extension EP is greater than 2 times the width W ₁ of the plurality of word lines WL, for example, 2.5 times to 3.5 times the width W ₁ of the plurality of word lines WL. The width W ₃ of the main body part MP is larger than the width W ₂ of the extension part EP, for example, 6 times to 9 times the width W ₁ of the plurality of word lines WL.

虛設結構DS是藉由硬罩幕圖案（又稱為虛設圖案）圖案轉移而形成。虛設結構DS的設置可以在形成字元線WL以及著陸墊LP的蝕刻過程中改善負載效應，使得陣列區的中心與末端具有相似的輪廓。上述記憶元件100的製程可以參照以下實施例來說明，但不以此為限。The dummy structure DS is formed by pattern transfer of a hard mask pattern (also called a dummy pattern). The arrangement of the dummy structure DS can improve the loading effect during the etching process of forming the word line WL and the landing pad LP, so that the center and end of the array area have similar profiles. The manufacturing process of the memory element 100 can be described with reference to the following embodiments, but is not limited thereto.

本發明一實施例提供一種記憶元件的製造方法，其步驟如下。首先，請參照圖2A至圖5A，提供基底10。基底10可包括陣列區R1、過渡區R2與繞線區R3。在本實施例中，陣列區R1可以是具有一或多個記憶體單元的記憶體陣列區，繞線區R3可以是具有一或多個字元線接點的繞線區。過渡區R2介於陣列區R1與繞線區R3之間。在一實施例中，基底10可例如為半導體基底、半導體化合物基底或是絕緣層上有半導體（SOI）基底。在本實施例中，基底10為矽基底。An embodiment of the present invention provides a method for manufacturing a memory element. The steps are as follows. First, please refer to FIGS. 2A to 5A to provide a substrate 10 . The substrate 10 may include an array region R1, a transition region R2, and a winding region R3. In this embodiment, the array area R1 may be a memory array area having one or more memory cells, and the wiring area R3 may be a wiring area having one or more word line contacts. The transition region R2 is between the array region R1 and the winding region R3. In one embodiment, the substrate 10 may be, for example, a semiconductor substrate, a semiconductor compound substrate, or a semiconductor on insulator (SOI) substrate. In this embodiment, the substrate 10 is a silicon substrate.

接著，在基底10上形成目標層12。目標層12可以是在方向D3堆疊的堆疊層110。具體來說，如圖5A的放大圖所示，堆疊層110可由下往上依序包括穿隧介電層102、圖案化的浮置閘極層104、閘間介電層106、控制閘極層108、金屬層112以及頂蓋層114。Next, the target layer 12 is formed on the substrate 10 . The target layer 12 may be the stacked layer 110 stacked in the direction D3. Specifically, as shown in the enlarged view of FIG. 5A , the stacked layer 110 may include a tunnel dielectric layer 102 , a patterned floating gate layer 104 , an intergate dielectric layer 106 , and a control gate in order from bottom to top. layer 108, metal layer 112, and capping layer 114.

穿隧介電層102的材料可例如是氧化矽。圖案化的浮置閘極層104可以是沿著方向D2延伸，其材料可包括導體材料，例如是摻雜多晶矽、非摻雜多晶矽或其組合。閘間介電層106可例如是由氮化物/氧化物/氮化物/氧化物/氮化物（Nitride/Oxide/Nitride/Oxide/Nitride, NONON）所構成的複合層，但本發明並不限於此，此複合層可為三層、五層或更多層。控制閘極層108的材料可包括導體材料，例如是摻雜多晶矽、非摻雜多晶矽或其組合。金屬層112的材料可例如是W、TiN或其組合。頂蓋層114的材料可包括介電材料，例如是氮化矽、氮氧化矽或其組合。The material of the tunnel dielectric layer 102 may be, for example, silicon oxide. The patterned floating gate layer 104 may extend along the direction D2, and its material may include a conductor material, such as doped polysilicon, non-doped polysilicon, or a combination thereof. The inter-gate dielectric layer 106 may be, for example, a composite layer composed of Nitride/Oxide/Nitride/Oxide/Nitride, NONON, but the invention is not limited thereto. , this composite layer can be three, five or more layers. The material of the control gate layer 108 may include a conductive material, such as doped polysilicon, undoped polysilicon, or a combination thereof. The material of the metal layer 112 may be, for example, W, TiN, or a combination thereof. The material of the capping layer 114 may include a dielectric material, such as silicon nitride, silicon oxynitride, or a combination thereof.

然後，在堆疊層110上形成犧牲層14與硬罩幕層16。犧牲層14亦可稱為硬罩幕層。犧牲層14可以是氧化矽層。硬罩幕層16可以是單層或是多層。硬罩幕層16例如是多晶矽層。之後，在硬罩幕層16上形成核心層18。核心層18包括分別在陣列區R1、過渡區R2以及繞線區R3的核心圖案18a、18b、18c。核心圖案18a在方向D1延伸；核心圖案18b、18c在方向D2延伸。方向D1與方向D2彼此垂直。核心圖案18b與核心圖案18a連接，且與核心圖案18c分離。Then, the sacrificial layer 14 and the hard mask layer 16 are formed on the stacked layer 110 . The sacrificial layer 14 may also be called a hard mask layer. Sacrificial layer 14 may be a silicon oxide layer. Hard mask layer 16 may be a single layer or multiple layers. The hard mask layer 16 is, for example, a polycrystalline silicon layer. Afterwards, the core layer 18 is formed on the hard mask layer 16 . The core layer 18 includes core patterns 18a, 18b, and 18c in the array region R1, the transition region R2, and the winding region R3 respectively. The core pattern 18a extends in the direction D1; the core patterns 18b and 18c extend in the direction D2. Direction D1 and direction D2 are perpendicular to each other. The core pattern 18b is connected to the core pattern 18a and separated from the core pattern 18c.

在一實施例中，核心層18可包括碳化物層。在另一實施例中，核心層18可包括碳化物層以及抗反射層。碳化物層的材料可例如是旋塗碳（spin-on-carbon，SoC）。抗反射層的材料可例如是氮氧化矽。核心層18的形成方法例如先形成碳化物材料層以及抗反射材料層，然後經由微影製程在抗反射材料層上形成光阻圖案。在一些實施例中，在形成光阻圖案之後，還進行修剪製程，以使得所形成的光阻圖案的寬度減少。其後，進行蝕刻製程，將光阻圖案的圖案往下轉移到抗反射材料層以及碳化物材料層。之後，再將光阻圖案移除。In one embodiment, core layer 18 may include a carbide layer. In another embodiment, core layer 18 may include a carbide layer and an anti-reflective layer. The material of the carbide layer may be, for example, spin-on-carbon (SoC). The material of the anti-reflection layer may be, for example, silicon oxynitride. The core layer 18 is formed by, for example, first forming a carbide material layer and an anti-reflective material layer, and then forming a photoresist pattern on the anti-reflective material layer through a photolithography process. In some embodiments, after forming the photoresist pattern, a trimming process is also performed to reduce the width of the formed photoresist pattern. Thereafter, an etching process is performed to transfer the pattern of the photoresist pattern down to the anti-reflective material layer and the carbide material layer. Afterwards, the photoresist pattern is removed.

請參照圖2B至圖5B以及圖2C至圖5C，進行自對準雙重圖案化（Self-Aligning Double Patterning，SADP）製程，以在硬罩幕層16上形成間隙壁20。間隙壁20的材料包括氧化物，例如是氧化矽。在替代實施例中，亦可進行自對準四重圖案化（Self-Aligning Quadruple Patterning，SAQP）製程以形成圖案密度更高的間隙壁20。間隙壁20的形成方法例如是先在硬罩幕層16上以及核心層18的頂面與側壁形成間隙壁材料層19，如圖2B至圖5B所示。然後對間隙壁材料層19進行非等向性蝕刻製程，以移除部分的間隙壁材料層19，直至硬罩幕層16以及核心層18的頂面裸露出來，以在核心層18的側壁形成間隙壁20。之後，以間隙壁20以及核心層18為罩幕，繼續進行蝕刻，移除未被間隙壁20以及核心層18覆蓋的硬罩幕層16，以在陣列區R1、過渡區R2以及繞線區R3分別形成硬罩幕圖案16a、16b、16c。在蝕刻硬罩幕層16的過程中，核心層18也會被蝕刻移除，而裸露出硬罩幕圖案16a、16b、16c的部分頂面，如圖2C至圖5C所示。硬罩幕圖案16a在方向D1延伸；硬罩幕圖案16b、16c在方向D2延伸。硬罩幕圖案16b與硬罩幕圖案16a連接，且與硬罩幕圖案16c分離。Referring to FIGS. 2B to 5B and 2C to 5C , a self-aligned double patterning (SADP) process is performed to form spacers 20 on the hard mask layer 16 . The material of the spacer 20 includes an oxide, such as silicon oxide. In an alternative embodiment, a self-aligned quadruple patterning (SAQP) process may also be performed to form the spacer 20 with a higher pattern density. The formation method of the spacer 20 is, for example, to first form the spacer material layer 19 on the hard mask layer 16 and the top surface and side walls of the core layer 18, as shown in FIGS. 2B to 5B. Then, an anisotropic etching process is performed on the spacer material layer 19 to remove part of the spacer material layer 19 until the hard mask layer 16 and the top surface of the core layer 18 are exposed to form a layer on the sidewall of the core layer 18 Spacer 20. After that, using the spacers 20 and the core layer 18 as masks, etching is continued to remove the hard mask layer 16 that is not covered by the spacers 20 and the core layer 18, so that the array area R1, the transition area R2 and the winding area R3 forms hard mask patterns 16a, 16b, and 16c respectively. During the etching process of the hard mask layer 16, the core layer 18 will also be etched away, exposing part of the top surface of the hard mask patterns 16a, 16b, and 16c, as shown in FIGS. 2C to 5C. The hard mask pattern 16a extends in the direction D1; the hard mask patterns 16b, 16c extend in the direction D2. The hard mask pattern 16b is connected to the hard mask pattern 16a and separated from the hard mask pattern 16c.

請參照圖2D至圖5D以及請參照圖2E至圖5E，進行間隙壁20切分製程（cutting process），以形成彼此分離的間隙壁20a、20b、20c。間隙壁20切分製程說明如下。Please refer to FIGS. 2D to 5D and please refer to FIGS. 2E to 5E to perform a cutting process on the spacers 20 to form spacers 20a, 20b, and 20c that are separated from each other. The process of dividing the spacer 20 is explained as follows.

首先，請參照圖2D至圖5D，在犧牲層14上形成罩幕層22。罩幕層22例如是圖案化的光阻層。罩幕層22包括罩幕圖案22a、22b、22c。罩幕圖案22a局部覆蓋陣列區R1；罩幕圖案22b覆蓋部分的繞線區R3與過渡區R2；罩幕圖案22c覆蓋另一部分的繞線區R3與過渡區R2。罩幕圖案22a、22b、22c彼此分離。罩幕圖案22a與22b之間以及罩幕圖案22a與22c之間裸露出位於陣列區R1的末端以及位於過渡區R2的一邊（靠近陣列區R1）的間隙壁20、硬罩幕圖案16a、16b以及犧牲層14。罩幕圖案22b與22c之間裸露出位於繞線區R3之中以及位於過渡區R2另一邊（遠離陣列區R1）的間隙壁20、硬罩幕圖案16c、16b以及犧牲層14。First, please refer to FIG. 2D to FIG. 5D to form the mask layer 22 on the sacrificial layer 14 . The mask layer 22 is, for example, a patterned photoresist layer. Mask layer 22 includes mask patterns 22a, 22b, 22c. The mask pattern 22a partially covers the array area R1; the mask pattern 22b covers part of the winding area R3 and the transition area R2; and the mask pattern 22c covers another part of the winding area R3 and the transition area R2. The mask patterns 22a, 22b, and 22c are separated from each other. Between the mask patterns 22a and 22b and between the mask patterns 22a and 22c, the spacer 20 and the hard mask patterns 16a and 16b located at the end of the array area R1 and at one side of the transition area R2 (near the array area R1) are exposed. and sacrificial layer 14. The spacers 20 located in the winding region R3 and on the other side of the transition region R2 (away from the array region R1), the hard mask patterns 16c, 16b and the sacrificial layer 14 are exposed between the mask patterns 22b and 22c.

請參照圖2E至圖5E，進行蝕刻製程，例如是非等向性蝕刻製程，移除未被罩幕圖案22a、22b、22c覆蓋的間隙壁20，以形成間隙壁20a、20b、20c。之後，將罩幕圖案22a、22b、22c移除。間隙壁20a彼此分離位於陣列區R1中，且其各自在方向D1上的長度小於陣列區R1中未被硬罩幕圖案16a覆蓋的犧牲層14的長度。間隙壁20b位於過渡區R2中，在方向D2延伸且在方向D2彼此分離排列。間隙壁20c位於繞線區R3中，在方向D2延伸且在方向D2彼此分離排列。Referring to FIGS. 2E to 5E , an etching process, such as an anisotropic etching process, is performed to remove the spacers 20 that are not covered by the mask patterns 22a, 22b, and 22c to form the spacers 20a, 20b, and 20c. Afterwards, the mask patterns 22a, 22b, 22c are removed. The spacers 20a are separated from each other in the array region R1, and their respective lengths in the direction D1 are less than the length of the sacrificial layer 14 not covered by the hard mask pattern 16a in the array region R1. The spacers 20b are located in the transition region R2, extend in the direction D2, and are arranged apart from each other in the direction D2. The spacers 20c are located in the winding region R3, extend in the direction D2, and are arranged apart from each other in the direction D2.

請參照圖2F至圖5H，進行目標層12的圖案化製程，以形成目標圖案12a、12b、12c。目標層12的圖案化製程說明如下。在目標層12是藉由圖2G所示的硬罩幕層16’做為蝕刻罩幕，而硬罩幕層16’的形成方法可參照圖2F至圖5G說明如下。Please refer to FIGS. 2F to 5H to perform a patterning process on the target layer 12 to form target patterns 12a, 12b, and 12c. The patterning process of the target layer 12 is described below. On the target layer 12, a hard mask layer 16' shown in Figure 2G is used as an etching mask, and the formation method of the hard mask layer 16' can be described as follows with reference to Figures 2F to 5G.

請參照圖2F至圖5G，在基底10上形成罩幕層24。罩幕層24例如是圖案化的光阻層。罩幕層24具有開口OP1與OP2。開口OP1裸露出在陣列區R1中的間隙壁20a、硬罩幕圖案16a與犧牲層14。開口OP2在方向D1以及D2延伸。開口OP2的形狀例如是由多個十字所組成的雙排梳狀。開口OP2在方向D1裸露出在繞線區R3中的硬罩幕圖案16c與犧牲層14。開口OP2在方向D2裸露出在繞線區R3中的硬罩幕圖案16c。Referring to FIGS. 2F to 5G , a mask layer 24 is formed on the substrate 10 . The mask layer 24 is, for example, a patterned photoresist layer. The mask layer 24 has openings OP1 and OP2. The opening OP1 exposes the spacer 20a, the hard mask pattern 16a and the sacrificial layer 14 in the array region R1. The opening OP2 extends in the directions D1 and D2. The shape of the opening OP2 is, for example, a double-row comb shape composed of a plurality of crosses. The opening OP2 exposes the hard mask pattern 16c and the sacrificial layer 14 in the winding region R3 in the direction D1. The opening OP2 exposes the hard mask pattern 16c in the winding area R3 in the direction D2.

請參照圖2G至圖5G，以罩幕層24以及間隙壁20a為罩幕，將硬罩幕圖案16a、16b與16c圖案化為硬罩幕層16’。硬罩幕層16’包括硬罩幕圖案16a’、16b’、16c’。硬罩幕圖案16a’覆蓋陣列區R1；硬罩幕圖案16b’覆蓋過渡區R2並延伸到陣列區R1；硬罩幕圖案16c’覆蓋繞線區R3。Referring to FIGS. 2G to 5G , the mask layer 24 and the spacer 20a are used as masks, and the hard mask patterns 16a, 16b and 16c are patterned into the hard mask layer 16'. The hard mask layer 16' includes hard mask patterns 16a', 16b', 16c'. The hard mask pattern 16a' covers the array area R1; the hard mask pattern 16b' covers the transition area R2 and extends to the array area R1; the hard mask pattern 16c' covers the winding area R3.

硬罩幕圖案16b’又可稱為虛設圖案。硬罩幕圖案16b’例如是呈梳狀。硬罩幕圖案16b’包括主體部mp與多個延伸部ep。主體部mp為實心塊狀體，其沿著方向D2延伸，位於過渡區R2中，且以非零距離d2’與硬罩幕圖案16c’相鄰。多個延伸部ep沿著方向D1延伸，沿著方向D2排列，位於陣列區R1中。多個延伸部ep與主體部mp連接，且以非零距離d1’與硬罩幕圖案16a’相鄰。主體部mp的寬度W ₃’大於每一延伸部ep部的寬度W ₂’，且每一延伸部ep的寬度W ₂’大於每一硬罩幕圖案16a’的寬度W ₁’。依據製程的能力控制硬罩幕圖案16b’與硬罩幕圖案16a’之間的距離d1’，以降低後續蝕刻製程的負載效應。例如將距離d1’控制在小於114nm，例如是30nm至114nm之間。 The hard mask pattern 16b' can also be called a dummy pattern. The hard mask pattern 16b' is, for example, comb-shaped. The hard mask pattern 16b' includes a main body part mp and a plurality of extension parts ep. The main body part mp is a solid block, which extends along the direction D2, is located in the transition area R2, and is adjacent to the hard mask pattern 16c' at a non-zero distance d2'. The plurality of extending portions ep extend along the direction D1, are arranged along the direction D2, and are located in the array region R1. The plurality of extension parts ep are connected to the main body part mp, and are adjacent to the hard mask pattern 16a' at a non-zero distance d1'. The width W ₃ ′ of the main body portion mp is greater than the width W ₂ ′ of each extension portion ep, and the width W ₂ ′ of each extension portion ep is greater than the width W ₁ ′ of each hard mask pattern 16 a ′. The distance d1' between the hard mask pattern 16b' and the hard mask pattern 16a' is controlled according to the process capability to reduce the load effect of the subsequent etching process. For example, the distance d1' is controlled to be less than 114 nm, for example, between 30 nm and 114 nm.

請參照圖2H至圖5H，以硬罩幕層16’為罩幕，進行蝕刻製程，其可以是非等向性蝕刻製程，例如是反應性離子蝕刻（RIE）製程，以將犧牲層14以及目標層12圖案化，進而形成圖案化的氧化物層以及目標圖案12a、12b、12c。之後再移除罩幕層24以及間隙壁20a。由於硬罩幕圖案16b’與硬罩幕圖案16a’的距離d1’控制在適當的範圍，且為具有實心的塊狀體，因此，在進行蝕刻的過程中可以降低陣列區的R1的中心區與末端區之間的負載效應，使得中心區與末端區之間的目標圖案12a具有相似的輪廓。Referring to FIGS. 2H to 5H , the hard mask layer 16 ′ is used as a mask to perform an etching process, which may be an anisotropic etching process, such as a reactive ion etching (RIE) process, to separate the sacrificial layer 14 and the target. Layer 12 is patterned to form a patterned oxide layer and target patterns 12a, 12b, 12c. Then, the mask layer 24 and the spacer 20a are removed. Since the distance d1' between the hard mask pattern 16b' and the hard mask pattern 16a' is controlled within an appropriate range and is a solid block, the central area of R1 in the array area can be reduced during the etching process. The load effect between the central area and the end area causes the target pattern 12a between the central area and the end area to have a similar profile.

目標圖案12a可以包括多個目標圖案12a ₁。多個目標圖案12a ₁位於陣列區R1中，沿著方向D1延伸，沿著方向D2排列。 The target pattern 12a may include a plurality of target patterns 12a ₁ . The plurality of target patterns 12a ₁ are located in the array region R1, extend along the direction D1, and are arranged along the direction D2.

多個目標圖案12c位於繞線區R3中。多個目標圖案12c包括多個目標圖案12c ₀與12c ₁，其分別沿著方向D2延伸。多個目標圖案12c ₀及12c ₁皆沿著方向D2延伸，沿著方向D1排列。目標圖案12c ₀與目標圖案12c ₁彼此分離，且沿著方向D2排列成一行。目標圖案12c的寬度例如是目標圖案12a ₁的寬度W ₁的4倍至6倍。 The plurality of target patterns 12c are located in the winding area R3. The plurality of target patterns 12c include a plurality of target patterns 12c ₀ and 12c ₁ , which respectively extend along the direction D2. The plurality of target patterns 12c ₀ and 12c ₁ both extend along the direction D2 and are arranged along the direction D1. The target pattern 12c ₀ and the target pattern 12c ₁ are separated from each other and arranged in a line along the direction D2. The width of the target pattern 12c is, for example, 4 to 6 times the width W ₁ of the target pattern 12a ₁ .

目標圖案12b位於多個目標圖案12a ₁與多個目標圖案12c之間。目標圖案12b又稱為虛設結構，例如是呈梳狀。目標圖案12b包括主體部MP與多個延伸部EP。主體部MP為實心塊狀體，其沿著方向D2延伸，位於過渡區R2中，且以非零距離與目標圖案12c相鄰。多個延伸部EP沿著方向D1延伸，沿著方向D2排列，位於陣列區R1中。多個延伸部EP與主體部MP連接，且以非零距離d1與目標圖案12a ₁相鄰，且以非零距離d2與目標圖案12c相鄰。延伸部EP與目標圖案12a ₁之間的距離d1小於114nm，例如是30nm至114nm之間。 The target pattern 12b is located between the plurality of target patterns 12a ₁ and the plurality of target patterns 12c. The target pattern 12b is also called a dummy structure, and is, for example, in the shape of a comb. The target pattern 12b includes a main body part MP and a plurality of extension parts EP. The main body MP is a solid block, which extends along the direction D2, is located in the transition region R2, and is adjacent to the target pattern 12c at a non-zero distance. The plurality of extension parts EP extend along the direction D1, are arranged along the direction D2, and are located in the array region R1. The plurality of extension parts EP are connected to the main body part MP, are adjacent to the target pattern 12a ₁ at a non-zero distance d1, and are adjacent to the target pattern 12c at a non-zero distance d2. The distance d1 between the extension part EP and the target pattern 12a ₁ is less than 114 nm, for example, between 30 nm and 114 nm.

延伸部EP的寬度W ₂大於2倍的目標圖案的寬度W ₁，例如是目標圖案的寬度W ₁的2.5倍至3.5倍。主體部MP的寬度W ₃大於延伸部EP的寬度W ₂，例如是目標圖案12a ₁的寬度W ₁的4倍至9倍。 The width W ₂ of the extension portion EP is greater than 2 times the width W ₁ of the target pattern, for example, 2.5 to 3.5 times the width W ₁ of the target pattern. The width W ₃ of the main body part MP is larger than the width W ₂ of the extension part EP, for example, 4 to 9 times the width W ₁ of the target pattern 12a ₁ .

請參照圖1B，目標圖案12a還可以包括多個目標圖案12a ₁₀、12a ₁₁。目標圖案12a ₁₀、12a ₁₁位於目標圖案12a ₁的兩側。目標圖案12a ₁₀、12a ₁₁位於陣列區R1中，沿著方向D1延伸，沿著方向D2排列。目標圖案12a ₁₀、12a ₁₁的寬度例如是目標圖案12a ₁的寬度W ₁的4倍至6倍。 Please refer to FIG. 1B , the target pattern 12a may also include multiple target patterns 12a ₁₀ , 12a ₁₁ . The target patterns 12a ₁₀ and 12a ₁₁ are located on both sides of the target pattern 12a ₁ . The target patterns 12a ₁₀ and 12a ₁₁ are located in the array region R1, extend along the direction D1, and are arranged along the direction D2. The widths of the target patterns 12a ₁₀ and 12a ₁₁ are, for example, 4 to 6 times the width W ₁ of the target pattern 12a ₁ .

請參照圖1A與圖1B，在一些實施例中，目標圖案12a ₁為包括字元線WL ₁的圖案化的堆疊層110a（如圖5H的局部放大圖所示）。圖案化的堆疊層110a包括穿隧介電層102、圖案化的浮置閘極層104a、閘間介電層106a、控制閘極層108、金屬層112a以及頂蓋層114a。在另一些實施例中，穿隧介電層102也可以被圖案化。圖案化的堆疊層110a的高寬比例如是10至12。目標圖案12a ₁₀、12a ₁₁分別為包括選擇線SG ₁₀與SG ₁₁的圖案化的堆疊層。目標圖案12c ₀、12c ₁分別為包括做為字元線WL ₀的著陸墊LP ₀₁以及字元線WL ₂的著陸墊LP ₂₀的圖案化的堆疊層。目標圖案12b為包括虛設結構DS ₁的圖案化的堆疊層。 Referring to FIGS. 1A and 1B , in some embodiments, the target pattern 12a ₁ is a patterned stacked layer 110a including a word line WL ₁ (as shown in the partial enlarged view of FIG. 5H ). The patterned stack layer 110a includes a tunnel dielectric layer 102, a patterned floating gate layer 104a, an inter-gate dielectric layer 106a, a control gate layer 108, a metal layer 112a, and a capping layer 114a. In other embodiments, the tunnel dielectric layer 102 may also be patterned. The aspect ratio of the patterned stacked layer 110a is, for example, 10 to 12. The target patterns 12a ₁₀ and 12a ₁₁ are patterned stacked layers including the selection lines SG ₁₀ and SG ₁₁ respectively. The target patterns 12c ₀ and 12c ₁ are patterned stacked layers including the landing pad LP ₀₁ as the word line WL ₀ and the landing pad LP ₂₀ as the word line WL ₂ respectively. The target pattern 12b is a patterned stacked layer including the dummy structure _DS1 .

雖然上述實施例是以快閃記憶體為例來說明一系列的圖案化的步驟，但本發明不以此為限。在其他實施例中，此圖案化的步驟亦可用以形成動態隨機存取記憶體（DRAM）或類似的目標層/膜。Although the above embodiments take a flash memory as an example to illustrate a series of patterning steps, the invention is not limited thereto. In other embodiments, this patterning step can also be used to form dynamic random access memory (DRAM) or similar target layers/films.

綜上所述，本發明實施例藉由設置用來形成虛設結構DS的硬罩幕圖案（又稱為虛設圖案）可以在形成字元線以及著陸墊的蝕刻過程中改善負載效應，使得陣列區的中心與末端具有相似的輪廓，避免發生橋接或是缺陷。而且在此情況下，陣列區與繞線區中的目標層可被同時圖案化，進而在陣列區與繞線區中形成不同圖案密度的多個堆疊結構。In summary, embodiments of the present invention can improve the loading effect during the etching process of forming word lines and landing pads by arranging hard mask patterns (also called dummy patterns) used to form dummy structures DS, so that the array area The center and ends have similar contours to avoid bridging or defects. Moreover, in this case, the target layers in the array area and the winding area can be patterned simultaneously, thereby forming multiple stacked structures with different pattern densities in the array area and the winding area.

10:基底 12:目標層 12a、12a1、12a10、12a11、12b、12c、12c0、12c1:目標圖案 14:犧牲層 16、16’:硬罩幕層 16a、16a’、16b、16b’、16c、16c’:硬罩幕圖案 18:核心層 18a、18b、18c:核心圖案 19:間隙壁材料層 20、20a、20b、20c:間隙壁 22、24:罩幕層 22a、22b、22c:罩幕圖案 50:區域 100:記憶元件 102:穿隧介電層 104、104a:浮置閘極層 106、106a:閘間介電層 108、108a:控制閘極層 110、110a:堆疊層 112、112a:金屬層 114、114a:頂蓋層 A0、A1、A2、A3:區塊 D1、D2、D3:方向 DS、DS ₁、DS ₃:虛設結構 E ₀₀、E ₁₀、E ₂₀、E ₃₀:末端 ep、EP:延伸部 L:長度 LP、LP ₀₁、LP ₂₀、LP ₂₁:著陸墊 mp、MP:主體部 OP1、OP2:開口 R1:陣列區 R2:過渡區 R3:繞線區 SG、SG ₀₁、SG ₁₀、SG ₁₁、SG ₂₀、SG ₂₁、SG ₃₀、SG ₃₁:選擇閘 W ₁、W ₁’、W ₂、W ₂’、W ₃、W ₃’:寬度 WL、WL ₀、WL ₁、WL ₂、WL ₃:字元線 d1、d1’、d2、d2’、d3:距離 III-III、IV-IV、V-V:線 10: Base 12: Target layer 12a, 12a1, 12a10, 12a11, 12b, 12c, 12c0, 12c1: Target pattern 14: Sacrificial layer 16, 16': Hard mask layer 16a, 16a', 16b, 16b', 16c, 16c': Hard mask pattern 18: Core layer 18a, 18b, 18c: Core pattern 19: Spacer material layer 20, 20a, 20b, 20c: Spacer 22, 24: Mask layer 22a, 22b, 22c: Mask Pattern 50: Region 100: Memory element 102: Tunnel dielectric layer 104, 104a: Floating gate layer 106, 106a: Intergate dielectric layer 108, 108a: Control gate layer 110, 110a: Stacked layer 112, 112a :Metal layers 114, 114a: Top cover layers A0, A1, A2, A3: Blocks D1, D2, D3: Directions DS, DS ₁ , DS ₃ : Dummy structures E ₀₀ , E ₁₀ , E ₂₀ , E ₃₀ : Ends ep, EP: extension part L: length LP, LP ₀₁ , LP ₂₀ , LP ₂₁ : landing pad mp, MP: main part OP1, OP2: opening R1: array area R2: transition area R3: winding area SG, SG ₀₁ , SG ₁₀ , SG ₁₁ , SG ₂₀ , SG ₂₁ , SG ₃₀ , SG ₃₁ : selection gate W ₁ , W ₁ ', W ₂ , W ₂ ', W ₃ , W ₃ ': width WL, WL ₀ , WL ₁ , WL ₂ , WL ₃ : character line d1, d1', d2, d2', d3: distance III-III, IV-IV, VV: line

圖1A是本發明一實施例的記憶元件的上視圖。 圖1B是圖1A的區域50的局部放大圖。 圖2A至圖2H是本發明一實施例的記憶元件的製造方法的上視圖。 圖3A至圖3H是圖2A至圖2H的線III-III的剖面圖。 圖4A至圖4H是圖2A至圖2H的線IV-IV的剖面圖。 圖5A至圖5H是圖2A至圖2H的線V-V的剖面圖。 FIG. 1A is a top view of a memory element according to an embodiment of the present invention. FIG. 1B is a partial enlarged view of the area 50 of FIG. 1A. 2A to 2H are top views of a method of manufacturing a memory element according to an embodiment of the present invention. 3A to 3H are cross-sectional views along line III-III of FIGS. 2A to 2H. 4A to 4H are cross-sectional views taken along line IV-IV of FIGS. 2A to 2H. 5A to 5H are cross-sectional views along line V-V of FIGS. 2A to 2H.

10:基底 10: Base

50:區域 50:Area

100:記憶元件 100:Memory component

A0、A1、A2、A3:區塊 A0, A1, A2, A3: block

D1、D2:方向 D1, D2: direction

DS、DS₁、DS₃:虛設結構 DS, DS ₁ , DS ₃ : dummy structure

E₀₀、E₁₀、E₂₀、E₃₀:末端 E ₀₀ , E ₁₀ , E ₂₀ , E ₃₀ : end

EP:延伸部 EP:Extension

LP、LP₀₁、LP₂₀、LP₂₁:著陸墊 LP, LP ₀₁ , LP ₂₀ , LP ₂₁ : landing pad

MP:主體部 MP: Main body

R1:陣列區 R1: array area

R2:過渡區 R2: Transition zone

R3:繞線區 R3: winding area

SG、SG₀₁、SG₁₀、SG₁₁、SG₂₀、SG₂₁、SG₃₀:選擇閘 SG, SG ₀₁ , SG ₁₀ , SG ₁₁ , SG ₂₀ , SG ₂₁ , SG ₃₀ : selection gate

WL、WL₀、WL₁、WL₂、WL₃:字元線 WL, WL ₀ , WL ₁ , WL ₂ , WL ₃ : word lines