TWI863373B - Receiver performing adaptive calibration - Google Patents
- ️Thu Nov 21 2024
TWI863373B - Receiver performing adaptive calibration - Google Patents
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Abstract
一種接收器包含一通道補償器、一解碼器及一適應性控制器。該通道補償器對一輸入資料信號進行通道補償以產生一饋入資料信號。該解碼器將源自該饋入資料信號的一待解碼資料信號解多工成多個解多工資料信號，並將該等解多工資料信號分別解碼成多個解碼信號。該適應性控制器根據該解碼輸出產生一輸出資料信號，並參考該等解碼信號的一第一樣本的誤差部分和在該等解碼信號的該第一樣本產生之前產生的該等解碼信號的一第二樣本的資料部分對該通道補償器執行適應性校準，以調整該通道補償器的增益。A receiver includes a channel compensator, a decoder and an adaptive controller. The channel compensator performs channel compensation on an input data signal to generate a feed data signal. The decoder demultiplexes a data signal to be decoded from the feed data signal into a plurality of demultiplexed data signals, and decodes the demultiplexed data signals into a plurality of decoded signals respectively. The adaptive controller generates an output data signal according to the decoded output, and performs adaptive calibration on the channel compensator with reference to an error portion of a first sample of the decoded signals and a data portion of a second sample of the decoded signals generated before the first sample of the decoded signals is generated, so as to adjust the gain of the channel compensator.
Description
本發明是有關於一種接收器，特別是指一種執行適應性校正的接收器。The present invention relates to a receiver, and more particularly to a receiver for performing adaptive calibration.
串行器/解串器（Serializer/Deserializer，SerDes）功能廣泛應用於通信標準（例如，乙太網、PCIe（Peripheral Component Interconnect express）、通用序列匯流排（Universal Serial Bus，USB）等）和超短距離傳輸（eXtra-Short Reach，XSR）應用（例如，封裝至封裝計算晶片、光通訊晶片等）。一個用於將串列輸入資料轉換為並列輸出資料的接收器能夠處理通道損失（Channel Loss）以及製程、電壓和溫度（PVT）變化，以便操作更穩定並達到更高的良率是至關重要的。The Serializer/Deserializer (SerDes) function is widely used in communication standards (e.g., Ethernet, PCIe (Peripheral Component Interconnect express), Universal Serial Bus (USB), etc.) and eXtra-Short Reach (XSR) applications (e.g., package-to-package computing chips, optical communication chips, etc.). It is critical that a receiver that converts serial input data to parallel output data can handle channel loss and process, voltage and temperature (PVT) variations in order to operate more stably and achieve higher yields.
因此，本發明之目的，即在提供一種能夠處理通道損失以及製程、電壓和溫度變化中至少一者的接收器。Therefore, an object of the present invention is to provide a receiver capable of handling channel loss and at least one of process, voltage and temperature variations.
根據本發明的一方面，該接收器包含一通道補償器、一解碼器及一適應性控制器。該通道補償器接收一輸入資料信號，並對該輸入資料信號進行通道補償以產生一饋入資料信號。該通道補償器的增益是可調整的。該解碼器連接該通道補償器以接收該饋入資料信號，將源自該饋入資料信號的一待解碼資料信號解多工成數量P的解多工資料信號，並將該等解多工資料信號分別解碼成數量P的解碼信號，其中 。該等解碼信號中的每一者包含多個樣本，該等解碼信號的該等樣本是依序產生的。該等解碼信號的每一樣本包含一資料部分，且該等解碼信號其中至少一者的每一樣本還包含一誤差部分。該適應性控制器連接該解碼器以接收源自該等解碼信號的一解碼輸出，並且還連接該通道補償器。該適應性控制器根據該解碼輸出產生一輸出資料信號，並參考該等解碼信號的一第一樣本的誤差部分和在該等解碼信號的該第一樣本產生之前產生的該等解碼信號的一第二樣本的資料部分對該通道補償器執行適應性校準，以調整該通道補償器的增益。 According to one aspect of the present invention, the receiver includes a channel compensator, a decoder and an adaptive controller. The channel compensator receives an input data signal and performs channel compensation on the input data signal to generate a feed data signal. The gain of the channel compensator is adjustable. The decoder is connected to the channel compensator to receive the feed data signal, demultiplexes a data signal to be decoded from the feed data signal into a number P of demultiplexed data signals, and decodes the demultiplexed data signals into a number P of decoded signals, wherein . Each of the decoded signals includes a plurality of samples, and the samples of the decoded signals are generated sequentially. Each sample of the decoded signals includes a data portion, and each sample of at least one of the decoded signals also includes an error portion. The adaptive controller is connected to the decoder to receive a decoded output from the decoded signals, and is also connected to the channel compensator. The adaptive controller generates an output data signal based on the decoded output, and performs adaptive calibration on the channel compensator with reference to the error portion of a first sample of the decoded signals and the data portion of a second sample of the decoded signals generated before the first sample of the decoded signals is generated, so as to adjust the gain of the channel compensator.
根據本發明的另一方面，該接收器包含一電壓調節器、一解碼器及一適應性控制器。該電壓調節器產生一具有可調大小的參考電壓。該解碼器連接該電壓調節器以接收該參考電壓，將一待解碼資料信號解多工成數量P的解多工資料信號，並根據該參考電壓將該等解多工資料信號分別解碼成數量P的解碼信號，其中P≥2。該等解碼信號中的每一者包含多個樣本，該等解碼信號的該等樣本是依序產生的。該等解碼信號的每一樣本包含一資料部分，且該等解碼信號其中至少一者的每一樣本還包含一誤差部分。該適應性控制器，連接該解碼器以接收源自該等解碼信號的解碼輸出，並且連接該電壓調節器。該適應性控制器根據該解碼輸出產生一輸出資料信號，並參考該等解碼信號的一樣本的誤差部分和資料部分，對該電壓調節器執行適應性校準，以調整該參考電壓的大小。According to another aspect of the present invention, the receiver includes a voltage regulator, a decoder and an adaptive controller. The voltage regulator generates a reference voltage with an adjustable size. The decoder is connected to the voltage regulator to receive the reference voltage, demultiplexes a data signal to be decoded into a number P of demultiplexed data signals, and decodes the demultiplexed data signals into a number P of decoded signals according to the reference voltage, where P≥2. Each of the decoded signals includes a plurality of samples, and the samples of the decoded signals are generated sequentially. Each sample of the decoded signals includes a data portion, and each sample of at least one of the decoded signals also includes an error portion. The adaptive controller is connected to the decoder to receive the decoded output from the decoded signals and is connected to the voltage regulator. The adaptive controller generates an output data signal according to the decoded output and performs adaptive calibration on the voltage regulator with reference to the error part and the data part of a sample of the decoded signals to adjust the magnitude of the reference voltage.
根據本發明的又一方面，該接收器包含一相位內插器、一解碼器裝置及一適應性控制器。該相位內插器接收一時脈輸入，並對該時脈輸入執行相位內插以數量N的內插時脈信號，其中 並且每個內差時脈信號的一相對於該時脈輸入的相移是可調整的。該解碼器裝置包括數量N的解碼器。每一解碼器連接該相位內插器以接收該等內插時脈信號中的一對應者並且延遲該對應內插時脈信號以產生一相對於該對應內插時脈信號的延遲是可調整的校正時脈信號。該等解碼器相互配合以接收一饋入資料信號，並根據由該等解碼器所產生的該等校正時脈信號將該饋入資料信號解多工成數量N的分別由該等解碼器所提供的第一解多工資料信號。每一解碼器緩衝自身所提供的該第一解多工資料信號以產生一待解碼資料信號、將該待解碼資料信號解多工成數量P的第二解多工資料信號並將該等第二解多工資料信號分別解碼成數量P的解碼信號，其中 、每一解碼信號包含多個樣本、該等解碼信號的樣本是依序產生的、該等解碼信號的每一樣本包含一資料部分且該等解碼信號其中至少一者的每一樣本還包含一誤差部分。該適應性控制器連接該解碼器裝置以接收源自由該等解碼器所產生的該等解碼信號的解碼輸出，並且還連接該相位內插器。該適應性控制器連接該解碼器裝置以接收源自由該等解碼器所產生的該等解碼信號的解碼輸出，並且還連接該相位內插器。該適應性控制器根據該解碼輸出產生一輸出資料信號，並對該相位內插器及該等解碼器執行適應性校準，以調整該等內插時脈信號的相移以及該等校正時脈信號的延遲。 According to another aspect of the present invention, the receiver includes a phase interpolator, a decoder device and an adaptive controller. The phase interpolator receives a clock input and performs phase interpolation on the clock input to obtain an interpolated clock signal of number N, wherein The decoder device includes a decoder having a phase shift relative to the clock input of each interpolated clock signal and a phase shift relative to the clock input of each interpolated clock signal. Each decoder is connected to the phase interpolator to receive a corresponding one of the interpolated clock signals and delay the corresponding interpolated clock signal to generate a correction clock signal whose delay relative to the corresponding interpolated clock signal is adjustable. The decoders cooperate with each other to receive a feed data signal and demultiplex the feed data signal into a first demultiplexed data signal of N number provided by the decoders respectively according to the correction clock signals generated by the decoders. Each decoder buffers the first demultiplexed data signal provided by itself to generate a data signal to be decoded, demultiplexes the data signal to be decoded into a number P of second demultiplexed data signals, and decodes the second demultiplexed data signals into a number P of decoded signals, respectively, wherein , each decoded signal includes a plurality of samples, the samples of the decoded signals are generated sequentially, each sample of the decoded signals includes a data portion and each sample of at least one of the decoded signals also includes an error portion. The adaptive controller is connected to the decoder device to receive a decoded output of the decoded signals generated by the decoders, and is also connected to the phase interpolator. The adaptive controller is connected to the decoder device to receive a decoded output of the decoded signals generated by the decoders, and is also connected to the phase interpolator. The adaptive controller generates an output data signal based on the decoded output, and performs adaptive calibration on the phase interpolator and the decoders to adjust the phase shift of the interpolated clock signals and the delay of the correction clock signals.
在本發明被詳細描述之前，應當注意在合適的情況下，參考編號或是參考編號的末端部分在圖式間重複以指示對應的或類似的元件，這些元件可以可選地具有類似的特徵。Before the present invention is described in detail, it should be noted that, where appropriate, reference numerals or the terminal parts of reference numerals are repeated among the drawings to indicate corresponding or similar elements, which elements may optionally have similar features.
參閱圖1及圖2，根據本發明實施例的一種接收器，適用於將串行輸入資料轉換為並行輸出資料，並包括一通道補償器11、一電壓調節器12、一多相濾波器13、一電流模式邏輯（Current Mode Logic，以下簡稱CML）至互補式金屬氧化物半導體（Complementary Metal Oxide Semiconductor，以下簡稱CMOS）轉換器14、一相位內插器15、一解碼器裝置16及一適應性控制器17。1 and 2 , a receiver according to an embodiment of the present invention is suitable for converting serial input data into parallel output data, and includes a channel compensator 11, a voltage regulator 12, a multi-phase filter 13, a current mode logic (CML) to complementary metal oxide semiconductor (CMOS) converter 14, a phase interpolator 15, a decoder device 16 and an adaptive controller 17.
該通道補償器11接收一以脈波振幅調變（Pulse-amplitude modulation，以下簡稱PAM）-2 M格式的輸入資料信號Din，並對該輸入資料信號Din進行通道補償，以產生一以PAM-2 M格式的饋入資料信號，其中M 2並且該通道補償器11的增益是可調整的。為了說明，在本實施例中，該輸入資料信號Din及該饋入資料信號均是PAM-4格式（即，M＝2），並且具有112 Gbps的資料率（即，56 Gbaud） The channel compensator 11 receives an input data signal Din in a pulse amplitude modulation (PAM)-2 M format and performs channel compensation on the input data signal Din to generate a feed data signal in a PAM-2 M format, wherein M 2 and the gain of the channel compensator 11 is adjustable. For illustration, in this embodiment, the input data signal Din and the feed data signal are both in PAM-4 format (ie, M=2) and have a data rate of 112 Gbps (ie, 56 Gbaud).
在本實施例中，該通道補償器11包括一等化器裝置111及一可變增益放大器（Variable Gain Amplifier，VGA）112。該等化器裝置111包括一連續時間線性等化器（Continuous Time Linear Equalizer，CTLE）116及一低頻等化器（Low Frequency Equalizer，LFEQ）117。該輸入資料信號Din的多個高頻成分由該連續時間線性等化器116來補償，該輸入資料信號（Din）的中頻和低頻成分由該低頻等化器117來補償，並由上述補償所導致的信號在脈波振幅上是由該可變增益放大器112來調整，以便產生該饋入資料信號。可以調整該連續時間線性等化器116和該低頻等化器117的多個參數來改變該通道補償器11的增益。In this embodiment, the channel compensator 11 includes an equalizer device 111 and a variable gain amplifier (VGA) 112. The equalizer device 111 includes a continuous time linear equalizer (CTLE) 116 and a low frequency equalizer (LFEQ) 117. Multiple high frequency components of the input data signal Din are compensated by the continuous time linear equalizer 116, and the intermediate frequency and low frequency components of the input data signal (Din) are compensated by the low frequency equalizer 117. The signal caused by the above compensation is adjusted in pulse amplitude by the variable gain amplifier 112 to generate the feed data signal. The gain of the channel compensator 11 can be changed by adjusting the parameters of the continuous time linear equalizer 116 and the low frequency equalizer 117.
該電壓調節器12生成一具有可調大小的參考電壓。The voltage regulator 12 generates a reference voltage with an adjustable magnitude.
該多相濾波器13接收一CML準位的差動輸入時脈信號對CKin，並將該差動輸入時脈信號對CKin分成兩個CML準位的且相位差呈90°的差動第一時脈信號對。為了說明，在本實施例中，該差動輸入時脈信號對CKin的頻率為14GHz。The polyphase filter 13 receives a CML-level differential input clock signal pair CKin and divides the differential input clock signal pair CKin into two CML-level differential first clock signal pairs with a phase difference of 90°. For illustration, in this embodiment, the frequency of the differential input clock signal pair CKin is 14 GHz.
該CML至CMOS轉換器14連接該多相濾波器13以接收該等差動第一時脈信號對，並將該等差動第一時脈信號對分別轉換成兩個CMOS準位的差動第二時脈信號對。The CML to CMOS converter 14 is connected to the polyphase filter 13 to receive the differential first clock signal pairs and convert the differential first clock signal pairs into two differential second clock signal pairs of CMOS levels respectively.
該相位內插器15與該適應性控制器17的一些組件配合構成一時脈資料恢復（Clock Data Recovery，CDR）電路。該相位內插器15連接該CML至CMOS轉換器14以接收共同構成一時脈輸入的該等差動第二時脈信號對，並對該時脈輸入進行相位內插以產生數量N的內插時脈信號，其中 。每一內插時脈信號相對於該時脈輸入的相移是可調整的。為了說明，在本實施例中，產生了四個內插時脈信號（即，N=4）。 The phase interpolator 15 cooperates with some components of the adaptive controller 17 to form a clock data recovery (CDR) circuit. The phase interpolator 15 is connected to the CML to CMOS converter 14 to receive the differential second clock signal pairs that together form a clock input, and performs phase interpolation on the clock input to generate N number of interpolated clock signals, wherein The phase shift of each interpolated clock signal relative to the clock input is adjustable. For illustration, in this embodiment, four interpolated clock signals are generated (ie, N=4).
該解碼器裝置16包括數量N的解碼器160（即，在本實施例中有四個解碼器160）。在本實施例中，每一解碼器160包括一時脈校正器161、一環形計數器162、一1/Q分頻器163、一第一解多工器164、一緩衝器165、一第二解多工器166、數量P的類比數位轉換器（Analog to Digital Converter，以下簡稱ADC）167、一相位校準電路168及一1對Q解多工器169，其中 並且 。為了說明，在本實施例中，使用了一1/2分頻器作為該1/Q分頻器163，四個類比數位轉換器167及一1:2解多工器作為該1對Q解多工器169（即，P=4且Q=2）。 The decoder device 16 includes a number N of decoders 160 (i.e., there are four decoders 160 in this embodiment). In this embodiment, each decoder 160 includes a clock corrector 161, a ring counter 162, a 1/Q frequency divider 163, a first demultiplexer 164, a buffer 165, a second demultiplexer 166, a number P of analog to digital converters (ADCs) 167, a phase calibration circuit 168, and a 1-to-Q demultiplexer 169, wherein And For illustration, in the present embodiment, a 1/2 frequency divider is used as the 1/Q frequency divider 163, four analog-to-digital converters 167 and a 1:2 demultiplexer is used as the 1:Q demultiplexer 169 (ie, P=4 and Q=2).
對於每一解碼器160，該時脈校正器161連接該相位內插器15以接收一個對應的內插時脈信號，並且延遲該對應的內插時脈信號以產生一校正時脈信號。該校正時脈信號相對於該對應的內插時脈信號的延遲是可調整的。該第一解多工器164連接該時脈校正器161以接收該校正時脈信號，並且還連接該通道補償器11。For each decoder 160, the clock corrector 161 is connected to the phase interpolator 15 to receive a corresponding interpolated clock signal, and delays the corresponding interpolated clock signal to generate a corrected clock signal. The delay of the corrected clock signal relative to the corresponding interpolated clock signal is adjustable. The first demultiplexer 164 is connected to the clock corrector 161 to receive the corrected clock signal, and is also connected to the channel compensator 11.
該等解碼器160的該等第一解多工器164相互配合以接收來自該通道補償器11的該饋入資料信號，並根據該等解碼器160的該等時脈校正器161所產生的該等校正時脈信號，將該饋入資料信號解多工成數量N的分別由該等第一解多工器164輸出的第一解多工資料信號（即，在本實施例中有四個第一解多工資料信號）。在本實施例中，每一第一解多工資料信號的資料率為14 Gbaud。The first demultiplexers 164 of the decoders 160 cooperate with each other to receive the feed data signal from the channel compensator 11, and demultiplex the feed data signal into a number N of first demultiplexed data signals (i.e., there are four first demultiplexed data signals in this embodiment) outputted by the first demultiplexers 164 according to the correction clock signals generated by the clock correctors 161 of the decoders 160. In this embodiment, the data rate of each first demultiplexed data signal is 14 Gbaud.
應注意的是，對於每一校正時脈信號，藉由調整該校正時脈信號的延遲，可以改變該校正時脈信號與其他任意一校正時脈信號之間的時滯。It should be noted that for each calibration clock signal, the time lag between the calibration clock signal and any other calibration clock signal can be changed by adjusting the delay of the calibration clock signal.
在本實施例中，對於每一解碼器160，該第一解多工器164包括一取樣開關1641。該取樣開關1641具有一連接該通道補償器11以接收該饋入資料信號的第一端、一提供對應的第一解多工資料信號的第二端、及一連接該時脈校正器161以接收該校正時脈信號的控制端。該取樣開關1641根據該校正時脈信號在導通和非導通之間切換。當該取樣開關1641導通時，該饋入資料信號通過該取樣開關1641傳輸以作為對應的第一解多工資料信號。In this embodiment, for each decoder 160, the first demultiplexer 164 includes a sampling switch 1641. The sampling switch 1641 has a first end connected to the channel compensator 11 to receive the feed data signal, a second end providing a corresponding first demultiplexed data signal, and a control end connected to the clock corrector 161 to receive the correction clock signal. The sampling switch 1641 switches between conduction and non-conduction according to the correction clock signal. When the sampling switch 1641 is turned on, the feed data signal is transmitted through the sampling switch 1641 as the corresponding first demultiplexed data signal.
對於每一解碼器160，該環形計數器162連接該時脈校正器161以接收該校正時脈信號，並且基於該校正時脈信號產生一P位元寬（本實施例中例如4位元寬）的計數輸出。一預定邏輯值（例如，邏輯值“1”）以由該校正時脈信號定義的速度在該計數輸出的該等位元之間循環。該1/Q分頻器163（本實施例中例如為1/2分頻器163）連接該環形計數器162以接收該計數輸出，並基於該計數輸出產生一頻率為該計數輸出的頻率的1/Q（本實施例中例如為1/2）的第三時脈信號。For each decoder 160, the ring counter 162 is connected to the clock corrector 161 to receive the correction clock signal, and generates a P-bit wide (for example, 4-bit wide in this embodiment) count output based on the correction clock signal. A predetermined logical value (for example, logical value "1") cycles between the bits of the count output at a speed defined by the correction clock signal. The 1/Q divider 163 (for example, 1/2 divider 163 in this embodiment) is connected to the ring counter 162 to receive the count output, and generates a third clock signal with a frequency of 1/Q (for example, 1/2 in this embodiment) of the count output based on the count output.
對於每一解碼器160，該緩衝器165連接該取樣開關1641的第二端以接收該第一解多工資料信號，並對該第一解多工資料信號進行緩衝以產生一PAM-2 M格式（本實施例中例如為PAM-4格式）的待解碼資料信號。該第二解多工器166連接該緩衝器165以接收該待解碼資料信號，還連接該環形計數器162以接收該計數輸出，並根據該計數輸出將該待解碼資料信號解多工成數量P的第二解多工資料信號（本實施例中例如為四個第二解多工資料信號）。每一ADC 167連接該第二解多工器166以接收對應的第二解多工資料信號，並且還連接該電壓調節器12以接收該參考電壓。該等ADC 167其中一者是一（M+1）位元ADC（本實施例中例如為3位元ADC），並根據該參考電壓對對應的第二解多工資料信號進行類比數位轉換以產生一不歸零（non-return-to-zero，以下簡稱NRZ）格式的第一解碼信號。該第一解碼信號包含一M位元寬（在本實施例中例如為2位元寬）的資料部分及一1位元寬的誤差部分。其他ADC 167中的每一者是一M位元ADC（本實施例中例如為2位元ADC），並且根據該參考電壓對對應的第二解多工資料信號進行類比數位轉換以產生一NRZ格式的第二解碼信號。該第二解碼信號包含一M位元寬（本實施例中例如為2位元寬）的資料部分。在本實施例中，每一第二解多工資料信號的資料率為3.5 Gbaud。 For each decoder 160, the buffer 165 is connected to the second end of the sampling switch 1641 to receive the first demultiplexed data signal, and buffers the first demultiplexed data signal to generate a data signal to be decoded in a PAM- 2M format (for example, a PAM-4 format in this embodiment). The second demultiplexer 166 is connected to the buffer 165 to receive the data signal to be decoded, and is also connected to the ring counter 162 to receive the count output, and demultiplexes the data signal to be decoded into a number P of second demultiplexed data signals (for example, four second demultiplexed data signals in this embodiment) according to the count output. Each ADC 167 is connected to the second demultiplexer 166 to receive the corresponding second demultiplexed data signal, and is also connected to the voltage regulator 12 to receive the reference voltage. One of the ADCs 167 is an (M+1)-bit ADC (for example, a 3-bit ADC in this embodiment), and performs analog-to-digital conversion on the corresponding second demultiplexed data signal according to the reference voltage to generate a first decoded signal in a non-return-to-zero (NRZ) format. The first decoded signal includes an M-bit wide (for example, 2-bit wide in this embodiment) data portion and a 1-bit wide error portion. Each of the other ADCs 167 is an M-bit ADC (for example, a 2-bit ADC in this embodiment), and performs analog-to-digital conversion on the corresponding second demultiplexed data signal according to the reference voltage to generate a second decoded signal in NRZ format. The second decoded signal includes a data portion with an M-bit width (for example, a 2-bit width in this embodiment). In this embodiment, the data rate of each second demultiplexed data signal is 3.5 Gbaud.
在本實施例中，對於每一解碼器160，該第二解多工器166包括數量P的取樣開關1661（本實施例中例如為四個取樣開關1661）。每一取樣開關1661具有一連接該緩衝器165以接收該待解碼資料信號的第一端、一提供對應的第二解多工資料信號的第二端、以及一連接該環形計數器162以接收該計數輸出的對應的位元的控制端。每一取樣開關1661在該計數輸出的該對應位元處於該預定邏輯值（本實施例中例如為邏輯值“1”）時導通，否則不導通。對於每一取樣開關1661，當該取樣開關1661導通時，該饋入資料信號通過該取樣開關1661傳輸，以作為該對應的第二解多工資料信號。另外，每一ADC 167都是一連續逼近（successive approximation）ADC。In this embodiment, for each decoder 160, the second demultiplexer 166 includes a number P of sampling switches 1661 (for example, four sampling switches 1661 in this embodiment). Each sampling switch 1661 has a first end connected to the buffer 165 to receive the data signal to be decoded, a second end providing a corresponding second demultiplexed data signal, and a control end connected to the ring counter 162 to receive the corresponding bit of the count output. Each sampling switch 1661 is turned on when the corresponding bit of the count output is at the predetermined logical value (for example, the logical value "1" in this embodiment), otherwise it is not turned on. For each sampling switch 1661, when the sampling switch 1661 is turned on, the feed data signal is transmitted through the sampling switch 1661 to serve as the corresponding second demultiplexed data signal. In addition, each ADC 167 is a successive approximation ADC.
對於每一解碼器160，該相位校準電路168連接該等ADC 167以接收該第一解碼信號及該等第二解碼信號，還連接該環形計數器162以接收該計數輸出，並且根據該計數輸出校準該第一解碼信號和該等第二解碼信號以產生一包括一資料部分及一誤差部分的校準信號。該校準信號的資料部分為 位元寬（本實施例中例如為8位元寬），並且源自該第一解碼信號和該等第二解碼信號的該等資料部分。該校準信號的誤差部分為1位元寬，並且源自該第一解碼信號的誤差部分。該1對Q解多工器169（本實施例中例如為1:2解多工器169）連接該相位校準電路168以接收該校準信號，還連接該1/Q分頻器163（本實施例中的1/2分頻器163）接收該第三時脈信號，並根據該第三時脈信號將該校準信號解多工成一包含一資料部分和一誤差部分的解多工信號。該解多工信號的資料部分是 位元寬（本實施例中例如為16位元寬），並且源自該第一解碼信號和該等第二解碼信號的資料部分。該解多工信號的誤差部分是Q位元寬（本實施例中例如為2位元寬），並且源自該第一解碼信號的誤差部分。由該等解碼器160的該等1對Q解多工器169（本實施例中例如為1:2解多工器169）產生的該等解多工信號共同構成一解碼輸出。在本實施例中，對於每一解碼器160，該校準信號的資料部分的資料率為 Gbps，並且該校準信號的誤差部分的資料率為 Gbps；該解多工信號的資料部分的資料率為 Gbps，並且該解多工信號的誤差部分的資料率為 Gbps。 For each decoder 160, the phase calibration circuit 168 is connected to the ADCs 167 to receive the first decoded signal and the second decoded signals, and is also connected to the ring counter 162 to receive the count output, and calibrates the first decoded signal and the second decoded signals according to the count output to generate a calibration signal including a data portion and an error portion. The data portion of the calibration signal is bit width (e.g., 8 bits in this embodiment), and is derived from the data parts of the first decoded signal and the second decoded signals. The error part of the calibration signal is 1 bit wide and is derived from the error part of the first decoded signal. The 1:2 demultiplexer 169 (e.g., 1:2 demultiplexer 169 in this embodiment) is connected to the phase calibration circuit 168 to receive the calibration signal, and is also connected to the 1/Q divider 163 (1/2 divider 163 in this embodiment) to receive the third clock signal, and demultiplexes the calibration signal into a demultiplexed signal including a data part and an error part according to the third clock signal. The data part of the demultiplexed signal is The demultiplexed signals are Q-bit wide (e.g., 16-bit wide in this embodiment) and are derived from the data portion of the first decoded signal and the second decoded signals. The error portion of the demultiplexed signal is Q-bit wide (e.g., 2-bit wide in this embodiment) and is derived from the error portion of the first decoded signal. The demultiplexed signals generated by the 1-to-Q demultiplexers 169 (e.g., 1:2 demultiplexers 169 in this embodiment) of the decoders 160 together constitute a decoded output. In this embodiment, for each decoder 160, the data rate of the data portion of the calibration signal is Gbps, and the data rate of the error portion of the calibration signal is Gbps; the data rate of the data portion of the demultiplexed signal is Gbps, and the data rate of the error portion of the demultiplexed signal is Gbps.
該適應性控制器17連接該等解碼器160的該等1對Q解多工器169（本實施例中的1:2解多工器169）以接收該解碼輸出，還連接該等化器裝置111、該電壓調節器12、該相位內插器15和該等解碼器160的該等時脈校正器161，並且基於該解碼輸出的一資料部分產生一輸出資料信號Dout，該解碼輸出的該資料部分源自由該等解碼器160的該等ADC 167所產生的該等第一解碼信號和該等第二解碼信號的該等資料部分。該適應性控制器17還對該等化器裝置111、該電壓調節器12、該相位內插器13及該等解碼器160的該等時脈校正器161執行適應性校準，以根據該解碼輸出的一個源自該等第一解碼信號的該等誤差部分的誤差部分和該解碼輸出的該資料部分來調整該通道補償器11的增益、該參考電壓的大小、該等內插時脈信號的相移及該等校正時脈信號的延遲，以便獲得該饋入資料信號的眼圖的最佳品質、該饋入資料信號的正確擺幅以及該饋入資料信號的最佳樣本位置。在本實施例中，該輸出資料信號Dout的資料率為 Gbps。 The adaptive controller 17 is connected to the 1-to-Q demultiplexers 169 (1:2 demultiplexers 169 in the present embodiment) of the decoders 160 to receive the decoded output, and is also connected to the quantizer device 111, the voltage regulator 12, the phase interpolator 15 and the clock corrector 161 of the decoders 160, and generates an output data signal Dout based on a data portion of the decoded output, wherein the data portion of the decoded output is derived from the data portions of the first decoded signals and the second decoded signals generated by the ADCs 167 of the decoders 160. The adaptive controller 17 also performs adaptive calibration on the equalizer device 111, the voltage regulator 12, the phase interpolator 13 and the clock corrector 161 of the decoders 160 to adjust the gain of the channel compensator 11, the reference voltage, the phase shift of the interpolated clock signals and the delay of the corrected clock signals according to an error portion of the decoded output derived from the error portions of the first decoded signals and the data portion of the decoded output, so as to obtain the best quality of the eye diagram of the feed data signal, the correct swing of the feed data signal and the best sample position of the feed data signal. In this embodiment, the data rate of the output data signal Dout is Gbps.
在本實施例中，該第一解碼信號和該等第二解碼信號其中的每一者包含多個依序排列的樣本。該等解碼器160的該等ADC 167按照一個對應於一頻率的時間間隔所定義的速度逐個循環地操作，該頻率為每一內插時脈信號的頻率的N倍（本實施例中例如為四倍），以便產生該等第一解碼信號和該等第二解碼信號的該等樣本。表1顯示了在每一操作週期中該等第一解碼信號和該等第二解碼信號的該等樣本產生的示例性順序，其中D[]表示該等第一解碼信號和該等第二解碼信號的一個樣本的資料部分，其處於邏輯值“00”（對應於-3）、邏輯值“01”（對應於-1）、邏輯值“10”（對應於+1）和邏輯值“11”（對應於+3）其中之一；且E[]表示該等第一解碼信號的一個樣本的誤差部分，其處於邏輯值“0”和邏輯值“1”其中之一。 表1 3位元ADC 2位元ADC (I) 2位元ADC (II) 2位元ADC (III) 解碼器(I) - - - 解碼器(II) - - - 解碼器(III) - - - 解碼器(IV) - - - r：非負整數 In the present embodiment, each of the first decoded signal and the second decoded signals comprises a plurality of samples arranged in sequence. The ADCs 167 of the decoders 160 operate one by one in a loop at a speed defined by a time interval corresponding to a frequency, which is N times (for example, four times in the present embodiment) the frequency of each interpolated clock signal, so as to generate the samples of the first decoded signals and the second decoded signals. Table 1 shows an exemplary order in which the samples of the first decoded signals and the second decoded signals are generated in each operation cycle, wherein D[] represents a data portion of a sample of the first decoded signals and the second decoded signals, which is one of a logical value "00" (corresponding to -3), a logical value "01" (corresponding to -1), a logical value "10" (corresponding to +1) and a logical value "11" (corresponding to +3); and E[] represents an error portion of a sample of the first decoded signals, which is one of a logical value "0" and a logical value "1". Table 1 3-bit ADC 2-bit ADC (I) 2-bit ADC (II) 2-bit ADC (III) Decoder(I) - - - Decoder(II) - - - Decoder (III) - - - Decoder(IV) - - - r: non-negative integer
在本實施例中，如表2所示，該適應性控制器17對該等化器裝置111進行適應性校準，以參考該等第一解碼信號的一個樣本的誤差部分（以E[a]表示）以及在產生該等第一解碼信號的該樣本之前產生的該等第一解碼信號和該等第二解碼信號的一個樣本的資料部分（以D[a-K]表示）來調整該通道補償器11的增益。在一個示例中，該等第一解碼信號和該等第二解碼信號的該樣本是在該等第一解碼信號的該樣本產生之前的數量K的時間間隔內產生的，其中 。 表2 D[a-K] E[a] 增益 1x 1 增加 0x 0 增加 1x 0 減少 0x 1 減少 x: 任意值 In this embodiment, as shown in Table 2, the adaptive controller 17 adaptively calibrates the equalizer device 111 to adjust the gain of the channel compensator 11 with reference to the error portion (expressed as E[a]) of a sample of the first decoded signals and the data portion (expressed as D[aK]) of a sample of the first decoded signals and the second decoded signals generated before the sample of the first decoded signals is generated. In one example, the samples of the first decoded signals and the second decoded signals are generated within a time interval of a quantity K before the sample of the first decoded signals is generated, wherein Table 2 D[aK] E[a] Gain 1x 1 Increase 0x 0 Increase 1x 0 Reduce 0x 1 Reduce x: any value
當滿足下列任一條件時，該適應性控制器17增加該通道補償器11的增益：（a）該等第一解碼信號和該等第二解碼信號的該樣本的資料部分D[a-K]是以一正值來表示（即，處於對應於+1的邏輯值“10”，或處於對應於+3的邏輯值“11”），並且該等第一解碼信號的該樣本的誤差部分E[a]處於邏輯值“1”；及（b）該等第一解碼信號和該等第二解碼信號的該樣本的資料部分D[a-K]是以一負值來表示（即，處於對應於-3的邏輯值“00”，或處於對應於-1的邏輯值“01”），且該等第一解碼信號的該樣本的誤差部分E[a]處於邏輯值“0”。The adaptive controller 17 increases the gain of the channel compensator 11 when any of the following conditions is met: (a) the data portion D[a-K] of the sample of the first decoded signals and the second decoded signals is represented by a positive value (i.e., at a logical value "10" corresponding to +1, or at a logical value "11" corresponding to +3), and the error part E[a] is at a logical value "1"; and (b) the data part D[a-K] of the sample of the first decoded signals and the second decoded signals is represented by a negative value (i.e., at a logical value "00" corresponding to -3, or at a logical value "01" corresponding to -1), and the error part E[a] of the sample of the first decoded signals is at a logical value "0".
當滿足下列任一條件時，該適應性控制器17減少該通道補償器11的增益：（a）該等第一解碼信號和該等第二解碼信號的該樣本的資料部分D[a-K]是以一正值來表示，且該等第一解碼信號的該樣本的誤差部分E[a]處於邏輯值“0”；及（b）該等第一解碼信號和該等第二解碼信號的該樣本的資料部分D[a-K]是以一負值來表示，且該等第一解碼信號的該樣本的誤差部分E[a]處於邏輯值“1”。The adaptive controller 17 reduces the gain of the channel compensator 11 when any of the following conditions is met: (a) the data portion D[a-K] of the sample of the first decoded signals and the second decoded signals is represented by a positive value, and the error portion E[a] of the sample of the first decoded signals is at a logical value of "0"; and (b) the data portion D[a-K] of the sample of the first decoded signals and the second decoded signals is represented by a negative value, and the error portion E[a] of the sample of the first decoded signals is at a logical value of "1".
否則，該適應性控制器17保持該通道補償器11的增益不變。Otherwise, the adaptive controller 17 keeps the gain of the channel compensator 11 unchanged.
在本實施例中，如表3所示，該適應性控制器17對該電壓調節器12執行適應性校準，以參考該等第一解碼信號的該樣本的誤差部分E[a]和資料部分D[a]調整該參考電壓的大小。 表3 D[a] E[a] 參考電壓的大小 1x 1 增大 0x 0 增大 1x 0 減小 0x 1 減小 x：不重要 In this embodiment, as shown in Table 3, the adaptive controller 17 performs adaptive calibration on the voltage regulator 12 to adjust the reference voltage with reference to the error portion E[a] and the data portion D[a] of the sample of the first decoded signals. Table 3 D[a] E[a] The size of the reference voltage 1x 1 Increase 0x 0 Increase 1x 0 Reduce 0x 1 Reduce x: not important
當滿足下列任一條件時，該適應性控制器17增大該參考電壓的大小：（a）該等第一解碼信號的該樣本的資料部分D[a]是以一正值來表示，且該等第一解碼信號的該樣本的誤差部分E[a]處於邏輯值“1”；及（b）該等第一解碼信號的該樣本的資料部分D[a]是以一負值來表示，且該等第一解碼信號的該樣本的誤差部分E[a]處於邏輯值“0”。The adaptive controller 17 increases the magnitude of the reference voltage when any of the following conditions is met: (a) the data portion D[a] of the sample of the first decoded signals is represented by a positive value, and the error portion E[a] of the sample of the first decoded signals is at a logical value of "1"; and (b) the data portion D[a] of the sample of the first decoded signals is represented by a negative value, and the error portion E[a] of the sample of the first decoded signals is at a logical value of "0".
當滿足下列任一條件時，該適應性控制器17減小該參考電壓的大小：（a）該等第一解碼信號的該樣本的資料部分D[a]是以一正值來表示，且該等第一解碼信號的該樣本的誤差部分E[a]處於邏輯值“0”；及（b）該等第一解碼信號的該樣本的資料部分D[a]是以一負值來表示，且該等第一解碼信號的該樣本的誤差部分E[a]處於邏輯值“1”。The adaptive controller 17 reduces the magnitude of the reference voltage when any of the following conditions is met: (a) the data portion D[a] of the sample of the first decoded signals is represented by a positive value, and the error portion E[a] of the sample of the first decoded signals is at a logical value of "0"; and (b) the data portion D[a] of the sample of the first decoded signals is represented by a negative value, and the error portion E[a] of the sample of the first decoded signals is at a logical value of "1".
否則，該適應性控制器17保持該參考電壓的大小不變。Otherwise, the adaptive controller 17 keeps the magnitude of the reference voltage unchanged.
在本實施例中，如表4所示，該適應性控制器17對該相位內插器15執行適應性校準，以參考該等第一解碼信號的該樣本的誤差部分E[a]和資料部分D[a]以及在該等第一解碼信號的該樣本產生之後的該時間間隔內產生的該等第一解碼信號的另一個樣本的誤差部分（以E[a+1]來表示）和資料部分（以D[a+1]來表示）來調整該等內插時脈信號的相移。 表4 D[a] D[a+1] E[a] E[a+1] 相移 11 00 1 1 延遲 11 00 0 0 提前 10 01 1 1 延遲 10 01 0 0 提前 01 10 1 1 提前 01 10 0 0 延遲 00 11 1 1 提前 00 11 0 0 延遲 In this embodiment, as shown in Table 4, the adaptive controller 17 performs adaptive calibration on the phase interpolator 15 to adjust the phase shift of the interpolated clock signals with reference to the error portion E[a] and the data portion D[a] of the sample of the first decoded signals and the error portion (represented by E[a+1]) and the data portion (represented by D[a+1]) of another sample of the first decoded signals generated in the time interval after the sample of the first decoded signals is generated. Table 4 D[a] D[a+1] E[a] E[a+1] Phase Shift 11 00 1 1 delay 11 00 0 0 in advance 10 01 1 1 delay 10 01 0 0 in advance 01 10 1 1 in advance 01 10 0 0 delay 00 11 1 1 in advance 00 11 0 0 delay
當滿足下列任一條件時，該適應性控制器17調整該等內插時脈信號的相移以延遲該等內插時脈信號的相位：（a）該等第一解碼信號的該樣本的資料部分D[a]是以+L的值來表示，該等第一解碼信號的該另一個樣本的資料部分D[a+1]是以-L的值來表示，該等第一解碼信號的該樣本的誤差部分E[a]處於邏輯值“1”，且該等第一解碼信號的該另一個樣本的誤差部分E[a+1]處於邏輯值“1”;及（b）該等第一解碼信號的該樣本的資料部分D[a]是以-L的值來表示，該等第一解碼信號的該另一個樣本的資料部分D[a+1]是以+L的值來表示，該等第一解碼信號的該樣本的誤差部分E[a]邏輯值“0”，且該等第一解碼信號的該另一個樣本的誤差部分E[a+1]處於邏輯值“0”，其中L為一小於2 M的正奇數（本實施例中例如L=1或L=3）。 When any of the following conditions is met, the adaptive controller 17 adjusts the phase shift of the interpolated clock signals to delay the phase of the interpolated clock signals: (a) the data portion D[a] of the sample of the first decoded signals is represented by a value of +L, the data portion D[a+1] of the other sample of the first decoded signals is represented by a value of -L, the error portion E[a] of the sample of the first decoded signals is at a logical value "1", and the other sample of the first decoded signals is The error part E[a+1] of the sample is at a logical value "1"; and (b) the data part D[a] of the sample of the first decoded signals is represented by a value of -L, the data part D[a+1] of the other sample of the first decoded signals is represented by a value of +L, the error part E[a] of the sample of the first decoded signals is at a logical value "0", and the error part E[a+1] of the other sample of the first decoded signals is at a logical value "0", where L is a positive odd number less than 2 M (for example, L=1 or L=3 in this embodiment).
當滿足下列任一條件時，該適應性控制器17調整該等內插時脈信號的相移以提前該等內插時脈信號的相位：（a）該等第一解碼信號的該樣本的資料部分D[a]是以+L的值來表示，該等第一解碼信號的該另一個樣本的資料部分D[a+1]是以-L的值來表示，該等第一解碼信號的該樣本的誤差部分E[a]處於邏輯值“0”，且該等第一解碼信號的該另一個樣本的誤差部分E[a+1]處於邏輯值“0”；及（b）該等第一解碼信號的該樣本的資料部分D[a]是以-L的值來表示，該等第一解碼信號的該另一個樣本的資料部分D[a+1]是以+L的值來表示，該等第一解碼信號的該樣本的誤差部分E[a]處於邏輯值“1”，且該等第一解碼信號的該另一個樣本的誤差部分E[a+1]處於邏輯值“1”。When any of the following conditions is met, the adaptive controller 17 adjusts the phase shift of the interpolated clock signals to advance the phase of the interpolated clock signals: (a) the data portion D[a] of the sample of the first decoded signals is represented by a value of +L, the data portion D[a+1] of the other sample of the first decoded signals is represented by a value of -L, the error portion E[a] of the sample of the first decoded signals is at a logical value of "0", and the error portion E[a] of the sample of the first decoded signals is at a logical value of "0". The error portion E[a+1] of one sample is at a logical value "0"; and (b) the data portion D[a] of the sample of the first decoded signals is represented by a value of -L, the data portion D[a+1] of the other sample of the first decoded signals is represented by a value of +L, the error portion E[a] of the sample of the first decoded signals is at a logical value "1", and the error portion E[a+1] of the other sample of the first decoded signals is at a logical value "1".
否則，該適應性控制器17保持該等內插時脈信號的相移不變。Otherwise, the adaptive controller 17 keeps the phase shift of the interpolated clock signals unchanged.
在本實施例中，如表5所示，該適應性控制器17對該等解碼器160的該等時脈校正器161執行適應性校準，以根據該等第一解碼信號的該樣本的誤差部分E[a]和資料部分D[a]、在該等第一解碼信號的該樣本生成之後的該時間間隔內產生的該等第一解碼信號的該另一個樣本的誤差部分E[a+1]和資料部分D[a+1]、在該等第一解碼信號的該樣本產生之前的該時間間隔內產生的該等第一解碼信號和該等第二解碼信號的該樣本的資料部分D[a-1]以及在該等第一解碼信號的該另一個樣本產生之後的該時間間隔內產生的該等第一解碼信號和該等第二解碼信號的該另一樣本的資料部分D[a+2]來調整該等校正時脈信號的延遲。 表5 D[a-1] D[a] D[a+1] D[a+2] E[a] E[a+1] 時滯 11 11 00 00 1 0 減少 11 11 00 00 0 1 增加 10 10 01 01 1 0 減少 10 10 01 01 0 1 增加 01 01 10 10 1 0 增加 01 01 10 10 0 1 減少 00 00 11 11 1 0 增加 00 00 11 11 0 1 減少 00 11 11 00 1 1 增加 00 11 11 00 0 0 減少 01 10 10 01 1 1 增加 01 10 10 01 0 0 減少 10 01 01 10 1 1 減少 10 01 01 10 0 0 增加 11 00 00 11 1 1 減少 11 00 00 11 0 0 增加 In this embodiment, as shown in Table 5, the adaptive controller 17 performs adaptive calibration on the isochronous clock corrector 161 of the decoders 160 to adjust the error portion E[a] and the data portion D[a] of the sample of the first decoded signals, the error portion E[a+1] and the data portion D[a] of the other sample of the first decoded signals generated in the time interval after the sample of the first decoded signals is generated, and the adaptive controller 17 performs adaptive calibration on the isochronous clock corrector 161 of the decoders 160 to adjust the error portion E[a] and the data portion D[a] of the sample of the first decoded signals, and the error portion E[a+1] and the data portion D[a+1] of the other sample of the first decoded signals generated in the time interval after the sample of the first decoded signals is generated. a+1], the data portion D[a-1] of the sample of the first decoded signals and the second decoded signals generated in the time interval before the sample of the first decoded signals is generated, and the data portion D[a+2] of the sample of the first decoded signals and the second decoded signals generated in the time interval after the another sample of the first decoded signals is generated to adjust the delay of the calibration clock signals. Table 5 D[a-1] D[a] D[a+1] D[a+2] E[a] E[a+1] Time lag 11 11 00 00 1 0 Reduce 11 11 00 00 0 1 Increase 10 10 01 01 1 0 Reduce 10 10 01 01 0 1 Increase 01 01 10 10 1 0 Increase 01 01 10 10 0 1 Reduce 00 00 11 11 1 0 Increase 00 00 11 11 0 1 Reduce 00 11 11 00 1 1 Increase 00 11 11 00 0 0 Reduce 01 10 10 01 1 1 Increase 01 10 10 01 0 0 Reduce 10 01 01 10 1 1 Reduce 10 01 01 10 0 0 Increase 11 00 00 11 1 1 Reduce 11 00 00 11 0 0 Increase
當滿足下列任一條件時，該適應性控制器17調整該等校正時脈信號的延遲，以減少在該等校正時脈信號中的兩個分別由兩個分別產生該等第一解碼信號的該樣本和該另一個樣本的解碼器160所產生的校正時脈信號之間的時滯：（a）該等第一解碼信號和該等第二解碼信號的該樣本的資料部分D[a-1]是以+L的值來表示，該等第一解碼信號的該樣本的資料部分D[a]是以+L的值來表示，該等第一解碼信號的該另一個樣本的資料部分D[a+1]是以-L的值來表示，該等第一解碼信號及該等第二解碼信號的該另一樣本的資料部分D[a+2]是以-L的值來表示，該等第一解碼信號的該樣本的誤差部分E[a]處於邏輯值“1”，且該等第一解碼信號的該另一個樣本的誤差部分E[a+1]處於邏輯值“0”；及（b）該等第一解碼信號和該等第二解碼信號的該樣本的資料部分D[a-1]是以-L的值來表示，該等第一解碼信號的該樣本的資料部分（D[a]）是以-L的值來表示，該等第一解碼信號的該另一個樣本的資料部分D[a+1]是以+L的值來表示，該等第一解碼信號和該等第二解碼信號的該另一樣本的資料部分D[a+2]是以+L的值來表示，該等第一解碼信號的該樣本的誤差部分E[a]為處於邏輯值“0”，該等第一解碼信號的該另一個樣本的誤差部分E[a+1]處於邏輯值“1”；（c）該等第一解碼信號和該等第二解碼信號的該樣本的資料部分D[a-1]是以-L的值來表示，該等第一解碼信號的該樣本的資料部分D[a]是以 +L的值來表示，該等第一解碼信號的該另一個樣本的資料部分D[a+1]是以 +L的值來表示，該等第一解碼信號和該等第二解碼信號的該另一個樣本的資料部分D[a+2]是以-L的值來表示，該等第一解碼信號的該樣本的誤差部分E[a]處於邏輯值“0”，該等第一解碼信號的該另一個樣本的誤差部分E[a+1]處於邏輯值“0”；及（d）該等第一解碼信號和該等第二解碼信號的該樣本的資料部分D[a-1]是以+L的值來表示，該等第一解碼信號的該樣本的資料部分D[a]是以-L的值來表示，該等第一解碼信號的該另一個樣本的資料部分D[a+1]是以-L的值來表示，該等第一解碼信號和該等第二解碼信號的該另一個樣本的資料部分D[a+2]是以+L的值來表示，該等第一解碼信號的該樣本的誤差部分E[a]處於邏輯值“1”，該等第一解碼信號的該另一個樣本的誤差部分E[a+1]處於邏輯值“1”，其中L為小於2 M的正奇數（本實施例中例如L=1或L=3）。 When any of the following conditions is met, the adaptive controller 17 adjusts the delay of the correction clock signals to reduce the time lag between two correction clock signals generated by the decoder 160 that respectively generates the sample of the first decoded signals and the other sample: (a) the data portion D[a-1] of the sample of the first decoded signals and the second decoded signals is represented by a value of +L, the data portion D[a] of the sample of the first decoded signals is represented by a value of +L, the data portion D[a+1] of the other sample of the first decoded signals is represented by a value of -L, and the data portion D[a+2] of the other sample of the first decoded signals and the second decoded signals is represented by a value of -L. L is used to represent the error portion E[a] of the sample of the first decoded signals being at a logical value "1", and the error portion E[a+1] of the other sample of the first decoded signals being at a logical value "0"; and (b) the data portion D[a-1] of the sample of the first decoded signals and the second decoded signals being represented by a value of -L, the data portion (D[a]) of the sample of the first decoded signals being represented by a value of -L, the data portion D[a+1] of the other sample of the first decoded signals being represented by a value of +L, the data portion D[a+2] of the other sample of the first decoded signals and the second decoded signals being represented by a value of +L, and the error portion E[a] of the sample of the first decoded signals being at a logical value "1", and the error portion E[a+1] of the other sample of the first decoded signals being at a logical value "0"; [a] is at a logical value "0", and the error part E[a+1] of the other sample of the first decoded signals is at a logical value "1"; (c) the data part D[a-1] of the sample of the first decoded signals and the second decoded signals is represented by a value of -L, the data part D[a] of the sample of the first decoded signals is represented by a value of +L, the data part D[a+1] of the other sample of the first decoded signals is represented by a value of +L, the data part D[a+2] of the other sample of the first decoded signals and the second decoded signals is represented by a value of -L, the error part E[a] of the sample of the first decoded signals is at a logical value "0", and the other sample of the first decoded signals is The error portion E[a+1] of the sample is at a logical value "0"; and (d) the data portion D[a-1] of the sample of the first decoded signals and the second decoded signals is represented by a value of +L, the data portion D[a] of the sample of the first decoded signals is represented by a value of -L, the data portion D[a+1] of the other sample of the first decoded signals is represented by a value of -L, the data portion D[a+2] of the other sample of the first decoded signals and the second decoded signals is represented by a value of +L, the error portion E[a] of the sample of the first decoded signals is at a logical value "1", and the error portion E[a+1] of the other sample of the first decoded signals is at a logical value "1", where L is less than 2. M is a positive odd number (for example, L=1 or L=3 in this embodiment).
當滿足下列任一條件時，該適應性控制器17調整該等校正時脈信號的延遲以增加該時滯：（a）該等第一解碼信號和該等第二解碼信號的該樣本的資料部分D[a-1]是以+L的值來表示，該等第一解碼信號的該樣本的資料部分D[a]是以+L的值來表示，該等第一解碼信號的該另一個樣本的資料部分D[a+1]是以-L的值來表示，該等第一解碼信號及該等第二解碼信號的該另一樣本的資料部分D[a+2]是以-L的值來表示，該等第一解碼信號的該樣本的誤差部分E[a]處於邏輯值“0”，該等第一解碼信號的該另一個樣本的誤差部分E[a+1]處於邏輯值“1”;（b）該等第一解碼信號和該等第二解碼信號的該樣本的資料部分D[a-1]是以-L的值來表示，該等第一解碼信號的該樣本的資料部分D[a]是以-L的值來表示，該等第一解碼信號的該另一個樣本的資料部分D[a+1]是以+L的值來表示，該等第一解碼信號和該等第二解碼信號的該另一個樣本的資料部分D[a+2]是以+L的值來表示，該等第一解碼信號的該樣本的誤差部分E[a]處於邏輯值“1”，該等第一解碼信號的該另一個樣本的誤差部分E[a+1]處於邏輯值“0”；（c）該等第一解碼信號和該等第二解碼信號的該樣本的資料部分D[a-1]是以-L的值來表示，該等第一解碼信號的該樣本的資料部分D[a]是以+L的值來表示，該等第一解碼信號的該另一個樣本的資料部分D[a+1]是以+L的值來表示，該等第一解碼信號和該等第二解碼信號的該另一個樣本的資料部分D[a+2]是以-L的值來表示，該等第一解碼信號的該樣本的誤差部分E[a]處於邏輯值“1”，該等第一解碼信號該另一個樣本的誤差部分E[a+1]處於邏輯值“1”；及（d）該等第一解碼信號和該等第二解碼信號的該樣本的資料部分D[a-1]是以+L的值來表示，該等第一解碼信號的該樣本的資料部分D[a]是以-L的值來表示，該等第一解碼信號的該另一個樣本的資料部分D[a+1]是以-L的值來表示，該等第一解碼信號和該等第二解碼信號的該另一個樣本的資料部分D[a+2]是以+L的值來表示，該等第一解碼信號的該樣本的誤差部分E[a]處於邏輯值“0”，該等第一解碼信號的該另一個樣本的誤差部分E[a+1]處於邏輯值“0”。When any of the following conditions is met, the adaptive controller 17 adjusts the delay of the correction clock signals to increase the time lag: (a) the data portion D[a-1] of the sample of the first decoded signals and the second decoded signals is represented by a value of +L, the data portion D[a] of the sample of the first decoded signals is represented by a value of +L, the data portion D[a+1] of the other sample of the first decoded signals is represented by a value of -L, the data portion D[a+2] of the other sample of the first decoded signals and the second decoded signals is represented by a value of -L, the error portion E[a] of the sample of the first decoded signals is at a logical value of "0", and the first decoded signals are The error portion E[a+1] of the other sample of the first decoded signal is at a logical value "1"; (b) the data portion D[a-1] of the sample of the first decoded signal and the second decoded signal is represented by a value of -L, the data portion D[a] of the sample of the first decoded signal is represented by a value of -L, the data portion D[a+1] of the other sample of the first decoded signal is represented by a value of +L, the data portion D[a+2] of the other sample of the first decoded signal and the second decoded signal is represented by a value of +L, the error portion E[a] of the sample of the first decoded signal is at a logical value "1", and the data portion D[a-1] of the other sample of the first decoded signal is represented by a value of -L. The error part E[a+1] of the sample is at a logical value "0"; (c) the data part D[a-1] of the sample of the first decoded signals and the second decoded signals is represented by a value of -L, the data part D[a] of the sample of the first decoded signals is represented by a value of +L, the data part D[a+1] of the other sample of the first decoded signals is represented by a value of +L, the data part D[a+2] of the other sample of the first decoded signals and the second decoded signals is represented by a value of -L, the error part E[a] of the sample of the first decoded signals is at a logical value "1", the error part E[a+1] of the other sample of the first decoded signals is is at a logical value of "1"; and (d) the data portion D[a-1] of the sample of the first decoded signals and the second decoded signals is represented by a value of +L, the data portion D[a] of the sample of the first decoded signals is represented by a value of -L, the data portion D[a+1] of the other sample of the first decoded signals is represented by a value of -L, the data portion D[a+2] of the other sample of the first decoded signals and the second decoded signals is represented by a value of +L, the error portion E[a] of the sample of the first decoded signals is at a logical value of "0", and the error portion E[a+1] of the other sample of the first decoded signals is at a logical value of "0".
否則，該適應性控制器17保持該等校正時脈信號的延遲不變。Otherwise, the adaptive controller 17 keeps the delays of the calibration clock signals unchanged.
綜上所述，本實施例的該接收器具有以下優點。In summary, the receiver of this embodiment has the following advantages.
一、該連續時間線性等化器116僅用於補償該輸入資料信號Din的高頻成分，因此該接收器適合於在通過一低損失通道傳輸該輸入資料信號Din的環境下操作。另外，該等解碼器160的該等ADC 167均爲連續逼近ADC，並且由於該等解碼器160的該等第一解多工器164和該等第二解多工器166而以時間交錯的方式操作。上述這些因素有利於降低該解碼器裝置16的功耗。First, the continuous time linear equalizer 116 is only used to compensate the high frequency components of the input data signal Din, so the receiver is suitable for operating in an environment where the input data signal Din is transmitted through a low loss channel. In addition, the ADCs 167 of the decoders 160 are all continuous approximation ADCs, and are operated in a time-interleaved manner due to the first demultiplexers 164 and the second demultiplexers 166 of the decoders 160. The above factors are conducive to reducing the power consumption of the decoder device 16.
二、對於每一解碼器160，只有一個ADC 167是（M+1）位元ADC（本實施例中的3位元ADC），其擷取分別對應於該等第一解碼信號的資料部分的2 M個資料值（本實施例中例如M=2，即，4個資料值）的誤差項，以用於對該等化器裝置111和該相位內插器15所執行的適應性校準。這可以幫助該時脈資料恢復電路達到可接受的抖動容忍度，增強該接收器的性能，並降低該接收器的功耗。 Second, for each decoder 160, only one ADC 167 is an (M+1)-bit ADC (a 3-bit ADC in this embodiment), which extracts error terms of 2 M data values (for example, M=2, i.e., 4 data values in this embodiment) respectively corresponding to the data portion of the first decoded signals, for use in the adaptive calibration performed by the equalizer device 111 and the phase interpolator 15. This can help the clock data recovery circuit achieve an acceptable jitter tolerance, enhance the performance of the receiver, and reduce the power consumption of the receiver.
三、該電壓調節器12產生一供該等解碼器160的所有ADC 167使用的參考電壓，這有利於減小該電壓調節器12的尺寸和功耗。3. The voltage regulator 12 generates a reference voltage for use by all ADCs 167 of the decoders 160, which is beneficial to reducing the size and power consumption of the voltage regulator 12.
四、藉由每一解碼器160中連接在該第一解多工器164和該第二解多工器166之間連接的該緩衝器165，該通道補償器11在其輸出端具有一輕負載電容，從而具有一寬的帶寬。Fourth, by connecting the buffer 165 between the first demultiplexer 164 and the second demultiplexer 166 in each decoder 160, the channel compensator 11 has a light load capacitor at its output end, thereby having a wide bandwidth.
五、藉由該適應性控制器17對該等化器裝置111、該電壓調節器12、該相位內插器15以及該等解碼器160的該等時脈校正器161執行適應性校準，該接收器可以處理通道損失，以及製程、電壓和溫度（PVT）變化，從而更穩定地操作並實現更高的良率。5. By performing adaptive calibration on the equalizer device 111, the voltage regulator 12, the phase interpolator 15, and the isochronous clock corrector 161 of the decoders 160 by the adaptive controller 17, the receiver can handle channel loss and process, voltage and temperature (PVT) variations, thereby operating more stably and achieving higher yield.
六、在對該等化器裝置111所執行的適應性校準中僅考慮了該等第一解碼信號和該等第二解碼信號的該樣本的資料部分D[a-K]的符號(正或負)，如此可以增加有效的有效模式密度（valid pattern density）。6. In the adaptive calibration performed on the quantizer devices 111, only the sign (positive or negative) of the data portion D[a-K] of the sample of the first decoded signals and the second decoded signals is considered, which can increase the effective pattern density.
七、在對該等解碼器160的該等時脈校正器161所執行的適應性校準中考慮了該等第一解碼信號和該等第二解碼信號的該樣本的資料部分D[a-1]以及該等第一解碼信號和該等第二解碼信號的該另一個樣本的資料部分D[a+2]，如此可以消除符號間幹擾（Inter-Symbol Interference，ISI）的影響，以提高適應性校準的準確性。7. In the adaptive calibration performed on the clock corrector 161 of the decoders 160, the data portion D[a-1] of the sample of the first decoded signals and the second decoded signals and the data portion D[a+2] of the other sample of the first decoded signals and the second decoded signals are taken into account, so that the influence of inter-symbol interference (ISI) can be eliminated to improve the accuracy of the adaptive calibration.
八、在對該相位內插器15所執行的適應性校準中考慮了更多的過渡模式，如此可以增加該時脈資料恢復電路的迴路帶寬並降低該時脈資料恢復電路的時脈抖動。8. More transition modes are taken into account in the adaptive calibration performed on the phase interpolator 15, so that the loop bandwidth of the clock data recovery circuit can be increased and the clock jitter of the clock data recovery circuit can be reduced.
惟以上所述者，僅為本發明之實施例而已，當不能以此限定本發明實施之範圍，凡是依本發明申請專利範圍及專利說明書內容所作之簡單的等效變化與修飾，皆仍屬本發明專利涵蓋之範圍內。However, the above is only an example of the implementation of the present invention, and it should not be used to limit the scope of the implementation of the present invention. All simple equivalent changes and modifications made according to the scope of the patent application of the present invention and the content of the patent specification are still within the scope of the patent of the present invention.
11:通道補償器11: Channel Compensator
111:等化器裝置111: Equalizer device
112:可變增益放大器112: Variable gain amplifier
116:連續時間線性等化器116: Continuous Time Linear Equalizer
117:低頻等化器117: Low frequency equalizer
12:電壓調節器12: Voltage regulator
13:多相濾波器13: Polyphase Filter
14:CML至CMOS 轉換器14: CML to CMOS Converter
15:相位內插器15: Phase Interpolator
16:解碼器裝置16: Decoder device
160:解碼器160:Decoder
161:時脈校正器161:Clock Corrector
162:環形計數器162: Ring counter
163:1/Q分頻器163:1/Q Crossover
164:第一解多工器164: First Demultiplexer
1641:取樣開關1641: Sampling switch
165:緩衝器165: Buffer
166:第二解多工器166: Second Demultiplexer
1661:取樣開關1661: Sampling switch
167:類比數位轉換器167:Analog-to-digital converter
168:相位校準電路168: Phase calibration circuit
169:1對Q解多工器169:1 to Q demultiplexer
17:適應性控制器17: Adaptive Controller
Din:輸入資料信號Din: Input data signal
CKin:差動輸入時脈信號對CKin: differential input clock signal pair
Dout:輸出資料信號Dout: output data signal
本發明之其他的特徵及功效，將於以下參照圖式的實施例中清楚地呈現。應注意的是，各種特徵可能未按比例繪製。 圖1是一電路方塊圖，說明根據本發明實施例的一種接收器；及 圖2是一方塊圖，説明該實施例的一通道補償器。 Other features and functions of the present invention will be clearly presented in the following embodiments with reference to the drawings. It should be noted that various features may not be drawn to scale. FIG. 1 is a circuit block diagram illustrating a receiver according to an embodiment of the present invention; and FIG. 2 is a block diagram illustrating a channel compensator of the embodiment.
11:通道補償器 11: Channel compensator
12:電壓調節器 12: Voltage regulator
13:多相濾波器 13: Polyphase filter
14:CML至CMOS：轉換器 14: CML to CMOS: Converter
15:相位內插器 15: Phase interpolator
16:解碼器裝置 16: Decoder device
160:解碼器 160:Decoder
161:時脈校正器 161: Clock Corrector
162:環形計數器 162: Ring counter
163:1/Q分頻器 163:1/Q crossover
164:第一解多工器 164: The first demultiplexer
1641:取樣開關 1641: Sampling switch
165:緩衝器 165: Buffer
166:第二解多工器 166: Second demultiplexer
1661:取樣開關 1661: Sampling switch
167:類比數位轉換器 167:Analog-to-digital converter
168:相位校準電路 168: Phase calibration circuit
169:1對Q解多工器 169:1 to Q demultiplexer
17:適應性控制器 17: Adaptive controller
Din:輸入資料信號 Din: Input data signal
CKin:差動輸入時脈信號對 CKin: differential input clock signal pair
Dout:輸出資料信號 Dout: output data signal
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Citations (3)
* Cited by examiner, † Cited by third party| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20200195475A1 (en) * | 2007-01-09 | 2020-06-18 | Rambus Inc. | Receiver with Clock Recovery Circuit and Adaptive Sample and Equalizer Timing |
| US11133963B1 (en) * | 2020-09-03 | 2021-09-28 | Xilinx, Inc. | Dsp cancellation of track-and-hold induced ISI in ADC-based serial links |
| US11271782B1 (en) * | 2020-09-04 | 2022-03-08 | Cadence Design Systems, Inc. | Capacitive coupling based feedback for decision feedback equalization |
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* Cited by examiner, † Cited by third party| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20200195475A1 (en) * | 2007-01-09 | 2020-06-18 | Rambus Inc. | Receiver with Clock Recovery Circuit and Adaptive Sample and Equalizer Timing |
| US11133963B1 (en) * | 2020-09-03 | 2021-09-28 | Xilinx, Inc. | Dsp cancellation of track-and-hold induced ISI in ADC-based serial links |
| US11271782B1 (en) * | 2020-09-04 | 2022-03-08 | Cadence Design Systems, Inc. | Capacitive coupling based feedback for decision feedback equalization |
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