M321548 八、新型說明： 【新型所屬之技術領域】 本創作係有關於一種可轉換内積體電路匯流排 (IIC)位準之控制裝置，且特別地是一種可轉換不同 晶片之IIC位準並達到lie雙向資料傳輸之控制裝 置。 x 【先前技術】 内積體電路匯流排（Inter Integrated Circuit，IIC)是1980年代由Philips所發展的 雙向二線式串列匯流排標準，其主要是應用於積體 電路（1C)之間溝通。相較於傳統平行匯流排所使用 的平行架構（8 bit或16 bit等等）而言，串列匯流 排不僅結構相當簡單，只須二條線係是一串列數據 線（SDA)及一串列時脈線（SCL)就能傳送資料，同時 也省去了平行匯流排所須的解碼電路。另外，nc 也大大降低了平行匯流排可能因為接線過多而可能 造成的電磁干擾和靜電放電等副作用。 由於IIC是雙向的資料傳輸介面，若應用中需 要有電壓位準上的轉換時，例如丨.8伏特與3· 3伏 特之間的轉換，一般會加上一顆nc專用的ic。但 在硬體空間寸土寸金的壓力下，為了簡化電路則會 運用複雜可程式邏輯裝置（complex pr〇grammaMe l〇g1Cdevice，CPLD)來解決周邊晶片與中央處理器 5 M321548 (CPU)有不同電位的問題，但可惜的事，由於cpld 有個先天的障礙，那就是一但腳位被訂定成輸入或 是輸出了之後則難以再更改，因此要把雙向的IIC 界面整合在CPLD裡，在原始的設計理念上則是有一 定的困難度。 【新型内容】 因此本創作的目的在於提供一種可轉換IIC 位準之控制裝置，用於讓具有不同IIC位準之晶片 可透過此控制裝置來傳輸資料。 根據本創作之目的，本創作係提供一種可轉換 11C位準之控制裝置，係設置於一中央處理器及一 晶片之間’該控制裝置包含複數個第一電壓接腳、 複數個弟一電壓接腳、一狀態彳貞測單元及一邏輯運 异單元。第一電壓接腳係連接中央處理器之lie界 面，以接收中央處理器所輸出之一串列數據（SDA) 信號及一串列時脈（SCL)信號，而第二電壓接腳係連 接晶片之IIC界面。狀態偵測單元係分別根據一第 一條件及一第二條件，以判斷控制裝置是否進入一 開始狀態（start condition)或一停止狀態（st〇p condition)。當開始狀態出現時，則邏輯運算單元 設定中央處理器為輸入端，而晶片為輸出端，並計 數该列時脈（SCL)信號之一周期數目，當周期數目等 於一預設數值時，則邏輯運算單元反向串列數據信 M321548 二之方向’並§又疋中央處理器為輸出端，而 =端，且邏輯運算單秘據該串列數據信號之資 料格式（Data Frame)之特定位元之值，而決列 數據信號之資料傳送的方向。 【實施方式】 以下詳細地討論目前較佳的實_。然而應被 • ^解的是，本創作提供許多可適用的新型觀念，而 攻些觀念能被體現於很寬廣多樣的特定具體背景 中。所討論的特定具體的實施例僅是說明使用本創 作的特定方式，而且不會限制本創作的範圍。 、凊參閱第1圖，其係繪示本創作之可轉換iIC 位準之控制裝置之方塊圖。圖中，控制裝置11包含 ♦ 複數個第一電壓接腳111、複數個第二電壓接腳 112、一狀態偵測單元114及一邏輯運算單元丨13。 癱 控制裝置11係設置於一中央處理器12及一晶片13 - 之間’第一電壓接腳111係連接中央處理器12之 11C界面121，以接收中央處理器12所輸出之一串 列數據（SDA)信號141及一串列時脈（SCL)信號 142 ’而第二電壓接腳112係連接晶片13之nc界 面131。在一實施例中，控制裝置^係為一複雜可 程式邏輯裝置（C〇mpiex pr〇grammabie Logic Device，CPLD)，而晶片13係為一記憶體晶片或任 一具有11C介面之晶片。而第一電壓接腳m可為 7 M321548 一接收1.8伏特之接腳’而第二電潘接腳ιΐ2可為 一接收3· 3伏特之接腳。 狀態偵測單元114係根據-第-條件，以判斷 邏輯運算單元113是否應進入一開始狀態 condition)。在一實施例中，第一條件可為於串列 數據信號141出現-負緣（falUng他）且串列時 脈信號142出現-輪詢負緣（p〇1Hngfaliingedge) 時。 當邏輯運算單元113進入開始狀態時，則邏輯 運算單元113設定中央處理器12為輸入端，而晶片 13為輸出端，並計數串列時脈信號142之一周期數 目。當周期數目等於一預設數值時，則邏輯運算單 元113反向串列數據信號141之方向，並設定中央 處理器12為輸出端，而晶片13為輸入端。在一實 細例中，此預設數值為9。在一實施例中，於SCl 仏號之第9個時脈時，係是處於SCL信號於R/w之 後的ACK狀態，因此設定中央處理器12為輸出端而 晶片13為輸入端，可使中央處理器a接收到晶片 13回傳的確認（ACK)信號。 欠接著，邏輯運算單元113根據串列數據信號141 之資料格式（Data Frame)之特定位元之值，而決定 串列數據信號141之資料傳送的方向。而狀態偵測 單元114係根據一第二條件，以判斷邏輯運算單元 113疋否應進入一停止狀癌（3七叩t i〇n)。在 M321548 一實施例中，第二條件可為於串列時脈信號142出 現一正緣（rising edge)且串列數據信號141出現一 輪詢正緣（polling rising edge)時。 請參閱第2圖，其繪示本創作之可轉換内積體 電路匯流排（11C)位準之控制裝置之操作過程之步 驟流程圖。圖中，此操作過程係對應第丨圖所示之 控制裝置11 ’此插作過程包含下列步驟： 步驟21 :將中央處理器12之IIC界面121連 接控制裝置11之複數個第一電壓接腳m，而控制 4置11之第一電壓接腳U2連接至一晶片13之iic 界面131。為人所熟知的11(：界面是一 SM接線及 一 SCL)接線，所以先將CPU 12之SM及SCL接線 連接至控制裝置11之控制裝置u係為一複雜可程 式邏輯裝置，而晶片13係為一記憶體晶片或任一具 有11C介面之晶片。 步驟22:控制裝置11透過第一電壓接腳lu， 接收>中央處理器12所輸出之一 SDA信號141及一 乜號142。因為I ic是一種同步傳輸協定，主要 J用由主控化（Master)發出SCL輪入時脈，藉以 將主=端和從屬端（Slave)之間的時序順序和SDA 輸為料同步。於本實施例中，作為主控端之cpu 21 ^分f傳送一 SDA信號及一 SCL信號至CPLD 22， ，、中别述的SDA信號至少包含此記憶體晶片23(從 M321548 屬端）的位址、讀/寫（R/W)及寫入的資料，而以IIC 標準模式為例，如表格1，此表格1為SDA信號之 資料格式（Data Frame)，其中，位址（Address)具有 7個位元、讀/寫（R/W)具有1個位元及資料（DATA) 具有7個位元，請注意，此資料格式在位址位元及 資料位元之後，皆含有自晶片（從屬端）所發出1 bit 的確認（Acknowledge，Ack)信號。 位址 讀/寫 確認 資料 確認 (Address) (R/W) (Ack) (DATA) (Ack) 表格1M321548 VIII. New Description: [New Technical Field] This creation is related to a control device for the switchable bus circuit (IIC) level, and in particular to a IIC level that can be converted to different wafers. Lie two-way data transmission control device. x [Prior Art] The Inter Integrated Circuit (IIC) is a bidirectional two-wire serial bus standard developed by Philips in the 1980s. It is mainly used for communication between integrated circuits (1C). Compared with the parallel architecture (8 bit or 16 bit, etc.) used in the traditional parallel bus, the serial bus is not only simple in structure, but only two lines are a series of data lines (SDA) and a string. The column clock line (SCL) can transmit data and also eliminates the decoding circuitry required for parallel bus bars. In addition, nc also greatly reduces the side effects of electromagnetic interference and electrostatic discharge that may occur due to excessive wiring in parallel busbars. Since the IIC is a two-way data transmission interface, if an application requires a voltage level conversion, such as conversion between 88 volts and 3.3 volts, an nc-specific ic is generally added. However, in order to simplify the circuit, complex logic logic devices (complex pr〇grammaMe l〇g1Cdevice, CPLD) are used to solve the difference between the peripheral chip and the central processing unit 5 M321548 (CPU) under the pressure of the hardware space. The problem, but a pity, because cpld has an innate obstacle, it is difficult to change once the foot is set as input or output, so the two-way IIC interface should be integrated in the CPLD. The original design concept is a certain degree of difficulty. [New content] Therefore, the purpose of this creation is to provide a control device capable of converting IIC levels, which allows wafers having different IIC levels to transmit data through the control device. According to the purpose of the present creation, the present invention provides a control device capable of converting 11C level, which is disposed between a central processing unit and a chip. The control device includes a plurality of first voltage pins and a plurality of first voltage pins. A pin, a state detection unit, and a logic transfer unit. The first voltage pin is connected to the lie interface of the central processing unit to receive a serial data (SDA) signal and a serial clock (SCL) signal output by the central processing unit, and the second voltage pin is connected to the chip. IIC interface. The state detecting unit determines whether the control device enters a start condition or a stop condition (st〇p condition) according to a first condition and a second condition, respectively. When the start state occurs, the logic operation unit sets the central processing unit as the input terminal, and the chip is the output terminal, and counts the number of cycles of the column clock (SCL) signal. When the number of cycles is equal to a preset value, then The logical operation unit reverses the serial data signal M321548, the direction of the second direction and the CPU is the output end, and the = terminal, and the logical operation single secret data is specific to the data frame of the serial data signal. The value of the element, and the direction in which the data signal is transmitted. [Embodiment] The presently preferred embodiment is discussed in detail below. However, it should be understood that this creation provides many new concepts that can be applied, and that these ideas can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways of using the present invention and do not limit the scope of the present invention. Referring to Figure 1, it is a block diagram showing the control device of the present convertible iIC level. In the figure, the control device 11 includes a plurality of first voltage pins 111, a plurality of second voltage pins 112, a state detecting unit 114, and a logic unit 丨13. The first control unit 11 is disposed between a central processing unit 12 and a chip 13 - the first voltage pin 111 is connected to the 11C interface 121 of the central processing unit 12 to receive a serial data output by the central processing unit 12. The (SDA) signal 141 and a series of clock (SCL) signals 142' and the second voltage pin 112 are coupled to the nc interface 131 of the wafer 13. In one embodiment, the control device is a complex programmable logic device (CLD), and the wafer 13 is a memory chip or any wafer having an 11C interface. The first voltage pin m can be 7 M321548 to receive a 1.8 volt pin' and the second power pin pin ι 2 can be a receiving pin of 3.3 volts. The state detecting unit 114 determines whether the logical operation unit 113 should enter a start condition condition according to the -th condition. In an embodiment, the first condition may be when the serial data signal 141 appears - negative edge (falUng) and the serial clock signal 142 appears - polls the negative edge (p 〇 1 Hngfaliingedge). When the logical operation unit 113 enters the start state, the logical operation unit 113 sets the central processing unit 12 as an input terminal, and the wafer 13 is an output terminal, and counts the number of cycles of the serial clock signal 142. When the number of cycles is equal to a predetermined value, then the logic unit 113 reverses the direction of the data signal 141 and sets the central processor 12 as the output and the wafer 13 as the input. In a practical example, this preset value is 9. In an embodiment, in the ninth clock of the SCl nickname, the ACK state is after the SCL signal is after R/w, so that the central processor 12 is set as the output terminal and the wafer 13 is the input terminal. The central processor a receives an acknowledgment (ACK) signal from the wafer 13 back. In turn, the logic operation unit 113 determines the direction of data transfer of the serial data signal 141 based on the value of the specific bit of the data frame of the serial data signal 141. The state detecting unit 114 determines whether the logical operation unit 113 should enter a stop-type cancer according to a second condition (3 叩t i〇n). In an embodiment of M321548, the second condition may be when a stringing clock signal 142 exhibits a rising edge and the serial data signal 141 exhibits a polling rising edge. Please refer to FIG. 2, which is a flow chart showing the operation of the control device of the present convertible inner circuit bus (11C) level. In the figure, the operation process corresponds to the control device 11 shown in the figure. The insertion process includes the following steps: Step 21: Connect the IIC interface 121 of the central processing unit 12 to the plurality of first voltage pins of the control device 11. m, and the first voltage pin U2 of the control 4 is connected to the iic interface 131 of a wafer 13. The well-known 11 (the interface is an SM wiring and an SCL) wiring, so the control device u connecting the SM and SCL wiring of the CPU 12 to the control device 11 is a complex programmable logic device, and the wafer 13 It is a memory chip or any wafer with an 11C interface. Step 22: The control device 11 receives one of the SDA signals 141 and an apostrophe 142 output by the central processing unit 12 through the first voltage pin lu. Since I ic is a synchronous transmission protocol, the main J uses the SCL to enter the clock by the master, thereby synchronizing the timing sequence between the master=slave and the slave (Slave) and the SDA. In this embodiment, as the master terminal cpu 21 ^ f transfer an SDA signal and an SCL signal to the CPLD 22, the other SDA signal includes at least the memory chip 23 (from the M321548 genre) Address, read/write (R/W) and written data, and the IIC standard mode is taken as an example, as in Table 1, this table 1 is the data frame of the SDA signal, where the address is Has 7 bits, read/write (R/W) has 1 bit and data (DATA) has 7 bits. Please note that this data format is included after the address bit and the data bit. A 1-bit Acknowledge (Ack) signal is issued from the chip (slave). Address Read/Write Confirmation Data Confirmation (Address) (R/W) (Ack) (DATA) (Ack) Table 1
步驟23 :狀態偵測單元114判斷是否串列數據 信號141中出現一負緣且串列時脈信號142中出現 一輪詢負緣，若是，則執行步驟25。如第3A圖所 不’其繪示SDA信號及SCL信號之波形圖。且由圖 中可知，當IIC沒有動作時，SCL和SDA都保持 在高電位（H)，之後，CPU先在SDA送出低電位（L)， 經一小段時間後，再將SCL變成低電位，此為開始 狀態之判斷條件。 ^步驟24 :邏輯運算單元進入開始狀態，設 定中央處理器12為輸入端，而晶片13為輸出端， 亦即中央處理器12可透過IIC介面121、控制狀置 11，IIC介面13卜將資料傳送至晶片13,且邏輯 運异單元113係計數SCL信號142之一周期數目。 M321548 在一實施例中，CPU 21(主控端）可於此步驟輸入位 址至晶片13(從屬端）。 步驟25:當周期數目等於一預設數值，例如9， 則邏輯運算單元113反向SCL信號142之方向，設 定中央處理器12為輸出端，且設定晶片13為輸入 端。在一實施例中，當計數SCL信號之周期數目為 弟9個時脈時，晶片13發出一位址確認回應 (Address Acknowledge)至 CPU 12，使得 CPU 12 能 判讀晶片13是否接收到此SDA信號141之位址。如 第3B圖所示，前述於SCL信號之第9個時脈時，係 是處於SCL信號於R/W之後的ACK狀態。 步驟26 ··邏輯運算單元113根據sda信號141 之資料格式之特定位元之值，而決定SDA信號141 之資料傳送的方向。請參閱表格1，前述特定位元 之值亦為SDA信號之資料格式之第8位元lbit讀/ 寫（R/W)，為人熟知的，ibi1： r/w以二進制，，〇，，及 二進制” Γ分別代表CPU對晶片進行一寫入動作 及CPU對晶片進行一讀取動作。 步驟27 ··狀態偵測單元114判斷是否SCL信號 142出現正緣（rising edge)且SDA信號141出現輪 詢正緣（polling rising edge)，若是，則執行步驟 28。 步驟28 ·則邏輯運算單元113進入一停止狀態 (stop condition)。如第3A圖所示，其繪示於cpu) 11 M321548 停止狀態下，SDA信號及SCL信號之波形圖，由圖 中可知，當CPU12(主控端）完成和晶片13(從屬端） 的動作後，先將SCL釋放至高電位（H)，經一小段 時間再將SDA釋放至南電位’此為停止狀態之判斷 條件。 在一實施例中，CPU透過CPLD之11C界面而將 SDA信號之7位元資料傳送至記憶體晶片，及記憶 體晶片透過CPLD回傳資料確認回應（dataStep 23: The state detecting unit 114 determines whether a negative edge occurs in the serial data signal 141 and a polling negative edge appears in the serial clock signal 142. If yes, step 25 is performed. As shown in Fig. 3A, the waveform diagrams of the SDA signal and the SCL signal are shown. As can be seen from the figure, when IIC does not operate, both SCL and SDA remain at high potential (H). After that, the CPU first sends a low potential (L) to SDA, and after a short period of time, SCL is turned low. This is the judgment condition of the start state. Step 24: The logic operation unit enters a start state, the central processing unit 12 is set as an input terminal, and the chip 13 is an output terminal, that is, the central processing unit 12 can pass through the IIC interface 121, the control device 11, and the IIC interface 13 The transfer to the wafer 13 is performed, and the logical transfer unit 113 counts the number of cycles of the SCL signal 142. M321548 In an embodiment, the CPU 21 (master) can input the address to the chip 13 (slave end) at this step. Step 25: When the number of cycles is equal to a predetermined value, for example 9, the logic operation unit 113 reverses the direction of the SCL signal 142, sets the central processing unit 12 as an output terminal, and sets the wafer 13 as an input terminal. In one embodiment, when the number of cycles of counting the SCL signal is 9 clocks, the wafer 13 issues an Address Acknowledge to the CPU 12, so that the CPU 12 can interpret whether the wafer 13 receives the SDA signal. 141 address. As shown in Fig. 3B, the ninth clock of the SCL signal is in the ACK state after the SCL signal is after R/W. Step 26: The logic operation unit 113 determines the direction of data transfer of the SDA signal 141 based on the value of the specific bit of the data format of the sda signal 141. Please refer to Table 1. The value of the above specific bit is also the 8th bit lbit read/write (R/W) of the data format of the SDA signal. It is well known that ibi1: r/w is binary, 〇,, And binary "" indicates that the CPU performs a write operation on the wafer and the CPU performs a read operation on the wafer. Step 27: The state detecting unit 114 determines whether a rising edge of the SCL signal 142 occurs and the SDA signal 141 appears. Polling rising edge, if yes, proceed to step 28. Step 28: The logic operation unit 113 enters a stop condition. As shown in Fig. 3A, it is shown in cpu) 11 M321548 In the state, the waveform diagram of the SDA signal and the SCL signal, as shown in the figure, when the CPU 12 (master) completes and the operation of the chip 13 (slave), the SCL is released to the high potential (H) for a short period of time. The SDA is released to the south potential. This is the judgment condition of the stop state. In one embodiment, the CPU transmits the 7-bit data of the SDA signal to the memory chip through the 11C interface of the CPLD, and the memory chip is returned through the CPLD. Data confirmation response (data
Acknowledge)至CPU，接著CPLD便可控制CPU與記 憶體晶片之11C介面之間的資料讀寫。 雖然本創作已以較佳實施例揭露如上，然其並 非用以限定本創作，任何熟習此技藝者，在不脫離 本創作之精神和範圍内，當可作各種之更動與潤 飾，因此本創作之保護範圍當視後附之申請專利範 圍所界定者為準。 【圖式簡單說明】 為讓本創作之上述和其他目的、特徵、優點與 實施例能更明顯易懂，所附圖式之詳細說明如下： 第1圖係為本創作之可轉換nc位準之控制裝 置之方塊圖； 第2圖係為本創作之可轉換IIC位準之控制裝 置之方塊圖之操作過程之步驟流程圖； 12 M321548 第3A圖係為繪示進入開始狀態下及進入停止 狀態下之SDA信號及SCL信號之波形圖；以及 第3B圖係為繪示資料傳輸期間，SDA信號及SCL 信號之波形圖。 【主要元件符號說明】 11 :控制裝置； 111 :第一電壓接腳； 112 :第二電壓接腳； 113 :狀態偵測單元； 114 :邏輯運算單元； 12 :中央處理器； 121 : IIC 介面； 13·晶片， 131 : IIC 介面； 141 : SDA 信號； 142 : SCL信號；以及 21〜28:步驟流程。 13Acknowledge) to the CPU, then the CPLD can control the reading and writing of data between the CPU and the 11C interface of the memory chip. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the present invention, and anyone skilled in the art can make various changes and refinements without departing from the spirit and scope of the present invention. The scope of protection is subject to the definition of the scope of the patent application. BRIEF DESCRIPTION OF THE DRAWINGS In order to make the above and other objects, features, advantages and embodiments of the present invention more obvious and obvious, the detailed description of the drawings is as follows: Figure 1 is a convertible nc level of the present creation. The block diagram of the control device; Fig. 2 is a flow chart of the operation process of the block diagram of the control device of the convertible IIC level of the present invention; 12 M321548 Fig. 3A shows the entry into the start state and enters the stop The waveform diagram of the SDA signal and the SCL signal in the state; and the 3B diagram is a waveform diagram showing the SDA signal and the SCL signal during data transmission. [Main component symbol description] 11 : Control device; 111 : First voltage pin; 112 : Second voltage pin; 113 : Status detection unit; 114 : Logic operation unit; 12 : Central processing unit; 121 : IIC interface 13·chip, 131: IIC interface; 141: SDA signal; 142: SCL signal; and 21~28: step flow. 13