US11127813B2 - Semiconductor inductors - Google Patents

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• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
  • H01L23/64—Impedance arrangements
  • H01L23/645—Inductive arrangements
• • H01L28/10—
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D1/00—Resistors, capacitors or inductors
  • H10D1/20—Inductors
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
  • H01F17/00—Fixed inductances of the signal type
  • H01F17/04—Fixed inductances of the signal type with magnetic core
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02365—Forming inorganic semiconducting materials on a substrate
  • H01L21/02436—Intermediate layers between substrates and deposited layers
  • H01L21/02439—Materials
  • H01L21/02441—Group 14 semiconducting materials
  • H01L21/02447—Silicon carbide
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  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
  • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
  • H01L21/565—Moulds
• • H—ELECTRICITY
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  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
  • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
  • H01L24/10—Bump connectors ; Manufacturing methods related thereto
  • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
  • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
  • H01L2224/10—Bump connectors; Manufacturing methods related thereto
  • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
  • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
  • H01L2224/161—Disposition
  • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
  • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
  • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
  • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
  • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
  • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
  • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
  • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
  • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
  • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
  • H01L25/16—Assemblies consisting of a plurality of semiconductor or other solid state devices the devices being of types provided for in two or more different subclasses of H10B, H10D, H10F, H10H, H10K or H10N, e.g. forming hybrid circuits
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
  • H01L25/18—Assemblies consisting of a plurality of semiconductor or other solid state devices the devices being of the types provided for in two or more different main groups of the same subclass of H10B, H10D, H10F, H10H, H10K or H10N

Definitions

• the present disclosure relates to the inductors used on semiconductor dies.
• Planar inductors both hollow and magnetic core, are used in conjunction with semiconductor circuits. Planar inductors may consume considerable die surface area. Given the increasing emphasis on smaller and miniaturized devices, increasing die surface area frequently is either not an option or presents an extremely unattractive option that may increase the size of the host device.
• FIG. 1 is a cross-section of an illustrative semiconductor inductor in which a coil is patterned or otherwise deposited on a stop layer that has been deposited on a sacrificial substrate, such as a silicon wafer, in accordance with at least one embodiment described herein;
• FIG. 2A is a cross-section of an illustrative system that includes a semiconductor inductor communicably coupled to an active die that includes a number of conductors or conductive pads disposed on, about, or across a surface of a substrate, a dielectric layer at least partially covers the conductors and the substrate, in accordance with at least one embodiment described herein;
• FIG. 2B is a cross section of an illustrative system that includes the semiconductor inductor and the active die depicted in FIG. 2A and in which a mold compound has been disposed on, across, or about the active die and about at least a portion of the perimeter of the semiconductor inductor, in accordance with at least one embodiment described herein;
• FIG. 2C is a cross-section of an illustrative system that includes the semiconductor inductor and the active die depicted in FIG. 2A and in which at least a portion of the sacrificial substrate has been removed from the semiconductor inductor to provide a void proximate the semiconductor inductor while the mold compound remains unaffected, in accordance with at least one embodiment described herein;
• FIG. 2D is a cross-section of an illustrative system that includes the semiconductor inductor and the active die depicted in FIG. 2A and in which mold compound has been deposited in the void space formed by the removal of the sacrificial substrate, in accordance with at least one embodiment described herein;
• FIG. 2E is a cross-section of an illustrative system that includes the semiconductor inductor and the active die depicted in FIG. 2A and in which a magnetic material has been deposited in the void space formed by the removal of the sacrificial substrate, in accordance with at least one embodiment described herein;
• FIG. 3A is a cross-section of an illustrative three-dimensional semiconductor inductor system that includes a first semiconductor inductor with the sacrificial substrate removed, communicably coupled to an active die, in accordance with at least one embodiment described herein;
• FIG. 3B is a cross-section of an illustrative three-dimensional semiconductor inductor system in which a second semiconductor inductor has been communicably coupled to the first semiconductor inductor depicted in FIG. 3A , in accordance with at least one embodiment described herein;
• FIG. 3C is a cross-section of an illustrative stacked, three-dimensional, semiconductor inductor system in which the second sacrificial substrate has been removed from the second semiconductor inductor, in accordance with at least one embodiment described herein;
• FIG. 3D is a cross-section of an illustrative stacked, three-dimensional, semiconductor inductor system in which a third semiconductor inductor has been communicably coupled to the second semiconductor inductor depicted in FIG. 3C , in accordance with at least one embodiment described herein;
• FIG. 3E is a cross-section of an illustrative stacked, three-dimensional, semiconductor inductor system in which the third sacrificial substrate has been removed from the third semiconductor inductor, in accordance with at least one embodiment described herein;
• FIG. 4A is a cross-section of an illustrative semiconductor inductor system that includes a first semiconductor inductor, communicably coupled to an active die, in accordance with at least one embodiment described herein;
• FIG. 4B is a cross-section of the illustrative semiconductor inductor system that includes the first semiconductor inductor, communicably coupled to an active die as depicted in FIG. 4A , and in which a stop layer has been deposited on, across, or about at least a portion of the surface of the active die, in accordance with at least one embodiment described herein;
• FIG. 4C is a cross-section of the illustrative semiconductor inductor system that includes the first semiconductor inductor, communicably coupled to the active die as depicted in FIG. 4B , and in which a removable etch resist has been deposited on, about, or across at least a portion of the exposed surface the active die, in accordance with at least one embodiment described herein;
• FIG. 4D is a cross-section of the illustrative semiconductor inductor system that includes the first semiconductor inductor, communicably coupled to the active die depicted in FIG. 4C and in which at least a portion of the sacrificial substrate has been removed from the first semiconductor inductor to provide a void proximate the first semiconductor inductor while the removable etch resist remains unaffected, in accordance with at least one embodiment described herein;
• FIG. 4E is a cross-section of the illustrative semiconductor inductor system that includes the first semiconductor inductor, communicably coupled to the active die depicted in FIG. 4D and in which at least a portion of the removable etch resist has been removed to expose at least a portion of the exposed surface of the active die, in accordance with at least one embodiment described herein;
• FIG. 4F is a cross-section of the illustrative semiconductor inductor system that includes the first semiconductor inductor and a conductively coupled second semiconductor inductor coupled to an active die, in accordance with at least one embodiment described herein;
• FIG. 5A is a cross-section of an illustrative semiconductor inductor system that includes a semiconductor inductor having the sacrificial substrate removed and replaced with a magnetic material, in accordance with at least one embodiment described herein;
• FIG. 5B is a cross-sectional elevation of an illustrative semiconductor inductor system that includes the semiconductor inductor that includes a magnetic material disposed proximate the stop layer, communicably coupled to the active die in which at least a portion of the removable etch resist has been removed to expose at least a portion of the exposed surface of the active die, in accordance with at least one embodiment described herein;
• FIG. 6 is a plan view of an illustrative system that includes a plurality of semiconductor inductors, in accordance with at least one embodiment described herein;
• FIG. 7 is a cross-sectional elevation of an illustrative embedded wafer level ball grid array (eWLB) semiconductor package using through mold vias (TMVs) and including a number of semiconductor inductors such as described in detail with regard to FIGS. 1-6 , in accordance with at least one embodiment described herein;
• eWLB embedded wafer level ball grid array
• TSVs through mold vias
• FIG. 8 is a cross-sectional elevation of another illustrative embedded wafer level ball grid array (eWLB) semiconductor package in which both the solder balls forming the ball grid array and the semiconductor inductor are disposed on the upper surface of the active die, in accordance with at least one embodiment described herein;
• eWLB embedded wafer level ball grid array
• FIG. 9 is a cross-sectional elevation of another illustrative embedded wafer level ball grid array (eWLB) semiconductor package using through mold vias (TMVs) and back-side metallization, in accordance with at least one embodiment described herein;
• eWLB embedded wafer level ball grid array
• FIG. 10 is a cross-sectional elevation of an illustrative wafer level chip scale package (WLCSP) semiconductor package in which a semiconductor inductor is conductively coupled to the upper surface of the active die, in accordance with at least one embodiment described herein;
• WLCSP wafer level chip scale package
• FIG. 11 is a cross-sectional elevation of an embedded wafer level ball grid array (eWLB) semiconductor package that includes a mold compound disposed on the lower surface of the active die and a removable etch resist disposed on the upper surface of the active die, in accordance with at least one embodiment described herein;
• eWLB embedded wafer level ball grid array
• FIG. 12 is a cross-sectional elevation of an illustrative wafer level chip scale package (WLCSP) semiconductor package in which a semiconductor inductor is fabricated using a removable etch resist and conductively coupled to the upper surface of the active die, in accordance with at least one embodiment described herein;
• WLCSP wafer level chip scale package
• FIG. 13 is a cross-sectional elevation of an illustrative wafer level chip scale package (WLCSP) semiconductor package in which semiconductor inductors are fabricated using a removable etch resist and conductively coupled to the active die by through silicon vias (TSVs), in accordance with at least one embodiment described herein;
• WLCSP wafer level chip scale package
• FIG. 14 is a cross-sectional elevation of an illustrative stacked die in which conductive members, such as copper pillars, couple a second semiconductor die to an active die encapsulated in a dielectric material and in which the active die is conductively coupled to a redistribution layer, in accordance with at least one embodiment described herein;
• conductive members such as copper pillars
• FIG. 15 is a cross-sectional elevation of an illustrative stacked die in which conductive members, such as copper pillars, couple a second semiconductor die to an active die coupled to a semiconductor inductor and in which the active die is conductively coupled to a redistribution layer, in accordance with at least one embodiment described herein;
• conductive members such as copper pillars
• FIG. 16 is a high-level flow diagram of an illustrative semiconductor inductor fabrication method in which a planar coil having one or more windings is formed or otherwise patterned onto a stop layer that has been deposited on a sacrificial substrate, in accordance with at least one embodiment described herein;
• FIG. 17 is a high-level flow diagram of an illustrative semiconductor inductor fabrication method in which at least a portion of the sacrificial substrate is removed to expose the stop layer, in accordance with at least one embodiment described herein;
• FIG. 18 is a high-level flow diagram of an illustrative semiconductor package fabrication method in which the semiconductor inductor is conductively coupled to an active die, in accordance with at least one embodiment described herein.
• a coil may be patterned or otherwise formed on a stop layer that has been deposited on a sacrificial substrate material, e.g., a silicon wafer.
• the coil may be covered with a dielectric material and channels or vias may be formed in the dielectric material, exposing the coil.
• Conductive members such as solder balls, solder bumps, or conductive pillars may be deposited, inserted, or otherwise formed in the channels or vias to conductively couple the coil to an external circuit, such as found on a semiconductor die.
• All or a portion of the sacrificial substrate may be removed in the region of the structure proximate the coil.
• a magnetic material such as a magnetic paste, may be deposited proximate the coil after removal of the sacrificial substrate.
• the planar (i.e., two-dimensional) coil may be encapsulated and coupled to a semiconductor die using the previously deposited conductive members.
• additional coils may be stacked to provide a three dimensional coil structure using a similar construction technique: invert the coil, use the conductive members to conductively couple to the underlying coil, and remove the sacrificial substrate. Any number of coils, each having one or more turns, may be combined.
• a gap may exist between the coil and the surface of the semiconductor die and, for stacked coils, between successive coil turns in the stack.
• the gap between the lowermost coil in the stack and the semiconductor die surface may be partially or filled by flowing an electrically insulating adhesive or underfill material between the lowermost coil in the stack and the surface of the semiconductor die.
• the gaps between successive coils may be filled by flowing an electrically insulating adhesive or underfill material between successive coils.
• the systems and methods described herein provide a single- or multi-turn coil that may be conductively coupled to an active die at the wafer level, i.e., prior to die singulation.
• the coil is formed on a stop layer deposited on a sacrificial substrate, such as a silicon carrier die.
• Conductive structures such as solder balls or conductive columns may be coupled to the coil and the coil encapsulated using a dielectric material.
• the coil may be coupled to an active die that is subsequently fully encapsulated, leaving only the sacrificial substrate exposed. Since the active die is encapsulated, the sacrificial substrate may be thinned or completely removed, for example using a wet-etch or plasma-etch, without exposing the active die to the etchant. Consequently, only the coil stack remains coupled to the active die after etching.
• Such construction offers significant, non-trivial, advantages that include: the thinnest possible coil structure for attachment to the active die since the sacrificial substrate may be partially or completely removed from the coil; compatibility with wafer level chip scale packaging (WLCSP) with the coil attached by the conductive members to the active die and using a removable resist as a first encapsulant; compatibility with existing manufacturing equipment and stack-up permitting the use of multiple materials (copper, aluminum, etc.) in a variety of line widths and thicknesses for coil fabrication; reduced area requirements on the active die; and, no handling of thin coil components.
• WLCSP wafer level chip scale packaging
• the semiconductor inductor may include: a first sacrificial substrate having a thickness, a first surface and a transversely opposed second surface; a first stop layer deposited across at least a portion of the first surface of the first sacrificial substrate; a first coil having a first surface and a second surface deposited across at least a portion of the first stop layer opposite the first sacrificial substrate; a first dielectric layer having a thickness disposed at least partially across the first coil; and at least one first conductive structure conductively coupled to the first coil and extending through the first dielectric layer thickness and projecting at least partially from the surface of the first dielectric layer opposite the first coil.
• a method of fabricating a first semiconductor inductor may include: depositing a first stop layer across at least a portion of a first surface of a first sacrificial substrate; forming a first coil having a first surface and an opposed second surface across at least a portion of the first stop layer opposite the first sacrificial substrate; depositing a first dielectric layer having a thickness at least partially across the first coil; and conductively coupling at least one first conductive structure to the first coil, the at least one first conductive structure extending through the thickness of the first dielectric layer and projecting at least partially from the surface of the first dielectric layer opposite the first coil.
• the semiconductor package may include: a semiconductor die; a semiconductor inductor conductively coupled to the semiconductor die, the semiconductor inductor including: a first sacrificial substrate having a thickness, a first surface and a second surface; a first stop layer deposited across at least a portion of the first surface of the first sacrificial substrate; a first coil having a first surface and a second surface deposited across at least a portion of the first stop layer opposite the first sacrificial substrate; a first dielectric layer having a thickness disposed at least partially across the first coil; and at least one first conductive structure conductively coupled to the first coil and extending through the thickness of the first dielectric layer and projecting at least partially from the surface of the first dielectric layer opposite the first coil, the at least one first conductive structure conductively coupled to the semiconductor die.
• a method of fabricating a first semiconductor package may include: the method comprising: forming a semiconductor inductor by: depositing a first stop layer across at least a portion of a first surface of a first sacrificial substrate having a first thickness; forming a first coil having a first surface and an opposed second surface across at least a portion of the first stop layer opposite the first sacrificial substrate; depositing a passivation layer and a first dielectric layer having a thickness at least partially across the first coil; and conductively coupling at least one first conductive structure to the first coil, the at least one first conductive structure extending through the thickness of the first dielectric layer and projecting at least partially from the surface of the first dielectric layer opposite the first coil; and conductively coupling the semiconductor inductor to a semiconductor die using the at least one conductive structure.
• top when used in relationship to one or more elements are intended to convey a relative rather than absolute physical configuration.
• an element described as an “uppermost element” or a “top element” in a device may instead form the “lowermost element” or “bottom element” in the device when the device is inverted.
• an element described as the “lowermost element” or “bottom element” in the device may instead form the “uppermost element” or “top element” in the device when the device is inverted.
• the term “logically associated” when used in reference to a number of objects, systems, or elements, is intended to convey the existence of a relationship between the objects, systems, or elements such that access to one object, system, or element exposes the remaining objects, systems, or elements having a “logical association” with or to the accessed object, system, or element.
• An example “logical association” exists between relational databases where access to an element in a first database may provide information and/or data from one or more elements in a number of additional databases, each having an identified relationship to the accessed element.
• accessing “A” will expose or otherwise draw information and/or data from “B,” and vice-versa.
• FIG. 1 is a cross-section of an illustrative semiconductor inductor 100 in which a coil 110 is patterned or otherwise deposited on a stop layer 120 that has been deposited on a sacrificial substrate 130 , such as a silicon wafer, in accordance with at least one embodiment described herein.
• a plurality of conductive structures 140 such as the solder balls illustrated in FIG. 1 , conductively couple to the coil 110 .
• At least one of a passivation layer and/or a dielectric layer 150 covers at least a portion of the coil 110 and surrounds the conductive structures 140 .
• the coil 110 may be patterned onto the stop layer 120 using any currently available or future developed deposition technique.
• Example deposition techniques include, but are not limited to: photolithography; electroplating; electro-less deposition; and similar.
• the coil 110 may have any dimensions, size, shape, or physical configuration. In embodiments, the coil 110 may be a two-dimensional coil having a plurality of concentric turns. In embodiments, the coil 110 may have only single turn.
• the coil 110 may have any regular physical shape, such as circular, oval, polygonal, and similar, or an irregular shape, such as trapezoidal, ovoid, and similar.
• the coil 110 may be fabricated from any conductive material including, but not limited to, one or more metals or metal alloys, one or more conductive polymers, or one or more conductive non-metallic materials, such as graphene.
• Example metals may include, but are not limited to: copper, copper alloys, aluminum, and aluminum alloys.
• the conductors forming the coil may have any width and/or thickness.
• the coil 110 may have a width of greater than: about 5 nanometers (nm); about 7 nm; about 10 nm; about 15 nm; about 20 nm; about 30 nm; about 50 nm; about 100 nm; about 250 nm; about 500 nm; about 1 ⁇ m; about 5 ⁇ m; about 10 ⁇ m.
• the coil 110 may be formed using a metal patterning process.
• the coil 110 may be formed using a patterning process such as: depositing a metal layer on the stop layer 120 ; depositing a photoresist on the metal layer; applying a mask to the photoresist and exposing the photoresist to electromagnetic radiation having a defined spectral content; selectively removing portions of the photoresist; etching the metal layer to produce the coil 110 ; and, removing the remaining photoresist from the coil structure.
• the coil may be formed using a patterning process such as: sputtering a metal (e.g., TiW/Cu) on the top layer 120 ; depositing a photoresist on the metal layer; applying a mask to the photoresist and exposing the photoresist to electromagnetic radiation having a defined spectral content; selectively removing portions of the photoresist; etching the metal layer to produce the coil 110 ; electro or electroless plating the resultant structure; strip the remaining photoresist; and, etching the TiW/Cu.
• a metal e.g., TiW/Cu
• the stop layer 120 may be deposited on, across, or about all or a portion of the sacrificial substrate 130 .
• the stop layer 120 may include one or more materials, compounds, or layers capable of preventing the passage of an etchant beyond the stop layer 120 .
• the stop layer 120 may include at least one of: silicon nitride (SiN); silicon carbide (SiC); Silicon Oxide (SiO 2 ).
• the stop layer 120 may be deposited using any currently available or future developed deposition technique.
• Example deposition techniques include, but are not limited to: chemical vapor deposition, physical vapor deposition, molecular beam epitaxy; electrochemical deposition; plasma enhanced chemical vapor deposition; spin coating; and similar.
• the stop layer 120 may have any thickness.
• the stop layer 120 may have a thickness of less than: about 20 nanometers (nm); about 30 nm; about 50 nm; about 70 nm; about 90 nm; or about 130 nm.
• the sacrificial substrate 130 provides structural support for the coil 110 and the stop layer 120 until fabrication of the coil structure is complete and the coil 110 is coupled to an active die.
• the sacrificial substrate 130 beneficially provides structural support for the coil 110 prior to communicably coupling the coil 110 to an active die and may be removed from the coil 110 once the coil is coupled to the active die, thereby beneficially reducing both the weight and thickness of the resultant semiconductor package.
• the sacrificial substrate may contain silicon.
• a silicon wafer may provide the sacrificial substrate 130 and multiple coils may be formed on the wafer prior to singulation.
• the sacrificial substrate 130 may have any thickness.
• the sacrificial substrate 130 may have a thickness of less than: about 800 micrometers ( ⁇ m); about 700 ⁇ m; about 600 ⁇ m; about 500 ⁇ m; about 400 ⁇ m; about 300 ⁇ m; or about 200 ⁇ m.
• the silicon wafer may have a diameter of: about 450 millimeter (mm); about 300 mm; about 200 mm; about 150 mm; about 130 mm; about 100 mm; about 76 mm; about 50 mm; or about 25 mm.
• the conductive structures 140 may include any device or feature capable of conductively coupling the inductor 100 to an external system, such as an active die. Any number and/or combination of conductive structure 140 may be used to communicably couple the coil 110 to an external device or system, such as an active die.
• the conductive structures 140 may include any currently available or future developed device and/or system capable of conductively coupling the inductor 100 to an external device or system.
• the conductive structures 140 may physically affix the inductor 100 to an external device or system.
• the conductive structures 140 may include one or more solder balls.
• the conductive structures 140 may include one or more conductive pillars. In some implementations, the conductive structures 140 may include solder bumps.
• the dielectric layer 150 is disposed on, across, or about the coil 110 and on, across, or about the stop layer 120 .
• the dielectric layer 150 encapsulates the coil 110 and at least partially encapsulates the conductive structures 140 .
• at least a portion of the conductive structures 140 may extend or project beyond the surface of the dielectric layer 150 opposite the coil 110 .
• the dielectric layer may include one or more electrically insulating materials.
• Example dielectric materials include, but are not limited to: nanoporous silica; hydrogensilsesquioxanes (HSQ); Teflon®-AF (polytetrafluoethylene or PTFE); silicon oxyflouride (FSG); silicon dioxide (SiO 2 ); silicon nitride; alkali halides; barium titanate (BaTiO 3 ); hafnium oxide (HfO 2 ); tantalum oxide (TaO 5 ); tungsten oxide (WO 3 ); zirconium oxide (ZrO 2 ); and similar.
• HSQ hydrogensilsesquioxanes
• Teflon®-AF polytetrafluoethylene or PTFE
• silicon oxyflouride FSG
• silicon dioxide SiO 2
• silicon nitride alkali halides
• barium titanate (BaTiO 3 ) hafnium oxide (HfO 2 ); tantalum oxide (TaO 5 ); tungs
• FIG. 2A is a cross-section of an illustrative system 200 A that includes a semiconductor inductor 100 communicably coupled to an active die 210 that includes a number of conductors or conductive pads 220 disposed on, about, or across a surface of a substrate 230 , a dielectric layer 240 at least partially covers the conductors 220 and the substrate 230 , in accordance with at least one embodiment described herein. It should be noted that the embodiments described in FIGS. 2A through 2E may be performed at the wafer level, i.e., prior to die singulation.
• the semiconductor inductor 100 may be inverted (such that the conductive structures 140 extend from the “bottom” of the semiconductor inductor 100 .
• the conductive structures 140 may contact and be physically and conductively coupled to the same or a different number of conductors 220 disposed on the surface of the active die 210 .
• the dielectric layer 240 may be disposed at least partially about the conductive structures 140 and conductors 220 . In embodiments, the dielectric layer 240 may electrically isolate the semiconductor inductor 100 from the active die 210 .
• the active die 210 may include any type or number of electrical components, semiconductor devices, and/or logic elements.
• the active die 210 may include one or more processors, microprocessor, controllers, microcontrollers, programmable gate arrays (PGAs), systems on a chip (SoCs), reduced instruction set computers (RISCs), application specific integrated circuits (ASICs), digital signal processors (DSPs), central processing units (CPUs), graphical processing units (GPUs), and similar.
• the active die 210 may include one or more mobile device processors, communications interfaces, such as: IEEE 802.11 (Wi-Fi); Bluetooth®, Near Field Communication (NFC), or combinations thereof.
• FIG. 2B is a cross section of an illustrative system 200 B that includes the semiconductor inductor 100 and the active die 210 depicted in FIG. 2A and in which a mold compound 250 has been disposed on, across, or about the active die 210 and about at least a portion of the perimeter of the semiconductor inductor 100 , in accordance with at least one embodiment described herein.
• the mold compound 250 may include any electrically non-conductive material, compound, or substance capable of protecting the active die 210 .
• Example mold compounds include, but are not limited to: elastomers, such as silicone, polyurethane, chloroprene, butyl, polybutadiene, neoprene, natural rubber or isoprene, and other synthetic rubber or compounds; composite compounds that include resins made from two or more constituent materials with significantly different physical or chemical properties; thermoplastics that include polymers that turn to liquid when heated and turn solid when cooled; thermosets that include polymer materials that have been irreversibly cured; and silicone molding compounds.
• the upper surface of the mold compound 250 opposite the active die may be lower, higher, or the same elevation as the upper surface of the sacrificial substrate 130 opposite the stop layer 120 .
• FIG. 2C is a cross-section of an illustrative system 200 C that includes the semiconductor inductor 100 and the active die 210 depicted in FIG. 2A and in which at least a portion of the sacrificial substrate 130 has been removed from the semiconductor inductor 100 to provide a void 260 proximate the semiconductor inductor 100 while the mold compound 250 remains unaffected, in accordance with at least one embodiment described herein. All or a portion of the thickness of the sacrificial substrate 130 may be removed using one or more material removal systems, processes, or devices to form the void 260 proximate the semiconductor inductor 100 .
• all or a portion of the thickness of the sacrificial substrate 130 may be removed using wet chemistry on a spin etcher.
• the etching process may halt upon reaching the stop layer 120 .
• the mold compound 250 remains unaffected by the etching process.
• FIG. 2D is a cross-section of an illustrative system 200 D that includes the semiconductor inductor 100 and the active die 210 depicted in FIG. 2A and in which mold compound 270 has been deposited in the void space 260 formed by the removal of the sacrificial substrate 130 , in accordance with at least one embodiment described herein.
• the mold compound 270 may be the same as or different from the mold compound 250 previously deposited on, about, or across the active die 210 .
• the upper surface 272 of mold compound 270 may be above, below, or at the same elevation as the upper surface 252 of mold compound 250 .
• the upper surface 272 of mold compound and the upper surface 252 of mold compound 250 may be mechanically planarized, chemically planarized, or any combination thereof.
• the upper surface 272 of mold compound 270 and the upper surface 252 of mold compound 250 may be finished using one or more chemical-mechanical planarization (CMP) processes.
• CMP chemical-mechanical planarization
• FIG. 2E is a cross-section of an illustrative system 200 E that includes the semiconductor inductor 100 and the active die 210 depicted in FIG. 2A and in which a magnetic material 280 has been deposited in the void space 260 formed by the removal of the sacrificial substrate 130 , in accordance with at least one embodiment described herein.
• the upper surface 282 of the magnetic material 280 may be above, below, or at the same elevation as the upper surface 252 of mold compound 250 .
• the upper surface 282 of the magnetic material 280 and the upper surface 252 of mold compound 250 may be mechanically planarized, chemically planarized, or any combination thereof.
• the upper surface 282 of the magnetic material 280 and the upper surface 252 of mold compound 250 may be finished using one or more chemical-mechanical planarization (CMP) processes.
• CMP chemical-mechanical planarization
• the magnetic material 280 improves the inductive performance of the semiconductor inductor 100 .
• the magnetic material 280 may include one or more non-electrically conductive materials demonstrating magnetic properties.
• Example magnetic materials may include one or more soft magnetic composite materials, such as one or more ferritic materials encapsulated in a non-electrically conductive material or polymer).
• the backside of the setup can be finally cover by a protection layer, e.g. backside protection tape (BSP).
• BSP backside protection tape
• FIG. 3A is a cross-section of an illustrative three-dimensional semiconductor inductor system 300 A that includes a first semiconductor inductor 110 A with the sacrificial substrate 130 A removed, communicably coupled to an active die 210 , in accordance with at least one embodiment described herein.
• a first semiconductor inductor 110 A is physically and communicably coupled to the active die 210 by a plurality of conductive structures 140 A.
• the active die 210 has been covered with a mold compound 250 and the sacrificial substrate 130 A has been removed from the semiconductor inductor 110 A, leaving a void space 260 above the semiconductor inductor 110 A.
• FIG. 3B is a cross-section of an illustrative three-dimensional semiconductor inductor system 300 B in which a second semiconductor inductor 100 B has been communicably coupled to the first semiconductor inductor 100 A depicted in FIG. 3A , in accordance with at least one embodiment described herein.
• removal of at least a portion of the first stop layer 120 A exposes the first semiconductor inductor coil 110 A.
• portions of the first stop layer 120 A may be selectively removed using one or more laser material removal processes or using one or more lithographic and reactive ion etching processes.
• the first stop layer 120 A may be removed in its entirety.
• the first stop layer 120 A may be completely removed using one or more plasma etch processes.
• the second semiconductor inductor 100 B may be physically and communicably coupled to the first semiconductor inductor 100 A using second conductive structures 140 B.
• a first etch seal 310 A may be added about all or a portion of the periphery of the second semiconductor inductor 100 B.
• a first gap 320 A may exist between the first semiconductor inductor 100 A and the second semiconductor inductor 100 B.
• one or more non-electrically conductive underfill materials may be used to at least partially fill the first gap 320 A between the first semiconductor inductor 100 A and the second semiconductor inductor 100 B.
• FIG. 3C is a cross-section of an illustrative stacked, three-dimensional, semiconductor inductor system 300 C in which the second sacrificial substrate 130 B has been removed from the second semiconductor inductor 100 B, in accordance with at least one embodiment described herein.
• All or a portion of the thickness of the second sacrificial substrate 130 B may be removed using one or more material removal systems, processes, or devices.
• all or a portion of the thickness of the second sacrificial substrate 130 B may be removed using wet chemistry on a spin etcher.
• the etching process may halt upon reaching the second stop layer 120 B.
• the mold compound 250 remains unaffected by the wet chemistry etching process.
• the presence of the first etch stop 310 A prevents the wet etch process from entering the first gap 320 A and affecting the underlying first semiconductor inductor 100 A.
• FIG. 3D is a cross-section of an illustrative stacked, three-dimensional, semiconductor inductor system 300 D in which a third semiconductor inductor 100 C has been communicably coupled to the second semiconductor inductor 100 B depicted in FIG. 3C , in accordance with at least one embodiment described herein.
• removal of at least a portion of the second stop layer 120 B exposes at least a portion of the second coil 110 B.
• portions of the second stop layer 120 B may be selectively removed using one or more laser material removal processes or using one or more lithographic and reactive ion etching processes.
• the second stop layer 120 B may be completely removed.
• the second stop layer 120 B may be completely removed using one or more plasma etch processes.
• the third semiconductor inductor 100 C may be physically and communicably coupled to the second semiconductor inductor 100 B using the third conductive structures 140 C.
• a second etch seal 310 B may be added about all or a portion of the periphery of the third semiconductor inductor 100 C.
• a second gap 320 B may exist between the second semiconductor inductor 100 B and the third semiconductor inductor 100 C.
• one or more non-electrically conductive underfill materials may be used to at least partially fill the second gap 320 B between the second semiconductor inductor 100 B and the third semiconductor inductor 100 C.
• FIG. 3E is a cross-section of an illustrative stacked, three-dimensional, semiconductor inductor system 300 E in which the third sacrificial substrate 130 C has been removed from the third semiconductor inductor 100 C, in accordance with at least one embodiment described herein.
• All or a portion of the thickness of the third sacrificial substrate 130 C may be removed using one or more material removal systems, processes, or devices.
• all or a portion of the thickness of the third sacrificial substrate 130 C may be removed using wet chemistry on a spin etcher.
• the etching process may halt upon reaching the third stop layer 120 C.
• the mold compound 250 remains unaffected by the wet chemistry etching process.
• the presence of the second etch stop 310 B prevents the wet etch process from entering the second gap 320 B and affecting the underlying second semiconductor inductor 100 B.
• FIG. 4A is a cross-section of an illustrative semiconductor inductor system 400 A that includes a first semiconductor inductor 100 A, communicably coupled to an active die 210 , in accordance with at least one embodiment described herein.
• a first semiconductor inductor 100 A is physically and communicably coupled to the active die 210 by a plurality of conductive structures 140 A.
• an electrically non-conductive material or filler 410 may be disposed at least partially beneath the first semiconductor inductor 100 A.
• the electrically non-conductive material or filler 410 may physically bond or adhere the first semiconductor inductor 100 A to the active die 210 .
• a removable etch resist may be used to encapsulate and protect the active die 210 .
• the use of a removable etch resist compound would permit re-exposing the active die 210 after the conductive coupling of one or more semiconductor inductors 100 to the active die 210 .
• Such a construction would beneficially facilitate the attachment of solder balls or similar conductive structures to the exposed surface 242 of the active die 210 to provide a wafer level package.
• FIG. 4B is a cross-section of the illustrative semiconductor inductor system 400 B that includes the first semiconductor inductor 100 A, communicably coupled to an active die 210 as depicted in FIG. 4A , and in which a stop layer 420 has been deposited on, across, or about at least a portion of the surface of the active die 210 , in accordance with at least one embodiment described herein.
• the stop layer 420 may include a layer that includes carbon or one or more carbon containing compounds.
• the stop layer 420 may extend across all or a portion of the surface 242 of the active die 210 , but may not extend beneath the first semiconductor inductor 100 A. In other embodiments, the stop layer 420 may extend across all or a portion of the surface 242 of the active die 210 and at least partially beneath the first semiconductor inductor 100 A.
• FIG. 4C is a cross-section of the illustrative semiconductor inductor system 400 C that includes the first semiconductor inductor 100 A, communicably coupled to the active die 210 as depicted in FIG. 4B , and in which a removable etch resist 430 has been deposited on, about, or across at least a portion of the exposed surface 242 the active die 210 , in accordance with at least one embodiment described herein.
• the removable etch resist 430 may include any compound that provides sufficient resistance to the wet chemistry used to remove the sacrificial substrate 130 from the first semiconductor inductor 100 A, but remains removable to permit additional processing of the active die after the assembly of the first semiconductor inductor 100 A to the active die 210 .
• the removable etch resist 430 may include one or more photosensitive removable etch resist compounds.
• FIG. 4D is a cross-section of the illustrative semiconductor inductor system 400 D that includes the first semiconductor inductor 100 A, communicably coupled to the active die 210 depicted in FIG. 4C and in which at least a portion of the sacrificial substrate 130 has been removed from the first semiconductor inductor 100 A to provide a void 260 proximate the first semiconductor inductor 100 A while the removable etch resist 430 remains unaffected, in accordance with at least one embodiment described herein. All or a portion of the thickness of the sacrificial substrate 130 may be removed using one or more material removal systems, processes, or devices to form the void 260 proximate the first semiconductor inductor 100 A.
• all or a portion of the thickness of the sacrificial substrate 130 may be removed using wet chemistry on a spin etcher.
• the etching process may halt upon reaching the stop layer 120 .
• the removable etch resist 430 remains unaffected by the wet chemistry etching process.
• FIG. 4E is a cross-section of the illustrative semiconductor inductor system 400 E that includes the first semiconductor inductor 100 A, communicably coupled to the active die 210 depicted in FIG. 4D and in which at least a portion of the removable etch resist 430 has been removed to expose at least a portion of the exposed surface 242 of the active die 210 , in accordance with at least one embodiment described herein.
• the removable etch resist 430 may be partially or completely removed using any currently available or future developed removal process that does not affect the performance of the stop layer 120 on the first semiconductor inductor 100 A.
• the removable etch resist 430 may be removed via one or more plasma etching processes or wet chemistry etching processes.
• exposing the surface 242 of the active die 210 beneficially facilitates the attachment of solder balls or similar conductive structures to the exposed surface 242 of the active die 210 to provide a wafer level package.
• FIG. 4F is a cross-section of the illustrative semiconductor inductor system 400 F that includes the first semiconductor inductor 100 A and a conductively coupled second semiconductor inductor 100 B coupled to an active die 210 , in accordance with at least one embodiment described herein.
• any number of additional semiconductor inductors 100 B- 100 n may be conductively coupled to the active die to provide a stacked, three-dimensional semiconductor inductor.
• Any number of semiconductor inductors 100 A- 100 n may stacked by: etching the stop layer 120 of the uppermost semiconductor inductor, conductively coupling the next semiconductor inductor to the upper most semiconductor inductor using one or more conductive structures 140 , and removing the sacrificial substrate 130 from the newly added semiconductor inductor.
• FIG. 5A is a cross-section of an illustrative semiconductor inductor system 500 A that includes a semiconductor inductor 100 having the sacrificial substrate 130 removed and replaced with a magnetic material 510 , in accordance with at least one embodiment described herein.
• the semiconductor inductor 100 conductively couples to an active die 210 having a removable etch resist 430 disposed on, about, or across at least a portion of the exposed surface 242 of the active die 210 .
• the upper surface 512 of the magnetic material 510 may be above, below, or at the same elevation as the upper surface 432 of the removable etch resist 430 .
• the magnetic material 510 improves the inductive performance of the semiconductor inductor 100 .
• the magnetic material 510 may include one or more non-electrically conductive materials demonstrating magnetic properties.
• Example magnetic materials may include one or more soft magnetic composite materials, such as one or more ferritic materials encapsulated in a non-electrically conductive material or polymer).
• FIG. 5B is a cross-sectional elevation of an illustrative semiconductor inductor system 500 B that includes the semiconductor inductor 100 that includes a magnetic material 510 disposed proximate the stop layer 120 , communicably coupled to the active die 210 in which at least a portion of the removable etch resist 430 has been removed to expose at least a portion of the exposed surface 242 of the active die 210 , in accordance with at least one embodiment described herein.
• the removable etch resist 430 may be partially or completely removed using any currently available or future developed removal process that does not affect the performance of the stop layer 120 on the semiconductor inductor 100 .
• the removable etch resist 430 may be removed via one or more plasma etching processes or wet chemistry etching processes.
• exposing the surface 242 of the active die 210 beneficially facilitates the attachment of solder balls or similar conductive structures to the exposed surface 242 of the active die 210 to provide a wafer level package.
• FIG. 6 is a plan view of an illustrative system 600 that includes a plurality of semiconductor inductors 100 A- 100 H, in accordance with at least one embodiment described herein.
• Each of the semiconductor inductors 100 A- 100 H includes a plurality of windings disposed across the surface of the active die 210 .
• FIG. 7 is a cross-sectional elevation of an illustrative embedded wafer level ball grid array (eWLB) semiconductor package 700 using through mold vias (TMVs) 710 A- 710 D (collectively, “TMVs 710 ”) and including a number of semiconductor inductors such as described in detail with regard to FIGS. 1-6 , in accordance with at least one embodiment described herein.
• the TMVs 710 conductively couple the pads 220 on the active die 230 to an exposed ball grid array that includes a number of solder balls 720 A- 720 D on the package bottom.
• a redistribution layer may provide all or a portion of the pads 220 .
• the semiconductor package 700 includes a single coil semiconductor inductor 100 and a stacked coil semiconductor inductor 300 that includes a first semiconductor inductor 100 A and a second semiconductor inductor 100 B.
• the single coil semiconductor inductor 100 and the stacked coil semiconductor inductor 300 conductively couple to the upper surface of the active die 230 .
• the active die 230 , the semiconductor inductor 100 and the stacked semiconductor inductor 300 are encapsulated in mold compound 250 to provide the eWLB semiconductor package 700 .
• FIG. 7 any number of semiconductor inductors 100 and/or stacked semiconductor inductors 300 may be similarly coupled to the active die 230 .
• FIG. 8 is a cross-sectional elevation of another illustrative embedded wafer level ball grid array (eWLB) semiconductor package 800 in which both the solder balls 820 A- 820 E forming the ball grid array and the semiconductor inductor 100 are disposed on the upper surface of the active die 230 , in accordance with at least one embodiment described herein.
• the active die 230 and the semiconductor inductor 100 may be encapsulated in mold compound 250 .
• the pads 220 on the upper surface of the active die 230 may be opened, for example using one or more laser ablation or other similar selective material removal processes, and the solder balls 820 inserted to conductively couple the eWLB semiconductor package 800 to an external device.
• any number of semiconductor inductors 100 may be similarly coupled to the active die 230 .
• FIG. 9 is a cross-sectional elevation of another illustrative embedded wafer level ball grid array (eWLB) semiconductor package 900 using through mold vias (TMVs) 910 A- 910 D (collectively, “TMVs 910 ”) and back-side metallization, in accordance with at least one embodiment described herein.
• the eWLB semiconductor package 900 includes three semiconductor inductors 100 A, 100 B, and 100 C.
• TMVs 910 conductively couple semiconductor inductors 100 A and 100 C to the active die 230 .
• Semiconductor inductors 100 A and 100 C are encapsulated by the mold compound 250 forming the eWLB semiconductor package 900 .
• Semiconductor inductor 100 B includes a magnetic material 270 cap disposed proximate the stop layer 120 . Although two semiconductor inductors 100 A, 100 C are depicted coupled to the front side of the active die 230 using TMVs in FIG. 9 , any number of semiconductor inductors 100 may be similarly coupled to the active die 230 using TMVs. Although a single semiconductor inductor 100 B is depicted coupled to the lower surface of the active die 230 , any number of semiconductor inductors may be similarly coupled to the lower surface of the active die 230 .
• FIG. 10 is a cross-sectional elevation of an illustrative embedded wafer level ball grid array (eWLB) semiconductor package 1000 in which a semiconductor inductor 100 is conductively coupled to the upper surface of the active die 230 , in accordance with at least one embodiment described herein.
• a mold compound 250 may be used to cover the upper surface of the active die 210 and may encapsulate the semiconductor inductor 100 .
• the pads 220 on the upper surface of the active die 230 may be opened, for example using one or more laser ablation or other similar selective material removal processes, and the solder balls 1020 inserted to conductively couple the eWLB semiconductor package 1000 to an external device.
• a solder-resist 1040 may be disposed about some or all of the pads 220 .
• a single semiconductor inductor 100 is depicted coupled to the upper surface of the active die 230 , any number of semiconductor inductors may be similarly coupled to the upper surface of the active die 210 .
• the semiconductor inductor 100 may be conductively coupled to the upper surface of the active die using any conductive coupling method including, but not limited to, solder balls, solder bumps, conductive pillars, and/or solder paste.
• FIG. 11 is a cross-sectional elevation of an embedded wafer level ball grid array (eWLB) semiconductor package 1100 that includes a mold compound 250 disposed on the lower surface of the active die 230 and a removable etch resist 430 disposed on the upper surface of the active die 230 , in accordance with at least one embodiment described herein.
• a solder-resist 1140 may be disposed about some or all of the pads 220 .
• the removable etch resist layer 430 may be removed exposing the pads 220 on the upper surface of the active die 230 .
• Solder balls 220 may be attached to some or all of the exposed pads 220 .
• the resultant eWLB semiconductor package 1100 may include exposed solder balls and semiconductor inductors 100 and 300 conductively coupled to the upper surface of the active die 230 . Although only two semiconductor inductors are depicted coupled to the upper surface of the active die 230 , any number of semiconductor inductors may be similarly coupled to the upper surface of the active die 230 .
• FIG. 12 is a cross-sectional elevation of an illustrative wafer level chip scale package (WLCSP) semiconductor package 1200 in which a semiconductor inductor 100 is fabricated using a removable etch resist 430 and conductively coupled to the upper surface of the active die 210 , in accordance with at least one embodiment described herein.
• a solder-resist 1140 may be disposed about some or all of the pads 220 .
• a removable etch resist 430 may be deposited about the semiconductor inductor 100 and may cover some or all of the pads 220 on the upper surface of the active die 210 . After forming the semiconductor inductor 100 , the removable etch resist 430 may be removed, exposing the pads 220 .
• Solder balls 1220 A- 1220 F may then be conductively coupled to some or all of the exposed pads 220 .
• the resultant WLCSP semiconductor package may include exposed solder balls 1220 and an exposed semiconductor inductor 100 . Although a single semiconductor inductor 100 is depicted coupled to the upper surface of the active die 210 , any number of semiconductor inductors may be similarly coupled to the upper surface of the active die 210 .
• FIG. 13 is a cross-sectional elevation of an illustrative wafer level chip scale package (WLCSP) semiconductor package 1300 in which semiconductor inductors 100 are fabricated using a removable etch resist 430 and conductively coupled to the active die 210 by through silicon vias (TSVs) 1310 A- 1310 D (collectively, “TSVs”), in accordance with at least one embodiment described herein.
• TSVs through silicon vias
• a solder-resist 1140 may be disposed about some or all of the pads 220 .
• a removable etch resist 430 may be deposited about the semiconductor inductors 100 on the surface of the silicon substrate 230 of the active die 210 .
• solder balls 1320 A- 1320 F may then be conductively coupled to some or all of the exposed pads 220 on the active surface 210 .
• the resultant WLCSP semiconductor package may include exposed solder balls 1220 on the active die 210 and exposed semiconductor inductors 100 A and 100 B on the silicon substrate 230 , opposite the active die 210 . Although two semiconductor inductors 100 A and 100 B are depicted coupled to the surface of the silicon substrate 230 , any number of semiconductor inductors may be similarly coupled to the surface of the silicon substrate 230 .
• FIG. 14 is a cross-sectional elevation of an illustrative stacked die in which conductive members 1450 , such as copper pillars, couple a second semiconductor die 1410 to an active die 210 encapsulated in a dielectric material 1440 and in which the active die 210 is conductively coupled to a redistribution layer, in accordance with at least one embodiment described herein.
• the semiconductor inductor 100 may be conductively coupled to the surface of the silicon substrate 230 that this opposite the active die 210 using a number of through silicon vias (TSVs) 1460 .
• TSVs through silicon vias
• an underfill may be disposed at least partially between the semiconductor inductor 100 and the surface of the silicon substrate 230 .
• the dielectric material 1440 may also encapsulate a number of conductive layers 1480 .
• a plurality of solder balls 1420 may be conductively coupled to the redistribution layer.
• FIG. 15 is a cross-sectional elevation of an illustrative stacked die in which conductive members 1550 , such as copper pillars, couple a second semiconductor die 1510 to an active die 210 coupled to a semiconductor inductor 100 and in which the active die 210 is conductively coupled to a redistribution layer, in accordance with at least one embodiment described herein.
• the semiconductor inductor 100 may be conductively coupled to the second semiconductor die 1510 using a number of through silicon vias (TSVs) 1560 .
• TSVs through silicon vias
• an underfill may be disposed at least partially between the semiconductor inductor 100 and the surface of the silicon substrate 230 .
• the dielectric material 1540 may also encapsulate a number of conductive layers 1580 .
• a plurality of solder balls 1520 may be conductively coupled to the active layer 210 .
• FIG. 16 is a high-level flow diagram of an illustrative semiconductor inductor fabrication method 1600 in which a planar coil 110 having one or more windings is formed or otherwise patterned onto a stop layer 120 that has been deposited on a sacrificial substrate 130 , in accordance with at least one embodiment described herein.
• the presence of the sacrificial substrate 130 beneficially and advantageously provides structural support for the coil 110 .
• the sacrificial substrate 130 may include a silicon substrate which permits the fabrication of a plurality of semiconductor inductors 100 on a silicon wafer.
• the semiconductor inductors 100 are singulated for coupling to active dies 210 .
• the active dies 210 may be formed on a silicon wafer and the semiconductor inductors 100 may be coupled to the active dies prior to singulation of the active dies. After coupling to the active die 210 , the sacrificial substrate may be removed from the semiconductor inductor 100 and the resultant package encapsulated in mold compound or forwarded for additional processing.
• the method 1600 commences at 1602 .
• Example deposition processes include, but are not limited to: chemical vapor deposition, physical vapor deposition, molecular beam epitaxy; electrochemical deposition; plasma enhanced chemical vapor deposition; spin coating; and similar.
• the stop layer 120 may have any thickness.
• the stop layer 120 may have a thickness of less than: about 20 nanometers (nm); about 30 nm; about 50 nm; about 70 nm; about 90 nm; or about 130 nm.
• the sacrificial substrate 130 provides structural support for the coil 110 and the stop layer 120 until fabrication of the coil structure is complete and the coil 110 is coupled to an active die.
• the sacrificial substrate 130 beneficially provides structural support for the coil 110 prior to communicably coupling the coil 110 to an active die and may be removed from the coil 110 once the coil is coupled to the active die, thereby beneficially reducing both the weight and thickness of the resultant semiconductor package.
• the sacrificial substrate may contain silicon.
• a silicon wafer may provide the sacrificial substrate 130 and multiple coils may be formed on the wafer prior to singulation.
• the sacrificial substrate 130 may have any thickness.
• the sacrificial substrate 130 may have a thickness of less than: about 800 micrometers ( ⁇ m); about 700 ⁇ m; about 600 ⁇ m; about 500 ⁇ m; about 400 ⁇ m; about 300 ⁇ m; or about 200 ⁇ m.
• the silicon wafer may have a diameter of: about 450 millimeter (mm); about 300 mm; about 200 mm; about 150 mm; about 130 mm; about 100 mm; about 76 mm; about 50 mm; or about 25 mm.
• a coil 110 is formed or otherwise patterned on, across, or about at least a portion of the stop layer 120 .
• the coil 110 may have any size, shape, and/or geometry.
• the coil 110 may have one or more turns or windings.
• the coil 110 may be patterned onto the stop layer 120 using any currently available or future developed deposition technique.
• the coil 110 may be fabricated from any conductive material including, but not limited to, one or more metals or metal alloys, one or more conductive polymers, or one or more conductive non-metallic materials, such as graphene.
• Example metals may include, but are not limited to: copper, copper alloys, aluminum, and aluminum alloys.
• the conductors forming the coil may have any width and/or thickness.
• the coil 110 may have a width of greater than: about 5 nanometers (nm); about 7 nm; about 10 nm; about 15 nm; about 20 nm; about 30 nm; or about 50 nm.
• one or more conductive structures 140 may be conductively coupled to the coil 110 .
• the one or more conductive structures 140 may include any device or feature capable of conductively coupling the inductor 100 to an external system, such as an active die.
• the conductive structures 140 may physically affix the inductor 100 to an external device or system.
• the conductive structures 140 may include one or more solder balls.
• the conductive structures 140 may include one or more conductive pillars.
• the conductive structures 140 may include solder bumps.
• a dielectric layer 150 is deposited across all or a portion of the coil 110 and across all or a portion of the stop layer 120 , at least partially encapsulating the coil 110 .
• the dielectric layer 150 is disposed on, across, or about the coil 110 and on, across, or about the stop layer 120 .
• the dielectric layer 150 encapsulates the coil 110 and at least partially encapsulates the conductive structures 140 .
• at least a portion of the conductive structures 140 may extend or project beyond the surface of the dielectric layer 150 opposite the coil 110 .
• the dielectric layer may include one or more electrically insulating materials.
• Example dielectric materials include, but are not limited to: nanoporous silica; hydrogensilsesquioxanes (HSQ); Teflon®-AF (polytetrafluoethylene or PTFE); silicon oxyflouride (FSG); silicon dioxide (SiO 2 ); silicon nitride; alkali halides; barium titanate (BaTiO 3 ); hafnium oxide (HfO 2 ); tantalum oxide (TaO 5 ); tungsten oxide (WO 3 ); zirconium oxide (ZrO 2 ); and similar.
• the method 1600 concludes at 1612 .
• FIG. 17 is a high-level flow diagram of an illustrative semiconductor inductor fabrication method 1700 in which at least a portion of the sacrificial substrate 130 is removed to expose the stop layer 120 , in accordance with at least one embodiment described herein.
• the method 1700 may be used in conjunction with the method 1600 described in detail above.
• the removal of the sacrificial substrate 130 may occur after physical attachment of the semiconductor inductor 100 to an active die 210 , based at least in part, on the structural strength and rigidity the sacrificial substrate 130 provides during the semiconductor inductor 100 attachment process.
• the sacrificial substrate 130 may be removed after attaching the semiconductor inductor 100 to an active die and after at least partially embedding the semiconductor inductor 100 in a mold compound 250 or removable etch resist 430 .
• the method 1700 commences at 1702 .
• the sacrificial substrate 130 is removed from the semiconductor inductor 100 .
• the removal of the sacrificial substrate 130 creates a void 260 proximate the semiconductor inductor 100 while the mold compound 250 or removable etch resist 430 remains unaffected.
• all or a portion of the thickness of the sacrificial substrate 130 may be removed using wet chemistry on a spin etcher.
• the etching process may halt upon reaching the stop layer 120 .
• a dielectric material 270 and/or a magnetic material 280 is deposited in the void 260 formed above the semiconductor inductor 100 by the removal of the sacrificial substrate 130 .
• the dielectric material 270 may include mold compound similar to that previously deposited about at least a portion of the perimeter of the semiconductor inductor 100 .
• the magnetic material 280 may include one or more non-electrically conductive materials demonstrating magnetic properties.
• Example magnetic materials may include one or more soft magnetic composite materials, such as one or more ferritic materials encapsulated in a non-electrically conductive material or polymer).
• the top surface of the dielectric material 270 and/or the magnetic material 180 may be finished flush with the surrounding mold compound 250 using one or more surface finishing techniques, such as chemical mechanical planarization (CMP).
• CMP chemical mechanical planarization
• FIG. 18 is a high-level flow diagram of an illustrative semiconductor package fabrication method 1800 in which the semiconductor inductor 100 is conductively coupled to an active die 210 , in accordance with at least one embodiment described herein.
• the method 1800 commences at 1802 .
• the semiconductor inductor 100 is conductively coupled to the active die 210 .
• the semiconductor inductor 100 may be coupled directly to the surface of the active die 210 .
• the semiconductor inductor 100 may be physically coupled to a substrate material 230 on which the active die 210 is formed and may be conductively coupled to the active die 210 using one or more through-silicon vias (TSVs).
• TSVs through-silicon vias
• the semiconductor inductor 100 may be physically coupled to an active die 210 using one or more through mold vias (TMVs).
• TSVs through-silicon vias
• TSVs through mold vias
• FIGS. 16 through 18 illustrate various operations according to one or more embodiments, it is to be understood that not all of the operations depicted in FIGS. 16 through 18 are necessary for other embodiments. Indeed, it is fully contemplated herein that in other embodiments of the present disclosure, the operations depicted in FIGS. 16 through 18 , and/or other operations described herein, may be combined in a manner not specifically shown in any of the drawings, but still fully consistent with the present disclosure. Thus, claims directed to features and/or operations that are not exactly shown in one drawing are deemed within the scope and content of the present disclosure.
• a list of items joined by the term “and/or” can mean any combination of the listed items.
• the phrase “A, B and/or C” can mean A; B; C; A and B; A and C; B and C; or A, B and C.
• a list of items joined by the term “at least one of” can mean any combination of the listed terms.
• the phrases “at least one of A, B or C” can mean A; B; C; A and B; A and C; B and C; or A, B and C.
• system or “module” may refer to, for example, software, firmware and/or circuitry configured to perform any of the aforementioned operations.
• Software may be embodied as a software package, code, instructions, instruction sets and/or data recorded on non-transitory computer readable storage mediums.
• Firmware may be embodied as code, instructions or instruction sets and/or data that are hard-coded (e.g., nonvolatile) in memory devices.
• Circuitry may comprise, for example, singly or in any combination, hardwired circuitry, programmable circuitry such as computer processors comprising one or more individual instruction processing cores, state machine circuitry, and/or firmware that stores instructions executed by programmable circuitry or future computing paradigms including, for example, massive parallelism, analog or quantum computing, hardware embodiments of accelerators such as neural net processors and non-silicon implementations of the above.
• the circuitry may, collectively or individually, be embodied as circuitry that forms part of a larger system, for example, an integrated circuit (IC), system on-chip (SoC), desktop computers, laptop computers, tablet computers, servers, smartphones, etc.
• IC integrated circuit
• SoC system on-chip
• any of the operations described herein may be implemented in a system that includes one or more mediums (e.g., non-transitory storage mediums) having stored therein, individually or in combination, instructions that when executed by one or more processors perform the methods.
• the processor may include, for example, a server CPU, a mobile device CPU, and/or other programmable circuitry. Also, it is intended that operations described herein may be distributed across a plurality of physical devices, such as processing structures at more than one different physical location.
• the storage medium may include any type of tangible medium, for example, any type of disk including hard disks, floppy disks, optical disks, compact disk read-only memories (CD-ROMs), rewritable compact disks (CD-RWs), and magneto-optical disks, semiconductor devices such as read-only memories (ROMs), random access memories (RAMs) such as dynamic and static RAMs, erasable programmable read-only memories (EPROMs), electrically erasable programmable read-only memories (EEPROMs), flash memories, Solid State Disks (SSDs), embedded multimedia cards (eMMCs), secure digital input/output (SDIO) cards, magnetic or optical cards, or any type of media suitable for storing electronic instructions.
• ROMs read-only memories
• RAMs random access memories
• EPROMs erasable programmable read-only memories
• EEPROMs electrically erasable programmable read-only memories
• flash memories Solid State Disks (SSDs), embedded multimedia cards (eMMC
• the present disclosure is directed to systems and methods for fabricating a semiconductor inductor that includes a coil deposited on a stop layer that is deposited on a sacrificial substrate.
• the semiconductor inductor may be fabricated on a silicon wafer and singulated.
• the sacrificial substrate beneficially provides structural support for the singulated semiconductor inductor.
• the singulated semiconductor inductor advantageously requires minimal active die surface area.
• the removal of the sacrificial substrate after coupling to the active die beneficially reduces the overall thickness (or height) of the semiconductor package, providing a decided advantage in low profile, portable, electronic devices.
• the following examples pertain to further embodiments.
• the following examples of the present disclosure may comprise subject material such as at least one device, a method, at least one machine-readable medium for storing instructions that when executed cause a machine to perform acts based on the method, means for performing acts based on the method and/or a system for fabricating a low-profile semiconductor inductor on a sacrificial substrate that can be coupled to an active die prior to singulation of the silicon wafer.
• the semiconductor inductor may include: a first sacrificial substrate having a thickness, a first surface and a transversely opposed second surface; a first stop layer deposited across at least a portion of the first surface of the first sacrificial substrate; a first coil having a first surface and a second surface deposited across at least a portion of the first stop layer opposite the first sacrificial substrate; a first dielectric layer having a thickness disposed at least partially across the first coil; and at least one first conductive structure conductively coupled to the first coil and extending through the first dielectric layer thickness and projecting at least partially from the surface of the first dielectric layer opposite the first coil.
• Example 2 may include elements of example 1 where the stop layer may include silicon carbide.
• Example 3 may include elements of example 1 where the at least one conductive structure may include at least one of: a solder ball, a solder bump, or a conductive solder paste.
• Example 4 may include elements of example 1 where the at least one conductive structure may include a conductive pillar.
• Example 5 may include elements of example 1 where the first coil may include a planar coil having a plurality of turns disposed on the first stop layer.
• Example 6 may include elements of example 1, and the semiconductor inductor may additionally include: a second coil disposed proximate and conductively coupled to the first coil by one or more second conductive structures extending through the first stop layer after removal of at least a portion of the first sacrificial substrate; where the second coil has a first surface disposed proximate a second dielectric layer and a second surface deposited across at least a portion of a second stop layer; and where the second conductive structures extend through the second dielectric layer.
• Example 7 may include elements of example 6 where the second coil is spaced a distance from the first coil, forming an interstitial space between the first oil and the second coil.
• Example 8 may include elements of example 7, and the semiconductor inductor may additionally include an underfill at least partially filling the interstitial space between the first coil and the second coil.
• Example 9 may include elements of example 1, and the semiconductor inductor may additionally include a magnetic core material disposed proximate at least a portion of the first stop layer after removal of at least a portion of the first sacrificial substrate.
• Example 10 may include elements of any of examples 1 through 9 where the first sacrificial substrate comprises a silicon wafer.
• a method of fabricating a first semiconductor inductor may include: depositing a first stop layer across at least a portion of a first surface of a first sacrificial substrate; forming a first coil having a first surface and an opposed second surface across at least a portion of the first stop layer opposite the first sacrificial substrate; depositing a first dielectric layer having a thickness at least partially across the first coil; and conductively coupling at least one first conductive structure to the first coil, the at least one first conductive structure extending through the thickness of the first dielectric layer and projecting at least partially from the surface of the first dielectric layer opposite the first coil.
• Example 12 may include elements of example 11, and the method may further include: removing at least a portion of the first sacrificial substrate to expose at least a portion of the first stop layer.
• Example 13 may include elements of example 11 where removing at least a portion of the first sacrificial substrate to expose at least a portion of the first stop layer may include: removing at least a portion of the first sacrificial substrate via spin etching to expose the portion of the first stop layer.
• Example 14 may include elements of example 11, and the method may additionally include: depositing a magnetic core material across at least a portion of the exposed portion of the first stop layer.
• Example 15 may include elements of example 11, and the method may additionally include: forming a second semiconductor inductor by: depositing a second stop layer across at least a portion of a first surface of a second sacrificial substrate; forming a second coil having a first surface and an opposed second surface across at least a portion of the second stop layer opposite the second sacrificial substrate; depositing a second dielectric layer having a thickness at least partially across the second coil; and conductively coupling at least one second conductive structure to the second planar coil, the at least one second conductive structure extending through the thickness of the second dielectric layer and projecting at least partially from the surface of the second dielectric layer opposite the second coil; and conductively coupling the at least one second conductive structure to the first coil, the at least one second conductive structure extending through the first stop layer thickness.
• Example 16 may include elements of example 15, and the method may additionally include: an underfill at least partially filling an interstitial space between the first coil and the second coil.
• Example 17 may include elements of example 11 where depositing a first stop layer across at least a portion of a first surface of a first sacrificial substrate may include: depositing a first stop layer that includes silicon carbide across at least a portion of a first surface of a first sacrificial substrate.
• Example 18 may include elements of example 11 where conductively coupling at least one first conductive structure to the first coil may include: conductively coupling at least one first conductive structure that includes a solder ball to the first coil.
• Example 19 may include elements of example 11 where conductively coupling at least one first conductive structure to the first coil may include: conductively coupling at least one first conductive structure that includes a conductive pillar to the first planar coil.
• Example 20 may include elements of example 11 where forming a first coil may include: forming a first coil that includes a plurality of turns.
• Example 21 may include elements of example 11 where forming a first coil across at least a portion of the first stop layer opposite the first sacrificial substrate may include: patterning a first planar coil across at least a portion of the first stop layer opposite the first sacrificial substrate.
• Example 22 may include elements of any of examples 11 through 21 where forming a first coil across at least a portion of the first stop layer opposite the first sacrificial substrate may include: forming a first coil across at least a portion of the first stop layer opposite a first sacrificial silicon substrate.
• the semiconductor package may include: a semiconductor die; a semiconductor inductor conductively coupled to the semiconductor die, the semiconductor inductor including: a first sacrificial substrate having a thickness, a first surface and a second surface; a first stop layer deposited across at least a portion of the first surface of the first sacrificial substrate; a first coil having a first surface and a second surface deposited across at least a portion of the first stop layer opposite the first sacrificial substrate; a first dielectric layer having a thickness disposed at least partially across the first coil; and at least one first conductive structure conductively coupled to the first coil and extending through the thickness of the first dielectric layer and projecting at least partially from the surface of the first dielectric layer opposite the first coil, the at least one first conductive structure conductively coupled to the semiconductor die.
• Example 24 may include elements of example 23, and the semiconductor package may additionally include: a mold compound disposed across at least a portion of the semiconductor die and at least partially about the semiconductor inductor.
• Example 25 may include elements of example 23, and the semiconductor package may additionally include: a mold compound disposed across at least a portion of the semiconductor die and across at least a portion of the first stop layer of the semiconductor inductor after removal of at least a portion of the thickness of the first sacrificial substrate.
• Example 26 may include elements of example 23 where the sacrificial substrate may include a silicon wafer.
• Example 27 may include elements of example 23 where the stop layer may include silicon carbide.
• Example 28 may include elements of example 23 where the at least one conductive structure may include a solder ball.
• Example 29 may include elements of example 23 where the at least one conductive structure may include a conductive pillar.
• Example 30 may include elements of example 23 where the first coil comprises a coil having a plurality of turns.
• Example 31 may include elements of example 23, and the semiconductor package may additionally include: a second coil disposed proximate and conductively coupled to the first coil by one or more second conductive structures extending through the first stop layer after removal of at least a portion of the first sacrificial layer; where the second coil has a first surface disposed proximate a second dielectric layer and an opposed second surface deposited across at least a portion of a second stop layer; and where the second conductive structures extend through the second dielectric layer.
• Example 32 may include elements of example 31 where the second coil is spaced a distance from the first coil, forming an interstitial space between the first coil and the second coil.
• Example 33 may include elements of example 32, and the semiconductor package may additionally include: an underfill at least partially filling the interstitial space between the first coil and the second coil.
• Example 34 may include elements of example 23, and the semiconductor inductor may additionally include: a magnetic core material disposed proximate at least a portion of the first stop layer after removal of at least a portion of the first sacrificial substrate.
• Example 35 may include elements of example 23, and the semiconductor inductor may additionally include: a mold compound disposed across at least a portion of the semiconductor die and at least partially about the semiconductor inductor.
• Example 36 may include elements or example 23, and the semiconductor inductor may additionally include: an etch-resist compound disposed across at least a portion of the semiconductor die and about at least a portion of the first sacrificial substrate.
• Example 37 may include elements of example 36, and the semiconductor inductor may additionally include: a magnetic core material disposed proximate at least a portion of the first stop layer after removal of at least a portion of the first sacrificial substrate.
• a method of fabricating a first semiconductor package may include: the method comprising: forming a semiconductor inductor by: depositing a first stop layer across at least a portion of a first surface of a first sacrificial substrate having a first thickness; forming a first coil having a first surface and an opposed second surface across at least a portion of the first stop layer opposite the first sacrificial substrate; depositing a first dielectric layer having a thickness at least partially across the first coil; and conductively coupling at least one first conductive structure to the first coil, the at least one first conductive structure extending through the thickness of the first dielectric layer and projecting at least partially from the surface of the first dielectric layer opposite the first coil; and conductively coupling the semiconductor inductor to a semiconductor die using the at least one conductive structure.
• Example 39 may include elements of example 38, and the method may additionally include: disposing a mold compound across at least a portion of the semiconductor die and at least partially about the semiconductor inductor.
• Example 40 may include elements of example 39, and the method may additionally include: removing at least a portion of the first sacrificial substrate to expose at least a portion of the first stop layer.
• Example 41 may include elements of example 40, and the method may additionally include: depositing a magnetic core material across at least a portion of the exposed portion of the first stop layer.
• Example 42 may include elements of example 40 where removing at least a portion of the first sacrificial substrate to expose at least a portion of the first stop layer may include: removing at least a portion of the first sacrificial substrate via spin etching to expose the portion of the first stop layer.
• Example 43 may include elements of example 38, and the method may additionally include: disposing a mold compound disposed across at least a portion of the semiconductor die and across at least a portion of the first semiconductor inductor stop layer after removing at least a portion of the first sacrificial substrate to expose at least a portion of the first stop layer.
• Example 44 may include elements of example 38, and the method may additionally include: forming a second semiconductor inductor by: depositing a second stop layer across at least a portion of a first surface of a second sacrificial substrate; forming a second coil having a first surface and an opposed second surface across at least a portion of the second stop layer opposite the second sacrificial substrate; depositing a second dielectric layer having a thickness at least partially across the second coil; and conductively coupling at least one second conductive structure to the second planar coil, the at least one second conductive structure extending through the thickness of the second dielectric layer and projecting at least partially from the surface of the second dielectric layer opposite the second coil; and conductively coupling the at least one second conductive structure to the first coil, the at least one second conductive structure extending through the first stop layer thickness.
• Example 45 may include elements of example 44, and the method may additionally include: at least partially filling an interstitial space between the first coil and the second coil using an underfill.
• Example 46 may include elements of example 38 where depositing a first stop layer across at least a portion of a first surface of a first sacrificial substrate may include: depositing a first stop layer that includes silicon carbide across at least a portion of a first surface of a first sacrificial substrate.
• Example 47 may include elements of example 38 where conductively coupling at least one first conductive structure to the first coil may include: conductively coupling at least one first conductive structure that includes a solder ball to the first coil.
• Example 48 may include elements of example 38 where conductively coupling at least one first conductive structure to the first coil may include: conductively coupling at least one first conductive structure that includes a conductive pillar to the first coil.
• Example 49 may include elements of example 38 where forming a first coil comprises: forming a first planar coil that includes a plurality of turns.
• Example 50 may include elements of example 38 where forming a first coil across at least a portion of the first stop layer opposite the first sacrificial substrate comprises: patterning a first planar coil across at least a portion of the first stop layer opposite the first sacrificial substrate.
• Example 51 may include elements of any of examples 38 through 50 where forming a first coil across at least a portion of the first stop layer opposite the first sacrificial substrate comprises: forming a first planar coil across at least a portion of the first stop layer opposite a first sacrificial silicon substrate.

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• 2017
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