US20060270196A1 - Methods of forming semiconductor devices and electrical interconnect structures in semiconductor devices and intermediate structures formed thereby - Google Patents

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• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
  • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
  • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
  • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
  • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
  • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
  • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
  • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
  • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
  • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
  • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
  • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
  • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
  • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
  • H01L23/53204—Conductive materials
  • H01L23/5328—Conductive materials containing conductive organic materials or pastes, e.g. conductive adhesives, inks
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/0001—Technical content checked by a classifier
  • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/10—Details of semiconductor or other solid state devices to be connected
  • H01L2924/11—Device type
  • H01L2924/12—Passive devices, e.g. 2 terminal devices
  • H01L2924/1204—Optical Diode
  • H01L2924/12044—OLED

Definitions

• the present invention relates generally to the fabrication of semiconductor device structures. More particularly, the present invention relates to a method for creating depressions in a semiconductor substrate or film using laser machining processes and using such depressions for defining precise electrical pathways in a semiconductor device structure.
• Connection lines e.g., lead and/or bond connections
• traces, signals and other elongated conductive elements are utilized in semiconductor device structures to carry electronic signals and other forms of electron flow between one region of the semiconductor device structure and another and between regions within the semiconductor device structure and external contacts (e.g., solder balls, bond pads and the like) associated therewith.
• Conventional methods for forming such elongated conductive elements utilize a damascene process wherein one or more depressions is etched in a semiconductor substrate or film, backfilled with an electrically conductive material and polished back or “planarized” even with the surface of the substrate or film.
• depression includes troughs, channels, vias, holes and other depressions in and through a semiconductor substrate or film, which depressions may be used to define electrical pathways that carry electronic signals between one region of a semiconductor device structure and another, and between regions within the semiconductor device structure and external contacts associated therewith, as well as providing power, ground and bias to integrated circuitry of the semiconductor device structure.
• electrical pathways may include, without limitation, the depressions used to define traces or lines for signal lines, power and ground lines, and the like.
• FIGS. 1A-1E schematically depict a conventional damascene process sequence for creating elongated conductive elements in the form of traces 26 in an interlevel dielectric layer 14 .
• the process depicted illustrates formation of a plurality of traces 26
• the process sequence is typically utilized for the formation of other elongated conductive elements, e.g., lines for signal lines, power and ground lines, as well.
• the methods and structures described herein do not form a complete process for manufacturing semiconductor device structures. The remainder of the process is known to those of ordinary skill in the art and, therefore, only the process steps and structures necessary to understand the conventional process sequence are described herein.
• FIG. 1A a cross-sectional view of a first intermediate structure 10 in the fabrication of a semiconductor device structure 24 having a plurality of traces 26 in the interlevel dielectric layer 14 thereof is illustrated.
• the first intermediate structure 10 includes an interlevel dielectric layer 14 , e.g., thermally grown silicon dioxide (SiO 2 ), which resides on a semiconductor substrate 12 , such as a silicon wafer.
• SiO 2 thermally grown silicon dioxide
• a photoresist layer 16 formed from a conventional photoresist material, is disposed atop the interlevel dielectric layer 14 and one or more trace precursors in the form of trace depressions 18 are patterned in the photoresist layer 16 using conventional photolithography techniques.
• the patterned trace depressions 18 may be of any shape or configuration including, but not limited to, circles, ovals, rectangles, elongated slots and the like.
• the interlevel dielectric layer 14 is subsequently etched using the photoresist layer 16 as a mask so that the patterned trace depressions 18 are extended into the interlevel dielectric layer 14 .
• etching processes are known to those of ordinary skill in the art and may include, without limitation, reactive ion etching (RIE) or an oxide etch.
• RIE reactive ion etching
• oxide etch oxide etch.
• the photoresist layer 16 is subsequently removed by a conventional process, such as a wet-strip process, a tape lift-off technique, or combinations thereof, creating a second intermediate structure 20 .
• an electrically conductive material 22 e.g., tungsten is subsequently blanket deposited over the interlevel dielectric layer 14 such that the trace depressions 18 are filled therewith.
• the electrically conductive material 22 is then planarized using, e.g., a mechanical abrasion technique, such as chemical mechanical planarization (CMP), to isolate the electrically conductive material 22 in the trace depressions 18 , as illustrated in FIG. 1E .
• CMP chemical mechanical planarization
• FIGS. 2A-2I illustrate a conventional dual damascene process sequence. Referring to FIG. 2A , a cross-sectional view of a first intermediate structure 10 ′ in the fabrication of a semiconductor device structure 24 ′ having a plurality of traces 26 ′ and a plurality of conductor-filled vias 32 in the interlevel dielectric layer 14 ′ thereof is illustrated.
• the first intermediate structure 10 ′ includes an interlevel dielectric layer 14 ′, e.g., thermally grown SiO 2 , which resides on a semiconductor substrate 12 ′, such as a silicon wafer.
• the patterned trace depressions 18 ′ may be of any shape or configuration including, but not limited to, circles, ovals, rectangles, elongated slots and the like.
• a photoresist layer 16 ′ formed from a conventional photoresist material, is subsequently deposited atop the mask layer 28 such that the patterned trace depressions 18 ′ are filled therewith.
• conventional photolithography is performed on the photoresist layer 16 ′, thereby forming a patterned photoresist layer 16 ′′ having a plurality of vias 30 patterned therein which align with the trace depressions 18 ′ of the mask layer 28 .
• the interlevel dielectric layer 14 ′ is subsequently etched, using, e.g., RIE, utilizing the patterned photoresist layer 16 ′′ as a mask.
• the pattern of vias 30 is accordingly extended into the upper portion of the interlevel dielectric layer 14 ′.
• the patterned photoresist layer 16 ′′ is subsequently removed, forming a second intermediate structure 20 ′.
• the interlevel dielectric layer 14 ′ is etched using the mask layer 28 with the patterned trace depressions 18 ′ therein and the upper portion of the interlevel dielectric layer 14 ′ with the vias 30 therein as a mask.
• FIG. 2F This step is shown in FIG. 2F .
• the desired trace pattern is extended into the upper portion of the interlevel dielectric layer 14 ′ and the vias 30 in the upper portion of the interlevel dielectric layer 14 ′ are concurrently extended into the lower portion of the interlevel dielectric layer 14 ′.
• the mask layer 28 is removed by a conventional process creating a third intermediate structure 34 .
• An electrically conductive material 22 ′ e.g.,tungsten, is then blanket deposited over the interlevel dielectric layer 14 ′ such that the trace depressions 18 ′ and vias 30 are filled therewith, as shown in FIG. 2H .
• the electrically conductive material 22 ′ is then planarized using, e.g., a mechanical abrasion technique such as chemical mechanical planarization (CMP), to isolate the electrically conductive material 22 ′ in the vias 30 and trace depressions 18 ′.
• CMP chemical mechanical planarization
• such techniques while effective for forming elongated conductive elements and discrete conductive structures in the material for which the technique was designed, e.g., SiO 2 , may not be as effective for creating such conductive elements or structures in other materials, such as semiconductor substrates (e.g., silicon wafers) or films (e.g., passivation films).
• semiconductor substrates e.g., silicon wafers
• films e.g., passivation films
• the inventor has recognized that a method of forming elongated conductive elements and discrete conductive structures in a semiconductor substrate or film that utilizes fewer process steps and less material than conventional processing techniques would be desirable. Further, the inventor has recognized that a method of forming elongated conductive elements and discrete conductive structures which is void of photoprocessing steps and which may be utilized to create multiple elongated conductive elements and discrete conductive structures substantially simultaneously would be advantageous.
• U.S. Pat. No. 6,114,240 discloses a method for laser machining conductive vias for interconnecting contacts (e.g., solder balls, bond pads and the like) on semiconductor components.
• a laser beam is focused to produce vias having a desired geometry, e.g., hourglass, inwardly tapered, or outwardly tapered.
• the inventor has recognized that a laser machine processing technique which may be used for the formation of elongated conductive elements, e.g., traces and the like, in semiconductor substrates or films would be advantageous. Further, a technique wherein multiple and different elongated conductive elements and discrete conductive structures may be defined in a single layer (e.g., a substrate or film) substantially simultaneously would be desirable.
• the present invention in one embodiment, includes a method for creating depressions in a semiconductor substrate using laser machining processes and using such depressions to define precise electrical pathways in a semiconductor device structure.
• the method includes providing a semiconductor substrate (e.g., a silicon wafer) and forming one or more electrical pathways in the semiconductor substrate using laser machining processes.
• the electrical pathways may subsequently be filled with an electrically conductive material (e.g., a metal, a conductive polymer, or conductive nano-particles) and planarized to create one or more elongated conductive elements in the semiconductor substrate.
• the semiconductor substrate is formed of a conductive semiconductor material such as silicon (e.g., a silicon substrate used for test purposes)
• a conductive semiconductor material such as silicon (e.g., a silicon substrate used for test purposes)
• an insulating layer comprising an insulating material, such as silicon dioxide (SiO 2 ), silicon nitride (Si 3 N 4 ), or parylene, may be deposited or grown on the surface of the semiconductor substrate prior to filling the electrical pathways therein with the electrically conductive material.
• the present invention in another embodiment, further includes a method for creating depressions in a film residing on a semiconductor substrate, which depressions define precise electrical pathways in a semiconductor device structure.
• the film may include, for instance, a dielectric film in the form of an interlevel dielectric layer, a passivation film, or the like.
• the method includes providing a semiconductor substrate and forming a film over the semiconductor substrate.
• the method further includes forming one or more electrical pathways in the film using laser machining processes.
• the electrical pathways may subsequently be filled with an electrically conductive material (e.g., a metal, a conductive polymer, or conductive nano-particles) to create one or more elongated conductive elements in the film.
• an electrically conductive material e.g., a metal, a conductive polymer, or conductive nano-particles
• ablated electrical pathways may extend into the film a depth less than the full thickness of the film.
• the ablated electrical pathways may extend through the full thickness of the film such that the semiconductor substrate, including any active areas thereon, may be contacted.
• the electrical pathways may be extended into and even through the semiconductor substrate.
• the present invention in a further embodiment, includes a method for creating one or more elongated conductive elements and one or more discrete conductive structures substantially simultaneously in a single semiconductor substrate or film layer.
• substantially simultaneously is used to indicate a rapid traversal of a laser beam over the surface of the substrate or film, as more fully described below.
• the method includes providing a semiconductor substrate, optionally providing a film layer over the semiconductor substrate, and substantially simultaneously forming locations and configurations for one or more elongated conductive elements and one or more discrete conductive structures in the substrate or film using laser machining processes.
• the resulting depressions defining the elongated conductive element(s) and discrete conductive structure(s) may subsequently be filled with an electrically conductive material (e.g., a metal, a conductive polymer, or conductive nano-particles).
• an electrically conductive material e.g., a metal, a conductive polymer, or conductive nano-particles.
• the present invention includes a method for creating electrical connections through a sidewall of a semiconductor device structure using laser machining processes.
• the electrical connections may include traces or lines for signal lines, power and ground lines, and the like, to provide access to power, signal and ground sources external to the semiconductor device structure.
• the method includes providing a semiconductor substrate, optionally forming a film layer over the semiconductor substrate and forming one or more electrical connections through a sidewall of the semiconductor substrate or film using laser machining processes.
• the electrical connection(s) may subsequently be filled with an electrically conductive material, e.g., a metal, a conductive polymer, or conductive nano-particles.
• Such method may be useful, for instance, in forming a die connect for a vertical surface mount package.
• FIGS. 1A-1E are side cross-sectional views schematically illustrating a prior art method of forming a damascene structure
• FIGS. 2A-2I are side cross-sectional views schematically illustrating a prior art method of forming a dual damascene structure
• FIGS. 3A-3E are side cross-sectional views schematically illustrating a method in accordance with the present invention for forming elongated conductive elements (e.g., traces) in a semiconductor substrate (e.g., a silicon wafer);
• a semiconductor substrate e.g., a silicon wafer
• FIG. 3F is a top plan view of a semiconductor device having a plurality of filled elongated conductive elements in a semiconductor substrate thereof;
• FIGS. 4A-4E are side cross-sectional views schematically illustrating a method in accordance with the present invention for forming elongated conductive elements in an interlevel dielectric layer;
• FIG. 4F is a top plan view of a semiconductor device having a plurality of filled elongated conductive elements in an interlevel dielectric layer thereof;
• FIGS. 5A-5E are side cross-sectional views schematically illustrating a method (in accordance with the present invention) for forming elongated conductive elements (e.g., traces) in a semiconductor substrate concurrently with the formation of a discrete conductive structure, e.g., a conductive via;
• elongated conductive elements e.g., traces
• FIG. 5F is a top plan view of a semiconductor device having a plurality of filled elongated conductive elements in a semiconductor substrate thereof and a discrete conductive structure in association with and connected to one of the elongated conductive elements;
• FIGS. 6A-6E are side cross-sectional views schematically illustrating a method (in accordance with the present invention) for forming elongated conductive elements in an interlevel dielectric layer concurrently with the formation of a discrete conductive structure;
• FIG. 6F is a top plan view of a semiconductor device having a plurality of filled elongated conductive elements in an interlevel dielectric layer thereof and a discrete conductive structure in association with and connected to one of the elongated conductive elements;
• FIG. 7 is a side view of a semiconductor device, e.g., a cellular telephone/Personal Digital Assistant (PDA) combination unit, which includes a plurality of stacked chips, such device having precise vertical electrical connections formed through the thickness of multiple chips in the stack; and
• a semiconductor device e.g., a cellular telephone/Personal Digital Assistant (PDA) combination unit, which includes a plurality of stacked chips, such device having precise vertical electrical connections formed through the thickness of multiple chips in the stack; and
• PDA Personal Digital Assistant
• FIG. 8 is a perspective view of a semiconductor device structure having an electrical connection formed directly through a sidewall thereof.
• the present invention is directed to a method for creating depressions in a semiconductor substrate or film using laser machining, or ablation, processes.
• the depressions define traces or lines for signals lines, power and ground lines, and other elongated conductive elements utilized for defining electrical pathways in a semiconductor device.
• the method requires fewer processing steps than conventional mask and etch techniques and enables the creation of lines or traces substantially simultaneously with discrete conductive structures, such as vias or bond pads. Further, the process offers a lower cost alternative to conventional damascene and dual damascene processes and enables the formation of elongated conductive elements and discrete conductive structures of varying shapes to maximize use of the substrate or film.
• An exemplary application of the technology of the present invention is for creating electrical pathways to form a redistribution layer in wafer level packaging.
• the particular embodiments described herein are intended in all respects to be illustrative rather than restrictive. Other and further embodiments will become apparent to those of ordinary skill in the art to which the present invention pertains without departing from its scope
• FIGS. 3A-3E , 4 A- 4 E, 5 A- 5 E and 6 A- 6 E illustrate various views of techniques according to the present invention for forming depressions in a semiconductor substrate ( FIGS. 3A-3E and 5 A- 5 E) or film ( FIGS. 4A-4E and 6 A- 6 E), which depressions define traces or lines for signal lines, power and ground lines, and other elongated conductive elements in semiconductor device structures.
• a semiconductor substrate FIGS. 3A-3E and 5 A- 5 E
• film FIGS. 4A-4E and 6 A- 6 E
• the methods and structures described herein do not form a complete process for manufacturing semiconductor device structures. The remainder of the process is known to those of ordinary skill in the art and, therefore, only the process steps and structures necessary to understand the method of the present invention are described herein.
• steps in an exemplary method according to the present invention for fabricating a semiconductor device structure 100 having a plurality of elongated conductive elements in the form of traces 102 in the semiconductor substrate 104 thereof are illustrated. It will be understood and appreciated by those of ordinary skill in the art that while the process depicted illustrates formation of a plurality of traces 102 , the process sequence illustrated may also be utilized for the formation of other elongated conductive elements as well.
• semiconductor substrate includes a semiconductor wafer or other substrate comprising a layer of semiconductor material, such as a silicon wafer, a silicon on insulator (“SOI”) substrate, a silicon on sapphire (“SOS”) substrate, an epitaxial layer of silicon on a base semiconductor foundation, and other semiconductor materials including, but not limited to, silicon-germanium, germanium, gallium arsenide and indium phosphide.
• SOI silicon on insulator
• SOS silicon on sapphire
• a desired pattern of one or more trace precursors in the form of trace depressions 108 may be formed in a surface 103 of the semiconductor substrate 104 using a focused laser beam 110 .
• a focused laser beam 110 In practice, one would place a semiconductor wafer, or other suitable semiconductor substrate 104 , on a platen of a suitable laser machining apparatus.
• the desired pattern of trace depressions 108 may be stored in a software program associated with the laser machining apparatus such that upon activation of the laser machining apparatus, the desired pattern may be ablated in the surface of the semiconductor substrate 104 .
• the focused laser beam 110 rapidly traverses the surface 103 of the semiconductor substrate 104 , pausing briefly in those locations where a trace depression 108 is desired. Due to the rapidity of the process, the method of the present invention would typically be carried out at the wafer level.
• a suitable laser machining apparatus for forming the trace depressions 108 is Model No. 2700 manufactured by Electro Scientific, Inc., of Portland, Oreg.
• Another suitable laser machining apparatus is manufactured by General Scanning of Somerville, Mass. and is designated as Model No. 670-W.
• Yet another suitable laser machining apparatus for forming the trace depressions 108 is manufactured by Synova S.A., Lausanne, Switzerland.
• a representative laser fluence for forming the trace depressions 108 through a semiconductor substrate 104 is from about 2 to about 10 watts/opening at a pulse duration of 20-25 NS, and at a repetition rate of up to several thousand per second.
• the wavelength of the focused laser beam 110 may be a standard UV wavelength (e.g., 355 nm) or green wavelength (e.g., 1064 nm-532 nm).
• the width of the trace depressions 108 can be from about 10 ⁇ m to about 2 mils or greater.
• the footprint of the focused laser beam 110 is limited only by the available optics.
• the footprint of the focused laser beam 110 will become reduced in dimension, such that trace depressions 108 having increasingly smaller widths may be formed utilizing the technology of the present invention.
• the laser machining process of the present invention results in the formation of trace depressions 108 which taper inward as the depth of the semiconductor substrate 104 increases.
• the trace depressions 108 may extend into the semiconductor substrate 104 a distance less than the thickness of the semiconductor substrate 104 as shown, or may extend through the full thickness of the semiconductor substrate 104 (embodiment not shown). Additionally, each trace depression 108 may extend the same distance into the semiconductor substrate 104 (embodiment not shown) or may extend into the semiconductor substrate 104 by varying distances as shown.
• the semiconductor substrate 104 may be etched to clean up the trace depressions 108 and smooth the cross-sectional shape thereof. Etching in this manner may remove slag created by the laser machining process as well as accent the desired shape(s) of the trace depressions 108 . Conventional wet etch or dry etch techniques may be employed.
• dry etch In contrast with wet etch techniques, techniques involving dry etch, including, without limitation, glow-discharge sputtering, ion milling, reactive ion etching (RIE), reactive ion beam etching (RIBE), plasma etching, point plasma etching, magnetic ion etching, magnetically enhanced reactive ion etching, plasma enhanced reactive ion etching, electron cyclotron resonance and high-density plasma etching, are capable of etching in a substantially anisotropic fashion. This means that the target area of a substrate is etched primarily in a substantially transverse or perpendicular direction relative to the plane of the surface of the semiconductor substrate 104 . Thus, such dry etch techniques are capable of defining structures with substantially vertical sidewalls. Due to a trend in semiconductor fabrication processes toward decreased dimensions of structures on semiconductor devices, dry etching is often desirable for defining structures upon semiconductor device substrates.
• An electrically conductive material 112 may subsequently be blanket coated over the etched semiconductor substrate 104 using a suitable deposition process such that the trace depressions 108 are filled therewith. This step is shown in FIG. 3D .
• Suitable deposition processes include, by way of example and not limitation, plating, solder, atomized nano-particle deposition, CVD, PECVD, sputtering, and the like.
• the electrically conductive material 112 may comprise a metal including, without limitation, solder, aluminum, titanium, nickel, iridium, copper, gold, tungsten, silver, platinum, palladium, tantalum, molybdenum, or alloys of these metals.
• the electrically conductive material 112 may comprise a conductive polymer, such as a metal-filled silicone, or an isotropically conductive or conductor-filled epoxy.
• a conductive polymer such as a metal-filled silicone, or an isotropically conductive or conductor-filled epoxy.
• Suitable conductive polymers are sold, for instance, by Epoxy Technology of Billerica, Mass. One example is its conductive polymer designated E3114-5.
• Further suitable conductive polymers include, without limitation, those sold by A.I. Technology of Trenton, N.J.; Sheldahl of Northfield, Minn.; and 3M of St. Paul, Minn.
• a conductive polymer may be deposited in the trace depressions 108 as a viscous material and subsequently cured as required and may be applied by a dispensing nozzle or squeegee, by spin-coating, or otherwise as known to those of ordinary skill in the art.
• the electrically conductive material 112 may comprise conductive nano-particles.
• traces 102 are formed in a semiconductor substrate 104 comprising a conductive semiconductor material, such as silicon
• an insulating layer comprising an insulating material such as silicon dioxide (SiO 2 ), silicon nitride (Si 3 N 4 ), or parylene) may optionally be deposited or grown over the surface of the semiconductor substrate 104 prior to filling electrical pathways formed therein with the electrically conductive material 112 .
• the electrically conductive material 112 may be planarized using, e.g., a mechanical abrasion technique, such as chemical mechanical planarization (CMP), to laterally isolate the electrically conductive material 112 in the trace depressions 108 .
• CMP chemical mechanical planarization
• the above-described method results in a semiconductor device structure 100 which includes a plurality of traces 102 in the semiconductor substrate 104 thereof (see, FIG. 3F ).
• the method requires fewer processing steps than conventional mask and etch techniques and, in part because there are no photolithography steps involved, the method offers a lower cost alternative to conventional damascene processes.
• the method of the present invention enables the formation of elongated conductive elements of varying shapes, sizes and depths to maximize the use of the substrate.
• the above-described method provides a simple process for altering a desired electrical pattern, prior to ablation, as a new pattern merely must be programmed into the laser machining apparatus. That is, no new masks are required making the process easier and more convenient than conventional mask and etch techniques.
• FIGS. 4A-4E steps in an exemplary method according to the present invention for fabricating a semiconductor device structure 100 ′ having a plurality of elongated conductive elements in the form of traces 102 ′ in the interlevel dielectric layer 114 thereof are illustrated.
• a similar process may also be utilized to form elongated conductive elements in other films, such as a passivation film (e.g., a silicon dioxide (SiO 2 ), silicon nitride (Si 3 N 4 ), or parylene film).
• a passivation film e.g., a silicon dioxide (SiO 2 ), silicon nitride (Si 3 N 4 ), or parylene film.
• the interlevel dielectric layer 114 resides on a semiconductor substrate 104 ′.
• the interlevel dielectric layer 114 may be deposited on the semiconductor substrate 104 ′ using, for example, chemical vapor deposition (CVD) techniques (such as plasma-enhanced chemical vapor deposition (PECVD)) or physical vapor deposition (PVD) techniques (such as sputtering).
• CVD chemical vapor deposition
• PECVD plasma-enhanced chemical vapor deposition
• PVD physical vapor deposition
• the interlevel dielectric layer 114 may be formed of an inorganic or organic material having a low dielectric constant, such as an oxide compound (e.g., SiO 2 ), an aerogel, or a polymer.
• a desired pattern of one or more trace precursors in the form of trace depressions 108 ′ may be formed in a surface 113 of the interlevel dielectric layer 114 using a focused laser beam 110 ′.
• a representative laser fluence for forming the trace depressions 108 ′ through an interlevel dielectric layer 114 is from about 2 to about 10 watts/opening at a pulse duration of 20-25 NS, and at a repetition rate of up to several thousand per second.
• the wavelength of the focused laser beam 110 ′ may be a standard UV wavelength (e.g., 355 nm) or infrared or green wavelength (e.g., 1064 nm-532 nm).
• the width of the trace depressions 108 ′ can be from about 10 ⁇ m to about 2 mils or greater.
• the laser machining process of the present invention results in the formation of trace depressions 108 ′ which taper inward as the depth of the interlevel dielectric layer 114 increases.
• the trace depressions 108 ′ may extend through the full thickness of the interlevel dielectric layer 114 such that the semiconductor substrate 104 ′, including any active areas 116 thereon, may be contacted through the trace depressions 108 ′, as shown in broken lines in FIG. 4B .
• the trace depressions 108 ′ may extend into the interlevel dielectric layer 114 a distance less than the thickness of the interlevel dielectric layer 114 .
• Each trace depression 108 ′ may extend the same distance into the interlevel dielectric layer 114 or the trace depressions 108 ′ may extend into the interlevel dielectric layer 114 by varying distances as shown. As a further option, the trace depressions 108 ′ may be extended into and even through the semiconductor substrate 104 ′ (embodiment not shown).
• the interlevel dielectric layer 114 may be etched to clean up the trace depressions 108 ′ and smooth the cross-sectional shape thereof using conventional wet or dry etch techniques.
• An electrically conductive material 112 ′ may subsequently be blanket coated over the etched interlevel dielectric layer 114 using a suitable deposition process such that the trace depressions 108 ′ are filled therewith. This step is shown in FIG. 4D .
• the electrically conductive material 112 ′ may be planarized using, e.g., a mechanical abrasion technique, such as chemical mechanical planarization (CMP), to laterally isolate the electrically conductive material 112 ′ in the trace depressions 108 ′.
• CMP chemical mechanical planarization
• the above-described method results in a semiconductor device structure 100 ′ which includes a plurality of traces 102 ′ in the interlevel dielectric layer 114 thereof (see, FIG. 4F ).
• trace depressions 108 ′ having a width as small as approximately 15 microns, or smaller, and a shape suitable to define the desired trace pattern, may be formed using currently available optics and the technology of the present invention.
• This offers a significant advantage over conventional mask and etch techniques, as utilizing such prior art processes, the smallest signal line traces that may be formed have a footprint or width of approximately 32 microns.
• the smallest power and ground traces that may be formed utilizing conventional mask and etch processes have an approximately 80 micron footprint or width
• the smallest lead connection dimensions are approximately 60 microns
• the smallest bond dimensions are approximately 30 microns.
• the technology of the present invention will enable a concurrent decrease in the footprint of conductive structures on such devices.
• cellular telephone/Personal Digital Assistant (PDA) combination units which include a plurality of stacked chips 200 (see FIG. 7 ).
• PDA Personal Digital Assistant
• Such devices may have a full thickness of approximately 150 microns.
• precise vertical electrical pathways 202 may be provided which will enable stacked units having a thickness of up to 750 microns or more.
• each chip 200 may be separately fabricated and a plurality of fabricated chips 200 may be assembled into a stack of the desired thickness.
• one or more depressions defining precise electrical pathways 202 may be ablated through one or more of the stacked chips 200 . The depressions may then be filled with the desired conductive material and planarized, as previously described.
• electrical connections 204 may be formed through the sidewalls 206 of a semiconductor device structure 208 as shown in FIG. 8 .
• This is in contrast to conventional mask and etch techniques wherein electrical pathways may be formed only through the top surface 210 and bottom surface (not shown) of the semiconductor device structure 208 .
• the ability to form electrical connections through the sidewalls 206 of the semiconductor device structure 208 offers a significantly greater array of options when forming electrical pathways than is offered using conventional techniques. Such method may be useful, for instance, in forming a die connect for a vertical surface mount package.
• the method of the present invention may also be utilized for creating electrical pathways in a semiconductor device structure, which pathways include an elongated conductive element, such as a trace, in combination with one or more discrete conductive structures, e.g., vias or bond pads, in a single layer (e.g., a semiconductor substrate or interlevel dielectric layer) thereof
• FIGS. 5A-5E and 6 A- 6 E illustrate this exemplary embodiment of the present invention. It will be understood by those of ordinary skill in the art that this method of the present invention may be used to ablate one or more elongated conductive elements and one or more discrete conductive structures in association with or connected to one another.
• the method may be used to substantially simultaneously form separate discrete conductive structures and elongated conductive elements, depending on the desired application.
• the terms “substantially simultaneously” and “concurrently” are interchangeable and are used to indicate a rapid traversal of the laser beam over the surface of the desired substrate or film.
• FIG. 5A a cross-sectional view of an intermediate structure 118 in the fabrication of a semiconductor device structure 120 having a plurality of traces 122 formed in a surface 123 of the semiconductor substrate 124 thereof is shown.
• a desired pattern of elongated conductive element precursors in the form of one or more trace depressions 126 and one or more discrete conductive structure precursors, e.g., vias 128 may be formed in the surface 123 of the semiconductor substrate 124 using a focused laser beam 130 .
• the trace depressions 126 and vias 128 may be of any size, shape and depth suitable to define the desired conductive pathway.
• the vias 128 may extend through the full thickness of the semiconductor substrate 124 (embodiment not shown), or may extend into the semiconductor substrate 124 a depth less than the full thickness thereof as shown.
• the semiconductor substrate 124 may be etched to clean up the trace depressions 126 and vias 128 and to smooth the shape thereof.
• Conventional wet or dry etch techniques as previously listed, may be utilized.
• An electrically conductive material 132 may subsequently be deposited using, e.g., CVD, over the etched semiconductor substrate 124 such that the trace depressions 126 and vias 128 are filled therewith. This step is shown in FIG. 5D .
• a conductive polymer or conductive nano-particles may be deposited.
• the electrically conductive material 132 may be planarized by using, for instance, a mechanical abrasion technique, such as CMP, to laterally isolate the electrically conductive material 132 in the trace depressions 126 and vias 128 .
• the above-described method results in a semiconductor device structure 120 which includes a plurality of traces 122 and one or more vias 128 in a semiconductor substrate 124 thereof (see, FIG. 5F ).
• FIGS. 5A-5E A similar process sequence to that shown in FIGS. 5A-5E may be utilized to ablate one or more elongated conductive elements and one or more discrete conductive structures substantially simultaneously in a semiconductor film such as an interlevel dielectric layer 134 .
• steps in an exemplary method according to the present invention for fabricating a semiconductor device structure 120 ′ having a trace 122 ′ in combination with a via 128 ′ in the interlevel dielectric layer 134 thereof are illustrated.
• a similar process may also be utilized to form elongated conductive elements in other films, such as a passivation film (e.g., a silicon dioxide (SiO 2 ), silicon nitride (Si 3 N 4 ), or parylene film).
• a passivation film e.g., a silicon dioxide (SiO 2 ), silicon nitride (Si 3 N 4 ), or parylene film.
• FIG. 6A a cross-sectional view of an intermediate structure 118 ′ in the fabrication of a semiconductor device structure 120 ′ having a plurality of traces 122 ′ and one or more vias 128 ′ formed in a surface 135 of the interlevel dielectric layer 134 thereof is shown.
• the intermediate structure 118 ′ includes a semiconductor substrate 124 ′, e.g., a silicon wafer, having an interlevel dielectric layer 134 (e.g., a SiO 2 layer) thereon.
• the interlevel dielectric layer 134 may be deposited on the semiconductor substrate 124 ′ using, for example, CVD techniques.
• a desired pattern of elongated conductive element precursors in the form of one or more trace depressions 126 ′ and one or more discrete conductive structure precursors, e.g., vias 128 ′, may be formed in the surface 135 of the interlevel dielectric layer 134 using a focused laser beam 130 ′.
• the trace depressions 126 ′ and vias 128 ′ may be of any size, shape and depth suitable to define the desired conductive pathway.
• the vias 128 ′ may extend through the full thickness of the interlevel dielectric layer 134 , as shown in broken lines in FIG.
• the vias 128 ′ may extend into the interlevel dielectric layer 134 a depth less than the thickness of the interlevel dielectric layer 134 .
• the vias 128 ′ may be extended into and even through the semiconductor substrate 124 ′ (embodiment not shown).
• the interlevel dielectric layer 134 may be etched to clean up the trace depressions 126 ′ and vias 128 ′ and to smooth the shape thereof.
• Conventional wet or dry etch techniques as previously listed, may be utilized.
• An electrically conductive material 132 ′ may subsequently be deposited using, e.g., CVD, over the etched interlevel dielectric layer 134 such that the trace depressions 126 ′ and vias 128 ′ are filled therewith. This step is shown in FIG. 6D .
• a conductive polymer may be deposited.
• the electrically conductive material 132 ′ may be planarized by using, for instance, a mechanical abrasion technique, such as CMP, to laterally isolate the electrically conductive material 132 ′ in the trace depressions 126 ′ and vias 128 ′. If desired, and if the vias 128 ′ are not formed entirely through the semiconductor substrate 124 ′, the semiconductor substrate 124 ′ may be back-ground or etched back to expose the electrically conductive material 132 ′ at the bottoms of the vias 128 ′.
• a mechanical abrasion technique such as CMP
• the above-described method results in a semiconductor device structure 120 ′ which includes a plurality of traces 122 ′ and one or more filled vias 128 ′ in a single interlevel dielectric layer 134 thereof (see, FIG. 6F ).
• the above-described method requires fewer processing steps than conventional dual damascene processes and, in part because there are no photolithography steps, the method offers a lower cost alternative to conventional dual damascene processes.
• the method of the present invention enables the formation of one or more elongated conductive elements or structures substantially simultaneously in a single layer, each such element or structure having a varying size and shape to maximize use of the substrate or film.
• the method provides a simple process for altering a desired electrical pattern, prior to ablation, as a new pattern merely must be programmed into the laser machining apparatus. That is, no new masks are required rendering the present invention easier and more convenient than conventional mask and etch techniques.

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• 2003
  • 2003-09-29 US US10/673,692 patent/US7364985B2/en not_active Expired - Fee Related
• 2006
  • 2006-08-04 US US11/499,078 patent/US20060270196A1/en not_active Abandoned

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