US20080123748A1 - Compression circuitry for generating an encoded bitstream from a plurality of video frames - Google Patents

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• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
  • H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
  • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
  • H04N19/102—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or selection affected or controlled by the adaptive coding
  • H04N19/124—Quantisation
  • H04N19/126—Details of normalisation or weighting functions, e.g. normalisation matrices or variable uniform quantisers
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
  • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
  • H04N19/102—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or selection affected or controlled by the adaptive coding
  • H04N19/13—Adaptive entropy coding, e.g. adaptive variable length coding [AVLC] or context adaptive binary arithmetic coding [CABAC]
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
  • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
  • H04N19/134—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or criterion affecting or controlling the adaptive coding
  • H04N19/136—Incoming video signal characteristics or properties
  • H04N19/137—Motion inside a coding unit, e.g. average field, frame or block difference
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
  • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
  • H04N19/134—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or criterion affecting or controlling the adaptive coding
  • H04N19/146—Data rate or code amount at the encoder output
  • H04N19/15—Data rate or code amount at the encoder output by monitoring actual compressed data size at the memory before deciding storage at the transmission buffer
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
  • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
  • H04N19/169—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding
  • H04N19/17—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object
  • H04N19/172—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a picture, frame or field
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
  • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
  • H04N19/169—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding
  • H04N19/17—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object
  • H04N19/176—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a block, e.g. a macroblock
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
  • H04N19/60—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding
  • H04N19/61—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding in combination with predictive coding
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
  • H04N19/90—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using coding techniques not provided for in groups H04N19/10-H04N19/85, e.g. fractals
  • H04N19/91—Entropy coding, e.g. variable length coding [VLC] or arithmetic coding

Definitions

• the present invention relates to motion picture compression circuits for pictures such as television pictures, and more particularly to a compression circuit complying with H.261 and MPEG standards.
• FIGS. 1A-1C schematically illustrate three methods for compressing motion pictures in accordance with H.261 and MPEG standards.
• pictures may be of intra or predicted type.
• the pictures can also be of bidirectional type.
• Intra (“I”) pictures are not coded with reference to any other pictures.
• Predicted (“P”) pictures are coded with reference to a past intra or past predicted picture.
• Bidirectional (“B”) pictures are coded with reference to both a past picture and a following picture.
• FIG. 1A illustrates the compression of an intra picture I 1 .
• Picture I 1 is stored in a memory area M 1 before being processed.
• the pictures have to be initially stored in a memory since they arrive line by line whereas they are processed square by square, the size of each square being generally 16 by 16 pixels.
• memory area M 1 must be filled with at least 16 lines.
• a macroblock includes four 8 by 8-pixel luminance blocks and two or four 8 by 8-pixel chrominance blocks. The processes hereinafter described are carried out by blocks of 8 by 8 pixels.
• each macroblock of picture 11 is submitted at 10 to a discrete cosine transform (DCT) followed at 11 by a quantization (Q).
• DCT discrete cosine transform
• Q quantization
• a DCT transforms a matrix of pixels (a block) into a matrix whose upper left corner coefficient tends to have a relatively high value. The other coefficients rapidly decrease as the position moves downwards to the right.
• Quantization involves dividing the coefficients of the matrix so transformed, such that a large number of coefficients which are a distance away from the upper left corner are cancelled.
• the quantified matrices are subject to zigzag scanning (ZZ) and to run/level coding (RLC).
• ZZ zigzag scanning
• RLC run/level coding
• Zigzag scanning has the consequence of improving the chances of consecutive series of zero coefficients, each of which is preceded by a non-zero coefficient.
• the run/level coding mainly includes replacing each series from the ZZ scanning with a pair of values, one representing the number of successive zero coefficients and the other representing the first following non-zero coefficient.
• the pairs of values from the RLC are subject to variable length coding (VLC) that includes replacing the more frequent pairs with short codes and replacing the less frequent pairs with long codes, with the aid of correspondence tables defined by the H.261 and MPEG standards.
• VLC variable length coding
• the quantification coefficients can be varied from one block to the next by multiplication by a quantization coefficient. That quantization coefficient is inserted during variable length coding in headers preceding the compressed data corresponding to macroblocks.
• Macroblocks of an intra picture are used to compress macroblocks of a subsequent picture of predicted or bidirectional type.
• decoding of a predicted or bidirectional picture is likely to be achieved from a previously decoded intra picture.
• This previously decoded intra picture does not exactly correspond to the actual picture initially received by the compression circuit, since this initial picture is altered by the quantification at 11 .
• the compression of a predicted or intra picture is carried out from a reconstructed intra picture I 1 rather than from the real intra picture I 1 , so that decoding is carried out under the same conditions as encoding.
• the reconstructed intra picture I 1 r is stored in a memory area M 2 and is obtained by subjecting the macroblocks provided by the quantification 11 to a reverse processing, that is, at 15 an inverse quantification (Q ⁇ 1 ) followed at 16 by an inverse DCT (DCT ⁇ 1 ).
• FIG. 1B illustrates the compression of a predicted picture P 4 .
• the predicted picture P 4 is stored in a memory area M 1 .
• a previously processed intra picture I 1 r has been reconstructed in a memory area M 2 .
• the processing of the macroblocks of the predicted picture P 4 is carried out from so-called predictor macroblocks of the reconstructed picture I 1 r .
• Each macroblock of picture P 4 (reference macroblock) is subject to motion estimation (ME) at 17 (generally, the motion estimation is carried out only with the four luminance blocks of the reference macroblocks).
• This motion estimation includes searching in a window of picture I 1 r for a macroblock that is nearest, or most similar to the reference macroblock.
• the nearest macroblock found in the window is the predictor macroblock. Its position is determined by a motion vector V provided by the motion estimation.
• the predictor macroblock is subtracted at 18 from the current reference macroblock. The resulting difference macroblock is subjected to the process described with relation to FIG. 1A .
• the predicted pictures serve to compress other predicted pictures and bidirectional pictures.
• the predicted picture P 4 is reconstructed (P 4 r ) in a memory area M 3 by an inverse quantification at 15 , inverse DCT at 19 , and addition at 19 of the predictor macroblock that was subtracted at 18 .
• the vector V provided by the motion estimation 17 is inserted in a header preceding the data provided by the variable length coding of the currently processed macroblock.
• FIG. 1C illustrates the compression of a bidirectional picture B 2 .
• Bidirectional pictures are provided for in MPEG standards only.
• the processing of the bidirectional pictures differs from the processing of predicted pictures in that the motion estimation 17 consists in finding two predictor macroblocks in two pictures I 1 r and P 4 r , respectively, that were previously reconstructed in memory areas M 2 and M 3 .
• pictures I 1 r and P 4 r respectively correspond to a picture preceding the bidirectional picture that is currently processed and to a picture following the bidirectional picture.
• the mean value of the two obtained predictor macroblocks is calculated and is subtracted at 18 from the currently processed macroblock.
• the bidirectional picture is not reconstructed because it is not used to compress another picture.
• the motion estimation 17 provides two vectors V 1 and V 2 indicating the respective positions of the two predictor macroblocks in pictures I 1 r and P 4 r with respect to the reference macroblock of the bidirectional picture.
• Vectors V 1 and V 2 are inserted in a header preceding the data provided by the variable length coding of the currently processed macroblock.
• the reference macroblock is submitted to either predicted processing with the vector that is found, predicted processing with a zero vector, or intra processing.
• the reference macroblock is submitted to either bidirectional processing with the two vectors, predicted processing with only one of the vectors, or intra processing.
• a predicted picture and a bidirectional picture may contain macroblocks of different types.
• the type of a macroblock is also data inserted in a header during variable length coding.
• the motion vectors can be defined with an accuracy of half a pixel.
• To search a predictor macroblock with a non integer vector first the predictor macroblock determined by the integer part of this vector is fetched, then this macroblock is submitted to so-called “half-pixel filtering”, which includes averaging the macroblock and the same macroblock shifted down and/or to the right by one pixel, depending on the integer or non-integer values of the two components of the vector.
• the predictor macroblocks may be subjected to low-pass filtering. For this purpose, information is provided with the vector, indicating whether filtering has to be carried out or not.
• a GOP generally begins with an intra picture. It is usual, in a GOP, to have a periodical series, starting from the second picture, including several successive bidirectional pictures, followed by a predicted picture, for example of the form IBBPBBPBB . . . where I is an intra picture, B a bidirectional picture, and P a predicted picture.
• I is an intra picture
• B a bidirectional picture
• P a predicted picture.
• the processing of each bidirectional picture B is carried out from macroblocks of the previous intra or predicted picture and from macroblocks of the next predicted picture.
• FIG. 2 The various functional blocks that are used in a typical prior art functional implementation are shown in FIG. 2 .
• the motion estimation engine and memory for storing macroblocks and video pictures have been omitted.
• a reference macroblock is supplied to a subtraction circuit, where the predictor for that macroblock is subtracted (in the case of B and P pictures, only).
• the resultant error block (or the original macroblock, for I pictures) is passed on to a DCT block, then to a quantization block for quantization.
• the quantized macroblock is forwarded to an encoding process and an inverse quantization block.
• the encoding process takes the quantized macroblock and zig-zag encodes it, performs run level coding on the resultant data, then variable length packs the result, outputting the now encoded bitstream.
• bitstream is monitored and can be controlled via feedback to a rate control system. This controls quantization (and dequantization) to meet certain objectives for bitstream.
• a typical objective is a maximum bit-rate, although other factors can also be used.
• the inverse quantization block in FIG. 2 is the start of a reconstruction chain that is used to generate a reconstructed version of each frame, so that the frames the motion prediction engine is searching for matching macroblocks are the same as will be regenerated during decoding proper.
• the macroblock is inverse DCT transformed in IDCT block and added to the original predictor used to generate the error macroblock. This reconstructed block is stored in memory for subsequent use in the motion estimation process.
• the various blocks required to generate the encoded output stream have different computational requirements, which themselves can vary according to the particular application or user selected restrictions. Throttling of the output bitstream to meet bandwidth requirements is typically handled by manipulating the quantization step.
• a decoder circuit comprises: a processor configured to inverse quantize macroblocks to generate inverse quantized macroblocks; an inverse discrete cosine transformation circuit that processes the inverse quantized macroblocks from the processor to generate IDCT transformed macroblocks; and an addition circuit that adds a single IDCT transformed macroblock and a corresponding predictor macroblock to generate a reconstructed picture macroblock.
• a method for decoding an encoded bitstream comprises: inverse quantizing decoded macroblocks in a processor to generate inverse quantized macroblocks; generating inverse discrete cosine transformation (IDCT) transformed macroblocks from the inverse quantized macroblocks; and adding a single IDCT transformed macroblock and a corresponding predictor macroblock to generate a reconstructed picture macroblock.
• IDCT inverse discrete cosine transformation
• a video compression circuit comprises: a discrete cosine transform (DCT) circuit for accepting prediction error macroblocks and generating DCT transformed macroblocks; a processor being configured to quantize the DCT transformed macroblocks to generate quantized macroblocks, and to inverse quantize the quantized macroblocks to generate inverse quantized macroblocks; an inverse discrete cosine transform (IDCT) circuit, wherein the IDCT circuit transforms the inverse quantized macroblocks to generate reconstructed prediction error macroblocks; and an addition circuit for adding a single reconstructed prediction error macroblock and a corresponding predictor macroblock to generate respective reconstructed macroblocks for use in the encoding of other macroblocks.
• DCT discrete cosine transform
• IDCT inverse discrete cosine transform
• a method of generating a compressed video bitstream comprises: generating DCT transformed macroblocks by applying prediction error macroblocks to a discrete cosine transform (DCT) circuit; quantizing the DCT transformed macroblocks to generate quantize macroblocks; inverse quantizing the quantize macroblocks to generate inverse quantize macroblocks; generating reconstructed prediction error macroblocks by applying the inverse quantize macroblocks to a IDCT circuit; and adding a single reconstructed prediction error macroblock and a corresponding predictor macroblock to generate respective reconstructed macroblocks for use in the encoding of other macroblocks.
• DCT discrete cosine transform
• an encoder/decoder circuit comprises: a discrete cosine transform (DCT) circuit to generate DCT transformed macroblocks from prediction error macroblocks; a processor configured to quantize the DCT transformed macroblocks to generate quantized macroblocks, and to inverse quantize the quantized macroblocks to generate inverse quantized macroblocks; an inverse discrete cosine transform (IDCT) circuit to transform the inverse quantized macroblocks to generate reconstructed prediction error macroblocks; an addition circuit to add a single reconstructed prediction error macroblock and a corresponding predictor macroblock to generate respective reconstructed macroblocks; and a control circuit to configure the encoder/decoder circuit to encode or decode a bitstream.
• DCT discrete cosine transform
• ICT inverse discrete cosine transform
• a method for encoding and decoding in an encoder/decoder circuit having a control circuit to configure the encoder/decoder circuit for encoding or decoding mode comprises: generating DCT transformed macroblocks by applying prediction error macroblocks to a discrete cosine transform (DCT) circuit; quantizing the DCT transformed macroblocks to generate quantized macroblocks; inverse quantizing the quantized macroblocks to generate inverse quantized macroblocks; generating reconstructed prediction error macroblocks by applying the inverse quantized macroblocks to the IDCT circuit; and adding the reconstructed prediction error macroblocks and corresponding predictor macroblocks to generate respective reconstructed macroblocks; wherein the reconstructed macroblocks are useful either as decoded reconstructed picture macroblocks or for encoding other macroblocks.
• DCT discrete cosine transform
• FIGS. 1A to 1C previously described, illustrate three picture compression processes according to H.261 and MPEG standards, in accordance with the prior art
• FIG. 2 previously described, is a schematic of the functional blocks in a typical MPEG encoding scheme, in accordance with the prior art
• FIG. 3 is a schematic of an encoder loop
• FIG. 4 is a schematic of compression circuitry for generating an encoded bitstream from a plurality of video frames.
• FIG. 3 shows an overview of the functional blocks of one embodiment, in which hardware functionality is represented by rectangular blocks and software functionality is represented by an oval block.
• the functional blocks include a subtraction circuit 300 for subtracting each predictor macroblock, as supplied by the motion estimation engine (described later) from its corresponding picture macroblock, to generate a prediction error macroblock. For an I picture, there is no predictor, so the macroblock is passed through the subtraction circuit with no change.
• the prediction error macroblock is supplied to a DCT circuit 301 where a forward discrete cosine transform (DCT) is performed.
• DCT forward discrete cosine transform
• variable length coded takes place in software.
• variable length coding and packing, or just packing is performed in hardware, since this provides a drastic increase in performance compared to software coding running on a general purpose processor.
• the processor 302 also performs inverse quantization (Q ⁇ 1 ), and the resultant inverse quantized macroblocks are sent to an inverse DCT (IDCT) circuit 303 via a streaming interface.
• IDCT inverse DCT
• An inverse DCT (IDCT) is performed and the resultant reconstructed error macroblock is added to the original predictor macroblock (for P and B pictures only) by an addition circuit 304 .
• the predictor macroblocks have been delayed in a delay buffer 305 .
• the macroblock is fully reconstructed after the IDCT circuit.
• the resultant reconstructed macroblocks are then stored in memory for use by the motion estimation engine in generating predictors for future macroblocks. This is necessary because it is reconstructed macroblocks that a decoder will subsequently use to reconstruct the pictures.
• FIG. 4 shows a more detailed version of the embodiment of FIG. 3 , and like features are denoted by corresponding reference numerals.
• the motion estimation engine 400 for use with the encoding circuitry is also shown.
• the motion estimation engine 400 determines the best matching macroblock (or average of two macroblocks) for each macroblock in the frame (for B and P pictures only) and subtracts it from the macroblock being considered to generate a predictor error macroblock.
• the method of selecting predictor macroblocks is not a part of the present solution and so is not described in greater detail herein.
• the motion estimation engine 400 outputs the macroblocks, associated predictor macroblocks and vectors, and other information such as frame type and encoding modes, to DCT/IDCT circuitry via a direct link. Alternatively, this information can be transferred over a data bus. Data bus transfer principles are well known and so is not described in detail.
• the DCT and IDCT steps are performed in a DCT/IDCT block 401 , which includes combined DCT/IDCT circuitry 301 / 303 that is selectable to perform either operation on incoming data.
• the input is selected by way of a multiplexer 402 , the operation of which will be described in greater detail below.
• the output of the multiplexer is supplied to the delay block 305 and the DCT/IDCT circuitry 301 / 303 .
• Additional data supplied by the motion estimation engine 400 such as the motion vector(s), encoding decisions (intra/non-intra, MC/no MC, field/frame prediction, field/frame DCT) is routed past the delay and DCT/IDCT blocks to a first streaming data interface SDI 403 .
• the outputs of the delay block and the DCT/IDCT circuitry are supplied to an addition circuit 304 , the output of which is sent to memory 450 .
• the output of the DCT/IDCT block 301 / 303 is also supplied to the first SDI port 403 .
• the first SDI port 403 accepts data from the DCT/IDCT block 301 / 303 and the multiplexer 402 and converts it into a format suitable for streaming transmission to a corresponding second streaming SDI port 404 .
• the streaming is controlled by a handshake arrangement between the respective SDI ports.
• the second streaming SDI port 404 takes the streaming data from the first SDI port 403 and converts it back into a format suitable for use within the processor 302 .
• the processor performs quantization 405 , inverse quantization 406 and zig-zag/run level coding 407 as described previously. It will be appreciated that the particular implementations of these steps in software is not relevant, and so is not described in detail.
• the macroblock is returned to a third SDI port 408 , which operates in the same way as the first streaming port to convert and stream the data to a fourth SDI port 409 , which converts the data for synchronous use and supplies it to the multiplexer 402 .
• the processor 302 outputs the run level coded data to a fifth SDI port 410 , which in a similar fashion to the first and third SDI ports, formats the data for streaming transmission to a sixth SDI port 411 , which in turn reformats the data into a synchronous format.
• the data is then variable length coded and packed in hardware VLC circuitry 412 .
• the particular workings of the hardware VLC packing circuitry 412 are well known in the art, are not critical to understanding the present solution and so will not be described in detail. Indeed, as mentioned previously, the VLC operation can be performed in software by the processor, for a corresponding cost in processor cycles.
• the multiplexer and DCT/IDCT block 301 / 303 need to be controlled to ensure that the correct data is being fed to the DCT/IDCT block and that the correct operation is being performed.
• the multiplexer 402 is controlled to provide data from the bus (supplied by the motion estimation engine) to the DCT/IDCT block 301 / 303 , which is set to DCT mode.
• the multiplexer 402 sends data from the fourth SDI port 409 to the DCT/IDCT block 301 / 303 , which is set to IDCT mode.
• the DCT and IDCT functions of the DCT/IDCT block 301 / 303 will be performed in an interleaved manner, with one or more DCT operations being interleaved with one or more IDCT operations, depending upon the order of I, P and B pictures being encoded.
• the encoding circuitry described above can perform decoding of an encoded MPEG stream. This is because the inverse quantization software and IDCT hardware are common to the encoding and decoding process. There are at least three ways this can be achieved:
• the dequantized coefficient blocks can be streamed from the processor to the IDCT/DCT block 301 / 303 via the third and fourth SDI ports 408 and 409 .
• the results of the IDCT are then read back via the first and second SDI ports 403 and 404 .
• Option 1 can be extended to allow more of the decoding load to be passed to the DCT/IDCT block 401 .
• the predictor blocks are read into the delay buffer 305 .
• the coefficient blocks are then read in via the same route by the DCT/IDCT block 301 / 303 (in IDCT 30 mode).
• the predictor and IDCT processed macroblocks are combined by the addition circuitry 304 and written to system memory via the system data bus.
• the motion estimation block is configured to provide the predictor blocks to the delay buffer 305 via the multiplexer 402 .
• the coefficient blocks are provided to the DCT/IDCT block 301 / 303 (in IDCT mode), and the remainder of the procedure is as per the second decoding arrangement.

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  • 2002-03-18 EP EP10183232A patent/EP2309759A1/en not_active Withdrawn
  • 2002-03-18 EP EP02251932A patent/EP1347650A1/en not_active Ceased
• 2003
  • 2003-03-17 US US10/391,442 patent/US7372906B2/en active Active
• 2008
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