US20100008003A1 - Electrostatic discharge protection device - Google Patents

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• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
  • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
  • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs

Definitions

• the present invention relates to an electrostatic discharge protection device. More particularly, the present invention relates to an electrostatic discharge protection device for providing an electrostatic discharge path between two circuitries.
• An electrostatic discharge phenomenon releases energy to a circuitry, causing a temporarily high voltage and current in the circuitry.
• This high voltage and current may damage the circuitry in a chip. For example, it may damage internal circuits, or the internal conducting wire. Thus, it is important to provide a non-damaging electrostatic discharge path between internal circuits.
• the power cut cell is generally a power cut diode combination comprising two power cut diode modules configured to conduct in contrary directions.
• the combination can be set between two power supply terminals or two ground terminals, as shown in FIG. 1 .
• FIG. 1 shows two power cut diode combinations 11 , 12 .
• the power cut diode combination 11 connects power supply terminals VCC 1 and VCC 2
• the power cut diode combination 12 connects ground terminals GND 1 and GND 2 .
• the power cut diode combination 11 comprises two power cut diode modules 111 and 112 configured to conduct in contrary directions.
• the power cut diode combination 12 comprises two power cut diode modules 121 and 122 configured to conduct in contrary directions.
• the power supply terminals and ground terminals respectively connect with the electrostatic discharge (ESD) protection device (not shown in FIG. 1 ) for conducting ESD energy out of the circuitry. Meanwhile, the turn-on voltage of the diode can block noise flowing between the two internal circuits when the power cut diode is not turned on.
• ESD electrostatic discharge
• the operations of the power cut diode combinations 11 , 12 are described as follows.
• an ESD protection device connected to the VCC 1 forces the ESD energy out of the circuitry.
• the power cut diode module 111 guides the ESD energy to the VCC 2 , so an ESD protection device connected to the VCC 2 can force the ESD energy out of the circuitry jointly.
• the power cut diode module 112 can guide the ESD energy to the VCC 1 .
• the power cut diode combination 12 operates in a similar way and forces the ESD energy out of the circuitry.
• FIG. 2 shows an ideal diode 21 and an internal resistor 22 in series, where the ideal diode 22 has an input 211 and an output 212 .
• the ideal diode 21 is presumed to have a threshold voltage without an internal resistor.
• the ideal diode 21 turns on, and the current flows through the internal resistor 22 and out the output 212 .
• the electrostatic discharge energy turns on the ideal diode 21 , a voltage is produced by the two ends of the internal resistor 22 due to the flowing current. As a result, the electrostatic discharge energy is more or less blocked by the internal resistor 22 .
• drawbacks of applying a combination of power cut diodes as a power cut cell there are drawbacks of applying a combination of power cut diodes as a power cut cell.
• an electrostatic discharge protection device with a low internal resistor and a noise blocking ability is needed in the semiconductor industry.
• the primary objective of this invention is to provide an electrostatic discharge protection device to provide an electrostatic discharge path between two circuits, with each of the circuits having a power supply terminal and a ground terminal.
• the electrostatic discharge protection device comprises an equivalent MOS with a source, a drain and a gate, the drain connecting to the gate, a first end connecting to the gate, and a second end connecting to the source. The first end connects to the power supply terminal and ground terminal of one circuit. The second end connects to the power supply terminal and ground terminal of the other circuit, respectively.
• the electrostatic discharge protection device array comprises a first end, a second end, and a plurality of equivalent MOSs in series, with each equivalent MOS having a source, a drain, and a gate.
• the plurality of equivalent MOSs has a first equivalent MOS and a last equivalent MOS.
• the first end connects to a gate of the first equivalent MOS, and the second end connects to a source of the last equivalent MOS.
• Each MOS has its drain connecting to its gate, while each source of the MOS connects to the gate of the next MOS.
• the first end connects to a power supply terminal and a ground terminal of one circuit.
• the second end connects to a power supply terminal and a ground terminal of another circuit, respectively.
• the invention provides an ESD protection device with a low internal resistor, and the turn-on voltage of the ESD protection device blocks noise from getting into the circuitry.
• FIG. 1 is a conventional electrostatic discharge protection structure
• FIG. 2 is an equivalent model of a diode
• FIG. 3 is a first embodiment of the present invention
• FIG. 4( a ) is a second embodiment of the present invention.
• FIG. 4( b ) is a third embodiment of the present invention.
• FIG. 5 is a fourth embodiment of the present invention.
• FIG. 3 is a first embodiment of the present invention.
• An ESD protection device 3 is equivalent to an N-type MOS (NMOS) device, and comprises a drain 31 with N+ dopant, a source 32 with N+ dopant, a gate 33 , a heavy doping region 34 with P+ dopant, a P-type substrate 35 , a first end 301 , and a second end 302 .
• the symbol “+” means “heavy doping” herein.
• the drain 31 , gate 33 , and first end 301 are electrically connected.
• the source 32 and the heavy doping region 34 are electrically connected to form a body contact.
• the source 32 is also connected to the second end 302 .
• the first end 301 is adapted to connect to the ground GND 1 of an internal circuit. Meanwhile the second end 302 is adapted to connect to the ground GND 2 of another internal circuit.
• a high voltage caused by ESD is present at the GND 1 .
• the high voltage is applied to the gate 33 .
• the voltage difference of the gate 33 and the source 32 is then large enough to turn on the ESD protection device 3 .
• the ESD protection device 3 turns on, it acquires a low turn-on resistor; the ESD energy can thus, be transmitted from the GND 1 to the GND 2 via the ESD protection device 3 .
• a second embodiment of the present invention comprises a protection device 3 and a protection device 4 conducted in the opposite direction to prevent the ESD from communicating with the GND 1 or GND 2 .
• the protection device 3 and the protection device 4 are in-parallel and connected to the GND 1 and the GND 2 .
• FIG. 4( a ) shows the second embodiment, wherein the protection device 3 comprises a first end 301 connecting to the GND 1 and a second end 302 connecting to the GND 2 .
• a plurality of protection devices can be arranged in parallel to provide a larger threshold voltage and thus gain better noise-blocking capabilities.
• FIG. 4( b ) shows a third embodiment of the present invention, wherein a protection device 41 is in-parallel with a protection device 42 to provide ESD protection, and another protection device 43 is in-parallel with its respective protection device 44 .
• FIG. 5 shows a fourth embodiment of the present invention.
• An ESD protection device 5 is equivalent to a P-type MOS (PMOS) device.
• the PMOS comprises a drain 51 with P+ dopant, a source 52 with P+ dopant, a gate 53 , a heavy doping region with N+ dopant, a Nwell 55 , a P substrate 56 , a first end 501 and a second end 502 .
• the Nwell 55 is adapted to a body of the PMOS.
• the drain 51 , gate 53 , and first end 501 are electrically connected together.
• the source 52 and the heavy doping region 54 are electrically connected to form a body contact.
• the source 32 connects to the second end 502 .
• the Nwell 55 is equivalent to a substantial substrate, which means that when a PMOS is based on a P substrate, it needs to form an N well first to isolate the later formed drain and source from the P substrate.
• the protection device 5 is within a P substrate, and the P substrate connects to the lowest voltage level of a chip, the first end 501 and the second end 502 are able to connect to power supply terminals VCC 1 and VCC 2 , or to ground terminals GND 1 and GND 2 .
• the protection device is within an N substrate and formed with an NMOS, the protection device is able to connect to the power supply terminals or ground terminals. As a result, the device can be applied to a different substrate without substantially changing the protection. People skilled in the art can understand and practice the protection device within an N substrate by reviewing the aforementioned disclosure, thus, the same descriptions are omitted.
• this following example will address the connection of two power supply terminals VCC 1 and VCC 2 using the protection device 5 , with the first end 501 connected to the VCC 1 , and the second end 502 connected to the VCC 2 .
• the high voltage also carries through to the source 52 .
• the voltage difference of the gate 53 and the source 52 is then large enough to turn on the ESD protection device 5 .
• the ESD protection device 5 turns on, it acquires a low turn-on resistor so that the ESD energy can be transmitted from the VCC 2 to the VCC 1 via the ESD protection device 5 .
• the protection device 5 can join another protection device that is conducted in an opposite direction to prevent the ESD from being present at the VCC 1 or VCC 2 .
• a plurality of protection devices in-series can provide a better noise-blocking effect. People skilled in the art can understand and practice various combinations of protection devices by reviewing the aforementioned disclosure. Thus, the redundant descriptions are omitted.
• the present invention is thus advantageous in providing an ESD protection device with a low internal resistor.

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• Semiconductor Integrated Circuits (AREA)
• Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

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Citations (9)

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• 2006
  • 2006-09-27 TW TW095135789A patent/TW200816878A/en unknown
• 2007
  • 2007-03-15 US US11/724,194 patent/US7608894B2/en not_active Expired - Fee Related
• 2009
  • 2009-09-18 US US12/562,823 patent/US20100006943A1/en not_active Abandoned
  • 2009-09-18 US US12/562,779 patent/US20100008003A1/en not_active Abandoned

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