US20140232017A1 - Identification mechanism for semiconductor device die - Google Patents

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Definitions

• This disclosure relates generally to semiconductor fabrication, and more specifically, to a mechanism for visibly identifying on each device die of a wafer.
• a typical procedure in the manufacturing process includes photolithography, which involves passing light through a reticle, or mask, to expose a layers image for one or more die on a wafer. The wafer is moved to a new position (a process called “stepping”) and the photolithographic processes are repeated until the pattern of the reticle has been replicated on each die of the wafer.
• photolithography which involves passing light through a reticle, or mask, to expose a layers image for one or more die on a wafer.
• the wafer is moved to a new position (a process called “stepping”) and the photolithographic processes are repeated until the pattern of the reticle has been replicated on each die of the wafer.
• a drawback of such a conventional photolithographic process is that it is not possible to provide a unique identification for each die on the wafer. This is because the same reticle is exposed in multiple locations and results in the same pattern at each location. But the ability to uniquely identify each die from a wafer, even after the die have been separated from the wafer, can provide certain advantages such as tracking of the die during and after test, assembly, and packaging processes. It is therefore desirable to provide a mechanism by which each die from a wafer can be uniquely identified. It is further desirable that the identification mechanism have minimal impact on overall device processing steps, as well as provide no increase in radio frequency interference on the device die.
• FIG. 1 is a simplified block diagram illustrating a semiconductor wafer map for individual integrated circuit dies formed thereon.
• FIG. 2 is a simplified block diagram illustrating an example of a semiconductor device die.
• FIG. 3 is a simplified block diagram illustrating a bond pad including identifying features, in accord with embodiments of the present invention.
• FIG. 4 is a simplified block diagram illustrating one example of a method by which a unique coding can be provided to a semiconductor device die, using embodiments of the present invention.
• FIG. 5 is a simplified block diagram illustrating a bond pad having identification features of different shapes, in accord with embodiments of the present invention.
• FIG. 6 is a simplified block diagram illustrating a bond pad having identification features provided by indentations in the bond pad, in accord with an alternative embodiment of the present invention.
• a method and system for uniquely identifying each semiconductor device die from a wafer is provided by embodiments of the present invention. Identifying features are associated with device die bond pads.
• one or more tab features are patterned and associated with each of one or more device die bond pads. These features can represent a code (e.g., binary or ternary) that uniquely identifies each device die on the wafer. For example, an (X, Y) coordinate system can be represented by the code.
• Each tab feature can be the same shape or different shapes, depending upon the nature of coding desired.
• portions of the one or more device die bond pads can be omitted as a mechanism for providing coded information, rather than adding portions to the device die bond pads.
• identifying features By associating the identifying features with the bond pads, practical size limitations of the identifying features can be significantly smaller than for standalone features. Further, by locating the identifying features in the bond pad region of the semiconductor device die, any RF interference associated with the additional metallization is minimized since the features are not located over a circuit region of the semiconductor device die.
• the semiconductor device die can have an electronic encoded chip identifier capability that can be read by an external device. But there are many semiconductor device die than do not have EECID capability.
• FIG. 1 is a simplified block diagram illustrating a semiconductor wafer map for individual integrated circuit dies formed thereon.
• Wafer perimeter 110 represents a semiconductor wafer used for semiconductor device fabrication.
• Grid 120 provides an (X, Y) coordinate system defining a set of squares within each of which a semiconductor device die (e.g., device die 140 ) is formed, if the square is located on the wafer and in a processable region of the wafer.
• corner region 130 has associated grid coordinates, but squares associated with those coordinates are either not within wafer parameter 110 or are so close to the edge of wafer perimeter 110 that no device die will be formed in that region.
• wafer diameters of 150 mm, 200 mm, and 300 mm are common.
• Semiconductor wafers of these dimensions can be processed to include hundreds to thousands of possible die per wafer (PDPW), depending upon the nature of the circuitry provided by those semiconductor device die and the nature of the processing technology used in manufacturing the semiconductor devices.
• PDPW die per wafer
• a cutting tool is used to singulate the individual dies (e.g., device die 140 ) from the semiconductor wafer and each other die. Once singulated, without unique identification for each die, it is not generally possible to determine where on the original wafer the individual device die were formed.
• FIG. 2 is a simplified block diagram illustrating an example of a semiconductor device die 140 .
• Semiconductor device die 140 includes multiple bond pads 210 for interconnecting the die with other components.
• the number of bond pads 210 on a die can vary depending upon the number of input/outputs to and from the device die circuitry that are required.
• Bond pads can be formed using metallization techniques known in the art, such as sputtering and photolithography, and couple to device interconnects within the die. Bond pads can be formed from a variety of metals, for example, aluminum, gold, metal alloys and the like, depending on the nature of the application.
• a typical semiconductor device die 140 also includes a circuit region 220 surrounded by a circuit perimeter 230 .
• Circuit region 220 is the area of the semiconductor device die that includes the active devices and electrical interconnects forming the integrated circuit, with the exception of input/output leads extending to the bond pads along device die perimeter 240 .
• Input/outputs of circuit region 220 are electrically connected to bond pads 210 using leads 250 .
• Leads 250 are often formed in a device interconnect built up in the device die.
• the bond pads are positioned in a region located between circuit perimeter 230 and device die perimeter 240 .
• the bond pads can be physically separating the circuit region from the region including the bond pads in this manner, damage to devices within the circuit region can be avoided during stresses associated with performing bond between the bond pads and external components (e.g., heating and pressures associated with wire bonding). Further, RF effects caused by bond pad metallization are reduced by this physical separation.
• the number of bond pads on a die can vary depending upon the number of inputs/outputs the die requires.
• Semiconductor device die can include thousands of bond pads for each die, depending upon the nature of the circuitry provided by the die.
• FIG. 3 is a simplified block diagram illustrating an example of a bond pad including identifying features, in accord with embodiments of the present invention.
• Bond pad 300 has a main bond pad body 310 and a set of identification features 320 , 322 , and 324 .
• the identification features can be used alone or in conjunction with identification features associated with other bond pads of a semiconductor device die to uniquely identify the semiconductor device die associated with the bond pads.
• Bond pad 300 is formed using photolithographic techniques known in the art.
• identification features 320 , 322 , and 324 can have a width 330 down to as low as on the order of 5 ⁇ m and the spaces between the identification features (e.g., space 340 ) can also be on the order of 5 ⁇ m, depending on the processes used to form bond pad 300 . Since a typical bond pad body 310 can be on the order of 100 ⁇ m in width or height, larger identification features can be provided having sufficient room for the identification features and spaces between them in order to optically distinguish between each identification feature.
• the unique identification features and bond pads can be provided by using a single plate that patterns all the bond pads for the wafer at one time (e.g., a 1 ⁇ plate). Thus, on this plate each die will be provided with a unique code pattern.
• FIG. 4 is a simplified block diagram illustrating one example of a method by which a unique coding can be provided to a semiconductor device die, using embodiments of the present invention.
• Bond pads 410 , 420 , and 430 can provide identification features that express a code for an X-coordinate of the semiconductor device die on, for example, grid 120 .
• Bond pads 440 , 450 , and 460 can provide notification features that express a code for a Y-coordinate of the semiconductor device die on, for example, grid 120 .
• the identification features correspond to a seven-place binary code where each digit of the binary code is represented by the presence or absence of an identification feature in a predetermined space along the edge of a set of three bond pads.
• the small squares represent the absence of an identification feature.
• the X-coordinate represented by the identification features on bond pads 410 , 420 , and 430 is 77 (1+4+8+64).
• the Y-coordinate represented by the identification features on bond pads 440 , 450 , and 460 is 79 (1+2+4+8+64).
• Identification of each die can be performed using optical inspection if the die is separate from a package, or by x-ray inspection if the die is encased in a package. In some applications, identifying small features that are in close proximity may be difficult (e.g., multiple tabs associated with a single bond pad).
• Embodiments of the present invention are not limited to including multiple features on a single bond pad (e.g., as in FIG. 3 ), but can associate a single identifying feature with a single bond pad, and then use more bond pads to provide the desired code. Alternatively, embodiments of the present invention can provide identifying features of various shapes, and therefore convey more complex coding mechanisms.
• FIG. 5 is a simplified block diagram illustrating a bond pad having identification features of different shapes, in accord with embodiments of the present invention.
• Bond pad 500 has a main bond pad body 510 and a set of identification features 520 and 530 .
• Identification feature 520 is in the form of a rectangle
• bond pad 530 is an alternative shape, here illustrated as a triangle.
• ternary coding systems and beyond can be used since each location along the edge of the bond pad can have shapes representative of a zero, one, two, and so forth. While a variety of shapes can be used, practical limitations related to optical or other detection means used for inspecting the identification features may limit usable shapes.
• FIG. 6 is a simplified block diagram illustrating a bond pad having identification features provided by indentations in the bond pad, in accord with an alternative embodiment of the present invention.
• Bond pad 600 has a main bond pad area 610 and an identification features area 615 .
• an identification space 620 is formed in identification features area 615 .
• a number of identification spaces can be formed in the identification features areas of one or more bond pads to encode the desired information on the device die. In some optical identification applications, identification spaces may be more easily detected than tabs.
• Embodiments of the present invention provide a mechanism by which identification information can be encoded on each device die of a semiconductor wafer. This information can be used, as discussed above, to uniquely identify each device die on the wafer by location or some other identification/mapping code. Since the identifying features are associated with bond pads formed on the device die, the identifying features can be provided with smaller minimum sizes than standalone features. Further, since the identifying features are associated with metalized features in a region of the die chosen to reduce RF interference and other interaction with the circuitry of the device die, such interactions will be minimized due to the identifying features themselves.
• the method includes forming a bond pad region of the semiconductor device die, forming a first bond pad in the bond pad region, and forming one or more bond pad features coupled to the first bond pad.
• An aspect of the one or more bond pad features provides information associated with the semiconductor device die.
• One aspect of the above embodiment further includes forming one or more bond pads in the bond pad region, selecting one or more of the one or more bond pads to comprise one or more of the bond pad features, and selecting the aspects of the one or more bond pad features associated with the one or more selected bond pads. Selecting the one or more selected bond pads is performed to provide the information associated with the semiconductor device die. Selecting the aspects of the one or more bond pad features is performed to provide the information associated with the semiconductor device die. Further to this aspect, the information associated with the semiconductor device die uniquely identifies the semiconductor device die on the wafer. Further to the above aspect, the information associated with the semiconductor device die uniquely identifies a location of the semiconductor device die on the wafer.
• the information associated with the semiconductor device die includes an X-coordinate associated with a grid square, corresponding to the semiconductor device die, on a wafer map associated with the wafer, and a Y-coordinate associated with the grid square.
• the method further includes encoding the X-coordinate using a binary system and encoding the Y-coordinate using the binary system.
• a first set of one or more bond pad features corresponds to each digit of the binary X-coordinate.
• a second set of one or more bond pad features corresponds to each digit of the binary Y-coordinate.
• Another aspect of the above embodiment provides for forming the one or more bond pad features associated with each of the one or more selected bond pads concurrently with forming the one or more selected bond pads.
• forming the one or more bond pad features associated with each of the one or more selected bond pads concurrently with forming the one or more selected bond pads includes: forming a conductive layer on a major surface of the wafer, forming a photoresist layer over the conductive layer, exposing the photoresist layer using a single photolithographic plate for the entire wafer, and etching the conductive layer in response to the exposed photoresist layer.
• Each semiconductor device die region of the single photolithographic plate provides the selected aspects of the one or more bond pad features associated with each of the one or more selected bond pads for the corresponding semiconductor device die.
• the aspects of the one or more bond pad features include a number of the bond pad features associated with each of the one or more selected bond pads. In another aspect of the above embodiment, the aspects of the one or more bond pad features include a shape of each bond pad feature. In still another aspect of the above embodiment, the aspects of the one or more bond pad features include indentations formed in the one or more selected bond pads. Another aspect provides for forming the first bond pad and the one or more bond pad features using a metal comprising one of gold or aluminum.
• Another embodiment provides for a die located on a semiconductor wafer having a first bond pad located in a bond pad region, and one or more bond pad features coupled to the first bond pad where an aspect of the one or more bond pad features provides information associated with the die.
• the die further includes a first set of one or more bond pads in the bond pad region.
• the first set of bond pads includes the first bond pad.
• the first set of bond pads is configured to provide the information associated with the die.
• One or more of the first set of bond pads each includes one or more bond pad features.
• the information associated with the die uniquely identifies the die on the semiconductor wafer. Further to the above aspect, the information associated with the die uniquely identifies a location of the die on the wafer. Further to this aspect, the information associated with the die includes an X-coordinate associated with a grid square, corresponding to the die, on a wafer map associated with the semiconductor wafer, and a Y-coordinate associated with the grid square. Further to this aspect the die further includes a first set of the one or more bond pad features corresponding to each digit of a binary representation of the X-coordinate and a second set of the one or more bond pad features corresponding to each digit of a binary representation of the Y-coordinate.
• the aspect of the one or more bond pad features includes one or more of a number of the bond pad features associated with the first bond pad, a shape of each bond pad feature, and indentations formed in the first bond pad.
• Another embodiment provides a semiconductor wafer including a plurality of integrated circuit dies formed on the semiconductor wafer.
• Each integrated circuit die includes one or more bond pads located on the integrated circuit die and a first set of the one or more bond pads configured to provide unique information associated with the integrated circuit die by virtue of comprising one or more bond pad features associated with one or more bond pads of the first set of bond pads.
• Coupled is not intended to be limited to a direct coupling or a mechanical coupling.

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• 2012
  • 2012-08-30 US US13/599,388 patent/US8742599B2/en not_active Expired - Fee Related
• 2014
  • 2014-04-28 US US14/263,460 patent/US20140232017A1/en not_active Abandoned

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