US20150339992A1 - Display device with electronic equipment therewith - Google Patents

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Classifications

• • G—PHYSICS
  • G02—OPTICS
  • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
  • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
  • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
  • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
  • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
  • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
  • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
  • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
  • G09G3/3611—Control of matrices with row and column drivers
  • G09G3/3614—Control of polarity reversal in general
• • G—PHYSICS
  • G02—OPTICS
  • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
  • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
  • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
  • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
  • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
  • G02F1/1333—Constructional arrangements; Manufacturing methods
  • G02F1/1345—Conductors connecting electrodes to cell terminals
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
  • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
  • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
  • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
  • G09G3/3611—Control of matrices with row and column drivers
  • G09G3/3648—Control of matrices with row and column drivers using an active matrix
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
  • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
  • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
  • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
  • G09G3/3611—Control of matrices with row and column drivers
  • G09G3/3696—Generation of voltages supplied to electrode drivers
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G2300/00—Aspects of the constitution of display devices
  • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
  • G09G2300/0809—Several active elements per pixel in active matrix panels
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
  • G09G2330/02—Details of power systems and of start or stop of display operation
  • G09G2330/021—Power management, e.g. power saving
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
  • G09G2330/02—Details of power systems and of start or stop of display operation
  • G09G2330/021—Power management, e.g. power saving
  • G09G2330/023—Power management, e.g. power saving using energy recovery or conservation

Definitions

• This invention relates to a display device provided with a power supply circuit and electronic equipment provided with the display device.
• an active matrix type liquid crystal display device that is manufactured by a low temperature polysilicon TFT (Thin Film Transistor) technology
• a power supply circuit that generates a positive power supply electric potential and a negative power supply electric potential to control turning on/off of pixel TFTs has been formed on a glass substrate of a liquid crystal panel in order to reduce a cost of a drive signal IC (Integrated Circuit).
• a horizontal transfer clock that drives a horizontal drive circuit, a vertical transfer clock that drives a vertical drive circuit or a dedicated clock is supplied from a driver IC as a drive clock to drive the power supply circuit.
• This kind of active matrix type liquid crystal display device is disclosed in Japanese Patent Application Publication No. 2004-146082.
• the power supply circuit When the power supply circuit is formed on the glass substrate of the liquid crystal panel, the power supply circuit is placed in an unused space in a frame of the glass substrate.
• the drive clock to drive the power supply circuit and a power supply electric potential are supplied to the power supply circuit through wirings from a terminal portion that is also placed on the glass substrate.
• a wiring load resistive and capacitive loads associated with the wirings to provide the power supply and the drive clock
• problems such as reduction in efficiency of the power supply circuit, increase in power consumption and display failures.
• This invention offers a display device including a pixel portion in which a plurality of pixel transistors are arrayed in a matrix form, a drive circuit to drive the pixel transistors, a positive power supply generation circuit to generate a positive power supply electric potential to drive the drive circuit, a negative power supply generation circuit to generate a negative power supply electric potential to drive the drive circuit, a terminal portion to externally apply a drive clock and a power supply electric potential to drive the positive power supply generation circuit and the negative power supply generation circuit, and a wiring disposed between the terminal portion and both the positive power supply generation circuit and the negative power supply generation circuit in order to supply the drive clock and the power supply electric potential, wherein the positive power supply generation circuit and the negative power supply generation circuit are placed closer to the terminal portion than the pixel portion and the drive circuit and are placed at substantially the same distance from the terminal portion.
• a wiring load can be reduced to prevent reduction in efficiency of the power supply generation circuits as well as preventing reduction in efficiency of either the positive power supply generation circuit or the negative power supply generation circuit due to an unbalanced wiring load, since the positive power supply generation circuit and the negative power supply circuit are placed close to the terminal portion and are placed at substantially the same distance from the terminal portion.
• This invention also offers a display device including a pixel portion in which a plurality of pixel transistors are arrayed in a matrix form, a positive power supply generation circuit to generate a positive power supply electric potential to control switching of the pixel transistors, a negative power supply generation circuit to generate a negative power supply electric potential to control switching of the pixel transistors, a terminal portion to externally apply a drive clock and a power supply electric potential to drive the positive power supply generation circuit and the negative power supply generation circuit, and a wiring disposed between the terminal portion and both the positive power supply generation circuit and the negative power supply generation circuit in order to supply the drive clock and the power supply electric potential, wherein the positive power supply generation circuit and the negative power supply generation circuit are placed at substantially the same distance from the terminal portion.
• This invention also offers a display device including a pixel portion in which a plurality of pixel transistors are arrayed in a matrix form, a positive power supply generation circuit to generate a positive power supply electric potential to control switching of the pixel transistors, a negative power supply generation circuit to generate a negative power supply electric potential to control switching of the pixel transistors, a terminal portion to externally apply a drive clock and a power supply electric potential to drive the positive power supply generation circuit and the negative power supply generation circuit, and a wiring disposed between the terminal portion and both the positive power supply generation circuit and the negative power supply generation circuit in order to supply the drive clock and the power supply electric potential, wherein the negative power supply generation circuit is placed closer to the terminal portion than the positive power supply generation circuit.
• This invention also offers electronic equipment using the display device described above.
• This invention offers excellent electronic equipment that does not cause an increase in power consumption or a display failure because the efficiency of the power supply circuit is not reduced.
• FIG. 1 shows a layout of a liquid crystal display device according to a first embodiment of this invention.
• FIG. 2 is a circuit diagram of a horizontal drive circuit.
• FIG. 3 is a waveform chart showing an operation of the liquid crystal display device according to the first embodiment of this invention.
• FIG. 4 is a circuit diagram of a positive power supply generation circuit.
• FIG. 5 is a waveform chart showing an operation of the positive power supply generation circuit.
• FIG. 6 is a circuit diagram of a negative power supply generation circuit.
• FIG. 7 is a waveform chart showing an operation of the negative power supply generation circuit.
• FIG. 8 shows a layout of a liquid crystal display device according to a second embodiment of this invention.
• FIG. 9 shows a layout of a liquid crystal display device according to a third embodiment of this invention.
• FIG. 1 shows a layout (plan view) of a liquid crystal display device according to a first embodiment of this invention.
• a pixel portion 105 , a horizontal drive circuit 110 and a vertical drive circuit 120 are formed on a TFT glass substrate 100 .
• a plurality of pixels (Only four pixels are shown in FIG. 1 .) is arrayed in a matrix form in the pixel portion 105 .
• the horizontal drive circuit 110 is provided with a shift register SR that is made of a plurality of flip-flops FF and transfers a horizontal start signal STH based on a horizontal clock CKH and its reverse clock *CKH and a plurality of horizontal switches HSW, each of which is turned on based on an output of each of the flip-flops FF, as shown in FIG. 2 .
• Each of the horizontal switches HSW is made of a TFT having a gate to which the output of corresponding each of the flip-flops FF is applied, a source to which a video signal Vsig is applied and a drain connected with a data line DL. That is, each of the horizontal switches HSW is turned on in a sequential order based on the output of corresponding each of the flip-flops FF to sample and output the video signal Vsig to the data line DL.
• the vertical drive circuit 120 is a shift register that sequentially transfers a vertical start signal STV based on a vertical transfer clock CKV and provides each of gate lines GL with a gate signal corresponding to its output.
• a pixel transistor GT in each of the pixels is made of a TFT having a drain connected with 25 corresponding each of the data lines DL and a gate connected with corresponding each of the gate lines GL, and is controlled to turn on/off by the gate signal.
• a source of the pixel transistor GT is connected with a pixel electrode 121 .
• the pixel electrode 121 is usually provided with a retention capacitor (not shown) to retain its electric potential.
• a counter glass substrate 200 is disposed to face the TFT glass substrate 100 .
• a common electrode 122 is formed on the counter glass substrate 200 so as to face the pixel electrodes 121 .
• a liquid crystal LC is sealed between the TFT glass substrate 100 and the counter glass substrate 200 .
• a driver IC disposed on the TFT glass substrate 100 of the liquid crystal panel or outside the liquid crystal panel provides the common electrode 122 with a common electrode signal VCOM that alternates between an H level and an L level once every horizontal period for line inversion drive.
• the pixel transistor GT is of N-channel type
• the pixel transistor GT is turned on when the gate signal turns to an H level.
• the video signal Vsig is applied from the data line DL to the pixel electrode 121 through the pixel transistor GT, and the display is performed by controlling alignment of the liquid crystal LC.
• the electric potential of the pixel electrode 121 is changed by capacitive coupling through the liquid crystal LC.
• the H level of the gate signal to turn on the pixel transistor GT is set at a positive power supply electric potential that is generated by boosting
• an L level of the gate signal to turn off the pixel transistor GT is set at a negative power supply electric potential.
• a positive power supply generation circuit 131 that generates the positive power supply electric potential and a negative power supply generation circuit 132 that generates the negative power supply electric potential are formed on the TFT glass substrate 100 .
• the positive power supply generation circuit 131 and the negative power supply generation circuit 132 are disposed close to a terminal portion 140 , to which a drive clock and the input power supply electric potential are applied externally, so that wiring loads (resistive and capacitive loads associated with wirings to provide the power supply and the drive clock) of the positive power supply generation circuit 131 and the negative power supply generation circuit 132 are reduced to suppress reduction in the circuit efficiency.
• the terminal portion 140 is formed in an edge portion of the TFT glass substrate 100 . That is, the positive power supply generation circuit 131 and the negative power supply generation circuit 132 are placed closer to the terminal portion 140 than primary circuits of the liquid crystal display device, which are the pixel portion 105 , the horizontal drive circuit 110 and the vertical drive circuit 120 . With this, a layout that minimizes the wiring loads is obtained.
• the positive power supply generation circuit 131 and the negative power supply generation circuit 132 are placed next to each other at substantially the same distance from the terminal portion 140 and parallel to an edge of the TFT glass substrate 100 , along which the terminal portion 140 is formed, so that the wiring loads are made equal to each other and the circuit efficiencies of the positive power supply generation circuit 131 and the negative power supply generation circuit 132 are balanced.
• VPP makes the H level of the gate signal and VBB makes the L level of the gate signal.
• the H level of the common electrode signal VCOM is 3.9 V and the L level of the common electrode signal VCOM is ⁇ 0.1 V.
• a polarity of the video signal Vsig against the common electrode signal VCOM is inverted once every horizontal period.
• An H level of the video signal Vsig is set at 4.1 V and an L level of the video signal Vsig is set at 0.1 V. Because of a voltage drop due to a resistance of the horizontal switch HSW, the H level is reduced to 3.9 V and the L level is reduced to ⁇ 0.1 V after passing through the horizontal switch HSW.
• the pixel transistors GT are of N-channel type in the explanation below.
• the gate signal corresponding to the row is set at the H level. Then, the pixel transistors GT in the row are turned on and the video signal Vsig is written into each of the pixels through the pixel transistor GT and retained in the pixel electrode 121 .
• the gate signal of the row turns to the L level and the pixel transistors GT are turned off.
• the common electrode signal VCOM changes from the L level to the H level
• an electric potential of the pixel electrode 121 is changed by +4.0 V toward positive direction by the capacitive coupling
• the electric potential of the pixel electrode 121 is changed by ⁇ 4.0 V by the capacitive coupling.
• VDD When VDD is reduced by increased loads of the wirings to provide the input power supply electric potential VDD and the drive clock, the output electric potential VPP from the positive power supply generation circuit 131 is reduced and the H level of the gate signal is also reduced accordingly. As a result, a voltage margin of the video signal Vsig in the programming operation is reduced. In the example shown in FIG. 3 , there is a margin comparatively large enough to turn on the pixel transistor GT, since VPP is 8.5 V and the highest electric potential of the video signal Vsig is 4.1 V (3.9 V after passing through the horizontal switch HSW). When the wiring loads are increased, however, VPP is further reduced to reduce the margin and the programming operation may end up in a malfunction.
• FIG. 4 is a circuit diagram showing the positive power supply generation circuit 131 .
• the horizontal transfer clock CKH, the vertical transfer clock CKV, the common electrode signal VCOM or the like can be used as the input clock CLK.
• the clock CPCLK 1 is applied to a first terminal of a flying capacitor C 1 while the reverse clock XPCLK 1 is applied to a first terminal of a flying capacitor C 2 .
• the buffer circuit such as the clock generation circuit 10 in the positive power supply generation circuit 131 is not necessarily required when the input clock CLK (drive clock) is directly inputted from an external IC through the terminal portion 140 .
• An N-channel type charge transfer transistor MN 1 and a P-channel type charge transfer transistor MP 1 are connected in series and a connecting node between them is connected with a second terminal of the flying capacitor C 1 .
• a gate of the N-channel type charge transfer transistor MN 1 and a gate of the P-channel type charge transfer transistor MP 1 are connected with a second terminal of the flying capacitor C 2 .
• An N-channel type charge transfer transistor MN 2 and a P-channel type charge transfer transistor MP 2 are connected in series and a connecting node between them is connected with the second terminal of the flying capacitor C 2 .
• a gate of the N-channel type charge transfer transistor MN 2 and a gate of the P-channel type charge transfer transistor MP 2 are connected with the second terminal of the flying capacitor C 1 .
• the flying capacitor C 1 is connected between external connection terminals P 1 and P 2 and placed outside the TFT glass substrate 100 . (hereafter referred to as an external capacitor)
• the flying capacitor C 2 is an external capacitor connected between external connection terminals P 3 and P 4 .
• the positive input power supply electric potential VDD is applied as an input electric potential to a common source of the N-channel type charge transfer transistors MN 1 and MN 2 . Assuming that the circuit efficiency is 100%, a positive electric potential of 2VDD is outputted as the output electric potential VPP as well as an output current Ivpp from a common drain (output terminal) of the P-channel type charge transfer transistors MP 1 and MP 2 by charge transfer operation in a steady state.
• a smoothing capacitor C 3 is another external capacitor, and is connected with an external connection terminal P 5 that is an output terminal of the positive power supply generation circuit 131 .
• the external connection terminals P 1 -P 5 are placed in the terminal portion 140 .
• an external connection terminal P 6 to apply the input power supply electric potential VDD from outside and an external connection terminal P 7 to apply the input clock CLK from outside are placed in the terminal portion 140 .
• a power supply wiring 133 to supply the input power supply electric potential VDD connects between the external connection terminal P 6 and the common source of the N-channel type charge transfer transistors MN 1 and MN 2 .
• a drive clock wiring 134 to supply the input clock CLK connects between the external connection terminal P 7 and the clock generation circuit 10 in the positive power supply generation circuit 131 . According to the layout described above, wiring lengths of the power supply wiring 133 and the drive clock wiring 134 are minimized to minimize the wiring loads.
• the clock CPCLK 1 turns to the L level (VSS)
• MN 1 and MP 2 are turned on
• MN 2 and MP 1 are turned off
• the electric potential V 2 is boosted by capacitive coupling through the flying capacitor C 2 to 2VDD that is outputted through MP 2 .
• the electric potential V 1 is charge to VDD. That is, the electric potential 2VDD is outputted alternately from left and right serially connected transistor circuits in the positive power supply generation circuit 131 . Note that this is for the case where the circuit efficiency is 100%.
• FIG. 6 is a circuit diagram showing the negative power supply generation circuit 132 .
• a clock generation circuit 20 in the negative power supply generation circuit 132 generates based on the input clock CLK a clock CPCLK 2 having amplitude of VDD and a reverse clock XCPCLK 2 that is an inversion of the clock CPCLK 2 .
• the clock generation circuit 20 does not need to be provided separately, and the clock generation circuit 10 may be shared by both the positive power supply generation circuit 131 and the negative power supply generation circuit 131 .
• An N-channel type charge transfer transistor MN 11 and a P-channel type charge transfer transistor MP 11 are connected in series and a connecting node between them is connected with a second terminal of a flying capacitor C 11 .
• a gate of the N-channel type charge transfer transistor MN 11 and a gate of the P-channel type charge transfer transistor MP 11 are connected with a second terminal of a flying capacitor C 12 .
• An N-channel type charge transfer transistor MN 12 and a P-channel type charge transfer transistor MP 12 are connected in series and a connecting node between them is connected with the second terminal of the flying capacitor C 12 .
• a gate of the N-channel type charge transfer transistor MN 12 and a gate of the P-channel type charge transfer transistor MP 12 are connected with the second terminal of the flying capacitor C 11 .
• the flying capacitor C 11 is an external capacitor connected between external connection terminals P 11 and P 12 .
• the flying capacitor C 12 is an external capacitor connected between external connection terminals P 13 and P 14 .
• the ground electric potential VSS is applied to a common source of the P-channel type charge transfer transistors MP 11 and MP 12 as an input electric potential.
• a negative electric potential of ⁇ VDD is outputted as the output electric potential VBB as well as an output current Ivbb from a common drain (output terminal) of the N-channel type charge transfer transistors MN 11 and MN 12 in a steady state.
• a smoothing capacitor C 13 is another external capacitor, and is connected with an external connection terminal P 15 that is the output terminal of the negative power supply generation circuit 132 .
• the external connection terminals P 11 -P 15 are placed in the terminal portion 140 .
• an external connection terminal P 16 to apply the input power supply electric potential VSS from outside and an external connection terminal P 17 to apply the input clock CLK from outside are placed in the terminal portion 140 .
• the external connection terminal P 7 for the positive power supply generation circuit 131 may be shared by the negative power supply generation circuit 132 to replace the external connection terminal P 17 .
• a power supply wiring 135 to supply the input power supply electric potential VSS connects between the external connection terminal P 16 and the common source of the P-channel type charge transfer transistors MP 11 and MP 12 .
• a drive clock wiring 136 to supply the input clock CLK connects between the external connection terminal P 17 and the clock generation circuit 20 in the negative power supply generation circuit 132 . According to the layout described above, wiring lengths of the power supply wiring 135 and the drive clock wiring 136 are minimized to minimize the wiring loads.
• the clock CPCLK 2 is at the H level 10 (VDD)
• the reverse clock XCPCLK 2 is at the L level (VSS)
• MN 11 and MP 12 are turned off
• MN 12 and MP 11 are turned on
• an electric potential V 3 at the connecting node between MN 11 and MP 11 is charged to VSS
• an electric potential V 4 at the connecting node between MN 12 and MP 12 is lowered by the capacitive coupling through the flying capacitor C 12 to ⁇ VDD that is outputted through MN 12 .
• FIG. 8 shows a layout (plan view) of a liquid crystal display device according to a second embodiment of this invention.
• the layout according to the second embodiment is effective in the case where it is difficult to place the positive power supply generation circuit 131 and the negative power supply generation circuit 132 closer to the terminal portion 140 than other circuits as in the liquid crystal display device according to the first embodiment. That is, when the shift register SR in the horizontal drive circuit 110 is mounted as an LSI chip on the TFT glass substrate 100 , i.e. as a COG (Chip on Glass), there is a case in which the positive power supply generation circuit 131 and the negative power supply generation circuit 32 can not be placed as close to the terminal portion 140 as in the liquid crystal display device according to the first embodiment because the frame area is increased accordingly.
• COG Chip on Glass
• the positive power supply generation circuit 131 and the negative power supply generation circuit 132 are arrayed next to each other in a direction (Y direction) of an edge of the TFT glass substrate 100 , on which the terminal portion 140 is placed, and placed along an edge that is perpendicular to the edge of the TFT glass substrate 100 , on which the terminal portion 140 is placed, as shown in FIG. 8 .
• the positive power supply generation circuit 131 is placed on the edge portion of the TFT glass substrate 100 and the negative power supply generation circuit 132 is placed between the positive power supply generation circuit 131 and the pixel portion 105 in FIG.
• the negative power supply generation circuit 132 may be placed on the edge portion of the TFT glass substrate 100 and the positive power supply generation circuit 131 may be placed between the negative power supply generation circuit 132 and the pixel portion 105 .
• the positive power supply generation circuit 131 and the negative power supply generation circuit 132 are placed at substantially the same distance from the terminal portion 140 . As a result, the reduction in the circuit efficiency of either the positive power supply generation circuit 131 or the negative power supply generation circuit 132 due to the unbalanced wiring loads can be prevented.
• FIG. 9 shows a layout (plan view) of a liquid crystal display device according to a third embodiment of this invention.
• the positive power supply generation circuit 131 and the negative power supply generation circuit 132 are placed side by side along the edge perpendicular to the edge of the TFT glass substrate 100 , on which the terminal portion 140 is placed, i.e. along X direction in FIG. 9 , and the negative power supply generation circuit 132 is placed closer to the terminal portion 140 than the positive power supply generation circuit 131 .
• the layout described above is effective in the case where a left portion of the frame area in FIG. 9 is too narrow to apply the layout as described in the second embodiment.
• the pixel leakage would be caused when the output electric potential VBB generated by the negative power supply generation circuit 132 rises. And there is only a small margin against the rise in VBB.
• the margin against the fall in VPP is relatively large.
• the negative power supply generation circuit 132 that has less margin is placed closer to the terminal portion 140 than the positive power supply generation circuit 131 to prevent the problem due to the reduction in the circuit efficiency.
• the liquid crystal display device is used as a display device mounted on electronic equipment.
• the electronic equipment means a monitor, a TV, a note PC, a PDA (Personal Digital Assistant), a digital still camera, a camcorder, a mobile telephone, a mobile photo viewer, a mobile video player, a mobile DVD player, a mobile audio player or the like.
• liquid crystal display devices are taken up as examples and explained in the embodiments described above. However, this invention is not limited to the above and is applicable to display devices other than the liquid crystal display devices such as an LED (Light Emitting Diode), an EL (Electro-Luminescence), a VFD (Vacuum Fluorescent Display) and a PDP (Plasma Display Panel), for example, since this invention is related to placement of the power supply circuit.
• LED Light Emitting Diode
• EL Electro-Luminescence
• VFD Vauum Fluorescent Display
• PDP Pasma Display Panel
• the reduction in the efficiency of the power supply circuit is prevented so that the increase in the power consumption, the malfunction of the display device and the like can be 10 prevented.

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• Physics & Mathematics (AREA)
• Engineering & Computer Science (AREA)
• General Physics & Mathematics (AREA)
• Chemical & Material Sciences (AREA)
• Crystallography & Structural Chemistry (AREA)
• Theoretical Computer Science (AREA)
• Computer Hardware Design (AREA)
• Nonlinear Science (AREA)
• Optics & Photonics (AREA)
• Mathematical Physics (AREA)
• Control Of Indicators Other Than Cathode Ray Tubes (AREA)
• Liquid Crystal Display Device Control (AREA)
• Liquid Crystal (AREA)
• Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

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Citations (27)

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• 2007
  • 2007-02-22 JP JP2007042568A patent/JP4281020B2/en active Active
• 2008
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• 2014
  • 2014-11-03 US US14/530,916 patent/US9076407B2/en not_active Expired - Fee Related
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