US20190115423A1 - Insulated gate power devices with reduced carrier injection in termination area - Google Patents

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• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
  • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
  • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
  • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
  • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
  • H10D62/107—Buried supplementary regions, e.g. buried guard rings 
• • H01L29/0623—
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/76—Making of isolation regions between components
  • H01L21/761—PN junctions
• • H01L29/0649—
• • H01L29/0834—
• • H01L29/36—
• • H01L29/66348—
• • H01L29/7397—
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
  • H10D12/01—Manufacture or treatment
  • H10D12/031—Manufacture or treatment of IGBTs
  • H10D12/032—Manufacture or treatment of IGBTs of vertical IGBTs
  • H10D12/038—Manufacture or treatment of IGBTs of vertical IGBTs having a recessed gate, e.g. trench-gate IGBTs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
  • H10D12/411—Insulated-gate bipolar transistors [IGBT]
  • H10D12/441—Vertical IGBTs
  • H10D12/461—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
  • H10D12/481—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D18/00—Thyristors
  • H10D18/60—Gate-turn-off devices 
  • H10D18/65—Gate-turn-off devices  with turn-off by field effect 
  • H10D18/655—Gate-turn-off devices  with turn-off by field effect  produced by insulated gate structures
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
  • H10D62/113—Isolations within a component, i.e. internal isolations
  • H10D62/115—Dielectric isolations, e.g. air gaps
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
  • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
  • H10D62/141—Anode or cathode regions of thyristors; Collector or emitter regions of gated bipolar-mode devices, e.g. of IGBTs
  • H10D62/142—Anode regions of thyristors or collector regions of gated bipolar-mode devices
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/60—Impurity distributions or concentrations
• • H01L29/1095—
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
  • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
  • H10D62/393—Body regions of DMOS transistors or IGBTs 

Definitions

• This invention relates to high power, insulated-gate-controlled devices used as switches and, more particularly, to a technique to reduce the current flow in termination regions surrounding a cellular array (active region) to prevent damage to the device when switching the device off, as well as to reduce turn-off time.
• the present invention is directed to improvements in the termination region of vertical, insulated-gate-controlled devices, such as Insulated Gate Bipolar Transistors (IGBTs), Insulated Gate Turn-off Devices (IGTOs), and other related devices that switch between an on state and an off state to control power to a load, such as a motor.
• IGBTs Insulated Gate Bipolar Transistors
• IGTOs Insulated Gate Turn-off Devices
• Such devices may conduct many amps and have a breakdown voltage in excess of 500 volts.
• An example of a prior art IGTO is shown in FIG. 1 to illustrate the problem with high current densities being created in the termination region surrounding the cellular array. The details of the device's operation are not important but are presented below for completeness.
• FIG. 1 is a cross-section of a small portion of an IGTO device 10 (similar in some respects to a thyristor) reproduced from the assignee's U.S. Pat. No. 8,878,237, incorporated herein by reference.
• the portion is near an edge of the device and shows a plurality of cells having vertical gates 12 (e.g., doped polysilicon) formed in insulated trenches.
• vertical gates 12 e.g., doped polysilicon
• a 2-dimensional array of the cells may be formed in a common p-well 14 , and the cells are connected in parallel.
• the area containing the cells is shown as the active region 15 .
• the edge of the device suffers from field crowding, and the edge cell is modified to increase ruggedness of the device.
• the edge cell has an opening 16 in the n+ source region 18 where the cathode electrode 20 shorts the n+ source region 18 to the p-well 14 . Such shorting increases the tolerance to transients to prevent unwanted turn on and prevents the formation of hot spots.
• the configuration of the edge cell may also be used in other cells of the device for a more uniform current flow across the device.
• the vertical gates 12 are insulated from the p-well 14 by an oxide layer 22 .
• a p+ contact (not shown) may be used at the opening 16 of the edge cell for improved electric contact to the p-well 14 .
• the narrow gates 12 are connected together outside the plane of the drawing and are coupled to a gate voltage via the gate electrode 25 contacting the polysilicon portion 28 .
• a patterned dielectric layer 26 insulates the metal from the various regions.
• the field limiting rings 29 at the edge of the cell in the termination region 27 reduce field crowding for increasing the breakdown voltage.
• the termination region 27 is designed to break down at a voltage higher than the breakdown voltage of the active region 15 , since the cathode electrode 20 is over the active region 15 and can efficiently conduct the breakdown current.
• the termination region 27 surrounds the active region 15 , which may have a generally rectangular shape.
• the active region 15 may take up the center area of a die or may be formed in strips separated by termination regions 27 .
• FIG. 1 An NPNP semiconductor layered structure is formed in FIG. 1 .
• a bipolar PNP transistor formed by a p+ substrate 30 , an n ⁇ epitaxial (epi) layer 32 , and the p ⁇ well 14 .
• a bipolar NPN transistor formed by the n-epi layer 32 , the p-well 14 , and the n+ source region 18 .
• An n-type buffer layer 35 which may be epitaxially grown or formed by implantation into the substrate 30 , has a dopant concentration higher than that of the n ⁇ epi layer 32 . The buffer layer 35 helps to set the breakdown voltage and reduces hole injection into the n-epi layer 32 .
• a metal, bottom anode electrode 36 contacts the substrate 30 , and a metal, cathode electrode 20 contacts the n+ source region 18 .
• the p-well 14 surrounds the gate structure, and the n ⁇ epi layer 32 extends to the surface around the p-well 14 .
• the gate When the gate is forward biased, electrons from the n+ source region 18 become the majority carriers along the gate sidewalls in an inversion layer, referred to as a “voltage induced emitter,” causing the effective width of the NPN base (the portion of the p-well 14 between the n-layers) to be reduced. As a result, the beta of the NPN transistor increases to cause the product of the betas to exceed one. This condition results in device turn-on, with holes being injected into the lightly doped n ⁇ epi layer 32 and electrons being injected into the p-well 14 . Accordingly, the gate bias initiates the turn-on, and the full turn-on (due to regenerative action) occurs when there is current flow through both the NPN transistor and the PNP transistor.
• the IGTO device turns off.
• the bottom p-type layer is formed by masking the bottom surface of the n-type substrate during implantation so that the p-type layer is heavily doped below the active region and only lightly doped below the termination region. This light doping below the termination region reduces the injected carriers (holes) in the termination region during the on-state, so that when the IGBT is turned off, there is much less heating effect from the injected carriers in the termination region.
• Various masking and doping techniques are described that reduce carrier injection into a termination region surrounding an active region (cell array) without reducing the breakdown voltage and efficiency of the vertical insulated-gate device, such as an IGBT or an IGTO device.
• the starting substrate is a p+ substrate.
• the top surface of the substrate will ultimately have various n-type layers epitaxially grown over it to fabricate the insulated-gate device.
• the p+ substrate bottom surface, after the substrate is thinned, may be the anode (or collector) of an IGBT or IGTO device.
• the top surface of the p+ substrate is masked prior to growing the n-type layers to expose the intended termination region surrounding the intended active region (cell array).
• N-type dopants are then implanted into the termination region to create either a very low concentration p-type layer or an n-layer below the intended termination region.
• the dopants implanted into the substrate are driven in by subsequent thermal processes.
• the area below the active region remains p+.
• the n-type epitaxial layers are then grown over the entire substrate, and the cell array is formed in the epitaxial layers. This structure achieves a high hole injection efficiency below the active region and a low hole injection efficiency below the termination region. Therefore, the problem with a high concentration of carriers in the termination region, when the device is switched off, is avoided.
• the entire top surface of the p+ substrate is doped with n-type dopants (e.g., phosphorus) to form an n-type layer or a low concentration p-type layer, and the area under the active region is doped with p-type dopants (to form a p+ or p++ type layer) to achieve a high hole injection efficiency below the active region and a low hole injection efficiency below the termination region.
• n-type dopants e.g., phosphorus
• both arsenic (a slow diffusing n-type dopant) and phosphorus (a fast diffusing n-type dopant) are implanted in the top surface of the p+ substrate below the intended termination region to form an n-type layer (or a low concentration p-type layer) below the termination region, with an n+ region at the center of the n-type layer (or low concentration p-type layer).
• the p+ substrate below the active region is not affected.
• the top surface of the p+ substrate is masked and doped with oxygen or nitrogen below the intended termination region to form an insulating layer of silicon dioxide or silicon nitride below the termination region.
• the substrate is not a p+ type but only a p-type (which will be a low efficiency hole injector).
• the top surface of the substrate corresponding to the active region is doped with p-dopants to form a p+ layer (or a p++ layer) for high efficiency hole injection below the active region.
• the area corresponding to the termination region is not additionally doped so remains a low efficiency hole injector.
• the bottom surface of the substrate is doped with p-type dopants, after the substrate is thinned, to form a p+ (or p++) bottom layer of the substrate.
• the p-type substrate is masked and n-type dopants are injected into the termination region to effectively cause the n-type buffer layer to be more highly doped in the termination region than in the active region.
• the p-type substrate may also be masked and doped to increase the p-type concentration below the active region to increase the hole injection efficiency below the active region.
• the hole injection is further reduced below the termination region while the hole injection efficiency is increased below the active region.
• the reduced injection of holes in the termination region lowers the concentration of holes in transient conditions between the on and off states of the device, thereby decreasing local power dissipation.
• the associated decrease in local temperature allows the device to handle a larger current without a failure.
• the techniques may be used with many different types of cell arrays and termination region structures in the vertical insulated-gate device.
• FIG. 1 is a cross-sectional view of the assignee's prior art vertical insulated-gate switch, formed as a die, used to illustrate possible active devices and termination structures that can be used in conjunction with the present invention.
• FIG. 2 is a simplified cross-sectional view of a portion of a silicon wafer corresponding to a single die of an insulated-gate switch to help explain the various doping techniques performed on the substrate prior to the growing of the epitaxial layers.
• FIG. 3A illustrates the simplified die structure of FIG. 2 , in accordance with one embodiment of the invention, after doping the substrate and after the various layers and regions are subsequently formed.
• FIG. 3B is the relative doping profile taken vertically through the termination region.
• FIG. 3C is the relative doping profile taken vertically through the active region.
• FIG. 4A illustrates the simplified die structure of FIG. 2 , in accordance with another embodiment of the invention, after doping the substrate and after the various layers and regions are subsequently formed.
• FIG. 4B is the relative doping profile taken vertically through the termination region.
• FIG. 4C is the relative doping profile taken vertically through the active region.
• FIG. 5A illustrates the simplified die structure of FIG. 2 , in accordance with another embodiment of the invention, after doping the substrate and after the various layers and regions are subsequently formed.
• FIG. 5B is the relative doping profile taken vertically through the termination region.
• FIG. 5C is the relative doping profile taken vertically through the active region.
• FIG. 6A illustrates the simplified die structure of FIG. 2 , in accordance with another embodiment of the invention, after doping the substrate and after the various layers and regions are subsequently formed.
• FIG. 6B is the relative doping profile taken vertically through the termination region.
• FIG. 6C is the relative doping profile taken vertically through the active region.
• FIG. 7A illustrates the simplified die structure of FIG. 2 , in accordance with another embodiment of the invention, after doping the substrate and after the various layers and regions are subsequently formed.
• FIG. 7B is the relative doping profile taken vertically through the termination region.
• FIG. 7C is the relative doping profile taken vertically through the active region.
• FIG. 8A illustrates the simplified die structure of FIG. 2 , in accordance with another embodiment of the invention, after doping the substrate and after the various layers and regions are subsequently formed.
• FIG. 8B is the relative doping profile taken vertically through the termination region.
• FIG. 8C is the relative doping profile taken vertically through the active region.
• FIG. 9A illustrates the simplified die structure of FIG. 2 , in accordance with another embodiment of the invention, after doping the substrate and after the various layers and regions are subsequently formed.
• FIG. 9B is the relative doping profile taken vertically through the termination region.
• FIG. 9C is the relative doping profile taken vertically through the active region.
• FIG. 10A is the doping profile vertically through an active region in a die in another embodiment of the invention.
• FIG. 10B is the doping profile vertically through a termination region in the die of FIG. 10A .
• FIG. 11A is the doping profile vertically through the active region of a die, where the top and bottom surfaces of a relatively lightly doped intrinsic p-type substrate are doped with p-type dopants to form p+ layers, rather than using a starting p+ substrate.
• the top surface of the substrate is not additionally doped in the termination region.
• FIG. 11B is the doping profile vertically through the termination region of the die of FIG. 11A , where there is no additional p-type doping in the top surface of the substrate.
• FIG. 12A is the doping profile vertically through the active region of a die, where the bottom surface of a relatively lightly doped intrinsic p-type substrate is doped with p-type dopants to form a p+ layer, rather than using a starting p+ substrate.
• FIG. 12B is the doping profile vertically through the termination region of the die of FIG. 12A , where the top surface of the substrate is doped with n-type dopants in the termination region prior to growing the epitaxial layers.
• FIG. 13 is a simplified cross-sectional view of an insulated-gate switch die, without details of a cell array and termination structures, to better understand the doping profiles of FIGS. 14-17 .
• FIG. 14A is the doping profile vertically through the active region of the die of FIG. 13 prior to a thermal step.
• FIG. 14B is the doping profile vertically through the termination region of the die of FIG. 13 prior to a thermal step, where an n-type dopant implant into the top surface of the p+ type substrate is performed in the termination region to reduce hole injection efficiency in the termination region.
• FIGS. 15A and 15B are the dopant profiles in the active region and termination region, respectively, after the dopants in FIGS. 14A and 14B are subjected to a thermal activation/drive-in step.
• FIG. 16A is the doping profile vertically through the active region of the die of FIG. 13 prior to a thermal step.
• FIG. 16B is the doping profile vertically through the termination region of the die of FIG. 13 prior to a thermal step, where an n-type dopant implant into the top surface of the p+ type substrate is performed in the termination region to reduce hole injection efficiency in the termination region.
• the dosage of the n-type dopants is about double that in FIG. 14B .
• FIGS. 17A and 17B are the dopant profiles in the active region and termination region, respectively, after the dopants in FIGS. 16A and 16B are subjected to a thermal activation/drive-in step.
• the invention is directed to an improved termination region in a vertical insulated-gate device (used as a high power switch), such as an IGBT or IGTO device, and also directed to fabrication techniques for forming the termination region.
• a vertical insulated-gate device used as a high power switch
• IGBT or IGTO device such as an IGBT or IGTO device
• the bottom metal of the device is an anode
• the top metal is a cathode, such as shown in FIG. 1 .
• a gate metal is also formed on the top for controlling the conduction of the device.
• the termination region surrounds an active region, which typically contains an array of cells. Assuming the bottom layer of the device is a p+ type substrate, the substrate injects holes (carriers) into the lightly doped n-type epitaxial base layer. In the active region, having a high hole injection efficiency is desirable, since it corresponds to a low forward voltage. When the device is turned off, the injected holes are quickly “removed” via the p-well and cathode metal.
• the present invention causes a great reduction in the carrier injection into the lightly doped n-type base in the termination region to improve turn-off time and avoid excess heat.
• FIG. 2 is a cross-section of a small portion of a starting silicon wafer (using an intrinsic p+ substrate 44 ), where the portion corresponds to a single die area to be later singulated.
• Subsequent figures illustrate the various doping techniques for the termination region 40 to reduce the hole injection efficiency of the termination region 40 .
• the doping techniques described below are performed prior to the growth of the epitaxial layers, the n-type buffer layer 35 and n-type epi layer 32 are shown, with the cellular array portion defining the active region 42 and the various termination structures surrounding the active region 42 defining the termination region 40 .
• the completed die will be a vertical insulated-gate switching device, such as an IGBT or an IGTO device.
• the device formed using the substrate 44 of FIG. 2 may be the IGTO device shown in FIG. 1 , except for the modifications described herein.
• the center active region 42 may correspond to the cell array active region 15 in FIG. 1
• the termination region 40 may correspond to the termination region 27 in FIG. 1 .
• the termination region 40 surrounds the active region 42 and is designed to reduce electric fields around the perimeter to improve the breakdown voltage.
• the termination region 40 will typically include conventional field limiting rings 29 ( FIG. 1 ) for spreading the electric fields.
• the field limiting rings 29 may include field plates (not shown) to aid in spreading the electric field.
• the field limiting rings 29 are typically floating. Breakdown occurs first in the active region 42 to limit heat dissipation, since the cathode electrode 20 over the active region 42 efficiently conducts the breakdown current.
• FIG. 3A illustrates the wafer portion of FIG. 2 after masking and doping the substrate 44 from its top surface, followed by growing an n-type buffer layer 35 and a lightly doped n-epi layer 32 (forming a base layer for a vertical PNP transistor).
• the layers 32 and 35 may be the same layers shown in FIG. 1 .
• the p-well 14 and the various cells from FIG. 1 are ultimately formed in the n-epi layer 32 , as described in the Assignee's U.S. Pat. No. 8,878,237. Other types of cells may be formed in the n-epi layer 32 .
• the top surface of the substrate 44 is masked, such as with a patterned photoresist, and n-type dopants (e.g., phosphorus) are implanted to form a continuous n-type region 46 as a ring in the termination region 40 .
• n-type dopants e.g., phosphorus
• the p+ substrate 44 may have a p-type dopant concentration greater than 10E19 cm ⁇ 3 .
• the n-type dopant concentration in the region 46 may be any amount since all that is required is to reduce the p-type dopant concentration of the substrate 44 to below its starting concentration to reduce the hole injection efficiency into the n-epi layer 32 in the termination region 40 .
• the hole injection is greatly reduced.
• the hole injection is greatly reduced.
• there will be far fewer holes in the n-epi layer 32 in the termination region 40 enabling a more rapid turn-off and virtually no increased heat.
• FIG. 3B shows the relative dopant concentrations in the termination region 40 , starting from the top down (left side of FIG. 3B ), referred to as the “A” direction.
• the n-dopant implant may be at any depth, while still achieving the goals of the invention.
• FIG. 3C shows the relative dopant concentrations in the active region 42 , starting from the top down, referred to as the “B” direction.
• the various epitaxial layers are then grown over the substrate 44 along with forming the cell array. Simulations show a great improvement in the turn-off characteristics of the device.
• the dopants are activated and diffused during subsequent thermal steps.
• the n-type doping of substrate 44 in the termination region 40 does not reduce the number of p-type dopants, the effect of the added n-dopants reduces the “effective” p-type dopant concentration by cancelling the holes created by the p-type dopants.
• the energy level of the implant can be selected to implant the dopants at any depth below the surface and even within a range of depths.
• the dopants are driven-in and diffused, they may or may not reach the top surface.
• the effect of reducing hole injection efficiency is still obtained. This applies to all embodiments described herein.
• FIG. 4A illustrates another technique where, prior to the growth of the epitaxial layers, the p+ (or p++) substrate 44 is subjected to a blanket (no mask) implant of n-type dopants to form a continuous n-type layer 48 on the top surface of the substrate 44 . Then, the termination region 40 is masked and p-type dopants are introduced into the substrate 44 in the active region 42 to form a center p++ region 50 to cause the substrate 44 to be a continuous p-type in the active region 42 . To improve the hole injection efficiency, the p-type doping increases the p-type dopant concentration in the active region 42 to above that of the substrate 44 , as shown by the dopant profiles of FIGS. 4B (termination region along “A” direction) and 4 C (active region along “B” direction).
• FIG. 5A illustrates another technique similar to that of FIG. 3A , but where the dosage of n-type dopants is much less so as to only lower the effective p-type dopant concentration in the substrate 44 in the termination region 40 .
• the substrate 44 surface in the active region 42 remains p+ (or p++) and the substrate 44 surface in the termination region 40 comprises the p ⁇ region 52 , as shown in FIGS. 5B and 5C .
• FIG. 6A illustrates another technique similar to that of FIG. 4A , but where the dosage of n-type dopants during the blanket implant is much less so as to only lower the effective p-type dopant concentration in the substrate 44 in the termination region 40 to form a p ⁇ layer 54 .
• the substrate 44 is then masked, and the active region 42 is implanted with p-type dopants to raise the p-type dopant concentration to above that of the original substrate 44 in the p++ region 56 to improve hole injection efficiency.
• FIGS. 6B and 6C show the relative dopants concentrations in the “A” and “B” directions.
• FIG. 7A illustrates another technique similar to FIG. 3A but where the substrate 44 is masked and fast diffusing phosphorus (an n-type dopant) is implanted in the termination region 40 followed by implanting slow diffusing arsenic (an n-type dopant).
• This forms an inner n+ region 58 and an outer n region 60 .
• One benefit of this technique is that the dopant level in the termination region 40 is more controllable after the various thermal steps used in forming the device.
• the implants in all embodiments may be shallow or deep.
• FIGS. 7B and 7C show the relative dopants concentrations in the “A” and “B” directions.
• FIG. 8A illustrates another technique similar to FIG. 7A but where the phosphorus dosage is much less so as to only form p ⁇ regions 62 surrounding the n+ regions 58 to lower the hole injection efficiency in the termination region 40 . Therefore, there is less concern about the fast-diffusing phosphorus affecting the active region 42 .
• FIGS. 8B and 8C show the relative dopants concentrations in the “A” and “B” directions.
• FIG. 9A illustrates a technique where insulating regions 66 (forming a ring) are formed in the substrate 44 in the termination region 40 .
• the active region 42 of the substrate 44 is masked, and oxygen or nitrogen is implanted in the termination region 40 to form the silicon dioxide or silicon nitride insulating regions 66 to reduce the hole injection efficiency in the termination region 40 .
• the n-type implant in the substrate 44 in the termination region 40 may diffuse up into the n-type buffer layer 35 to increase its n-type dopant concentration.
• FIG. 10A illustrates the relative doping profile in the active region 42 , with the substrate 44 doping on the left side and the n-type buffer layer 35 doping on the right side, where the n-type doping of the substrate 44 does not affect the n-type dopant concentration in the n-type buffer layer 35 in the active region 42 .
• FIG. 10A illustrates the relative doping profile in the active region 42 , with the substrate 44 doping on the left side and the n-type buffer layer 35 doping on the right side, where the n-type doping of the substrate 44 does not affect the n-type dopant concentration in the n-type buffer layer 35 in the active region 42 .
• 10B illustrates the relative doping profile in the termination region 40 , with the substrate 44 doping on the left side and the n-type buffer layer 35 doping on the right side, where the n-type doping of the substrate 44 increases the n-type dopant concentration in the n-type buffer layer 35 near the interface to reduce hole injection in the termination region 40 .
• the starting intrinsic substrate is a p-type but not highly doped. It has a p-type dopant concentration of on the order of 10E18 cm ⁇ 3 , which is considered less than a p+ type (e.g., dopant concentration greater than 10E19/cm ⁇ 3 ).
• the top surface of the substrate Prior to the growth of the epitaxial layers, the top surface of the substrate is masked to expose the active region, and additional p-type dopants (e.g., boron) are implanted to make the surface p+, while the surrounding termination region is unaffected.
• additional p-type dopants e.g., boron
• the termination region Since the termination region has a low concentration of p-type dopants, it has poor hole injection efficiency, while the active region, being a p+ type, has a high hole injection efficiency for good device performance in the on-state.
• the p-type substrate is thinned, and the bottom surface is further doped with p-type dopants to form a bottom p+ type layer. This structure is ideal for ohmic contact with the bottom anode metal.
• FIG. 11A is a dopant profile of the active region in such an embodiment, where the dopant levels on the left side correspond to the bottom of the substrate.
• the bottom of the thinned substrate is a p+ type (>10E19 cm ⁇ 3 )
• the middle portion of the substrate is a p-type
• the top of the substrate is a p+ type for high hole injection efficiency.
• the n-type dopant concentration of the n-type buffer layer 35 ( FIG. 1 ) is shown on the right side of FIG. 11A .
• FIG. 11B is a dopant profile of the termination region in such an embodiment, where there is no extra doping of the top surface of the p-type substrate in the termination region, so there is low hole injection efficiency in the termination region.
• the hole injection efficiency in the termination region can also be reduced by increasing the n-type dopant concentration of the n-type buffer layer 35 ( FIG. 1 ) in the termination region.
• FIG. 12A is a dopant profile of the active region in such an embodiment, where the dopant levels on the left side correspond to the bottom of the substrate.
• the n-type dopant concentration in the buffer layer 35 ( FIG. 1 ) in the active region is conventional and optimized for breakdown voltage and on-resistance.
• the substrate is assumed to be a p-type where the top surface is not further doped and the bottom surface, after thinning, is doped p+ for good ohmic contact with the anode metal.
• the top surface may be further doped in the active region as shown in FIG. 11A .
• FIG. 12B is a dopant profile of the termination region in such an embodiment, where the dopant levels on the left side correspond to the bottom of the substrate.
• the n-type buffer layer 35 ( FIG. 1 ) is masked during growth to increase the n-type dopant concentration only in the termination region.
• n-type arsenic dopants may be shallow-implanted into the top surface of the p-type substrate in the termination region so the n-type dopants will up-diffuse into the n-type buffer layer 35 to increase the n-type dopant concentration in the termination region.
• FIG. 13 is a simplified cross-section of an insulated-gate switch used to better understand the doping profiles of FIGS. 14-17 .
• the relative doping concentrations are identified in FIGS. 14-17 , and the y-axis is logarithmic.
• the approximate range of concentrations along the y-axis is about 10E13 to 10E19 cm ⁇ 3 , and the range of distance along the x-axis is about 15 microns.
• Optimal concentrations and depths depend on the requirements of the device and can be determined by simulation. Termination structures and cells are not shown for simplicity.
• the starting substrate 44 is a p+ type.
• FIGS. 14A and 14B illustrate doping profiles for the active region 42 and termination region 40 , respectively, after the n-type buffer layer 35 and n-epi layer 32 are grown but before a high temperature anneal step.
• the dopant profile in the active region 42 may be that in the prior art device of FIG. 1 .
• the dopant profile in the termination region 40 ( FIG. 14B ) is novel and shows an increased n-type dopant concentration in the n-type buffer layer 35 in the termination region 42 as a result of a masked n-type implant step where n-type phosphorus is implanted in the p+ type substrate 44 at a dose of 5E14/cm 2 at 70 KeV.
• FIGS. 15A and 15B illustrate the same active region 42 and termination region 40 , respectively, after a high temperature anneal step at the end of the wafer fabrication process. Note how the dopant concentrations have been smoothed out due to diffusion.
• FIGS. 16A and 16B are similar to FIGS. 14A and 14B except that the dosage of phosphorus has been increased to 1E15/cm 2 (twice the dosage as in FIGS. 14-15 ).
• FIGS. 16A and 16B show the dopant profiles of the active region 40 and termination region 40 , respectively, after the epitaxial layer growth and before the high temperature anneal. Note the higher level of n-type dopant concentration in the n-type buffer layer 35 at the interface of the substrate 44 and buffer layer 35 .
• the substrate 44 top surface may be doped n-type in the termination region so as to effectively form the lower portion of the n-type buffer layer 35 .
• FIGS. 17A and 17B show the dopant profiles of the active region 40 and termination region 40 , respectively, after the high temperature anneal.
• Simulations may be used for determining the optimal implant depths and dosages.
• Opposite conductivity type devices are formed by making dopant types the opposite of those describe above.
• the bottom of the device may be the cathode.

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