US20210335660A1 - Semiconductor structure having void between bonded wafers and manufacturing method tehreof - Google Patents

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  • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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  • H01L24/02—Bonding areas ; Manufacturing methods related thereto
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  • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
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  • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
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Definitions

• the present disclosure relates to a semiconductor structure, and a method of manufacturing the semiconductor structure.
• the present disclosure relates to a semiconductor structure having a through via electrically connected to components in two semiconductive wafers or circuitries or components external to the wafers, and a method of manufacturing the semiconductor structure including forming a void between two semiconductive wafers and filling the void with conductive material connecting components within the wafers.
• Semiconductor devices are used in a variety of electronic applications, such as personal computers, cellular phones, digital cameras, and other electronic equipment.
• the fabrication of semiconductor devices involves sequentially depositing various material layers over a semiconductive wafer, and patterning the material layers using lithography and etching processes to form microelectronic components, including transistors, diodes, resistors and/or capacitors, on or in the semiconductive wafer.
• the semiconductor industry continues to improve the integration density of the microelectronic components by continual reduction of minimum feature size, which allows more components to be integrated into a given area. Smaller package structures with smaller footprints are developed to package the semiconductor devices. For example, in an attempt to further increase density of the semiconductor device, three-dimensional (3D) integrated circuits including stacks of two or more microelectronic components have been investigated.
• 3D three-dimensional
• the semiconductor structure includes a first wafer including a first dielectric layer and a first component disposed within the first dielectric layer; a second wafer disposed over the first wafer and including a second dielectric layer over the first dielectric layer, and a second component disposed within the second dielectric layer; and a conductive structure including a first member surrounded by the first dielectric layer and the second dielectric layer, and a second member protruding from the first member and surrounded by the second wafer.
• the first dielectric layer is in contact with the second dielectric layer.
• the first component, the second component and the conductive structure are electrically connected to each other.
• the first component and the second component at least partially contact the first member of the conductive structure.
• a thickness of the first wafer is substantially greater than a thickness of the second wafer.
• the first dielectric layer and the second dielectric layer include oxide.
• the semiconductor structure further includes an isolating layer surrounding at least a portion of the second member of the conductive structure and disposed between the second dielectric layer and the second member of the conductive structure.
• the isolating layer includes oxide.
• Another aspect of the present disclosure provides a method of manufacturing a semiconductor structure.
• the method includes steps of providing a first wafer including a first substrate, a first dielectric layer disposed over the first substrate and a first component for iced within the first dielectric layer; providing a second wafer including a second substrate, a second dielectric layer disposed over the second substrate, and a second component formed within the second dielectric layer; removing a first portion of the first dielectric layer to form a first recess; removing a second portion of the second dielectric layer to form a second recess; disposing the second wafer over the first wafer to bond the first dielectric layer to the second dielectric layer; removing a third portion of the second substrate and the second dielectric layer to form a third recess coupled to the second recess; and disposing a conductive material to fill the first recess, the second recess and the third recess to form a conductive structure.
• the removal of the first portion of the first dielectric layer includes exposing a portion of the first component through the first dielectric layer.
• the removal of the second portion of the second dielectric layer includes exposing a portion of the second component through the second dielectric layer.
• the first recess is aligned with the second recess.
• a void defined by the first recess and the second recess is formed after the disposing of the second wafer over the first wafer.
• the removal of the third portion of the second substrate and the second dielectric layer includes removing a first section of the third portion to form a first opening, disposing an isolating layer conformal to the first opening, removing a bottom portion of the isolating layer, and removing a second section of the third portion to form a second opening.
• the conductive material is disposed by electroplating.
• the third portion of the second substrate and the second dielectric layer is removed by dry etching or laser drilling.
• the disposing of the second wafer over the first wafer includes forming a first interface between the first dielectric layer and the second dielectric layer.
• a second interface between the conductive structure and the first dielectric layer or a third interface between the conductive structure and the second dielectric layer is formed after the disposing of the conductive material.
• the method further includes grinding the second substrate to reduce a thickness of the second wafer prior to the removal of the third portion of the second substrate and the second dielectric layer.
• the first recess and the second recess are filled with the conductive material after the first dielectric layer is bonded to the second dielectric layer.
• a semiconductor structure including a void between two wafers and a conductive structure within the void is formed. Since the conductive structure is formed after bonding of two wafers, alignment between two wafers would not adversely affect reliability of the conductive structure interconnecting two wafers. Therefore, overall performance of the semiconductor structure having the conductive structure formed after the bonding of two wafers can be improved.
• FIG. 1 is a cross-sectional view of a first semiconductor structure in accordance with some embodiments of the present disclosure.
• FIG. 2 is a cross-sectional view of a second semiconductor structure in accordance with some embodiments of the present disclosure.
• FIG. 3 is a cross-sectional view of a third semiconductor structure in accordance with some embodiments of the present disclosure.
• FIG. 4 is a cross-sectional view of a fourth semiconductor structure in accordance with some embodiments of the present disclosure.
• FIG. 5 is a flow diagram illustrating a method of manufacturing a semiconductor structure in accordance with some embodiments of the present disclosure.
• FIGS. 6 through 17 illustrate cross-sectional views of intermediate stages in the formation of a semiconductor structure in accordance with some embodiments of the present disclosure.
• FIG. 18 is a flow diagram illustrating a method of manufacturing a semiconductor structure in accordance with some embodiments of the present disclosure.
• FIGS. 19 through 27 illustrate cross-sectional views of intermediate stages in the formation of a semiconductor structure in accordance with some embodiments of the present disclosure.
• first, second, third, etc. may be used herein to describe various elements, components, regions, layers or sections, these elements, components, regions, layers or sections are not limited by these terms. Rather, these terms are merely used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present inventive concept.
• FIG. 1 is a schematic cross-sectional view of a first semiconductor structure 100 in accordance with some embodiments of the present disclosure.
• the first semiconductor structure 100 is a part of a die, a package or a device.
• the first semiconductor structure 100 includes a first wafer 101 and a second wafer 102 stacked over the first wafer 101 .
• the first wafer 101 is bonded to the second wafer 102 .
• the second wafer 102 is stacked over the first wafer 101 in front-to-front configuration.
• the first wafer 101 is a bottom wafer, and the second wafer 102 is a top wafer.
• a thickness of the first wafer 101 is substantially greater than a thickness of the second wafer 102 .
• the first wafer 101 includes a first substrate 101 a and a first dielectric layer 101 b disposed over the first substrate 101 a.
• the first substrate 101 a is a semiconductive layer.
• the first substrate 101 a includes semiconductive material such as silicon, germanium, gallium, arsenic, or a combination thereof.
• the first substrate 101 a is a silicon layer.
• a thickness of the first substrate 101 a is between about 500 ⁇ m and about 800 ⁇ m.
• circuitries or electrical components such as transistors, capacitors, resistors, diodes, photodiodes or the like are disposed over the first substrate 101 a.
• electrical circuitries formed on the first substrate 101 a can be any type of circuitry suitable for a particular application.
• the electrical circuitries may include various n-type metal-oxide semiconductor (NMOS) and/or p-type metal-oxide semiconductor (PMOS) devices such as transistors, capacitors, resistors, diodes, photodiodes, fuses or the like.
• the electrical circuitries may be connected to perform one or more functions.
• the functions may include memory, processing, sensing, amplification, power distribution, input/output, or the like.
• the first dielectric layer 101 b is disposed on the first substrate 101 a.
• the first dielectric layer 101 b includes dielectric material such as oxide, nitride, silicon dioxide, silicon nitride, silicon oxynitride, silicon carbide, polymer or the like.
• the first dielectric layer 101 b includes several dielectric layers stacked over one another.
• the first dielectric layer 101 b is an interlayer dielectric (ILD) layer.
• a thickness of the first dielectric layer 101 b is substantially less than 5 ⁇ m. In some embodiments, the thickness of the first dielectric layer 101 b is between about 2 ⁇ m and about 3 ⁇ m.
• a first component 103 is included in the first wafer 101 a. In some embodiments, the first component 103 is disposed over the first substrate 101 a. In some embodiments, the first component 103 is disposed within the first dielectric layer 101 b. In some embodiments, the first component 103 can be an electrical component or device such as a transistor, capacitor, resistor, diode, photodiode or the like. In some embodiments, the first component 103 is electrically connected to the circuitry disposed within or over the first substrate 101 a.
• the first component 103 is a conductive feature within the first dielectric layer 101 b.
• the first component 103 includes conductive material such as copper, aluminum, silver or the like.
• the first component 103 includes a first conductive pad 103 a and a first conductive via 103 b extending from the first conductive pad 103 a.
• the first conductive pad 103 a extends laterally in the first dielectric layer 101 b, and the first conductive via 103 b extends vertically in the first dielectric layer 101 b.
• the first conductive pad 103 a is in contact with the first conductive via 103 b.
• the second wafer 102 is disposed over the first wafer 101 .
• the second wafer 102 includes a second substrate 102 a and a second dielectric layer 102 b disposed over the second substrate 102 a.
• the second substrate 102 a is a semiconductive layer.
• the second substrate 102 a includes semiconductive material such as silicon, germanium, gallium, arsenic, or a combination thereof.
• the second substrate 102 a is a silicon layer. In some embodiments, the second substrate 102 a has a configuration similar to that of the first substrate 101 a. In some embodiments, the second substrate 102 a includes a same material as the first substrate 101 a. In some embodiments, the thickness of the first substrate 101 a is substantially greater than a thickness of the second substrate 102 a. In some embodiments, the thickness of the second substrate 102 a is substantially less than or equal to 50 ⁇ m.
• circuitries or electrical components such as transistors, capacitors, resistors, diodes, photodiodes or the like are disposed over the second substrate 102 a.
• electrical circuitries formed on the second substrate 102 a can be any type of circuitry suitable for a particular application.
• the electrical circuitries may include various n-type metal-oxide semiconductor (NMOS) and/or p-type metal-oxide semiconductor (PMOS) devices such as transistors, capacitors, resistors, diodes, photodiodes, fuses or the like.
• the electrical circuitries may be connected to perform one or more functions.
• the functions may include memory, processing, sensing, amplification, power distribution, input/output or the like.
• the second dielectric layer 102 b is disposed on the second substrate 102 a.
• the second dielectric layer 102 b includes dielectric material such as oxide, nitride, silicon dioxide, silicon nitride, silicon oxynitride, silicon carbide, polymer or the like.
• the second dielectric layer 102 b includes several dielectric layers stacked over one another.
• the second dielectric layer 102 b is an interlayer dielectric (ILD) layer.
• ILD interlayer dielectric
• a thickness of the second dielectric layer 102 b is substantially less than 5 ⁇ m. In some embodiments, the thickness of the second dielectric layer 102 b is between about 2 ⁇ m and about 3 ⁇ m. In some embodiments, the second dielectric layer 102 b has a configuration similar to that of the first dielectric layer 101 b. In some embodiments, the second dielectric layer 102 b includes a same material as the first dielectric layer 101 b.
• the second dielectric layer 102 b is bonded to the first dielectric layer 101 b. In some embodiments, the first dielectric layer 101 b is in contact with the second dielectric layer 102 b. In some embodiments, the second dielectric layer 102 b is bonded to the first dielectric layer 101 b by a dielectric-to-dielectric bonding process. In some embodiments, a first interface 106 is present between the first dielectric layer 101 b and the second dielectric layer 102 b. In some embodiments, the first interface 106 may be absent, such that the first dielectric layer 101 b is integral with the second dielectric layer 102 b.
• a second component 104 is included in the second wafer 102 a. In some embodiments, the second component 104 is disposed over the second substrate 102 a. In some embodiments, the second component 104 is disposed within the second dielectric layer 102 b. In some embodiments, the second component 104 can be an electrical component or device such as a transistor, capacitor, resistor, diode, photodiodes or the like. In some embodiments, the second component 104 is electrically connected to the circuitry disposed within or over the second substrate 102 a. In some embodiments, the second component 104 has a configuration similar to that of the first component 103 . In some embodiments, the second component 104 includes a same material as the first component 103 .
• the second component 104 is a conductive feature within the second dielectric layer 102 b.
• the second component 104 includes conductive material such as copper, aluminum, silver or the like.
• the second component 104 includes a second conductive pad 104 a and a second conductive via 104 b extending from the second conductive pad 104 a.
• the second conductive pad 104 a extends laterally in the second dielectric layer 102 b, and the second conductive via 104 b extends vertically in the second dielectric layer 102 b. In some embodiments, the second conductive pad 104 a is in contact with the second conductive via 104 b. In some embodiments, the second component 104 is disposed over the first component 103 . In some embodiments, the second component 104 is aligned with the first component 103 .
• a conductive structure 105 is included in the first semiconductor structure 100 . In some embodiments, the conductive structure 105 is disposed within the first wafer 101 and the second wafer 102 . In some embodiments, the conductive structure 105 is surrounded by the first dielectric layer 101 b, the second dielectric layer 102 b and the second substrate 102 a.
• the conductive structure 105 is electrically connected to the first component 103 and/or the second component 104 .
• the first component, the second component and the conductive structure are electrically connected to each other.
• at least a portion of the conductive structure 105 is disposed between the first component 103 and the second component 104 .
• the conductive structure 105 includes conductive material such as copper, aluminum, silver or the like.
• the conductive structure 105 includes a first member 105 a and a second member 105 b protruding from the first member 105 a.
• the first member 105 a is surrounded by the first dielectric layer 101 b and the second dielectric layer 102 b.
• the first member 105 a is disposed adjacent to the first interface 106 .
• the first member 105 a is disposed between two sections of the first interface 106 .
• the first member 105 a extends from the first dielectric layer 101 b to the second dielectric layer 102 b.
• the first component 103 and the second component 104 at least partially contact the first member 105 a of the conductive structure 105 .
• the first member 105 a is disposed between the first component 103 and the second component 104 .
• the first member 105 a contacts the first conductive via 103 b and the second conductive via 104 b.
• the second member 105 b is surrounded by the second wafer 102 . In some embodiments, an end of the second member 105 b is coupled to the first member 105 a. In some embodiments, the second member 105 b is integral with the first member 105 a. In some embodiments, at least a surface of the second member 105 b is exposed through an upper surface of the second wafer 102 . In some embodiments, a surface of an end of the second member 105 b is exposed through an upper surface of the second substrate 102 a. In some embodiments, the second member 105 b is disposed adjacent to the second component 104 . That is, the second member 105 b is not disposed over the second component 104 .
• the second member 105 b extends from the first member 105 a toward the second substrate 102 a. In some embodiments, the second member 105 b extends through the second dielectric layer 102 b. In some embodiments, the second member 105 b extends away from the first wafer 101 . In some embodiments, the second member 105 b extends away from the first substrate 101 a and the first dielectric layer 101 b. In some embodiments, the second member 105 b is substantially orthogonal to the first member 105 a. In some embodiments, a length of the second member 105 b is substantially equal to a total thickness of the second substrate 102 a and the second dielectric layer 102 b. In some embodiments, the second member 105 b is a through substrate via (TSV).
• TSV through substrate via
• FIG. 2 is a schematic cross-sectional view of a second semiconductor structure 200 in accordance with some embodiments of the present disclosure.
• the second semiconductor structure 200 has a configuration similar to that of the first semiconductor structure 100 , except the second member 105 b has a tapered configuration, and an isolating layer 107 and a first seed layer 108 are included.
• the second member 105 b of the conductive structure 105 is tapered from the second substrate 102 a toward the second dielectric layer 102 b. In some embodiments, a width of a portion of the second member 105 b surrounded by the second substrate 102 a is substantially greater than a width of a portion of the second member 105 b surrounded by the second dielectric layer 102 b.
• the isolating layer 107 surrounds at least a portion of the second member 105 b of the conductive structure 105 and is disposed between the second dielectric layer 102 b and the second member 105 b of the conductive structure 105 . In some embodiments, the isolating layer 107 is disposed between the second substrate 102 a and the second member 105 b.
• the isolating layer 107 is absent between the second member 105 b and the second dielectric layer 102 b. That is, a portion of the second member 105 b contacts the second dielectric layer 105 b. In some embodiments, the isolating layer 107 isolates the second member 105 b from the second substrate 102 a. In some embodiments, the isolating layer 107 includes oxide or any other suitable material.
• the first seed layer 108 surrounds the first member 105 a of the conductive structure 105 . In some embodiments, the first seed layer 108 is disposed between the first member 105 a and the first dielectric layer 101 b and between the first member 105 a and the second dielectric layer 102 b. In some embodiments, the first seed layer 108 includes conductive material. In some embodiments, the first seed layer 108 includes two kinds of conductive materials. In some embodiments, the first seed layer 108 includes titanium and copper.
• FIG. 3 is a schematic cross-sectional view of a third semiconductor structure 300 in accordance with some embodiments of the present disclosure.
• the third semiconductor structure 300 has a configuration similar to that of the first semiconductor structure 100 , except that, in the third semiconductor structure 300 , the first member 105 a includes a first part 105 c and a second part 105 d offset from the first part 105 c.
• the first part 105 c and the second part 105 d are not aligned with each other.
• the first part 105 c is laterally offset from the second part 105 d.
• a portion of the first part 105 c contacts the second dielectric layer 102 b, and a portion of the second part 105 d contacts the first dielectric layer 105 b.
• a portion of the first part 105 c is coupled to a portion of the second part 105 d.
• the second member 105 b protrudes from the second part 105 d of the first member 105 a.
• the first component 103 is coupled to the first part 105 c
• the second component 104 is coupled to the second part 105 d.
• a width of the first part 105 c is substantially equal to a width of the second part 105 d.
• FIG. 4 is a schematic cross-sectional view of a fourth semiconductor structure 400 in accordance with some embodiments of the present disclosure.
• the fourth semiconductor structure 400 has a configuration similar to that of the first semiconductor structure 100 , except that, in the fourth semiconductor structure 400 , the first member 105 a includes the first part 105 c and the second part 105 d, wherein a width of the second part 105 d is different from a width of the first part 105 c.
• the width of the first part 105 c is substantially different from the width of the second part 105 d. In some embodiments, the width of the first part 105 c is substantially greater than or less than the width of the second part 105 d. In some embodiments, a portion of the first part 105 c contacts the second dielectric layer 102 b, and a portion of the second part 105 d does not contact the first dielectric layer 105 b. In some embodiments, a portion of the first part 105 c does not contact the second dielectric layer 102 b, and a portion of the second part 105 d contacts the first dielectric layer 105 b. In some embodiments, a portion of the first part 105 c is coupled to a portion of the second part 105 d.
• FIG. 5 is a flow diagram illustrating a first method S 500 of manufacturing a first semiconductor structure 100 in accordance with some embodiments of the present disclosure
• FIGS. 6 through 17 illustrate cross-sectional views of intermediate stages in the formation of the first semiconductor structure 100 in accordance with some embodiments of the present disclosure.
• the stages shown in FIGS. 6 to 17 are also illustrated schematically in the flow diagram in FIG. 5 .
• the fabrication stages shown in FIGS. 6 to 17 are discussed in reference to the process steps shown in FIG. 5 .
• the first method S 500 includes a number of operations and the description and illustration are not deemed as a limitation as the sequence of the operations.
• the first method S 500 includes a number of steps (S 501 , S 502 , S 503 , S 504 , S 505 , 5506 and S 507 ).
• a first wafer 101 including a first substrate 101 a, a first dielectric layer 101 b disposed over the first substrate 101 a, and a first component 103 formed within the first dielectric layer 101 b, is provided according to a step S 501 in FIG. 5 .
• the first substrate 101 a is a semiconductive layer. In some embodiments, the first substrate 101 a includes semiconductive material such as silicon, germanium, gallium, arsenic, or combinations thereof. In some embodiments, the first substrate 101 a is a silicon layer. In some embodiments, a thickness of the first substrate 101 a is between about 500 ⁇ m and about 800 ⁇ m.
• the first dielectric layer 101 b is disposed on the first substrate 101 a.
• the first dielectric layer 101 b is formed by spin coating, plasma-enhanced chemical vapor deposition (PECVD), or any other suitable operation.
• PECVD plasma-enhanced chemical vapor deposition
• a planarizing process can be optionally performed on the first dielectric layer 101 b to yield an acceptably flat topology.
• the first dielectric layer 101 b includes dielectric material such as oxide, nitride, silicon dioxide, silicon nitride, silicon oxynitride, silicon carbide, polymer or the like.
• the first dielectric layer 101 b includes several dielectric layers stacked over each other.
• the first dielectric layer 101 b is an interlayer dielectric (ILD) layer.
• a thickness of the first dielectric layer 101 b is substantially less than 5 ⁇ m.
• the first component 103 is included in the first wafer 101 . In some embodiments, the first component 103 is disposed within the first dielectric layer 101 b. In some embodiments, the first component 103 can be formed by deposition, etching, implantation, photolithography, annealing or any other suitable operation. In some embodiments, the first component 103 can be an electrical component or device such as a transistor, capacitor, resistor, diode, photodiodes or the like. In some embodiments, the first component 103 is electrically connected to the circuitry disposed within or over the first substrate 101 a.
• the first component 103 is a conductive feature within the first dielectric layer 101 b.
• the first component 103 includes conductive material such as copper, aluminum, silver or the like.
• the first component 103 includes a first conductive pad 103 a and a first conductive via 103 b extending from the first conductive pad 103 a.
• the first conductive pad 103 a is in contact with the first conductive via 103 b.
• a second wafer 102 including a second substrate 102 a, a second dielectric layer 102 b disposed over the second substrate 102 a and a second component 104 formed within the second dielectric layer 102 b is provided according to a step S 502 in FIG. 5 .
• the second substrate 102 a is a semiconductive layer. In some embodiments, the second substrate 102 a includes semiconductive material such as silicon, germanium, gallium, arsenic, or a combination thereof. In some embodiments, the second substrate 102 a is a silicon layer. In some embodiments, the second substrate 102 a has a configuration similar to that of the first substrate 101 a. In some embodiments, the second substrate 102 a includes a same material as the first substrate 101 a. In some embodiments, the thickness of the first substrate 101 a is substantially equal to a thickness of the second substrate 102 a.
• the second dielectric layer 102 b is disposed on the second substrate 102 a.
• the second dielectric layer 102 b is formed by spin coating, plasma-enhanced chemical vapor deposition (PECVD) or any other suitable operation.
• PECVD plasma-enhanced chemical vapor deposition
• a planarizing process can be optionally performed on the second dielectric layer 102 b to yield an acceptably flat topology.
• the second dielectric layer 102 b includes dielectric material such as oxide, nitride, silicon dioxide, silicon nitride, silicon oxynitride, silicon carbide, polymer or the like. In some embodiments, the second dielectric layer 102 b includes several dielectric layers stacked over each other. In some embodiments, the second dielectric layer 102 b is an interlayer dielectric (ILD) layer. In some embodiments, a thickness of the second dielectric layer 102 b is substantially less than 5 ⁇ m. In some embodiments, the second dielectric layer 102 b has a configuration similar to that of the first dielectric layer 101 b. In some embodiments, the second dielectric layer 102 b includes a same material as the first dielectric layer 101 b.
• ILD interlayer dielectric
• the second component 104 is included in the second wafer 102 . In some embodiments, the second component 104 is disposed within the second dielectric layer 102 b. In some embodiments, the second component 104 can be formed by deposition, etching, implantation, photolithography, annealing or any other suitable operation.
• the second component 104 can be an electrical component or device such as a transistor, capacitor, resistor, diode, photodiodes or the like. In some embodiments, the second component 104 is electrically connected to the circuitry disposed within or over the second substrate 102 a. In some embodiments, the second component 104 has a configuration similar to that of the first component 103 . In some embodiments, the second component 104 includes a same material as the first component 103 .
• the second component 104 is a conductive feature within the second dielectric layer 102 b.
• the second component 104 includes conductive material such as copper, aluminum, silver or the like.
• the second component 104 includes a second conductive pad 104 a and a second conductive via 104 b extending from the second conductive pad 104 a.
• a first portion of the first dielectric layer 101 b is removed to form a first recess 101 c according to a step S 503 in FIG. 5 .
• the first portion of the first dielectric layer 101 b can be removed by photolithography, etching or any other suitable operation.
• the first recess 101 c is formed by disposing a first patterned photoresist 109 over the first dielectric layer 101 b and removing the first portion of the first dielectric layer 101 b exposed through the first patterned photoresist 109 .
• the first patterned photoresist 109 is formed by performing an exposure process and a develop process on a photoresist material.
• the first patterned photoresist 109 is removed after the formation of the first recess 101 c.
• the first patterned photoresist 109 can be removed by stripping, etching or any other suitable operation.
• the first recess 101 c exposes at least a portion of the first component 103 . In some embodiments, a portion of the first conductive via 103 b of the first component 103 is exposed by the first recess 101 c. In some embodiments, a portion of the first component 103 is exposed through the first dielectric layer 101 b. In some embodiments, the step S 503 can be implemented prior to the step S 502 .
• a second portion of the second dielectric layer 102 b is removed to form a second recess 102 c according to a step S 504 in FIG. 5 .
• the second portion of the second dielectric layer 102 b can be removed by photolithography, etching or any other suitable operation.
• the second recess 102 c is formed by disposing a second patterned photoresist 110 over the second dielectric layer 102 b and removing the second portion of the second dielectric layer 102 b exposed through the second patterned photoresist 110 .
• the second patterned photoresist 110 is formed by performing an exposure process and a develop process on a photoresist material.
• the second patterned photoresist 110 is removed after the formation of the second recess 102 c.
• the second patterned photoresist 110 can be removed by stripping, etching or any other suitable operation.
• the second recess 102 c exposes at least a portion of the second component 104 . In some embodiments, a portion of the second conductive via 104 b of the second component 104 is exposed by the second recess 102 c. In some embodiments, a portion of the second component 104 is exposed through the second dielectric layer 102 b.
• the step S 504 can be implemented after the step S 502 . In some embodiments, the step S 504 can be implemented before or after the step S 503 . In some embodiments, the step S 503 and the step S 504 can be implemented separately or simultaneously.
• the second wafer 102 is disposed over the first wafer 101 to bond the first dielectric layer 101 b to the second dielectric layer 102 b according to a step S 505 in FIG. 5 .
• the second wafer 102 is flipped and then disposed over the first wafer 101 .
• the first dielectric layer 101 b is in contact with the second dielectric layer 102 b.
• the second wafer 102 is bonded to the first wafer 101 by bonding the first dielectric layer 101 b to the second dielectric layer 102 b.
• the first dielectric layer 101 b is bonded to the second dielectric layer 102 b by oxide fusion bonding, dielectric-to-dielectric bonding or any other suitable operation.
• the step S 505 is implemented after the step S 503 and the step S 504 .
• a first interface 106 is formed between the first dielectric layer 101 b and the second dielectric layer 102 b.
• the first dielectric layer 101 b is bonded to the second dielectric layer 102 b, so that the first recess 101 c is aligned with the second recess 102 c.
• the second component 104 is disposed over the first component 103 . In some embodiments, the second component 104 is aligned with the first component 103 .
• the first dielectric layer 101 b is bonded to the second dielectric layer 102 b, wherein the first recess 101 c is offset from the second recess 102 c in a manner similar to that of the first recess 101 c and the second recess 102 c in the third semiconductor structure 300 described above or illustrated in FIG. 3 .
• a void 111 is formed after the bonding of the first dielectric layer 101 b to the second dielectric layer 102 b.
• the void 111 is defined by the first recess 101 c and the second recess 102 c.
• the void 111 is filled with air or gas.
• a thickness of the second substrate 102 a is reduced after the step S 505 .
• the thickness of the second substrate 102 a can be reduced by removing some of the second substrate 102 a from a back side of the second substrate 102 a farthest from the first wafer 101 .
• the reduction of the thickness of the second substrate 102 a can be implemented by grinding, etching, chemical mechanical polishing (CMP) or any other suitable operation.
• CMP chemical mechanical polishing
• the back side of the second substrate 102 a is ground in order to reduce a thickness of the second substrate 102 a and an overall thickness of the second wafer 102 .
• a third portion of the second substrate 102 a and the second dielectric layer 102 b is removed to form a third recess 102 d according to a step S 506 in FIG. 5 .
• the thickness of the second substrate 102 a is reduced prior to the step S 506 .
• the third portion of the second substrate 102 a and the second dielectric layer 102 b can be removed by etching, deep reactive ion etching (DRIE), isotropic etching, laser drilling or any other suitable operation.
• the third recess 102 d is formed by one or more iterations of etching processes.
• the third recess 102 d is formed by removing a portion of the second substrate 102 a, and then removing a portion of the second dielectric layer 102 b.
• the third recess 102 d is coupled to the second recess 102 c.
• the void 111 is accessible through the third recess 102 d.
• a conductive material is disposed to fill the first recess 101 c, the second recess 102 c and the third recess 102 d and form a conductive structure 105 according to a step S 507 in FIG. 5 .
• the conductive material is disposed by electroplating or any other suitable operation.
• the conductive material includes copper or any other suitable material.
• the conductive structure 105 is formed by filling the void 111 with the conductive material, and then filling the third recess 102 d with the conductive material.
• the first recess 101 c and the second recess 102 c are filled with the conductive material after the first dielectric layer 101 b is bonded to the second dielectric layer 102 b (the step S 505 ).
• the conductive structure 105 including a first member 105 a and a second member 105 b is formed.
• the first member 105 a is surrounded by the first dielectric layer 101 b and the second dielectric layer 102 b.
• the second member 105 b is surrounded by the second wafer 102 .
• the conductive structure 105 is electrically connected to the first component 103 and the second component 104 after the disposing of the conductive material.
• the first semiconductor structure 100 as shown in FIG. 1 is formed.
• FIG. 18 is a flow diagram illustrating a second method S 600 of manufacturing a second semiconductor structure 200 in accordance with some embodiments of the present disclosure
• FIGS. 1 to 13 and 19 to 27 illustrate cross-sectional views of intermediate stages in the formation of the second semiconductor structure 200 in accordance with some embodiments of the present disclosure.
• the stages shown in FIGS. 1 to 13 and 19 to 27 are also illustrated schematically in the flow diagram in FIG. 18 .
• the fabrication stages shown in FIGS. 1 to 13 and 19 to 27 are discussed in reference to the process steps shown in FIG. 18 .
• the second method S 600 includes a number of operations and the description and illustration are not deemed as a limitation as the sequence of the operations.
• the second method S 600 includes a number of steps (S 601 , S 602 , S 603 , S 604 , S 605 , S 606 , S 607 , S 608 , S 609 , S 610 and S 611 ).
• Steps 5601 to S 604 are same as the steps S 501 to S 504 described above or illustrated by FIGS. 1 to 13 , and repeated description of such steps is omitted for brevity.
• a first seed layer 108 is disposed over the first dielectric layer 101 b and the second dielectric layer 102 b respectively according to a step S 605 in FIG. 18 .
• the first seed layer 108 is conformal to the first recess 101 c and the second recess 102 c.
• the first seed layer 108 is disposed by deposition, physical vapor deposition (PVD) or any other suitable operation.
• the first seed layer 108 includes titanium and copper.
• portions of the first seed layer 108 disposed on the first dielectric layer 101 b and the second dielectric layer 102 b and outside of the first recess 101 c and the second recess 102 c are removed.
• the second wafer 102 is disposed over the first wafer 101 to bond the first dielectric layer 101 b to the second dielectric layer 102 b according to a step S 606 in FIG. 18 .
• the step S 606 is same as the step S 505 described above or illustrated in FIG. 14 .
• a thickness of the second substrate 102 a is reduced after the step S 606 , similar to the step described above or illustrated in FIG. 15 .
• a first section of the second substrate 102 a and the second dielectric layer 102 b is removed to form a first opening 112 according to a step S 607 in FIG. 18 .
• the first section of the second substrate 102 a and the second dielectric layer 102 b can be removed by etching, deep reactive ion etching (DRIE), isotropic etching, laser drilling or any other suitable operation.
• the first opening 112 extends through the second substrate 102 a and partially through the second dielectric layer 102 b.
• an isolating layer 107 is disposed conformal to the first opening 112 according to a step S 608 in FIG. 18 .
• the isolating layer 107 is disposed by atomic layer deposition (ALD), sputtering or any other suitable operation.
• the isolating layer 107 is disposed along sidewalls of the first opening 112 .
• the isolating layer 107 includes oxide or any other suitable material.
• a bottom portion of the isolating layer 107 is removed according to a step S 609 in FIG. 18 .
• the bottom portion of the isolating layer 107 can be removed by etching or any other suitable operation.
• a thickness of the second dielectric layer 102 b between a bottom of the first opening 112 and the void 111 is about 1 ⁇ m.
• a thickness of the second dielectric layer 102 b between the bottom of the first opening 112 and the first seed layer 108 is about 1 ⁇ m.
• a second section of the second substrate 102 a and the second dielectric layer 102 b is removed to form a second opening 113 according to a step S 610 in FIG. 18 .
• the second section of the second substrate 102 a and the second dielectric layer 102 b can be removed by etching, deep reactive ion etching (DRIE), isotropic etching, laser drilling or any other suitable operation.
• the second substrate 102 a serves as a hard mask during the removal of the second section.
• the second section is removed, such that the first opening 112 is coupled to the void 111 through the second opening 113 .
• the void 111 is now accessible through the first opening 112 and the second opening 113 .
• the second opening 113 is surrounded by the second dielectric layer 102 b only.
• the step S 609 and the step S 610 are implemented separately or simultaneously. In some embodiments, the step S 609 is performed prior to the step S 610 .
• a conductive material is disposed to fill the first recess 101 c, the second recess 102 c, the first opening 112 and the second opening 113 and form a conductive structure 105 according to a step S 611 in FIG. 18 .
• a second seed layer is disposed conformal to the first recess 101 c, the second recess 102 c, the first opening 112 and the second opening 113 prior to the disposing of the conductive material.
• the second seed layer is disposed by PVD, sputtering or any other suitable operation.
• the second seed layer includes titanium and copper.
• the conductive material is disposed by electroplating or any other suitable operation. In some embodiments, the conductive material includes copper or any other suitable material. In some embodiments, the conductive structure 105 is formed by filling the void 111 with the conductive material, and then filling the first opening 112 and the second opening 113 with the conductive material. In some embodiments, the conductive structure 105 includes a first member 105 a and a second member 105 b.
• the first member 105 a is surrounded by the first dielectric layer 101 b and the second dielectric layer 102 b. In some embodiments, the second member 105 b is surrounded by the second wafer 102 . In some embodiments, the conductive structure 105 is electrically connected to the first component 103 and the second component 104 after the disposing of the conductive material. In some embodiments, the second semiconductor structure is formed as shown in FIG. 2 .
• the third semiconductor structure shown in FIG. 3 is formed after the disposing of the conductive material.
• a second interface between the conductive structure 105 and the first dielectric layer 101 b is formed after the disposing of the conductive material.
• a third interface between the conductive structure 105 and the second dielectric layer 102 b is formed after the disposing of the conductive material.
• the semiconductor structure 100 , 200 , 300 or 400 including a void 111 between the first wafer 101 and the second wafer 102 and a conductive structure 105 within the void 111 is formed. Since the conductive structure 105 is formed after bonding of the first wafer 101 and the second wafer 102 , alignment between the first wafer 101 and the second wafer 102 would not adversely affect formation of the conductive structure 105 . Therefore, reliability of the conductive structure 105 and overall performance of the semiconductor structure 100 , 200 , 300 or 400 having such conductive structure 105 can be improved.
• the semiconductor structure comprises a first wafer including a first dielectric layer and a first component disposed within the first dielectric layer; a second wafer disposed over the first wafer and including a second dielectric layer over the first dielectric layer, and a second component within the second dielectric layer; and a conductive structure including a first member surrounded by the first dielectric layer and the second dielectric layer, and a second member protruding from the first member and surrounded by the second wafer.
• One aspect of the present disclosure provides a method of manufacturing a semiconductor structure.
• the method includes steps of providing a first wafer including a first substrate, a first dielectric layer disposed over the first substrate, and a first component formed within the first dielectric layer; providing a second wafer including a second substrate, a second dielectric layer disposed over the second substrate, and a second component formed within the second dielectric layer; removing a first portion of the first dielectric layer to form a first recess; removing a second portion of the second dielectric layer to form a second recess; disposing the second wafer over the first wafer to bond the first dielectric layer to the second dielectric layer; removing a third portion of the second substrate and the second dielectric layer to form a third recess coupled to the second recess; and disposing a conductive material to fill the first recess, the second recess and the third recess to form a conductive structure.

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