US4926231A - Integrated pin photo-detector - Google Patents

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• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
  • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
  • H10F39/10—Integrated devices
  • H10F39/103—Integrated devices the at least one element covered by H10F30/00 having potential barriers, e.g. integrated devices comprising photodiodes or phototransistors

Definitions

• This invention relates, in general, to semiconductor devices and, more particularly, to a means and method for providing an integrated photosensor for semiconductor integrated circuits in a fashion compatible with the methods and structures used for such integrated circuits.
• Integrated circuits containing thousands to millions of transistors and other elements are commonplace today. These integrated circuits operate at such high speeds that the propagation time of signals from one part to another of the integrated circuit chip or from one integrated circuit chip to another are of concern. For these and other reasons there is great interest in providing optical devices within integrated circuits so that signals may be coupled optically rather than electrically.
• intrinsic in connection with semiconductor materials is intended to refer to semiconductor materials of either conductivity type having a resistivity greater than about one hundred ohm-cm.
• a semiconductor wafer having a major surface in which a cavity is formed.
• the cavity has a sidewall extending into the wafer and a bottom of a first conductivity type spaced from the wafer surface.
• a dielectric liner is provided on the cavity sidewall.
• a substantially intrinsic semiconductor material is formed in the cavity in contact with the bottom and its surface is doped with a dopant of a second conductivity type opposite the first type. An ohmic contact is formed to the doped region.
• the substrate has a thin surface epi-layer, it is desirable that the cavity extend through the surface epi-layer to the substrate.
• An integrated photodetector constructed according to the foregoing process comprises a semiconductor wafer with an optional surface epi-layer, a cavity extending through the surface epi-layer to the substrate, a dielectric liner on the cavity sidewall, a substantially intrinsic semiconductor material nucleated from the cavity bottom and substantially filling the cavity, and a doped region of opposite type to the substrate formed in the outer surface of the intrinsic material.
• An ohmic contact is provided to the doped region which admits light into the underlying intrinsic material.
• FIGS. 1-6 show simplified schematic cross-sectional views of a portion of a semiconductor wafer during different stages of fabrication according to the present invention.
• semiconductor wafer 10 having surface epi-layer 12 is provided with protective layers 14, 16, 18.
• substrate 10 is P-type and epi-layer 12 is N-type silicon, which is a frequently used arrangement in integrated circuits, particularly bipolar integrated circuits.
• epi-layer 12 has thickness 13 in the range of about 0.6 to 2.0 micrometers with about 0.8 to 1.2 micrometers being convenient and about 1.0 micrometers being typical.
• Epi-layer 12 is not essential to the present invention but is of special concern since it is frequently used in integrated circuits. The present method and structure for forming an integrated photosensor works whether epi-layer 12 is present or not.
• Layer 14 is conveniently of silicon dioxide formed, for example, by thermal oxidation of epi-layer 12. Layer 14 is desirable but not essential and is intended to function primarily as a buffer layer between epi-layer 12 and layers 16, 18. Layer 14 is conveniently about 0.05 to 0.1 micrometers thick with about 0.07 micrometers being preferred. Layer 14 may be prepared by any convenient technique, but thermal oxidation is preferred for silicon substrates. Thicker or thinner layers may also be used. Method for forming such layers are well known in the art.
• Layer 16 is conveniently of silicon nitride, but other masking materials resistant to etching of epi-layer 12 and substrate 10 may also be used. Layer 16 is conveniently about 0.1 to 0.2 micrometers thick with about 0.15 micrometers being typical, but thicker or thinner layers may also be used. Methods for forming silicon nitride layers are well known in the art.
• Layer 18 functions as a mask for delineating opening 20 through underlying layers 14, 16 and etching epi-layer 12 and substrate 10.
• Layer 18 may be ⁇ f any convenient masking material. Photoresist and electron beam resist are typical materials well known in the art. Hard masking materials such as oxides, nitride, glasses or combinations thereof may also be used. Means and methods for forming mask layer 18 and delineating opening 20 are well known in the art.
• the shape and lateral dimension of the photosensor is determined by the shape and lateral dimensions of opening 20, less the thickness of sidewall spacers 36 (see FIG. 6) to be subsequently described.
• lateral dimensions of about ten micrometers are typical, and when for use with multi-mode optical fibers, lateral dimensions of about one hundred micrometers are typical. Larger sensors may be used but consume increased die area which is not desirable in dense circuits. Smaller sensors may be used provided the optical input can be adequately focused within the sensor area so that there is negligible optical signal loss laterally outside the sensor.
• a single masking layer either graded or homogeneous, that is able to protect surface portion 21 of semiconductor 10, 12 against etching and other process steps may also be used. Methods for forming such layers are well known. Glasses, silicon oxide, silicon nitride, or silicon oxy-nitride are non-limiting examples of suitable single layer masking materials. As will be subsequently explained, it is also desirable that the masking layer be non-nucleating during selective epitaxial deposition of the semiconductor material which forms the photosensor region.
• cavity 24 of depth 25 is etched in surface portion 22 of semiconductor 10, 12 under opening 20.
• Anisotropic etching is preferred.
• Depth 25 desirably exceeds thickness 13 so that cavity 24 extends through epi-layer 12. This is because in most high performance bipolar integrated circuits, thickness 13 of epi-layer 12 is smaller than the distance needed for efficient absorption of light.
• cavity 24 in which the integrated optical sensor is to be formed should in most cases have depth 25 greater than thickness 13.
• Depth 25 is conveniently in the range of about 3 to 20 micrometers with 7 to 13 micrometers being useful and about 10 micrometers being typical. Larger depths may also be used.
• Mask 18 may be removed after etching cavity 24.
• Layer 14 is reconstituted on bottom 26 and sidewall 28 of cavity 24, for example by thermal oxidation, although other techniques may also be used. This step is desirable but not essential.
• Layer 32 has thickness conveniently of about 0.1 to 0.5 micrometers with about 0.3 micrometers being typical.
• CVD and LPCVD are suitable deposition techniques well known in the art, but other techniques may also be used. Thicker or thinner layers may also be used, provided that sufficient thickness remains on sidewall 28 to provide for lateral dielectric isolation between the sensor formed in cavity 24 and epilayer 12.
• Layer 32 is then etched using anisotropic etching techniques well known in the art to remove portions 34 and 35 of layer 32 while leaving portion 36 on sidewall 28 (see FIG. 4).
• bottom 26 of cavity 24 is desirably doped in region 38 to enhance its conductivity.
• it is doped P + so as to provide a low resistance contact to P-type substrate 10, however this is not essential.
• Ion implantation is a convenient method but other techniques may also be used. No masking step is required since layers 14, 16 continue to protect surface 21 while bottom 26 is exposed. If desired a thin screen oxide may be provided on bottom 26 before the implant to reduce implant damage, but this is not essential. If used, it should be removed before proceeding to the next step. Also, before filling cavity 24 with semiconductor, it is desirable to lightly etch bottom 26 of cavity 24 to remove any structural damage which may have been caused by earlier process steps. Wet etching is preferred.
• Intrinsic semiconductor region 40 is formed in cavity 24 on (optional) doped region 38 (see FIG. 5). While polycrystalline material may be used for semiconductor region 40, single crystal material grown epitaxially on bottom 26 gives better results. Region 40 has upper surface 42. It is important that the semiconductor forming region 40 have high resistivity, that is, greater than about one hundred ohm-cm, preferably about one thousand ohm-cm or larger. This is because, in most integrated circuits, particularly modern integrated circuits of high density and complexity, power supply and logic voltages are only a few volts, typically five volts or less. Further, the present trend is toward even lower voltages. The lower the voltage, the higher the resistivity material that is required in order to have a space charge region of adequate width.
• the space charge region is too narrow, most of the light will be absorbed outside the space charge region and sensitivity will be poor. In silicon and with light of about 830 nanometers wavelength, the optical absorption depth is about 10 micrometers. With a five volt supply, the intrinsic region should have a resistivity of about 100 ohm-cm in order to provide a space charge region of approximately comparable thickness. Those cf skill in the art will understand based on the description herein how to select the resistivity and thickness of the intrinsic material in region 40 so as to provide a space charge region of adequate thickness.
• region 40 be formed by selective epitaxial deposition, that is, under conditions such that semiconductor material 40 nucleates on exposed cavity bottom 26 in substrate 10 and not on the surface of the dielectric on other layers above surface portion 21 laterally outside cavity 24.
• Means for selective epitaxial growth are well known in the art and are described, for example, in U.S. Pat. Nos., 4,400,411, 4,395,433 and 4,101,350 and J. O. Borland et al. "Advanced Dielectric Isolation Through Selective Epitaxial Growth Techniques", Solid State Technology, Vol. 28 (8) (1985) pages 141-148.
• Silicon oxide, silicon nitride and mixtures thereof are examples of materials which can be arranged to be non-nucleating during epitaxial silicon growth.
• a conformal epitaxial layer of semiconductor material may be formed everywhere, filling cavity 24 and extending above the layers on surface 21, and then etched or lapped back to leave portion 40 in cavity 24.
• upper surface 42 of intrinsic semiconductor region 40 is desirably doped to provide, in this example, shallow N + region 44 extending to surface 42.
• Ion implantation is a suitable doping method, but other methods well known in the art may also be used.
• region 44 be relatively shallow, that is, less than about ten percent of the thickness of intrinsic region 40, preferably less than about five percent and conveniently about one to two percent of the thickness, so as to allow adequate room for the junction space charge region to expand into the remaining intrinsic material
• the structure in cavity 24 now provides PIN photo-sensor 38, 40, 44 having a space charge region comparable in thickness to the light absorption depth. This provides high sensitivity and is very desirable for use in connection with modern integrated circuits.
• Convenient thicknesses for layer 46 are about 0.15 to 0.4 micrometers with about 0.3 micrometers being typical.
• Convenient sheet resistance are about 10 to 200 ohms/square with about 100 ohms/square being typical. Methods for forming such layers are well known in the art.
• layer 46 may be deposited before doped region 44 is formed and doped region 44 formed by outdiffusion of dopant from layer 46. This procedure has the advantage that a separate doping step for forming region 44 is not required. Layer 46 may be deposited doped or deposited without significant doping and subsequently doped by ion implantation or other well known methods.
• Layer 46 is used, for example, for interconnecting PIN sensor 38, 40, 44 to an input terminal of another device on the same substrate, e.g. the gate of a FET or base of a bipolar transistor.
• another device on the same substrate e.g. the gate of a FET or base of a bipolar transistor.
• Such devices and the use of polysilicon contact and interconnect layers are described for example, in U.S. patent application Ser. No. 07/009,322 to Peter J. Zdebel et al., entitled "Integrated Circuit Structures Having Polycrystalline Electrode Contacts and Process", which is incorporated herein by reference.
• Light 47 falling on PIN sensor 38, 40, 44 causes the sensor to become conductive and/or generate a current, either of which can be coupled using means well known in the art to the input of a bipolar or field effect transistor or other amplifying device to provide the desired output signal to the remaining integrated circuitry on the same semiconductor die so that the light input, at least in part, controls the electrical output.
• Further conductor 48 having light transparent opening 50 may be applied over conductor 46 to reduce its series resistance (see FIG. 6). Doped semiconductors, intermetallics and metals are suitable. Opening 50 should be of such dimensions so as to not obstruct passage of light 47 into PIN sensor 38, 40, 44.
• Passivation layer 54 of, for example, glass, silicon dioxide, silicon nitride or mixtures thereof or organic insulator may be applied on layers 46, 48 to provide improved surface protection and stabilization. Layer 54 must be transparent to light 47. Methods for applying such conductors and dielectrics are well known in the art.
• the thickness cf intrinsic region 40 may be separately adjusted independent of the thickness of epi-layer 12 so as to obtain the optimal photo-electric response from sensor 38, 40, 44.
• the space charge region produced by the applied voltage substantially overlap the region in which light is absorbed.
• the electric field in the space charge region separates the electron-hole pairs created by the absorbed photons. If the space charge region is thin, then only a small fraction of the light is absorbed therein and most of the electron-hole pairs will be created elsewhere and sensitivity will be poor. This is what happens if the photosensor is constructed within the epi-layer of a high performance integrated circuit where the epi-layer is too thin for efficient light absorption therein.
• the ability provided by the present process to tailor the thickness of the intrinsic region independently of the constraints on the other device regions making up the integrated circuit is of great value.
• the various layers used for the construction of the described photosensor are common to present day integrated circuit fabrication.
• the selective epitaxy step for cavity refill may be incorporated in the normal bipolar or MOS process flow without disruption since it may be carried out early in the fabrication cycle for such devices and has no substantial deleterious effect thereon. Steps necessary to provide doped regions 38 and 44, and highly doped layer 46, as well as layers 48 and 54 are routine in integrated circuit fabrication today.
• Layer 46 either alone or in combination with layer 48 permits integrated sensor 38, 40, 44 to be directly coupled to other devices on the same die using well known planar fabrication techniques and without need for wire-bonds, tabs, solder bumps or the like.
• the present invention provides an improved means and method for forming a photosensor as part of an integrated circuit and which uses fabrication techniques and layers which are compatible with those used for fabricating integrated circuits on the same wafer and die, and which may be coupled thereto without external wires or the like.

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Cited By (25)

Citations (8)

• 1988
  • 1988-12-28 US US07/290,960 patent/US4926231A/en not_active Expired - Fee Related

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